Semiconductor structure and method for manufacturing the same

Abstract

The present invention relates to a method for preparing a semiconductor structure, comprising: providing a base, the base comprising a substrate and a first dielectric layer located on the substrate; forming a through silicon via in the substrate, the through silicon via penetrating the first dielectric layer and extending into the substrate, and the depth of the through silicon via is less than the thickness of the substrate; forming a conductive structure in the through silicon via; forming a filling hole in the first dielectric layer and the substrate, the filling hole surrounding the conductive structure and exposing the side wall of the conductive structure and a part of the substrate, the side wall of the filling hole being in a step shape; forming a thermal conductive structure in the filling hole. The above-mentioned method for preparing a semiconductor structure, by preparing the side wall of the filling hole in a step shape, makes the thermal conductive structure formed in the filling hole also in a step shape, which is conducive to the upward diffusion of heat from the conductive structure, improves the heat dissipation capacity of the through silicon via structure, and thus obtains a through silicon via structure with better reliability and stability.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a semiconductor structure and a preparation method thereof. Background Art

[0002] Through Silicon Via (TSV) is a high-density packaging technology that achieves vertical electrical interconnection of through silicon vias by filling them with conductive materials such as copper, tungsten, and polysilicon.

[0003] Since TSV stacks multiple chips together, the power consumption density increases sharply. The high heat generation and poor heat dissipation make the chip's operating temperature higher, seriously affecting the reliability and stability of TSV. The high operating temperature can also easily cause the expansion of TSV metal, causing stress deformation of the silicon substrate and dielectric layer, affecting component performance. Summary of the invention

[0004] Based on this, it is necessary to provide a semiconductor structure and a preparation method thereof to solve the problems of high heat generation and poor heat dissipation caused by chip stacking.

[0005] The present application provides a method for preparing a semiconductor structure, comprising: providing a substrate, wherein the substrate comprises a substrate and a first dielectric layer located on the substrate; forming a through silicon via in the substrate, wherein the through silicon via penetrates the first dielectric layer and extends into the substrate, and the depth of the through silicon via is less than the thickness of the substrate; forming a conductive structure in the through silicon via; forming a filling hole in the first dielectric layer and the substrate, wherein the filling hole surrounds the conductive structure and exposes a side wall of the conductive structure and a portion of the substrate, and the side wall of the filling hole is step-shaped; and forming a heat conductive structure in the filling hole.

[0006] The method for preparing the semiconductor structure is to prepare the sidewall of the filling hole in a step shape so that the thermal conductive structure formed in the filling hole is also in a step shape. The step-shaped thermal conductive structure is conducive to the upward diffusion of heat from the conductive structure, avoiding heat accumulation causing excessive temperature of the device and affecting the component characteristics of the active area in the semiconductor structure. By improving the heat dissipation capacity of the through silicon via structure, the reliability and stability of the through silicon via structure can be improved.

[0007] In one embodiment, the conductive structure includes a metal barrier layer and a conductive layer, and before forming the conductive structure in the silicon via, the steps further include: forming a second dielectric layer on the sidewall and bottom of the silicon via; and forming a first metal layer on the surface of the second dielectric layer.

[0008] In one embodiment, forming a filling hole in the first dielectric layer and the substrate includes: etching the first dielectric layer to form a filling through hole in the first dielectric layer; removing a portion of the second dielectric layer so that the upper surface of the retained second dielectric layer is lower than the upper surface of the substrate to form a filling gap in the substrate, and the filling gap and the filling through hole together constitute the filling hole.

[0009] In one embodiment, the diameter of the filling hole increases in a step-like manner from the bottom to the top.

[0010] In one embodiment, forming the heat-conducting structure in the filling hole includes: filling the filling hole with a heat-conducting metal as the heat-conducting structure, and the heat-conducting structure fills up the filling hole.

[0011] In one embodiment, the substrate comprises a silicon substrate, and the forming of the heat-conducting structure in the filling hole further comprises: annealing the obtained heat-conducting structure, wherein the heat-conducting structure reacts with the substrate to form a metal silicide layer.

[0012] In one embodiment, the second dielectric layer includes a silicon dioxide layer; the first metal layer includes a cobalt layer, an aluminum layer, a titanium nitride layer or a ruthenium layer; the metal barrier layer includes a tantalum layer or a tantalum nitride layer; and the thermally conductive metal includes tungsten, silver, platinum, aluminum, nickel, ruthenium or cobalt.

[0013] In one embodiment, after forming a filling hole in the first dielectric layer and before forming a thermal conductive structure in the filling hole, the method further includes: performing ion bombardment on the exposed substrate to form a loose area in the substrate, wherein the loose area surrounds the conductive structure.

[0014] The present application also provides a semiconductor structure, comprising: a substrate, the substrate comprising a substrate and a first dielectric layer located on the upper surface of the substrate; a conductive structure, penetrating the first dielectric layer and extending into the substrate, the depth of the conductive structure being less than the thickness of the substrate; a thermal conductive structure, located in the substrate and surrounding the conductive structure, the sidewalls of the thermal conductive structure being step-shaped.

[0015] In one embodiment, the semiconductor structure further includes: a first metal layer located on the sidewall and bottom of the conductive structure; and a second dielectric layer located in the substrate and covering the bottom and part of the sidewall of the first metal layer.

[0016] In one of the embodiments, the conductive structure includes a metal barrier layer and a conductive layer; the metal barrier layer is located between the conductive layer and the first metal layer.

[0017] In one embodiment, the diameter of the heat-conducting structure increases in a step-like manner from the bottom to the top.

[0018] In one embodiment, the thermally conductive structure comprises a thermally conductive metal.

[0019] In one embodiment, the substrate includes a porous region, which is located in the substrate and surrounds the conductive structure.

[0020] In one embodiment, the substrate includes a silicon substrate, the semiconductor structure further includes a metal silicide layer, and the metal silicide layer is located between the heat conductive structure and the loose region.

[0021] The heat-conducting structure in the semiconductor structure is surrounded by the conductive structure, and the sidewall of the heat-conducting structure is in a step-like shape, thereby effectively improving the heat dissipation performance of the conductive structure and improving the reliability and stability of the conductive structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 This is a flow chart of a method for preparing a semiconductor structure in one embodiment of the present application.

[0023] Figure 2 Schematic diagram of the cross-sectional structure of a semiconductor structure obtained after forming a through silicon via in a substrate in one embodiment of the present application.

[0024] Figure 3 Schematic diagram of the cross-sectional structure of a semiconductor structure obtained after forming a second dielectric layer in a through silicon via in one embodiment of the present application.

[0025] Figure 4 Schematic diagram of the cross-sectional structure of a semiconductor structure obtained after forming a first metal layer on the surface of the second dielectric layer in one embodiment of the present application.

[0026] Figure 5 It is a schematic cross-sectional structural diagram of a semiconductor structure obtained after a metal barrier layer is formed on the surface of the first metal layer in one embodiment of the present application.

[0027] Figure 6 It is a schematic diagram of the cross-sectional structure of a semiconductor structure obtained after forming a conductive layer in one embodiment of the present application.

[0028] Figures 7 to 13 Schematic diagram of the cross-sectional structure of the step of forming a filled through hole in the first dielectric layer in one embodiment of the present application.

[0029] Fig.14 It is a schematic diagram of the cross-sectional structure of a semiconductor structure obtained after forming a filling gap in a substrate in one embodiment of the present application.

[0030] Fig.15It is a schematic diagram of the cross-sectional structure of a semiconductor structure obtained after forming a heat-conducting structure in one embodiment of the present application.

[0031] Fig.16 It is a schematic diagram of the cross-sectional structure of a semiconductor structure obtained after a loose region is formed in a substrate in one embodiment of the present application.

[0032] Fig.17 It is a schematic cross-sectional structural diagram of a semiconductor structure obtained after forming a heat-conducting structure in another embodiment of the present application.

[0033] Explanation of the accompanying drawings: 11, base; 111, first dielectric layer; 112, substrate; 12, through silicon via; 13, second dielectric layer; 14, first metal layer; 15, conductive structure; 151, metal barrier layer; 152, conductive layer; 16, photoresist layer; 17, filling hole; 171, filling through hole; 172, filling gap; 18, thermal conductive structure; 19, loose area. DETAILED DESCRIPTION

[0034] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. Preferred embodiments of the present invention are provided in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present invention more thorough and comprehensive.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0036] When describing positional relationships, unless otherwise specified, when an element such as a layer, film, or substrate is referred to as being "on" another film layer, it can be directly on the other film layer or there can be an intermediate film layer. Further, when a layer is referred to as being "under" another layer, it can be directly below or there can be one or more intermediate layers. It is also understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there can be one or more intermediate layers.

[0037] In the case of using “including”, “having”, and “comprising” described herein, another component may be added unless a clear limiting term such as “only”, “consisting of”, etc. is used. Unless mentioned otherwise, a term in the singular form may include a plural form and should not be understood as being one in number.

[0038] An embodiment of the present application provides a method for preparing a semiconductor structure, such as Figure 1 As shown, including:

[0039] S10: Providing a substrate, the substrate comprising a substrate and a first dielectric layer located on the substrate.

[0040] S20: forming a through silicon via in the substrate, wherein the through silicon via penetrates the first dielectric layer and extends into the substrate, and a depth of the through silicon via is less than a thickness of the substrate.

[0041] S30: forming a conductive structure in the through silicon via.

[0042] S40: forming a filling hole in the first dielectric layer and the substrate, wherein the filling hole surrounds the conductive structure and exposes a side wall of the conductive structure and a portion of the substrate, and the side wall of the filling hole is in a step shape.

[0043] S50: forming a heat-conducting structure in the filling hole.

[0044] The method for preparing the semiconductor structure is to prepare the sidewall of the filling hole in a step shape so that the thermal conductive structure formed in the filling hole is also in a step shape. The step-shaped thermal conductive structure is conducive to the upward diffusion of heat from the conductive structure, avoiding heat accumulation causing excessive temperature of the device and affecting the component characteristics of the active area in the semiconductor structure. By improving the heat dissipation capacity of the through silicon via structure, the reliability and stability of the through silicon via structure can be improved.

[0045] Wherein, in step S10, the material of the substrate may be silicon, silicon carbide, silicon nitride, silicon on insulator, stacked silicon on insulator, stacked silicon germanium on insulator, silicon germanium on insulator or germanium on insulator, etc., and the material of the first dielectric layer may be at least one of silicon dioxide, silicon oxynitride, silicon nitride and low dielectric constant (Low-k) dielectric. Wherein, the low dielectric constant dielectric material may be a hydrogen silicate or a porous silicate. In the embodiment of the present application, the first dielectric layer may be a silicon dioxide layer. A shallow trench isolation structure and an active area may be provided on the upper surface of the substrate.

[0046] In step S20, a cross-sectional view of the semiconductor structure obtained after forming the through silicon via 12 in the substrate 11 is as shown in FIG. Figure 2 As shown, the through silicon via 12 penetrates the first dielectric layer 111 and partially extends into the substrate 112. The through silicon via 12 does not penetrate the substrate 112, so the depth of the through silicon via 12 is less than the thickness of the substrate 11.

[0047] In one embodiment, after forming the TSV 12 in the substrate 11 , it is necessary to first form a second dielectric layer 13 and a first metal layer 14 in the TSV 12 , and then form a conductive structure 15 in the TSV 12 .

[0048] Specifically, Figure 3 As shown, a second dielectric layer 13 is formed on the sidewall and bottom of the through silicon via 12. The material of the second dielectric layer 13 can be at least one of a silicon dioxide layer, silicon oxynitride, silicon nitride and a low dielectric constant (Low-k) dielectric. Among them, the low dielectric constant dielectric material can be a hydrogen-containing silicate or a porous silicate. As an example, a silicon oxide layer can be deposited on the sidewall and bottom of the through silicon via 12 by a chemical vapor deposition process (CVD) or an atomic layer deposition process (ALD) as the second dielectric layer 13. Figure 4 The cross-sectional structure schematic diagram of the semiconductor structure obtained after forming the first metal layer 14 on the surface of the second dielectric layer 13 is shown. The first metal layer 14 can be a cobalt layer, an aluminum layer, a titanium nitride layer or a ruthenium layer.

[0049] In step S30, a conductive structure 15 is formed in the through silicon via 12, wherein the conductive structure 15 includes a metal barrier layer 151 and a conductive layer 152. Figure 5 Specifically, a metal barrier layer 151 may be deposited on the surface of the first metal layer 14. The metal barrier layer 151 may be a tantalum layer or a tantalum nitride layer. Figure 5 Based on the structure shown in FIG. 1 , a conductive layer 152 is formed in the through silicon via 12. Specifically, a copper seed layer can be deposited on the surface of the metal barrier layer 151, and then copper is deposited in the through silicon via 12 using an electroplating process to fill the through silicon via 12 so that the copper layer is flush with the upper surface of the first dielectric layer 111. A schematic diagram of the cross-sectional structure of the semiconductor structure obtained after forming the conductive structure 15 in the through silicon via 12 is shown in FIG. Figure 6 shown.

[0050] In step S40 , a filling hole 17 is formed in the first dielectric layer 111 and the substrate 112 . The filling hole 17 surrounds the conductive structure 15 and exposes the sidewall of the conductive structure 15 and a portion of the substrate 112 . The sidewall of the filling hole 17 is stepped.

[0051] Specifically, the step of forming the filling hole 17 in the first dielectric layer 111 and the substrate 112 includes:

[0052] S41 : etching the first dielectric layer 111 to form a filling through hole 171 in the first dielectric layer 111 .

[0053] S42 : removing a portion of the second dielectric layer 13 so that the upper surface of the remaining second dielectric layer 13 is lower than the upper surface of the substrate 112 , so as to form a filling gap 172 in the substrate 112 . The filling gap 172 and the filling through hole 171 together constitute a filling hole 17 .

[0054] The specific steps of forming the filling through hole 171 in S41 can be referred to Figures 7 to 13By performing multiple photolithography processes on the first dielectric layer 111, a Fig.13 Specifically, first, Figure 6 A photoresist layer 16 is formed on the upper surface of the semiconductor structure. Figure 7 Then, after exposure and development, a portion of the upper surface of the first dielectric layer 111 is exposed, that is, the portion to be etched and removed, such as Figure 8 As shown; after the etching process, part of the first dielectric layer 111 is removed, and the photoresist is removed by cleaning, the Fig. 9 In the semiconductor structure shown in FIG. 1 , a portion of the first dielectric layer 111 is removed by dry etching, and the etching gas may include fluorine-based gases such as sulfur hexafluoride and carbon tetrafluoride. Further, in order to form a complete step-shaped filled through hole 171 structure, processes such as coating photoresist, exposure, development, etching, and cleaning may be performed again. Figures 10 to 12 As shown, Fig. 9 The semiconductor structure shown is processed to obtain Fig.12 The semiconductor structure shown; repeat Figure 10-12 By using the process in the embodiment, a step-shaped filling through hole 171 can be formed in the first dielectric layer 111, such as Fig.13 shown.

[0055] In order to further improve the heat dissipation capability of the through silicon via 12 structure, Fig.13 Based on the semiconductor structure shown in FIG. 1 , a portion of the second dielectric layer 13 is removed so that the upper surface of the second dielectric layer 13 is lower than the upper surface of the substrate 112, thereby forming a filling gap 172 in the substrate 112. Fig.14 The filling through hole 171 and the filling gap 172 together form a filling hole 17, and the diameter of the filling hole 17 increases in a step-like manner from the bottom to the top.

[0056] In step S50, a heat-conducting structure 18 is formed in the filling hole 17. Specifically, a heat-conducting metal can be filled in the filling hole 17 as the heat-conducting structure 18, and the heat-conducting structure 18 fills the filling hole 17. Fig.15 As shown. The thermally conductive metal may be tungsten, silver, platinum, aluminum, nickel, ruthenium or cobalt. As an example, the thermally conductive metal may be in granular form to facilitate heat dissipation. By forming a stepped thermally conductive structure 18 around the through silicon via 12 structure, and the thermally conductive structure 18 is narrow at the bottom and wide at the top, it is beneficial for heat to be dissipated upward, thereby preventing the heat from being unable to dissipate in time and affecting the components around the bottom of the through silicon via 12. At the same time, since the bottom diameter of the thermally conductive structure 18 is small and the top diameter is large, the area occupied by the active area can be reduced, the crowding of the devices in the active area can be alleviated, and the heat dissipation efficiency can be increased.

[0057] In one embodiment, the substrate 112 may be a silicon substrate. After the heat-conducting structure 18 is formed in the filling hole 17, the obtained heat-conducting structure 18 is annealed, and the heat-conducting structure 18 reacts with the substrate 112 to form a metal silicide layer. Metal silicide can effectively solve the problem of heat dissipation difficulties in the TSV structure. Metal silicide has good thermal conductivity. When the heat-conducting metal conducts the heat from the conductive structure 15 to the substrate 112, the metal silicide will not block the heat, but can quickly conduct the heat to avoid heat accumulation on the substrate 112 and increase the base temperature, affecting the working performance of the active area device.

[0058] In one embodiment, before forming the thermal conductive structure 18 in the filling hole 17, the following step is further included: ion bombarding the exposed substrate 112 to form a loose region 19 in the substrate 112, and the loose region 19 surrounds the conductive structure 15. As an example, the substrate 112 exposed by the filling hole 17 can be bombarded with Ar ions to form the loose region 19. Specifically, the RF power can be controlled at 30W to 100W, for example, 40W, 50W, 60W, 70W, 80W and 90W, the Ar gas flow rate is 10sccm-150sccm, for example, 30sccm, 50sccm, 80sccm, 100sccm and 120sccm, and the ion bombardment time can be 10 seconds to 200 seconds, for example, 30 seconds, 50 seconds, 80 seconds, 100 seconds, 150 seconds and 180 seconds. Optionally, after forming the filling hole 17, the substrate 112 may be ion bombarded after the residual photoresist is removed, or the substrate 112 may be ion bombarded before the residual photoresist is removed. A schematic diagram of the cross-sectional structure of the semiconductor structure obtained after ion bombardment is shown in FIG. Fig.16 After forming the loose area 19, the filling hole 17 is filled with a heat-conducting metal to form a heat-conducting structure 18, and the Fig.17 The semiconductor structure shown.

[0059] The heat dissipation capacity of the semiconductor structure can be further improved by forming the loose region 19 by ion bombarding the substrate 112. This is because, after the heat conducting structure 18 conducts heat to the substrate 112, the loose region 19 in the substrate 112 can accelerate the heat dissipation and avoid heat accumulation.

[0060] An embodiment of the present application also provides a semiconductor structure, such as Fig.15 As shown, it includes: a base 11, the base 11 includes a substrate 112 and a first dielectric layer 111 located on the upper surface of the substrate 112; a conductive structure 15, which penetrates the first dielectric layer 111 and extends into the substrate 112, and the depth of the conductive structure 15 is less than the thickness of the base 11; a thermal conductive structure 18, which is located in the base 11 and surrounds the conductive structure 15, and the side wall of the thermal conductive structure 18 is stepped.

[0061] The substrate 11 may be a silicon substrate 11, and the first dielectric layer 111 may be a silicon dioxide layer. The conductive structure 15 may be located in the through silicon via 12 to achieve vertical electrical interconnection of multi-layer chips. Since the multi-layer chips are stacked, the power consumption density may increase sharply, causing the temperature of the conductive structure 15 to increase sharply, which may affect the reliability and stability of the conductive structure 15 and the electronic device. By providing a thermal conductive structure 18 with a stepped side wall around the conductive structure 15, the speed of heat dissipation upward may be increased, thereby increasing the heat dissipation efficiency.

[0062] In one embodiment, the semiconductor structure further includes a first metal layer 14 and a second dielectric layer 13. Fig.15 The first metal layer 14 is located on the sidewall and bottom of the conductive structure 15 , and the first metal layer 14 is arranged on the sidewall and bottom of the conductive structure 15 . The second dielectric layer 13 is located in the substrate 112 , covering the bottom and part of the sidewall of the first metal layer 14 .

[0063] In one embodiment, the conductive structure 15 includes a metal barrier layer 151 and a conductive layer 152, wherein the metal barrier layer 151 is located between the conductive layer 152 and the first metal layer 14. The metal barrier layer 151 may be a tantalum layer or a tantalum nitride layer, and the conductive layer 152 may be a copper layer.

[0064] In one embodiment, the diameter of the heat conducting structure 18 increases in a step-like manner from the bottom to the top. Fig.15 As shown, by designing the heat-conducting structure 18 to have a diameter that increases in a step-like manner from the bottom to the top, the area occupied by the heat dissipation structure in the active area of ​​the substrate 112 can be reduced, thereby avoiding aggravating the crowding of active devices. At the same time, since heat is generally dissipated upward, by designing the heat dissipation structure to be narrow at the bottom and wide at the top, it is beneficial to accelerate the upward dissipation of heat, avoid heat accumulation around the bottom of the conductive structure 15, and cause the temperature of the substrate 112 to rise, thereby affecting the performance of the electronic devices in the active area.

[0065] In one embodiment, the heat-conducting structure 18 includes a heat-conducting metal, for example, the heat-conducting metal may be tungsten, silver, platinum, aluminum, nickel, ruthenium or cobalt. As an example, the heat-conducting metal may be filled in the filling hole 17 in a granular form. By designing the heat-conducting structure 18 to be granular, the excellent heat-conducting property of the heat-conducting metal may be fully utilized to conduct the heat away in time, and the gaps between the particles may be utilized to facilitate heat dissipation.

[0066] In one embodiment, the substrate 112 includes a porous region 19. Fig.17As shown, the loose region 19 is located in the substrate 112 and surrounds the conductive structure 15. By providing the loose region 19 in the substrate 112, the heat conducted by the thermal conductive structure 18 can be further dissipated, thereby preventing the heat from accumulating in the substrate 112 and increasing the temperature of the substrate 112, thereby affecting the working performance of the active device.

[0067] In one embodiment, the substrate 112 includes a silicon substrate, and the semiconductor structure further includes a metal silicide layer, which is located between the heat-conducting structure 18 and the loose region 19. The metal silicide is similar to the heat-conducting metal and also has high thermal conductivity, and can accelerate the conduction and dissipation of the heat generated by the conductive structure 15 together with the heat-conducting structure 18, thereby reducing heat accumulation.

[0068] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0069] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a substrate and a first dielectric layer located on the substrate; forming a through silicon via in the substrate, wherein the through silicon via penetrates the first dielectric layer and extends into the substrate, and the depth of the through silicon via is less than the thickness of the substrate; forming a conductive structure in the through silicon via; forming a filling hole in the first dielectric layer and the substrate, the filling hole surrounds the conductive structure and exposes the sidewall of the conductive structure and a portion of the substrate, and the sidewall of the filling hole is in a step shape; forming a heat-conducting structure in the filling hole; After forming a filling hole in the first dielectric layer and before forming a heat-conducting structure in the filling hole, the method further includes: Ion bombardment is performed on the exposed substrate to form a loose region in the substrate, wherein the loose region surrounds the conductive structure.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: The conductive structure includes a metal barrier layer and a conductive layer, and before forming the conductive structure in the through silicon via, the method further includes: forming a second dielectric layer on the sidewall and bottom of the through silicon via; A first metal layer is formed on the surface of the second dielectric layer.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that: The forming of the filling holes in the first dielectric layer and the substrate comprises: Etching the first dielectric layer to form a filled through hole in the first dielectric layer; A portion of the second dielectric layer is removed so that the upper surface of the remaining second dielectric layer is lower than the upper surface of the substrate, so as to form a filling gap in the substrate, wherein the filling gap and the filling through hole together constitute the filling hole.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that: The diameter of the filling hole increases in a step-like manner from the bottom to the top.

5. The method for preparing a semiconductor structure according to claim 3, characterized in that: The step of forming a heat-conducting structure in the filling hole comprises: A heat-conducting metal is filled in the filling hole as the heat-conducting structure, and the heat-conducting structure fills up the filling hole.

6. The method for preparing a semiconductor structure according to claim 5, characterized in that: The substrate comprises a silicon substrate, and the heat-conducting structure is formed in the filling hole, and further comprises: The obtained heat-conducting structure is subjected to annealing treatment, and the heat-conducting structure reacts with the substrate to form a metal silicide layer.

7. The method for preparing a semiconductor structure according to claim 5, characterized in that: The second dielectric layer includes a silicon dioxide layer; the first metal layer includes a cobalt layer, an aluminum layer, a titanium nitride layer or a ruthenium layer; the metal barrier layer includes a tantalum layer or a tantalum nitride layer; and the thermally conductive metal includes tungsten, silver, platinum, aluminum, nickel, ruthenium or cobalt.

8. A semiconductor structure, characterized in that: include: A substrate, comprising a substrate and a first dielectric layer located on an upper surface of the substrate; A conductive structure, penetrating the first dielectric layer and extending into the substrate, wherein the depth of the conductive structure is less than the thickness of the substrate; A heat-conducting structure, located in the substrate and surrounding the conductive structure, wherein a side wall of the heat-conducting structure is in a step shape; The substrate includes a porous area located in the substrate and surrounding the conductive structure.

9. The semiconductor structure according to claim 8, characterized in that: Also includes: A first metal layer, located on the sidewall and bottom of the conductive structure; The second dielectric layer is located in the substrate and covers the bottom and part of the side wall of the first metal layer.

10. The semiconductor structure according to claim 9, characterized in that: The conductive structure includes a metal barrier layer and a conductive layer; the metal barrier layer is located between the conductive layer and the first metal layer.

11. The semiconductor structure according to claim 8, characterized in that: The diameter of the heat-conducting structure increases in a step-like manner from the bottom to the top.

12. The semiconductor structure according to claim 8, characterized in that The heat-conducting structure includes a heat-conducting metal.

13. The semiconductor structure according to claim 8, characterized in that The substrate includes a silicon substrate, and the semiconductor structure further includes a metal silicide layer, wherein the metal silicide layer is located between the heat-conducting structure and the loose region.

Images