A high-precision delayed clock generation circuit and chip

Abstract

The present invention discloses a high-precision delayed clock generation circuit and chip. The delayed clock generation circuit includes a clock delay chain unit, a delayed clock output unit, an original clock output unit and a gating control unit. The external given clock signal port is connected to the input end of the clock delay chain unit and the original clock output unit; the multiple output ends of the clock delay chain unit are respectively connected to the multiple input ends of the delayed clock output unit, and the output end of the delayed clock output unit is connected to the first output end of the delayed clock generation circuit; the output end of the original clock output unit is connected to the second output end of the delayed clock generation circuit; the external system control signal port is connected to the input end of the gating control unit, and the output end of the gating control unit is connected to the control end of the delayed clock output unit and the original clock output unit. The delayed clock generation circuit realizes the generation and adjustable output of one or more delayed clock signals.

Description

Technical Field

[0001] The invention relates to a high-precision delayed clock generating circuit and also to an integrated circuit chip comprising the delayed clock generating circuit, belonging to the technical field of integrated circuits. Background Art

[0002] Clock synchronization refers to maintaining a certain strict and specific relationship between two or more clock signals in terms of frequency and phase. In digital communication systems, the role of clock synchronization is to control the clock frequencies of all switching devices and transmission devices in the digital communication network within a predetermined tolerance range, so that the digital streams passing through each node device in the network can be correctly and effectively transmitted and exchanged. Delayed clock refers to maintaining a certain equal delay time in phase between two or more clock signals with the same frequency. Usually, the requirements for clock signal accuracy in integrated circuits are very high to ensure high-quality communication in digital communication systems and high-precision PWM (pulse width modulation) drives in industrial control systems.

[0003] In the prior art, digitally controlled phase shifters are mainly composed of PIN diodes or ferrite devices or use phase-locked loop technology to adjust the frequency and phase of the clock signal to generate a delayed clock signal. They have the disadvantages of poor phase shifting accuracy, small number of phase shifts, and inflexible system adjustment methods.

[0004] In the Chinese invention patent application with application publication number CN 110034750A, a clock delay circuit is disclosed. The clock delay circuit comprises a latch, the output end of the latch provides the output clock signal; and a delay control circuit provides a third clock signal. The latch comprises a first input end for receiving the input clock signal and a second input end for receiving the third clock signal. The delay amount provided by the latch depends on the duty cycle of the third clock signal. Summary of the invention

[0005] The primary technical problem to be solved by the present invention is to provide a high-precision delayed clock generating circuit.

[0006] Another technical problem to be solved by the present invention is to provide an integrated circuit chip including the delayed clock generating circuit.

[0007] In order to achieve the above object, the present invention adopts the following technical solutions:

[0008] According to a first aspect of an embodiment of the present invention, a high-precision delayed clock generation circuit is provided, comprising a clock delay chain unit, a delayed clock output unit, an original clock output unit and a gating control unit; wherein,

[0009] The clock delay chain unit is used to generate a plurality of delayed clock signals with increasing delay times according to an external given clock signal, and output them to the delayed clock output unit;

[0010] The gating control unit is used to control the signal paths of the delayed clock output unit and the original clock output unit, and its output end is connected to the control end of the delayed clock output unit and the original clock output unit respectively;

[0011] The delayed clock output unit is used to provide an output path for the delayed clock signal generated by the clock delay chain unit, and its output end is connected to the first output end of the delayed clock generation circuit;

[0012] The original clock output unit is used to provide an output path for the given clock signal, and an output end of the original clock output unit is connected to the second output end of the delayed clock generating circuit.

[0013] Preferably, the clock delay chain unit is composed of a plurality of delay stages connected in series, each of which is composed of two or other even number of inverters connected in series and a tap output terminal; wherein,

[0014] The input end of the first delay stage is connected to the external given clock signal port, the output end of the first delay stage is connected to the tap output end of the first delay stage and the input end of the second delay stage; the output end of the second delay stage is connected to the tap output end of the second delay stage and the input end of the third delay stage, and so on, and multiple delay stages are connected in series in sequence.

[0015] Preferably, the delayed clock output unit is composed of a multi-stage data selector, each of which has two input terminals;

[0016] In the first-stage data selectors, two input terminals of each data selector are respectively connected to two delayed clock signal output terminals of the clock delay chain unit;

[0017] In the second-stage data selectors, two input terminals of each data selector are respectively connected to the output terminals of the two first-stage data selectors;

[0018] In the third-stage data selectors, two input terminals of each data selector are respectively connected to the output terminals of two second-stage data selectors;

[0019] By analogy, the final stage data selector is a data selector, whose output end is connected to the first output end of the delay clock generating circuit;

[0020] The control ends of all the data selectors are connected to the output end of the gating control unit.

[0021] Preferably, the original clock output unit is composed of data selectors of the same number as the delayed clock output unit, each level of data selectors is a data selector, and each data selector has two input terminals; wherein,

[0022] The two input ends of the first-level data selector are connected to the given clock signal port, the output end of the first-level data selector is connected to the two input ends of the second-level data selector, the output end of the second-level data selector is connected to the two input ends of the third-level data selector, and so on. The output end of the final-level data selector is connected to the second output end of the delayed clock generating circuit, and the control ends of all the data selectors are connected to the output end of the selection control unit.

[0023] Preferably, the delayed clock output unit is formed by a first-level data selector having a plurality of input terminals;

[0024] The multiple input ends of the data selector are respectively connected to the multiple delayed clock signal output ends of the clock delay chain unit, the control end of the data selector is connected to the output end of the selection control unit, and the output end of the data selector is connected to the first output end of the delayed clock generating circuit.

[0025] Preferably, the original clock output unit is composed of a first-level data selector having two input terminals; wherein the two input terminals of the data selector are connected to an external given clock signal port, the control terminal of the data selector is connected to the output terminal of the selection control unit, and the output terminal of the data selector is connected to the second output terminal of the delayed clock generating circuit.

[0026] Preferably, when the number of the delay stages in the clock delay chain unit is increased, the accuracy of the delayed clock signal output by the clock delay chain unit is improved accordingly.

[0027] Preferably, when the even number of inverters connected in series in the delay stage is reduced, the accuracy of the delayed clock signal output by the clock delay chain unit is improved accordingly.

[0028] Preferably, when a plurality of the delay clock generating circuits are connected in cascade, the cascade-connected delay clock generating circuits can simultaneously generate and output a plurality of delay clock signals; wherein,

[0029] The first output end of the delay clock generating circuit of the previous stage is connected to the input end of the delay clock generating circuit of the next stage, and the second output end of the delay clock generating circuit of each stage serves as the delayed clock signal output end.

[0030] According to a second aspect of an embodiment of the present invention, there is provided an integrated circuit chip, comprising the above-mentioned high-precision delayed clock generating circuit.

[0031] Compared with the prior art, the high-precision delayed clock generation circuit provided by the present invention realizes the generation and adjustable output of one or more delayed clock signals by adopting the technical solution of using inverters to form a clock delay chain and using a data selector to form a clock output. The delayed clock generation circuit has the beneficial effects of adjustable delay time, high precision, flexible system adjustment, ingenious and reasonable structural design, and low design cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A schematic diagram of the structure of a high-precision delayed clock generation circuit provided by the present invention;

[0033] Figure 2 A circuit schematic diagram of a clock delay chain unit in the first embodiment of the present invention;

[0034] Figure 3 A timing comparison diagram of a clock delay chain unit in the first embodiment of the present invention;

[0035] Figure 4 A circuit schematic diagram of a delayed clock output unit in the first embodiment of the present invention;

[0036] Figure 5 A schematic diagram of the delay time of the delayed clock output unit outputting the delayed clock signal in the first embodiment of the present invention;

[0037] Figure 6 This is a circuit schematic diagram of the original clock output unit in the first embodiment of the present invention;

[0038] Figure 7 A circuit schematic diagram of a delayed clock output unit in a second embodiment of the present invention;

[0039] Figure 8 A circuit schematic diagram of an original clock output unit in a second embodiment of the present invention;

[0040] Fig. 9 A timing comparison diagram of the original clock output unit in the second embodiment of the present invention;

[0041] Fig.10 Schematic diagram of the structure of a high-precision delayed clock generation circuit with multiple delayed clock outputs in an embodiment of the present invention. DETAILED DESCRIPTION

[0042] The technical solution of the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0043] like Figure 1 As shown, a high-precision delayed clock generation circuit provided by the present invention includes a clock delay chain unit, a delayed clock output unit, an original clock output unit and a gating control unit. Among them, the external given clock signal port is connected to the input end of the clock delay chain unit and the original clock output unit; the multiple output ends of the clock delay chain unit are respectively connected to the multiple input ends of the delayed clock output unit, and the output end of the delayed clock output unit is connected to the first output end of the delayed clock generation circuit; the output end of the original clock output unit is connected to the second output end of the delayed clock generation circuit; the external system control signal port is connected to the input end of the gating control unit, and the output end of the gating control unit is connected to the control end of the delayed clock output unit and the original clock output unit.

[0044] The clock delay chain unit is used to generate a plurality of delayed clock signals with increasing delay times corresponding to the external given clock signal, and output them to the delayed clock output unit. The clock delay chain unit is composed of a plurality of delay stages connected in series in sequence, and each delay stage is composed of two or other even number of inverters connected in series and a tap output terminal. Among them, the input terminal of the first delay stage is connected to the external given clock signal port, the output terminal of the first delay stage is connected to the tap output terminal of the first delay stage and the input terminal of the second delay stage; the output terminal of the second delay stage is connected to the tap output terminal of the second delay stage and the input terminal of the third delay stage, and so on, and the plurality of delay stages are connected in series in sequence.

[0045] The delayed clock output unit is used to provide an output path for multiple delayed clock signals output by the clock delay chain unit. The delayed clock output unit is controlled by the selection control unit to connect the output path of a delayed clock signal according to system requirements and output a delayed clock signal. The delayed clock output unit is composed of one or more stages of data selectors (MUX).

[0046] The original clock output unit is used to provide an output path for a given clock signal. The output path is controlled by the gating control unit according to system requirements to output an original clock signal. The original clock output unit is composed of one or more stages of data selectors.

[0047] The gating control unit is used to control the signal path of the delayed clock output unit and the original clock output unit according to the system delay time requirement, and output the corresponding delayed clock signal and the original clock signal. The gating control unit is composed of a MUX decoding logic circuit.

[0048] In the first embodiment of the present invention, Figure 2As shown, the clock delay chain unit is composed of 14 delay stages connected in series in sequence, the input end of the first delay stage is connected to the external given clock signal port, and a tap output end is led out at the end of each delay stage, including the tap output end connected to the input end of the external given clock signal, and the clock delay chain unit has a total of 15 tap output ends. Among them, each delay stage includes two inverters, the input end of the first inverter is connected to the output end of the previous delay stage, the output end of the first inverter is connected to the input end of the second inverter, and the output end of the second inverter is connected to the tap output end of this stage and the input end of the next delay stage.

[0049] Since the delay time caused by the inverter outputting high level and low level is not completely equal when the clock pulse signal passes through the inverter, each delay stage is composed of two or other even number of inverters connected in series, which can effectively solve the problem of unequal delay time while ensuring that the delayed clock signal is consistent with the given clock signal pulse direction. Assuming that the delay time generated by the clock pulse signal passing through each delay stage is Δt, then relative to the given clock signal at the input end of the clock delay chain unit, the delay time of the clock signal at the first tap output end is Δt, the delay time of the clock signal at the second tap output end is 2Δt, and the delay time of the clock signal at the third tap output end is 3Δt, and so on. Figure 3 As shown, 14 delayed clock signals with increasing delay times can be obtained.

[0050] It should be noted that the number of delay stages connected in series in the clock delay chain unit is not limited to 14, and the number of inverters included in the delay stage is not limited to 2. In other embodiments of the present invention, the number of delay stages and / or the even number of inverters in the delay stage can be increased or decreased according to the different accuracy requirements of the system for the delayed clock signal. When the number of delay stages in the clock delay chain unit increases and the even number of inverters in the delay stage decreases, the delay time accuracy of the output delayed clock signal increases.

[0051] In the first embodiment of the present invention, Figure 4 As shown, the delayed clock output unit is composed of a first-level multi-terminal data selector (MUX). Among them, the multiple input terminals of the data selector are respectively connected to the multiple delayed clock signal output terminals of the clock delay chain unit, the control terminal of the data selector is connected to the output terminal of the selection control unit, and the output terminal of the data selector is connected to the first output terminal of the delayed clock generation circuit. Assume that the multi-terminal data selector has 15 input terminals, namely, terminal A, terminal B, terminal C...terminal O, and the 15 input terminals are respectively connected to the 15 tap output terminals of the clock delay chain unit, and the output terminal of the multi-terminal data selector is the Y terminal.

[0052] When the delayed clock generating circuit outputs a delayed clock signal according to system requirements, assuming that a second delayed clock signal needs to be output, the tap output end of the delayed clock signal is connected to the input end C of the multi-terminal data selector. At this time, the selection control unit sends a corresponding control signal to control the multi-terminal data selector to connect the input end C with the output end Y, thereby completing the output of the second delayed clock signal.

[0053] In the process of the delayed clock output unit selecting a certain path to complete the output of the delayed clock signal, since the multi-terminal data selector is a device formed by a synthesis tool, the delayed clock signal will have a second time delay from the input end to the output end, and the second time delay generated from each input end to the output end is uncertain and different. Assume that the time delay from input end A to output end Y is Δt0, the time delay from input end B to output end Y is Δt1, the time delay from input end C to output end Y is Δt2, and so on. The time delay from input end O to output end Y is Δt 14 , then relative to the given clock signal at the input end of the delayed clock generating circuit, at the first output end of the delayed clock generating circuit, the delay time of the given clock signal is Δt0, the delay time of the first delayed clock signal is (Δt+Δt1), the delay time of the second delayed clock signal is (2Δt+Δt2), the delay time of the third delayed clock signal is (3Δt+Δt3), and so on, the delay time of the fourteenth delayed clock signal is (14Δt+Δt 14 ). Taking the output of the second delayed signal as an example, Figure 5 As shown, at the first output terminal of the delayed clock generating circuit, the delay time of the second delayed clock signal includes two parts: the delay time 2Δt generated by the delay chain and the delay time Δt2 generated by the data selector. Generally, the delay time Δt of the delay stage composed of two inverters is about 0.68ns, and the delay time range from each input terminal to the output terminal of the multi-terminal data selector is about 0.006 to 0.025ns.

[0054] From the above analysis, it can be seen that when the delayed clock output unit is composed of a first-level multi-terminal data selector, at the first output end of the delayed clock generating circuit, each delayed clock signal produces a second time delay, and the second time delay is uncertain and different. Therefore, the accuracy of the output delayed clock signal is affected to some extent.

[0055] In the first embodiment of the present invention, Figure 6 As shown, the original clock output unit is composed of a first-level two-terminal data selector, wherein both input ends of the data selector are connected to the external given clock signal port, the control end of the data selector is connected to the output end of the gating control unit, and the output end of the data selector is connected to the second output end of the delayed clock generation circuit.

[0056] When the delayed clock generation circuit outputs the original clock signal according to system requirements, the selection control unit sends a corresponding control signal to control the data selector of the original clock output unit to connect the input terminal A or the input terminal B with the output terminal Y to complete the output of the original delayed clock signal.

[0057] In the original clock output unit, the original delayed clock signal will also generate a second time delay from the input terminal A or input terminal B of the two-terminal data selector to the output terminal Y. Usually, the second time delay generated by the two input terminals is about 0.003-0.004ns.

[0058] The number of data selectors in the original clock output unit is selected to be the same as the number of data selectors in the delayed clock output unit, so that the delayed clock signal output by the delayed clock generation circuit and the original clock signal can offset and remove the secondary delay time or part of the secondary delay time generated by the data selector in the next-level application circuit.

[0059] In a second embodiment of the present invention, Figure 7 As shown, the delayed clock output unit is composed of a multi-stage two-terminal data selector. Among them, the two input ends of each data selector in the first stage are respectively connected to the two delayed clock signal output ends of the clock delay chain unit, the two input ends of each data selector in the second stage are respectively connected to the output ends of the two first-stage data selectors, and the two input ends of each data selector in the third stage are respectively connected to the output ends of the two second-stage data selectors, and so on. The last stage is a data selector, and its output end is connected to the first output end of the delayed clock generation circuit; the control ends of all data selectors are connected to the output end of the gating control unit. Assuming that the clock delay chain unit has 15 delayed clock signal output ends, the number of the first-stage two-terminal data selectors is 8, the number of the second-stage two-terminal data selectors is 4, the number of the third-stage two-terminal data selectors is 2, and the fourth stage is the last stage, and the number of its two-terminal data selectors is 1.

[0060] When the delayed clock generating circuit outputs a delayed clock signal according to system requirements, assuming that a second delayed clock signal needs to be output, the tap output end of the delayed clock signal is connected to the input end A of the second data selector in the first stage. At this time, the selection control unit sends a corresponding control signal to control the corresponding paths of the data selectors at each stage to be closed. The output path of the second delayed clock signal is from the A end to the Y end of the first-stage data selector, from the B end to the Y end of the second-stage data selector, from the A end to the Y end of the third-stage data selector, and from the A end to the Y end of the fourth-stage data selector, and finally the output of the second delayed clock signal is completed.

[0061] When the delayed clock output unit selects a certain path to complete the output of the delayed clock signal, the delayed clock signal will generate a second time delay from the input terminal A or input terminal B of the two-terminal data selector to the output terminal Y. Figure 6 As shown, assuming that the time delay from input terminal A to output terminal Y is Δta, and the time delay from input terminal B to output terminal Y is Δtb, the second delay time generated by each delayed clock signal passing through the delayed clock output unit of the four-stage MUX structure is as follows:

[0062] The delay time of a given clock signal is 4Δta; the delay time of the first, second, fourth, and eighth delayed clock signals is (3Δta+Δtb); the delay time of the third, fifth, sixth, ninth, tenth, and twelfth delayed clock signals is (2Δta+2Δtb); the delay time of the seventh, eleventh, and thirteenth delayed clock signals is (Δta+3Δtb); the delay time of the fourteenth delayed clock signal is 4Δtb. Generally, the time delay Δta from the input terminal A to the output terminal Y of the two-terminal data selector is about 0.003ns (nanoseconds), and the time delay Δtb from the input terminal B to the output terminal Y is about 0.004ns. Then, the second delay time generated by the above-mentioned delayed clock signals through the delayed clock output unit is about in the range of 0.012ns to 0.016ns, the maximum error between the second delay times generated by the head-end and the end-end paths is 0.004ns, and the maximum error between the second delay times generated by the intermediate paths is 0.002ns.

[0063] From the above analysis, it can be seen that when the delayed clock output unit is composed of a multi-stage two-terminal data selector, at the first output end of the delayed clock generation circuit, each delayed clock signal generates a second time delay, but the error between the second time delays generated by each path is very small. Therefore, the accuracy of the output delayed clock signal is less affected.

[0064] In a second embodiment of the present invention, Figure 8 As shown, the original clock output unit is composed of two-terminal data selectors of the same number of stages as the delayed clock output unit, and each stage includes a data selector. Among them, the two input ends of the first-stage data selector are connected to the given clock signal port, the output end of the first-stage data selector is connected to the two input ends of the second-stage data selector, the output end of the second-stage data selector is connected to the two input ends of the third-stage data selector, and so on. The output end of the final-stage data selector is connected to the second output end of the delayed clock generation circuit, and the control ends of all data selectors are connected to the output end of the gating control unit.

[0065] When the delayed clock output unit is composed of four-stage two-terminal data selectors, the original clock output unit is also composed of four two-terminal data selectors connected in series in sequence, and the number of stages of the data selectors is the same as that of the delayed clock output unit.

[0066] When the delayed clock generating circuit outputs a delayed clock signal according to system requirements, it is assumed that a second delayed clock signal needs to be output, such as Figure 7 In the delayed clock output unit shown, the output path of the second delayed clock signal is from the A terminal to the Y terminal of the first-stage data selector, from the B terminal to the Y terminal of the second-stage data selector, from the A terminal to the Y terminal of the third-stage data selector, and from the A terminal to the Y terminal of the fourth-stage data selector, and finally the second delayed clock signal is output at the first output terminal of the delayed clock generation circuit. The delay time of the output second delayed clock signal is (2Δt+3Δta+Δtb), where 2Δt is generated by the clock delay chain unit, and (3Δta+Δtb) is the secondary delay time generated by the delayed clock output unit. At this time, the original clock output unit, under the control of the output control unit, follows the same output path as the second delayed clock signal in the delayed clock output unit, that is, the first-level data selector is from end A→end Y, the second-level data selector is from end B→end Y, the third-level data selector is from end A→end Y, and the fourth-level data selector is from end A→end Y, so that the given clock signal is output at the output end of the original clock output unit. The delay time of the output given clock signal is (3Δta+Δtb), which is the same as the secondary delay time generated when the second delayed clock signal is output by the delayed clock output unit.

[0067] like Fig. 9 As shown, the difference in delay time between the second delayed signal outputted from the first output terminal of the delayed clock generating circuit and the given clock signal outputted from the second output terminal of the delayed clock generating circuit is the delay time 2Δt generated by the clock delay chain unit, and the delay time is the delay time expected by the system. Therefore, in the second embodiment provided by the present invention, the original clock signal outputted by the original clock output unit and the delayed clock signal outputted by the delayed clock output unit are provided to the next-level application circuit together, which can offset and remove the secondary delay time of the delayed clock signal generated by the delayed clock output unit.

[0068] In the second embodiment of the present invention, the structures and working principles of the clock delay chain unit and the gating control unit are the same as those of the first embodiment, so they will not be described in detail.

[0069] The high-precision delayed clock generation circuit provided by the present invention can output multiple delayed clock signals with adjustable delay times at the same time through a cascade mode, and provide a group of delayed clock signals for high-precision PWM (pulse width modulation) drive of measurement, industrial control and other systems.

[0070] like Fig.10 As shown, when multiple delayed clock signals need to be output simultaneously, multiple high-precision delayed clock generation circuits can be used to achieve this through cascading. Among them, the input end of the first delayed clock generation circuit is connected to the external given clock signal port, and its second output end is used as the original clock output end, and the first output end is connected to the input end of the second delayed clock generation circuit; the second output end of the second delayed clock generation circuit is used as the delayed clock 1 output end, and the first output end is connected to the input end of the third delayed clock generation circuit; the second output end of the third delayed clock generation circuit is used as the delayed clock 2 output end, and the first output end is connected to the input end of the fourth delayed clock generation circuit; and so on, the second output end of the Nth delayed clock generation circuit is used as the delayed clock n-1 output end, and the first output end is used as the delayed clock n output end.

[0071] The embodiment of the present invention further provides an integrated circuit chip, which includes the above-mentioned high-precision delayed clock generation circuit, and is used in the integrated circuit to provide one or more delayed clock signals for the system. The specific structure of the high-precision delayed clock generation circuit in the integrated circuit chip will not be described in detail here.

[0072] In summary, compared with the prior art, the high-precision delayed clock generation circuit provided by the present invention realizes the generation and adjustable output of one or more delayed clock signals by adopting the technical solution of using inverters to form a clock delay chain and using a data selector to form a clock output. The delayed clock generation circuit has the beneficial effects of adjustable delay time, high precision, flexible system adjustment, ingenious and reasonable structural design, and low design cost.

[0073] The above is a detailed description of a high-precision delayed clock generation circuit and chip provided by the present invention. For those skilled in the art, any obvious changes made to it without departing from the essence of the present invention will fall within the protection scope of the patent right of the present invention.

Claims

1. A high-precision delayed clock generation circuit, characterized in that It includes a clock delay chain unit, a delayed clock output unit, an original clock output unit and a gating control unit; wherein, The clock delay chain unit is used to generate a plurality of delayed clock signals with increasing delay times according to an external given clock signal, and output them to the delayed clock output unit; The gating control unit is used to control the signal paths of the delayed clock output unit and the original clock output unit, and its output end is connected to the control end of the delayed clock output unit and the original clock output unit respectively; The delayed clock output unit is used to provide an output path for the delayed clock signal generated by the clock delay chain unit, and its output end is connected to the first output end of the delayed clock generation circuit; The original clock output unit is used to provide an output path for the given clock signal, and its output end is connected to the second output end of the delayed clock generating circuit; The number of selectors in the original clock output unit is the same as the number of selectors in the delayed clock output unit, so that the delayed clock signal and the original clock signal output by the delayed clock generation circuit offset the secondary delay time generated by the selector in the delay time of the delayed clock signal in the next-level application circuit, thereby improving the accuracy of the delayed clock signal.

2. The high-precision delayed clock generation circuit according to claim 1, characterized in that: The clock delay chain unit is composed of a plurality of delay stages connected in series, each of which is composed of two or other even number of inverters connected in series and a tap output terminal; wherein, The input end of the first delay stage is connected to the external given clock signal port, the output end of the first delay stage is connected to the tap output end of the first delay stage and the input end of the second delay stage; the output end of the second delay stage is connected to the tap output end of the second delay stage and the input end of the third delay stage, and so on, and multiple delay stages are connected in series in sequence.

3. The high-precision delayed clock generation circuit according to claim 1, wherein: The delayed clock output unit is composed of a multi-stage data selector, each of which has two input terminals; wherein, In the first-stage data selectors, two input terminals of each data selector are respectively connected to two delayed clock signal output terminals of the clock delay chain unit; In the second-stage data selectors, two input terminals of each data selector are respectively connected to the output terminals of the two first-stage data selectors; In the third-stage data selectors, two input terminals of each data selector are respectively connected to the output terminals of two second-stage data selectors; By analogy, the final stage data selector is a data selector, whose output end is connected to the first output end of the delay clock generating circuit; The control ends of all the data selectors are connected to the output end of the gating control unit.

4. The high-precision delayed clock generation circuit according to claim 1, wherein: The original clock output unit is composed of the same number of data selectors as the delayed clock output unit, each level of data selectors is a data selector, and each data selector has two input terminals; wherein, The two input ends of the first-level data selector are connected to the given clock signal port, the output end of the first-level data selector is connected to the two input ends of the second-level data selector, the output end of the second-level data selector is connected to the two input ends of the third-level data selector, and so on. The output end of the final-level data selector is connected to the second output end of the delayed clock generating circuit, and the control ends of all the data selectors are connected to the output end of the selection control unit.

5. The high-precision delayed clock generation circuit according to claim 1, wherein: The delayed clock output unit is composed of a first-level data selector, which has multiple input terminals; wherein, The multiple input ends of the data selector are respectively connected to the multiple delayed clock signal output ends of the clock delay chain unit, the control end of the data selector is connected to the output end of the selection control unit, and the output end of the data selector is connected to the first output end of the delayed clock generating circuit.

6. The high-precision delayed clock generating circuit according to claim 1, characterized in that: The original clock output unit is composed of a first-level data selector having two input terminals; wherein the two input terminals of the data selector are connected to an external given clock signal port, the control terminal of the data selector is connected to the output terminal of the selection control unit, and the output terminal of the data selector is connected to the second output terminal of the delayed clock generation circuit.

7. The high-precision delayed clock generating circuit according to claim 2, characterized in that: When the number of the delay stages in the clock delay chain unit is increased, the accuracy of the delayed clock signal output by the clock delay chain unit is improved accordingly.

8. The high-precision delayed clock generating circuit according to claim 2, wherein: When the even number of serially connected inverters in the delay stage is reduced, the accuracy of the delayed clock signal output by the clock delay chain unit is improved accordingly.

9. The high-precision delayed clock generating circuit according to claim 1, wherein: When a plurality of the delay clock generating circuits are connected in cascade, the cascade-connected delay clock generating circuits can simultaneously generate and output a plurality of delay clock signals; wherein, The first output end of the delay clock generating circuit of the previous stage is connected to the input end of the delay clock generating circuit of the next stage, and the second output end of the delay clock generating circuit of each stage serves as the delayed clock signal output end.

10. An integrated circuit chip, characterized in that The invention comprises the high-precision delayed clock generating circuit as claimed in any one of claims 1 to 9.

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