A silicon-based fan-out 3D packaging structure and method for preferentially forming a redistribution layer

Abstract

The present invention discloses a silicon-based fan-out 3D packaging structure and method for preferentially forming a redistribution layer, the structure comprising: a silicon wafer, a first dielectric layer, a first passivation layer, a first redistribution layer and a first chip sequentially arranged on the front side of the silicon wafer, the first chip being packaged by a plastic package, a second chip being embedded on the back side of the silicon wafer, and a second dielectric layer, a dry film material, a second passivation layer and a second redistribution layer being sequentially arranged on the back side of the silicon wafer and the surface of the second chip. The present invention pre-prepares a redistribution layer on a silicon wafer surface with high flatness, and since the flatness of the silicon wafer surface is high, it is conducive to forming a fine redistribution layer, and then mounting a high I / O density functional chip, and at the same time embedding a low I / O density chip on the back side, a three-dimensional stacking package of a high I / O density chip and a low I / O density chip can be realized.

Description

Technical field:

[0001] The present invention belongs to the technical field of semiconductor packaging, and in particular relates to a silicon-based fan-out 3D packaging structure and method for preferentially forming a redistribution layer. Background technology:

[0002] With the development of science and technology, the functions of consumer electronic products are becoming increasingly rich. The functional development of terminal products has also put forward more requirements for chip packaging. Multi-chip system integration has also become a trend. Therefore, the packaging structure of a single chip can no longer meet actual needs. Silicon-based fan-out three-dimensional packaging came into being in this context.

[0003] At present, the three-dimensional stacking structure of silicon-based fan-out mainly adopts the method of first preparing a reconstructed wafer based on a silicon wafer carrier, and then making a rewiring layer. However, this process still has the following shortcomings: when reconstructing the wafer, it is necessary to first prepare a groove on the silicon wafer, and then embed the chip into the groove, but it is difficult to make the surface of the chip and the surface of the silicon wafer completely flush, resulting in an undulating structure on the surface of the reconstructed wafer, which is not conducive to multi-layer fine wiring, so it is impossible to achieve integrated packaging of high I / O density chips.

[0004] The information disclosed in this background technology section is only intended to enhance the understanding of the overall background of the invention and should not be regarded as an acknowledgment or any form of suggestion that the information constitutes the prior art already known to a person skilled in the art. Summary of the invention:

[0005] The object of the present invention is to provide a silicon-based fan-out 3D packaging structure and method for preferentially forming a redistribution layer, thereby overcoming the above-mentioned defects in the prior art.

[0006] In order to achieve the above object, the present invention provides a silicon-based fan-out 3D packaging structure that preferentially forms a redistribution layer, comprising:

[0007] A silicon wafer, wherein the silicon wafer is provided with through silicon vias, the through silicon vias are filled with conductive pillars, and a groove structure is also etched on the back side of the silicon wafer;

[0008] A first dielectric layer, wherein the first dielectric layer is deposited on the front side of the silicon wafer;

[0009] a first passivation layer, the first passivation layer being disposed on the first dielectric layer;

[0010] a first redistribution layer, the first redistribution layer being disposed on the first passivation layer;

[0011] A first chip, wherein the first chip is mounted on a first redistribution layer, and the first chip is electrically connected to the first redistribution layer and the conductive pillar;

[0012] A plastic package, the plastic package is located on the first redistribution layer and packages the first chip inside;

[0013] a second chip, wherein the second chip is embedded in a groove on the back side of the silicon wafer;

[0014] A second dielectric layer, wherein the second dielectric layer is deposited on the back side of the silicon wafer and in the gap between the conductive pillar and the inner wall of the through silicon via;

[0015] A dry film material, wherein the dry film material covers the surface of the second dielectric layer and the second chip and fills the gap between the second chip and the groove;

[0016] a second passivation layer, the second passivation layer being disposed on the dry film material;

[0017] The second redistribution layer is disposed on the second passivation layer, and solder joints are formed on the surface of the second redistribution layer.

[0018] Further, preferably, the line width of the first redistribution layer is 1.5 μm-2 μm, and the line spacing is 1.5 μm-2 μm.

[0019] Further, preferably, the number of layers of the first redistribution layer is not less than 1.

[0020] Further, preferably, the number of layers of the first redistribution layer is 2-6 layers.

[0021] Furthermore, preferably, the number of the first chip is no less than one.

[0022] Furthermore, preferably, the first dielectric layer and the second dielectric layer are made of silicon oxide or silicon nitride material.

[0023] The present invention also provides a silicon-based fan-out 3D packaging method for preferentially forming a redistribution layer, comprising the following steps:

[0024] S1: depositing a first dielectric layer on the front side of the silicon wafer;

[0025] S2: sequentially preparing a first passivation layer and a first redistribution layer on the first dielectric layer, and forming a pad on the outermost surface of the first redistribution layer;

[0026] S3: mounting the first chip on the surface of the first redistribution layer with solder joints formed thereon;

[0027] S4: packaging the first chip by a plastic package;

[0028] S5: thinning the back side of the silicon wafer, etching a through silicon via after thinning, and depositing a second dielectric layer on the inner wall of the through silicon via and the back side of the silicon wafer;

[0029] S6: Filling the through silicon via with metal material to form a conductive column, wherein the conductive column is conductively connected to the first redistribution layer and the first chip;

[0030] S7: etching a groove structure on the back side of the silicon wafer using an etching process;

[0031] S8: embedding a second chip having a pad formed thereon into the groove structure;

[0032] S9: using a dry film material to cover the second dielectric layer and fill the gap between the second chip and the groove structure, wherein an opening is formed at the position of the pad and the conductive column of the second chip;

[0033] S10: preparing a second passivation layer on the dry film material, preparing a second redistribution layer on the second passivation layer, and finally preparing solder joints on the surface of the second redistribution layer.

[0034] Further, preferably, the first redistribution layer and the second redistribution layer are both copper wire layers.

[0035] Furthermore, preferably, the first passivation layer and the second passivation layer are made of solid dry film or PI adhesive film.

[0036] Furthermore, preferably, the conductive pillars are metal copper pillars.

[0037] Compared with the prior art, one aspect of the present invention has the following beneficial effects:

[0038] (1) The present invention prepares the first redistribution layer on the surface of a silicon wafer with high flatness by conventional bumping wiring technology, and the line width and line spacing can be 2μm / 2μm, or even 1.5μm / 1.5μm, and the number of layers can be 2-6 layers, or even more, which is suitable for the integrated packaging of high I / O density chips and can effectively control the manufacturing cost;

[0039] (2) The present invention first prepares a fine first redistribution layer on the front side of the silicon wafer and then mounts the functional chip, thereby avoiding the chip yield loss caused by defects in the first redistribution layer;

[0040] (3) In the present invention, a fine first redistribution layer is first prepared on the front side of the silicon wafer, and then the first chip is mounted, and then the second chip is embedded on the back side of the silicon wafer. Since the first redistribution layer is relatively fine, the first chip can be a chip with high I / O density, and the second chip can be a chip with low I / O density, thereby realizing three-dimensional stacking packaging of high I / O density chips and low I / O density chips. Description of the drawings:

[0041] Figure 1 is a schematic diagram of depositing a first dielectric layer on the front side of a silicon wafer in the present invention;

[0042] Figure 2 It is a schematic diagram of preparing a first passivation layer and a first redistribution layer on a first dielectric layer in the present invention;

[0043] Figure 3 It is a schematic diagram of mounting a first chip on a first redistribution layer in the present invention;

[0044] Figure 4 is a schematic diagram of packaging the first chip in the present invention;

[0045] Figure 5 A schematic diagram of manufacturing a through silicon via on a silicon wafer in the present invention;

[0046] Figure 6 A schematic diagram of filling a metal material in a through silicon via to form a conductive column in the present invention;

[0047] Figure 7 It is a schematic diagram of forming a groove structure on the back side of a silicon wafer in the present invention;

[0048] Figure 8 is a schematic diagram of embedding a second chip in a groove structure in the present invention;

[0049] Fig. 9 It is a schematic diagram of the overall silicon-based fan-out 3D packaging structure of the present invention;

[0050] Figure markings: 1-silicon wafer, 2-first dielectric layer, 3-first passivation layer, 4-first redistribution layer, 5 / 17-solder pad, 6 / 7-first chip, 8 / 21-solder point, 9-plastic package, 10-silicon through via, 11-second dielectric layer, 12-conductive column, 13-groove structure, 14-second chip, 15-gap, 16-adhesive material, 18-dry film material, 19-second passivation layer, 20-second redistribution layer. Specific implementation method:

[0051] The specific embodiments of the present invention are described in detail below, but it should be understood that the protection scope of the present invention is not limited by the specific embodiments.

[0052] A brief summary of one or more aspects is given below to provide a basic understanding of these aspects. This summary is not an exhaustive overview of all conceived aspects, and is neither intended to identify the key or critical elements of all aspects nor to define the scope of any or all aspects. Its only purpose is to give some concepts of one or more aspects in a simplified form as a prelude to a more detailed description that will be given later.

[0053] Embodiment 1:

[0054] like Fig. 9As shown, a silicon-based fan-out 3D packaging structure for preferentially forming a redistribution layer includes:

[0055] A silicon wafer 1, wherein the silicon wafer 1 is provided with a through silicon via, wherein the through silicon via is filled with a conductive column 12, and a groove structure is also etched on the back side of the silicon wafer 1;

[0056] A first dielectric layer 2, wherein the first dielectric layer 2 is deposited on the front side of the silicon wafer 1;

[0057] A first passivation layer 3, wherein the first passivation layer 3 is disposed on the first dielectric layer 2;

[0058] A first redistribution layer 4, wherein the first redistribution layer 4 is disposed on the first passivation layer 3, and a pad 5 is formed on the outermost surface of the first redistribution layer 4;

[0059] A first chip 6, wherein the first chip 6 is mounted on the first redistribution layer 4, the first chip 6 is electrically connected to the first redistribution layer 4 and the conductive pillar 12, two first chips are used, namely the first chip 6 and the first chip 7, or more than two chips may be used; solder joints 8 are pre-formed on the chip, and the solder joints 8 are interconnected with the pads 5 by soldering;

[0060] A plastic package 9, wherein the plastic package 9 is located on the first redistribution layer 4 and encapsulates the first chip 6 / 7 inside;

[0061] A second chip 14, wherein the second chip 14 is embedded in a groove on the back side of the silicon wafer 1;

[0062] A second dielectric layer 11, which is deposited on the back side of the silicon wafer 1 and in the gap between the conductive pillar 12 and the inner wall of the through silicon via;

[0063] A dry film material 18, wherein the dry film material 18 covers the surface of the second dielectric layer 11 and the second chip 14, and fills the gap between the second chip 14 and the groove;

[0064] A second passivation layer 19, wherein the second passivation layer 19 is disposed on the dry film material 18;

[0065] The second redistribution layer 20 is disposed on the second passivation layer 19 , and a solder joint 21 is formed on the surface of the second redistribution layer 20 .

[0066] The present invention also provides a silicon-based fan-out 3D packaging method for preferentially forming a redistribution layer, comprising the following steps:

[0067] S1: Figure 1 As shown, a first dielectric layer 2 is deposited on the front side of the silicon wafer 1. The first dielectric layer 2 plays an insulating role and serves as a stop layer when the silicon wafer is etched. A material such as silicon oxide or silicon nitride may be used.

[0068] S2: Figure 2 As shown, a first passivation layer 3 and a first redistribution layer 4 are sequentially prepared on the first dielectric layer 1, and a pad 5 is formed on the outermost surface of the first redistribution layer 4. Since the surface flatness of the silicon wafer 1 is relatively high, the first redistribution layer 4 can be made very fine, and the line width and line spacing can be 2μm / 2μm, or even 1.5μm / 1.5μm. The number of layers of the first redistribution layer 4 can be two or more layers; the first redistribution layer 4 is usually a copper circuit, and the first passivation layer 3 can be a solid dry film or a PI film;

[0069] S3: Figure 3 As shown, through the flip chip process, the first chips 6 and 7 with solder joints 8 formed are mounted on the surface of the first redistribution layer 4, and the solder joints 8 are interconnected with the solder pads 5 on the outermost surface of the first redistribution layer 4 through welding, so as to form signal transmission; the first chips can be two or more, and two are used in this embodiment; the solder joints are usually formed by electroplating of materials such as Cu, Ni, Sn and Ag; the first chips 6 and 7 are high I / O density chips;

[0070] S4: Figure 4 As shown, the first chips 6 and 7 are packaged by a plastic package 9, and the plastic package 9 can protect the chips and support the entire reconstructed wafer;

[0071] S5: Figure 5 As shown, with the plastic package 9 as a support, the back side of the silicon wafer 1 is thinned, and after thinning, a through silicon via 10 is etched out by an etching process. The through silicon via 10 is used for front and back signal interconnection. A second dielectric layer 11 is deposited on the inner wall of the through silicon via 10 and the back side of the silicon wafer 1. The second dielectric layer 11 can be a material such as silicon oxide or silicon nitride;

[0072] S6: Figure 6 As shown, the through silicon via 10 is filled with metal material through a metal sputtering process and an electroplating process, and then the metal on the surface is removed by grinding, chemical mechanical polishing, reverse electrolysis, wet etching with adhesive, etc. to form a conductive column 12, and the conductive column 12 is connected to the first redistribution layer 4 and the first chips 6 and 7. In this embodiment, the filling metal material is usually made of copper material, and the electroplating process can be equal wall electroplating or filling electroplating;

[0073] S7: Figure 7 As shown, a groove structure 13 is etched from the back side of the silicon wafer 1 by using an etching process;

[0074] S8: Figure 8As shown, a second chip 14 with a pad 17 formed thereon is embedded in the groove structure 13, the functional layer of the second chip 14 faces outward, and the pad 17 on the surface is exposed; a narrow gap 15 is formed between the second chip 14 and the sidewall of the groove structure 13, and the second chip 14 and the bottom of the groove structure 13 are fixed by an adhesive material 16; ideally, the surface of the second chip 14 is required to be substantially flush with the surface of the silicon wafer 1, but in reality, it is impossible to achieve complete flushness, and the height difference between the second chip 14 and the surface of the silicon wafer 1 is usually several microns; the second chip 14 can be one or more;

[0075] S9: Fig. 9 As shown, a dry film material 18 is used to cover the second dielectric layer 11 and fill the gap 15 between the second chip 14 and the groove structure 13, wherein an opening is formed at the position of the pad 17 of the second chip 14 and the conductive column 12 to facilitate signal interconnection; in this embodiment, the dry film material 18 is a photosensitive dry film, and a pattern is formed by a photolithography process;

[0076] S10: Fig. 9 As shown, a second passivation layer 19 is prepared on the dry film material 18, and a second redistribution layer 20 is prepared on the second passivation layer 19, and finally a solder joint 21 is prepared on the surface of the second redistribution layer 20 to form an overall silicon-based fan-out 3D packaging structure; in this embodiment, the second redistribution layer 20 is usually a copper wire, which can be a single layer or multiple layers; the second passivation layer 19 adopts a solid dry film or PI film material; the solder joint 21 can be Sn, Ag material, or other alloy materials.

[0077] Since the second chip 14 cannot be completely flush with the surface of the silicon wafer 1, and the warping of the plastic package 9 is significantly greater than the warping of the silicon wafer 1, the line width and line spacing of the second redistribution layer 20 on the back of the silicon wafer 1 is significantly greater than the line width and line spacing of the first redistribution layer 4 on the front of the silicon wafer 1. Therefore, the first chips 6 and 7 welded on the front side can use chips with high I / O density, while the second chip 14 embedded on the back side can use chips with low I / O density.

[0078] The present invention preferentially forms a multi-layer fine rewiring layer on the front side of a silicon wafer, welds a high I / O density chip on the rewiring layer, then performs plastic sealing on the high I / O density chip, and after the plastic sealing material is cured, serves as a carrier for supporting the silicon wafer, then thins the silicon wafer to a certain thickness, forms silicon through vias at corresponding positions, then forms a groove structure on the back side of the silicon wafer, and pastes a low I / O density chip into the groove structure, and finally further rewires to interconnect the chip embedded in the groove structure with the chip on the other side, thereby forming a three-dimensional packaging structure; the wiring process of the present invention adopts mature bumping wiring technology, and preferential wiring can control manufacturing costs and perform fine wiring, thereby realizing three-dimensional stacking packaging of high I / O density chips and low I / O density chips.

[0079] The foregoing description of specific exemplary embodiments of the present invention is for the purpose of illustration and demonstration. These descriptions are not intended to limit the present invention to the precise form disclosed, and it is clear that many changes and variations can be made based on the above teachings. The purpose of selecting and describing the exemplary embodiments is to explain the specific principles of the present invention and its practical application, so that those skilled in the art can realize and utilize various different exemplary embodiments of the present invention and various different selections and changes. The scope of the present invention is intended to be limited by the claims and their equivalents.

Claims

1. A silicon-based fan-out 3D packaging structure that preferentially forms a redistribution layer, characterized in that: include: A silicon wafer, wherein the silicon wafer is provided with through silicon vias, the through silicon vias are filled with conductive pillars, and a groove structure is also etched on the back side of the silicon wafer; A first dielectric layer, wherein the first dielectric layer is deposited on the front side of the silicon wafer; a first passivation layer, the first passivation layer being disposed on the first dielectric layer; a first redistribution layer, the first redistribution layer being disposed on the first passivation layer; A first chip, wherein the first chip is mounted on a first redistribution layer, and the first chip is electrically connected to the first redistribution layer and the conductive pillar; A plastic package, the plastic package is located on the first redistribution layer and packages the first chip inside; a second chip, wherein the second chip is embedded in a groove on the back side of the silicon wafer; A second dielectric layer, wherein the second dielectric layer is deposited on the back side of the silicon wafer and in the gap between the conductive pillar and the inner wall of the through silicon via; A dry film material, wherein the dry film material covers the surface of the second dielectric layer and the second chip and fills the gap between the second chip and the groove; a second passivation layer, the second passivation layer being disposed on the dry film material; A second redistribution layer, wherein the second redistribution layer is disposed on the second passivation layer, and solder joints are formed on the surface of the second redistribution layer; The method for preferentially forming a silicon-based fan-out 3D packaging structure of a redistribution layer comprises the following steps: S1: depositing a first dielectric layer on the front side of the silicon wafer; S2: sequentially preparing a first passivation layer and a first redistribution layer on the first dielectric layer, and forming a pad on the outermost surface of the first redistribution layer; S3: mounting the first chip on the surface of the first redistribution layer with solder joints formed thereon; S4: packaging the first chip by a plastic package; S5: thinning the back side of the silicon wafer, etching a through silicon via after thinning, and depositing a second dielectric layer on the inner wall of the through silicon via and the back side of the silicon wafer; S6: Filling the through silicon via with metal material to form a conductive column, wherein the conductive column is conductively connected to the first redistribution layer and the first chip; S7: etching a groove structure on the back side of the silicon wafer using an etching process; S8: embedding a second chip having a pad formed thereon into the groove structure; S9: using a dry film material to cover the second dielectric layer and fill the gap between the second chip and the groove structure, wherein an opening is formed at the position of the pad and the conductive column of the second chip; S10: preparing a second passivation layer on the dry film material, preparing a second redistribution layer on the second passivation layer, and finally preparing solder joints on the surface of the second redistribution layer.

2. A silicon-based fan-out 3D packaging structure with a preferential formation of a redistribution layer according to claim 1, characterized in that: The line width of the first redistribution layer is 1.5 μm-2 μm, and the line spacing is 1.5 μm-2 μm.

3. The silicon-based fan-out 3D packaging structure for preferentially forming a redistribution layer according to claim 1, characterized in that: The number of layers of the first redistribution layer is not less than one.

4. The silicon-based fan-out 3D packaging structure for preferentially forming a redistribution layer according to claim 1, characterized in that: The number of layers of the first redistribution layer is 2-6.

5. The silicon-based fan-out 3D packaging structure for preferentially forming a redistribution layer according to claim 1, characterized in that: The number of the first chip is no less than one.

6. The silicon-based fan-out 3D packaging structure with a preferential formation of a redistribution layer according to claim 1, characterized in that: The first dielectric layer and the second dielectric layer are made of silicon oxide or silicon nitride.

7. The silicon-based fan-out 3D packaging structure for preferentially forming a redistribution layer according to claim 1, characterized in that: The first redistribution layer and the second redistribution layer are both copper wire layers.

8. The silicon-based fan-out 3D packaging structure for preferentially forming a redistribution layer according to claim 1, characterized in that: The first passivation layer and the second passivation layer are made of solid dry film or PI adhesive film.

9. The silicon-based fan-out 3D packaging structure with a preferential formation of a redistribution layer according to claim 1, characterized in that: The conductive column is a metal copper column.

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