A DDR test system and method

Abstract

The present invention belongs to the field of DDR testing technology, and its purpose is to provide a DDR testing system and method. The present invention generates DDR test instructions by encoding based on a main control module. When testing the DDR under test, the DDR test instructions can be decoded by an instruction decoding control module to obtain all sub-test instructions in the DDR test instructions. Finally, all sub-test instructions are converted into control signals that comply with a specified interface protocol by a DDR control module, and the DDR under test is tested through the DDR physical layer. In this process, since the DDR test instructions are generated by encoding, compared with the solution in which the memory controller directly performs read and write tests on the DDR under test based on the read and write operation instructions of the CPU in the traditional technology, it can realize accurate measurement of various timing parameters defined by DDR JEDEC, thereby making the control of the DDR under test more accurate and flexible, and at the same time, it is conducive to compatible testing of various types of DDR, and the test application range is wider.

Description

Technical Field

[0001] The invention belongs to the technical field of DDR testing, and in particular relates to a DDR testing system and method. Background Art

[0002] DDR (Double Data Rage SDRAM) is a type of DDR SDRAM (synchronous dynamic random-access memory), known for its low power consumption and small size, and is specifically used in mobile electronic products. DDR testing is required to verify the performance and stability of DDR and to ensure the quality of DDR products.

[0003] However, in the process of using the prior art, the inventors found that the prior art has at least the following problems:

[0004] In the existing technology, DDR3, DDR4 and LPDDR4 are more commonly used, while DDR5 and LPDDR5 are less used, resulting in a relatively low specification level for DDR testing in the current market. Most of them only support testing of DDR, DDR2, DDR3 and DDR4, while there are relatively few or no related devices supporting testing of DDR5 and LPDDR5.

[0005] In addition, when DDR is measured, the following methods are usually used: Figure 1 In the prior art implementation shown, the memory controller directly performs read and write tests on the DDR under test through the DDR physical layer based on the read and write operation instructions of the main control module. Since the DDR commands and various timing parameters are directly determined by the memory controller, the main control module cannot accurately control the DDR read and write timing behavior, which limits the measurable DDR related parameters. Some parameters defined in DDR JEDEC cannot be accurately measured according to the current testing methods, such as the DDR timing parameters defined in DDR JEDEC cannot be accurately measured. Summary of the invention

[0006] The present invention aims to solve the above technical problems at least to a certain extent, and provides a DDR test system and method.

[0007] In order to achieve the above object, the present invention adopts the following technical solutions:

[0008] In a first aspect, the present invention provides a DDR test system, comprising a main control module, an instruction decoding control module, a DDR control module and a DDR physical layer which are sequentially communicatively connected; wherein:

[0009] The main control module is used to generate a DDR test instruction by encoding, and send the DDR test instruction to the instruction decoding control module;

[0010] The instruction decoding control module is used to decode the DDR test instruction, obtain all sub-test instructions in the DDR test instruction, and send all sub-test instructions to the DDR control module;

[0011] The DDR control module is used to convert all sub-test instructions into control signals that comply with the specified interface protocol, and perform test operations on the tested DDR through the DDR physical layer.

[0012] The present invention can be beneficial to realize the precise control of DDR test, with stronger flexibility, and can realize various types of chip tests such as DDR4 / LPDDR4 / DDR5 / LPDDR5, and the test application scope is wider. Specifically, the present invention generates DDR test instructions by encoding based on the main control module. When testing the DDR under test, the DDR test instructions can be decoded by the instruction decoding control module to obtain all sub-test instructions in the DDR test instructions, and finally all sub-test instructions are converted into control signals that comply with the specified interface protocol by the DDR control module, and the DDR under test is tested through the DDR physical layer. In this process, since the DDR test instructions are generated by encoding, compared with the solution in which the memory controller directly performs read and write tests on the DDR under test based on the read and write operation instructions of the CPU in the traditional technology, it can realize accurate measurement of various timing parameters defined by DDRJEDEC, thereby making the control of the DDR under test more accurate and flexible, and at the same time conducive to compatible testing of various types of DDR, and the test application scope is wider.

[0013] In one possible design, the DDR test instructions include configuration instructions, command operation instructions, address operation instructions and / or loop instructions.

[0014] In the present invention, the DDR test instructions include configuration instructions, command operation instructions, address operation instructions and loop instructions, which can facilitate the implementation of various types of tests on DDR.

[0015] In a possible design, DDR test instructions are generated by coding, including:

[0016] Get initial test instructions;

[0017] According to the instruction type of the initial test instruction and the preset DDR timing, the initial test instruction is encoded to obtain an encoded test instruction;

[0018] The encoded test instruction is converted into a DDR test instruction in the form of a binary code stream.

[0019] Based on the above process, a specific technical solution for generating DDR test instructions by encoding is disclosed. It should be noted that in the present invention, the initial test instruction is determined according to the task to be tested on the DDR, and may include configuration instructions, command operation instructions, address operation instructions and / or loop instructions and other main instructions, which are not limited here. When encoding the initial test instruction, it is necessary to encode it in the manner of a DDR command that requires each instruction to control the operation of a DDR clock cycle according to the preset DDR timing requirement, and perform binary conversion on the encoded test instruction to obtain a DDR test instruction in the form of a binary code stream.

[0020] In a possible design, the DDR test system further includes a test signal generation module, the input end of the test signal generation module is communicatively connected to the instruction decoding control module, and the output end of the test signal generation module is communicatively connected to the DDR control module; wherein,

[0021] The test signal generating module is used to receive a sub-test instruction of a specified type sent by the instruction decoding control module, and send the sub-test instruction of the specified type to the DDR control module, so that the DDR control module performs a test operation of the specified type on the DDR under test through the DDR physical layer.

[0022] It should be noted that the setting of the test signal generation module can achieve the purpose of performing a specified type of test operation on the DDR, which is conducive to realizing targeted testing on the DDR.

[0023] In one possible design, the test signal generation module includes a DDR command generator module, a DDR address generator module and a DDR data generator module; wherein,

[0024] The DDR command generator module is used to receive the sub-test instruction of the operation type from the instruction decoding control module, and perform the test operation of the operation type on the DDR under test through the DDR control module;

[0025] The DDR address generator module is used to receive the sub-test instruction of the address type from the instruction decoding control module, and perform the test operation of the address type on the tested DDR through the DDR control module;

[0026] The DDR data generator module is used to receive the sub-test instruction of the data type from the instruction decoding control module, and perform the test operation of the data type on the DDR under test through the DDR control module.

[0027] It should be noted that the test signal generation module can be set to one or more, such as only including the command generator module. In this case, the DDR test system of the present invention can only implement command tests on DDR, such as activation, refresh, precharge, etc. In the present invention, the test signal generation module is set to multiple, specifically including a DDR command generator module, a DDR address generator module and a DDR data generator module, which can facilitate the implementation of various types of tests on DDR, so as to achieve the purpose of sufficient testing.

[0028] In a possible design, the address type sub-test instruction includes an address initialization configuration instruction; correspondingly, the address type test operation is performed on the DDR under test, including:

[0029] Based on the address initialization configuration instruction, initialization configuration is performed on the DDR address in the tested DDR that matches the sub-test instruction of the address type to obtain an initialized address;

[0030] An arithmetic operation test and / or a command operation test is performed on the initialized address.

[0031] In the present invention, by performing an address type test operation on the DDR, the effect of changing the test address can be achieved, which is beneficial to periodically and repeatedly testing the performance of the DDR based on different DDR operation instructions.

[0032] In a possible design, the DDR test system further includes an instruction cache module, the input end of the instruction cache module is communicatively connected to the main control module, and the output end of the instruction cache module is communicatively connected to the instruction decoding control module; wherein,

[0033] The instruction cache module is used to receive the DDR test instruction generated by the main control module and cache the DDR test instruction;

[0034] The instruction cache module is also used to send the cached DDR test instructions to the instruction decoding control module.

[0035] In a second aspect, the present invention provides a DDR test method, which is performed based on any one of the above-mentioned DDR test systems; the DDR test method comprises:

[0036] The main control module generates a DDR test instruction by encoding, and sends the DDR test instruction to the instruction decoding control module;

[0037] The instruction decoding control module decodes the DDR test instruction to obtain all sub-test instructions in the DDR test instruction, and sends all sub-test instructions to the DDR control module;

[0038] The DDR control module converts all sub-test instructions into control signals that comply with a specified interface protocol, and performs test operations on the DDR under test through the DDR physical layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 It is a module block diagram of a DDR test system in the prior art;

[0040] Figure 2 FIG. 4 is a module block diagram of a DDR test system in an embodiment. DETAILED DESCRIPTION

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the present invention will be briefly introduced below in combination with the drawings and the description of the embodiments or the prior art. Obviously, the following description of the structure of the drawings is only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. It should be noted that the description of these embodiments is used to help understand the present invention, but does not constitute a limitation of the present invention.

[0042] Embodiment 1:

[0043] This embodiment discloses a DDR test system. Figure 2 As shown, a DDR test system may include, but is not limited to, a main control module, an instruction decoding control module, a DDR control module, and a DDR physical layer that are sequentially connected in communication; wherein,

[0044] The main control module is used to generate DDR test instructions by encoding, and send the DDR test instructions to the instruction decoding control module; it should be noted that the DDR test instructions include all operation instruction sequences defined by DDR4 / LPDDR4 / DDR5 / LPDDR5JEDECD (Joint Electron Device Engineering Council, an international semiconductor device standard organization), such as DDR's ACTIVE command, PRECHANGE command, WR command and RD command and other operation instructions. In addition, based on the DDR test instructions, predetermined operations can be performed on the addresses such as ROW (row) / COL (column) / BANK (storage body) / BANKGROUP (storage body group) of the specified DDR.

[0045] The instruction decoding control module is used to decode the DDR test instruction to obtain all sub-test instructions in the DDR test instruction, and send all sub-test instructions to the DDR control module so as to perform different subsequent operations according to different types of DDR test instructions;

[0046] The DDR control module is used to convert all sub-test instructions into control signals that comply with the specified interface protocol, and perform test operations on the tested DDR through the DDR physical layer. It should be noted that the specified interface protocol is a protocol supported by DDR, such as the DFI protocol, which is not limited here.

[0047] This embodiment can be helpful to realize precise control of DDR test, with greater flexibility, and can realize various types of chip tests such as DDR4 / LPDDR4 / DDR5 / LPDDR5, and has a wider range of test applications. Specifically, this embodiment generates DDR test instructions through encoding based on the main control module. When testing the DDR under test, the DDR test instructions can be decoded by the instruction decoding control module to obtain all sub-test instructions in the DDR test instructions. Finally, all sub-test instructions are converted into control signals that comply with the specified interface protocol through the DDR control module, and the DDR under test is tested through the DDR physical layer. In this process, since the DDR test instructions are generated by encoding, compared to Figure 1 In the prior art shown, the memory controller directly performs read and write tests on the DDR under test based on the read and write operation instructions of the main control module, which can realize accurate measurement of various timing parameters defined by DDR JEDEC, such as tRCD (RAS to CAS Delay, also known as: Active to CMD, row addressing to column addressing delay time), tCCD (CAS to CAS Delay, time interval between CAS commands to CAS commands) and tRP (Row Precharge Timing, also known as: Precharge to Active, memory row address controller precharge time) and other timing parameters, so that the chip quality and chip reliability of the DDR under test can be accurately measured and evaluated, thereby making the control of the DDR under test more accurate and flexible, and at the same time facilitating compatible testing of various types of DDR, and the test application range is wider.

[0048] In this embodiment, the DDR test instructions include configuration instructions, command operation instructions, address operation instructions and / or loop instructions.

[0049] In this embodiment, the DDR test instructions include configuration instructions, command operation instructions, address operation instructions and loop instructions, which can facilitate the implementation of various types of tests on DDR.

[0050] Specifically, based on the configuration instructions, the configuration of the DDR address initialization register or the DDR data initialization register can be implemented; based on the command operation instructions, the test operations such as DDR activation, DDR read operation, DDR write operation, DDR precharge, refresh, etc. can be implemented; based on the address operation operation instructions, the operation operation of the DDR address can be implemented; based on the loop instruction, the function of looping execution of a certain instruction block in the DDR test instruction can be implemented. For example, a certain instruction block consists of the following two instructions: a. write operation to the DDR memory with the ROW starting address of 0, b. add 1 to the ROW address. Based on the loop instruction, the instructions composed of instruction a and instruction b can be looped, for example, looped 64 times, so that write operations can be performed on the addresses with ROW addresses from 0 to 63.

[0051] It should also be noted that, the DDR test instruction is subsequently decoded, and if the sub-test instruction in the obtained DDR test instruction is a configuration instruction, the DDR can be directly configured; if the sub-test instruction is a command operation instruction, the DDR can be directly command-operated; if the sub-test instruction is an address operation instruction, the corresponding DDR address can be operated and tested; if the sub-test instruction is a loop instruction, the corresponding instruction block is taken out and looped according to the position of the instruction block that needs to be looped in the cache area specified in the sub-test instruction, and after the loop is completed, the next instruction is taken out from the instruction cache area to continue decoding and execution.

[0052] In this embodiment, the DDR test instruction is generated by encoding, including:

[0053] Get initial test instructions;

[0054] According to the instruction type of the initial test instruction and the preset DDR timing, the initial test instruction is encoded to obtain an encoded test instruction;

[0055] The encoded test instruction is converted into a DDR test instruction in the form of a binary code stream.

[0056] Based on the above process, a specific technical solution for generating DDR test instructions by encoding is disclosed. It should be noted that, in this embodiment, the initial test instruction is determined according to the task to be tested on the DDR, and may include configuration instructions, command operation instructions, address operation instructions and / or loop instructions and other main instructions, which are not limited here. When encoding the initial test instruction, it is necessary to encode it in the manner of a DDR command that controls the operation of one DDR clock cycle according to the preset DDR timing requirement, and perform binary conversion on the encoded test instruction to obtain a DDR test instruction in the form of a binary code stream.

[0057] As an example, when encoding the initial test instruction, the instructions will be edited one by one in the order that each DDR operation command on the DDR bus is an instruction, and the instructions will be organized according to the sequence of the commands sent on the DDR bus. For example, the commands sent on the DDR bus are DES, ACT, DES, DES, DES, DES, WR, DES, DES, DES, RD, DES, DES, DES, DES, PRE, a total of 16 DDR instruction operation instruction sequences. Then the main control module needs to program 16 instructions to represent these 16 DDR operation instruction sequences to implement the encoding operation of the initial test instruction, and then conveniently assemble it into a binary code stream to obtain the DDR test instruction.

[0058] In this embodiment, the DDR test system further includes a test signal generation module, the input end of the test signal generation module is communicatively connected to the instruction decoding control module, and the output end of the test signal generation module is communicatively connected to the DDR control module; wherein,

[0059] The test signal generating module is used to receive a sub-test instruction of a specified type sent by the instruction decoding control module, and send the sub-test instruction of the specified type to the DDR control module, so that the DDR control module performs a test operation of the specified type on the DDR under test through the DDR physical layer.

[0060] It should be noted that the setting of the test signal generation module can achieve the purpose of performing a specified type of test operation on the DDR, which is conducive to realizing targeted testing on the DDR.

[0061] Specifically, in this embodiment, the test signal generating module includes a DDR command generator module, a DDR address generator module and a DDR data generator module; wherein,

[0062] The DDR command generator module is used to receive the sub-test instruction of the operation type from the instruction decoding control module, and perform the test operation of the operation type on the DDR under test through the DDR control module;

[0063] The DDR address generator module is used to receive the sub-test instruction of the address type from the instruction decoding control module, and perform the test operation of the address type on the tested DDR through the DDR control module;

[0064] The DDR data generator module is used to receive the sub-test instruction of the data type from the instruction decoding control module, and perform the test operation of the data type on the DDR under test through the DDR control module.

[0065] It should be noted that the test signal generation module may be provided with one or more modules, such as only including the command generator module. In this case, the DDR test system in this embodiment can only implement command tests on DDR, such as activation, refresh, precharge, etc. In this embodiment, the test signal generation module is provided with multiple modules, specifically including a DDR command generator module, a DDR address generator module, and a DDR data generator module, which can facilitate the implementation of various types of tests on DDR, so as to achieve the purpose of sufficient testing.

[0066] In this embodiment, the sub-test instruction of the address type includes an address initialization configuration instruction; correspondingly, the test operation of the address type is performed on the tested DDR, including:

[0067] Based on the address initialization configuration instruction, the DDR address (including ROW / COL / BANK / BANKGROUP addresses, etc.) matching the sub-test instruction of the address type in the tested DDR is initialized and configured to obtain an initialized address;

[0068] Perform operation test and / or command operation test on the initialized address. It should be noted that, in this embodiment, the operation test on the initialized address may include address increment, decrement, circular left and right movement, inversion, reset, random, and other defined AND, OR, NOT, XOR and other operations, and a new DDR test address will be obtained after the operation. Perform command operation test on the initialized address, which may include read and write test, as well as activation, refresh, precharge and other operation tests, which are not limited here.

[0069] In this embodiment, by performing an address type test operation on the DDR, the effect of changing the test address can be achieved, which is beneficial for periodically and repeatedly testing the performance of the DDR based on different DDR operation instructions.

[0070] In addition, the data type test operation is performed on the DDR under test, including: after the write data of the DDR under test is initialized and configured, the DDR data operation code contained in the sub-test instruction of the data type will initialize the data for calculation operation. The calculation method is the same as the DDR address calculation method, including the address of the data, decrement, inversion, circular left and right movement, random, and other XOR, AND, and other arithmetic operations, and then new DDR write data is generated for the read and write test of the DDR in the next cycle.

[0071] In addition, in this embodiment, the DDR test system further includes an instruction cache module, the input end of the instruction cache module is communicatively connected to the main control module, and the output end of the instruction cache module is communicatively connected to the instruction decoding control module; wherein,

[0072] The instruction cache module is used to receive the DDR test instruction generated by the main control module and cache the DDR test instruction;

[0073] The instruction cache module is also used to send the cached DDR test instructions to the instruction decoding control module.

[0074] The setting of the instruction cache module can facilitate the storage of multiple DDR test instructions so as to realize uninterrupted testing of the DDR under test.

[0075] Embodiment 2:

[0076] This embodiment discloses a DDR test method, which is executed based on the DDR test system in Embodiment 1; the DDR test method includes:

[0077] The main control module generates a DDR test instruction by encoding, and sends the DDR test instruction to the instruction decoding control module;

[0078] The instruction decoding control module decodes the DDR test instruction to obtain all sub-test instructions in the DDR test instruction, and sends all sub-test instructions to the DDR control module;

[0079] The DDR control module converts all sub-test instructions into control signals that comply with a specified interface protocol, and performs test operations on the DDR under test through the DDR physical layer.

[0080] It should be noted that the working process, working details and technical effects of the DDR testing method provided in this embodiment 2 can be found in embodiment 1 and will not be described in detail here.

[0081] Obviously, those skilled in the art should understand that the above modules or steps of the present invention can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, and optionally, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present invention is not limited to any specific combination of hardware and software.

[0082] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the above embodiments, a person skilled in the art should understand that the technical solutions described in the above embodiments can still be modified, or some of the technical features can be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A DDR test system, characterized in that: It includes a main control module, an instruction decoding control module, a DDR control module and a DDR physical layer which are sequentially connected in communication; wherein, The main control module is used to generate a DDR test instruction by encoding, and send the DDR test instruction to the instruction decoding control module; The instruction decoding control module is used to decode the DDR test instruction, obtain all sub-test instructions in the DDR test instruction, and send all sub-test instructions to the DDR control module; The DDR control module is used to convert all sub-test instructions into control signals that comply with the specified interface protocol, and perform test operations on the DDR under test through the DDR physical layer; Generate DDR test instructions by coding, including: Get initial test instructions; According to the instruction type of the initial test instruction and the preset DDR timing, the initial test instruction is encoded to obtain an encoded test instruction; The encoded test instruction is converted into a DDR test instruction in the form of a binary code stream.

2. A DDR test system according to claim 1, characterized in that: The DDR test instructions include configuration instructions, command operation instructions, address operation instructions and / or loop instructions.

3. A DDR test system according to claim 1, characterized in that: The DDR test system further includes a test signal generation module, an input end of the test signal generation module is communicatively connected to the instruction decoding control module, and an output end of the test signal generation module is communicatively connected to the DDR control module; wherein, The test signal generating module is used to receive a sub-test instruction of a specified type sent by the instruction decoding control module, and send the sub-test instruction of the specified type to the DDR control module, so that the DDR control module performs a test operation of the specified type on the DDR under test through the DDR physical layer.

4. A DDR test system according to claim 3, characterized in that: The test signal generating module includes a DDR command generator module, a DDR address generator module and a DDR data generator module; wherein, The DDR command generator module is used to receive the sub-test instruction of the operation type from the instruction decoding control module, and perform the test operation of the operation type on the DDR under test through the DDR control module; The DDR address generator module is used to receive the sub-test instruction of the address type from the instruction decoding control module, and perform the test operation of the address type on the tested DDR through the DDR control module; The DDR data generator module is used to receive the sub-test instruction of the data type from the instruction decoding control module, and perform the test operation of the data type on the DDR under test through the DDR control module.

5. A DDR test system according to claim 4, characterized in that: The sub-test instruction of the address type includes an address initialization configuration instruction; correspondingly, the test operation of the address type is performed on the DDR under test, including: Based on the address initialization configuration instruction, initialization configuration is performed on the DDR address in the tested DDR that matches the sub-test instruction of the address type to obtain an initialized address; An arithmetic operation test and / or a command operation test is performed on the initialized address.

6. A DDR test system according to claim 1, characterized in that: The DDR test system further includes an instruction cache module, the input end of the instruction cache module is communicatively connected to the main control module, and the output end of the instruction cache module is communicatively connected to the instruction decoding control module; wherein, The instruction cache module is used to receive the DDR test instruction generated by the main control module and cache the DDR test instruction; The instruction cache module is also used to send the cached DDR test instructions to the instruction decoding control module.

7. A DDR testing method, characterized in that: Based on the DDR test system according to any one of claims 1 to 6, the DDR test method comprises: The main control module generates a DDR test instruction by encoding, and sends the DDR test instruction to the instruction decoding control module; The instruction decoding control module decodes the DDR test instruction to obtain all sub-test instructions in the DDR test instruction, and sends all sub-test instructions to the DDR control module; The DDR control module converts all sub-test instructions into control signals that comply with a specified interface protocol, and performs test operations on the DDR under test through the DDR physical layer.

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