A high frequency driving circuit based on a switching device and a control method thereof
By designing a high-frequency driving circuit based on switching devices, using signal input module, buffer module and delay control module to control the delay time, the edge overcharge and undershoot problems of switching devices at high frequency are solved, and the switching devices are realized Optimal operating performance at high frequencies.
Patent Information
- Application Number
- CN202311863860.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-29
- Publication Date
- 2024-12-17
- Estimated Expiration
- 2043-12-29
AI Technical Summary
The prior art has serious edge overcharge and undershoot problems in switching devices at high frequencies, resulting in a decrease in the system's operating frequency and cannot effectively solve this problem.
A high-frequency driving circuit based on switching devices is designed, including a signal input module, a buffer module, a driving current dual-channel control module and a delay control module. By controlling the delay time, the optimal overshoot and downshoot amplitude are obtained. , enables the switching device to operate at high frequencies.
It realizes the optimal overshoot and downshoot amplitude control of switching devices at high frequencies, maintains the fastest rising and falling edge speeds when switching devices are turned on, solves the overshoot and downshoot problems, and ensures the high system Frequent working ability.
Smart Images
Figure CN117674800B_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of gate drive circuits, and in particular to a high-frequency drive circuit based on a switching device and a control method thereof. Background Art
[0002] Silicon-based MOS tubes (field effect transistors) and gallium nitride devices are basic components of electronic circuits and are widely used in various electronic products. With the development trend of miniaturization and high frequency of electronic products, the driving technology of silicon-based MOS tubes and gallium nitride devices (collectively referred to as switching devices) is facing more and more challenges, especially when switching devices work at high frequencies, the edge overcharge and undershoot problems are becoming more and more serious.
[0003] The existing gate drive technology method will produce undershoot when the switching tube gate is discharged due to the influence of parasitic inductance and gate capacitance during rapid discharge, and then a resistor is connected in series with the gate to weaken the oscillation, thereby reducing overcharging and undershoot. However, it also reduces the operating frequency of the system, making the switching device unable to operate at high frequency.
[0004] In summary, the technical problems existing in the relevant technologies need to be improved. Summary of the invention
[0005] The main purpose of the embodiments of the present application is to propose a high-frequency driving circuit based on a switching device and a control method thereof, which can obtain the optimal overshoot and undershoot amplitudes by controlling the delay time and enable the switching device to operate at a high frequency.
[0006] To achieve the above-mentioned purpose, an embodiment of the present application provides a high-frequency driving circuit based on a switching device in one aspect, wherein the high-frequency driving circuit comprises a signal input module, a buffer module, a driving current dual-channel control module and a delay control module, wherein the output end of the signal input module is connected to the input end of the buffer module, the first output end of the buffer module is connected to the first input end of the driving current dual-channel control module, the second output end of the buffer module is connected to the input end of the delay control module, and the output end of the delay control module is connected to the second input end of the driving current dual-channel control module, wherein:
[0007] The signal input module is used to obtain a pulse input signal and an enable signal, and output a pulse control signal;
[0008] The buffer module is used to obtain the pulse control signal and perform splitting processing to obtain a first pulse control signal and a second pulse control signal;
[0009] The delay control module is used to generate a delay control signal;
[0010] The driving current dual-channel control module is used to obtain the first pulse control signal and the second pulse control signal, and control the output of the first pulse control signal and the second pulse control signal according to the delay control signal to obtain a driving signal.
[0011] In some embodiments, the signal input module includes a first Schmitt trigger, a second Schmitt trigger and a three-input NAND gate unit, wherein the input end of the first Schmitt trigger is connected to the non-inverting input end of the pulse input signal, the input end of the second Schmitt trigger is connected to the inverting input end of the pulse input signal, the output end of the first Schmitt trigger is connected to the first input end of the three-input NAND gate unit, the output end of the second Schmitt trigger is connected to the second input end of the three-input NAND gate unit, the third input end of the three-input NAND gate unit is connected to the enable signal, and the output end of the three-input NAND gate unit is connected to the input end of the buffer module.
[0012] In some embodiments, the buffer module includes a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter and a sixth inverter, wherein the input end of the first inverter is connected to the output end of the three-input NAND gate unit, the first output end of the first inverter is connected to the input end of the second inverter, the second output end of the first inverter is connected to the input end of the third inverter, the output end of the second inverter is connected to the input end of the drive current dual-channel control module, the first output end of the third inverter is respectively connected to the input end of the fourth inverter and the delay control module, the output end of the fourth inverter is connected to the input end of the fifth inverter, the output end of the fifth inverter is connected to the input end of the sixth inverter, and the output end of the sixth inverter is connected to the input end of the drive current dual-channel control module.
[0013] In some embodiments, the delay control module includes a first thermometer code unit, a second thermometer code unit, a plurality of PMOS tubes, a plurality of NMOS tubes and a first capacitor, wherein the input end of the first thermometer code unit is connected to the first code value signal, the input end of the second thermometer code unit is connected to the second code value signal, the output end of the first thermometer code unit is connected to the gate of the PMOS tube, the output end of the second thermometer code unit is connected to the gate of the NMOS tube, the source of the PMOS tube, the drain of the NMOS tube, the output end of the third inverter and the input end of the fourth inverter are connected, the drain of the PMOS tube, the source of the NMOS tube and the first end of the first capacitor are connected, and the second end of the first capacitor is connected to the driving current dual-channel control module.
[0014] In some embodiments, the driving current dual-channel control module includes a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a first resistor and a second resistor, wherein the gate of the first MOS tube and the gate of the fourth MOS tube are connected to the output end of the second inverter, the source of the first MOS tube is connected to a high level, the drain of the first MOS tube, the first end of the first resistor and the source of the second MOS tube are connected, the gate of the second MOS tube and the gate of the third MOS tube are connected to the output end of the sixth inverter, the drain of the second MOS tube, the second end of the first resistor, the drain of the third MOS tube and the first end of the second resistor are connected and connected to the final output endpoint, the source of the third MOS tube, the second end of the second resistor and the drain of the fourth MOS tube are connected, and the source of the fourth MOS tube is connected to the second end of the first capacitor and grounded.
[0015] In some embodiments, the driving current dual-channel control module also includes a charging current dual channel at the rising edge of the switching device gate and a discharging current dual channel at the falling edge of the switching device gate, wherein the charging current dual channel at the rising edge of the switching device gate is composed of the second MOS tube and the first resistor, and the discharging current dual channel at the falling edge of the switching device gate is composed of the third MOS tube and the second resistor.
[0016] To achieve the above object, another aspect of the embodiment of the present application provides a control method of a high-frequency drive circuit based on a switching device, the method comprising:
[0017] Obtain pulse input signal and enable signal, and output pulse control signal;
[0018] Acquire the pulse control signal and perform splitting processing to obtain a first pulse control signal and a second pulse control signal;
[0019] Acquire a first code value signal and a second code value signal to generate a delay control signal;
[0020] According to the first pulse control signal and the second pulse control signal, and by controlling the output of the first pulse control signal and the second pulse control signal through the delay control signal, a driving signal is obtained, and the driving signal includes a charging current driving signal and a discharging current driving signal.
[0021] In some embodiments, the first code value signal is used to control the rising edge of the dual channels of the charging current, and the second code value signal is used to control the falling edge of the dual channels of the discharging current.
[0022] In some embodiments, when the driving signal is the charging current driving signal, it includes:
[0023] The charging current driving signal performs charging processing on the device to be charged through the first charging channel and the final output endpoint, and the first charging channel includes the first MOS transistor and the second MOS transistor;
[0024] Until the gate of the first MOS tube and the gate of the second MOS tube reach a first preset charging voltage threshold, the charging current driving signal charges the device to be charged through the second charging channel and the final output endpoint, and the second charging channel includes the first MOS tube and the first resistor;
[0025] Charging is completed until the gate of the first MOS tube reaches a second preset charging voltage threshold.
[0026] In some embodiments, when the driving signal is the discharge current driving signal, it includes:
[0027] The discharge current driving signal performs discharge processing on the device to be discharged through the first discharge channel and the final output terminal, and the first discharge channel includes the third MOS tube and the fourth MOS tube;
[0028] Until the gate of the third MOS tube and the gate of the fourth MOS tube reach a first preset discharge voltage threshold, the discharge current driving signal performs discharge processing on the device to be discharged through the second discharge channel and the final output endpoint, and the second discharge channel includes the fourth MOS tube and the second resistor;
[0029] The discharge is completed until the gate of the fourth MOS tube reaches the second preset discharge voltage threshold.
[0030] The embodiments of the present application include at least the following beneficial effects: The present application provides a high-frequency driving circuit based on a switching device and a control method thereof. The scheme obtains a pulse input signal and an enable signal through a signal input module, outputs a pulse control signal, and further divides the pulse control signal into two paths through a buffer module. Since the transmission time of the signal in the two paths is different, the transistors can be turned on at the same time, or the transistors can be turned on with a delay before and after. The delay time is then controlled by a delay control module, achieving optimal delay time control, thereby obtaining the optimal overshoot and undershoot amplitudes. Finally, the drive current dual-channel control module outputs the drive control signal, so that the switching device can operate at a high frequency. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] Figure 1 is a structural schematic diagram of a high-frequency driving circuit based on a switching device provided in an embodiment of the present application;
[0032] Figure 2It is a structural schematic diagram of an existing gate drive circuit;
[0033] Figure 3 It is a schematic diagram of the application structure of the existing gate drive circuit in the laser radar transmitting circuit;
[0034] Figure 4 This is a schematic diagram of the application structure of a high-frequency driving circuit based on a switching device in a laser radar transmitting circuit according to an embodiment of the present application;
[0035] Figure 5 It is a schematic diagram of the steps of a control method of a high-frequency drive circuit based on a switching device provided in an embodiment of the present application. DETAILED DESCRIPTION
[0036] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below in conjunction with the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the embodiments of the present application. They are only examples of devices and methods consistent with some aspects of the embodiments of the present application as detailed in the attached claims.
[0037] It is understood that the terms "first", "second", etc. used in this application can be used to describe various concepts in this article, but unless otherwise specified, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another concept. For example, without departing from the scope of the embodiment of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the words "if" and "if" as used herein can be interpreted as "at the time of" or "when" or "in response to determination".
[0038] The terms "at least one", "multiple", "each", "any", etc. used in this application, at least one includes one, two or more, multiple includes two or more, each refers to each of the corresponding multiple, and any refers to any one of the multiple.
[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.
[0040] Existing gate drive circuits such as Figure 2As shown in the figure, the core circuit mainly consists of a buffer composed of multiple inverters, and the last stage is used to drive the gate of the switching device. When the switching device needs to be turned on, the upper tube of the last inverter is turned on, and the power is added to the gate of the switching device from VDD through the upper tube. At this time, due to the existence of gate capacitance and parasitic inductance, overcharge oscillation will occur. When the switching device needs to be turned off, the lower tube of the last inverter will be turned on, and the upper tube will be turned off at the same time. The gate voltage of the switching device is conducted from the lower tube to the bottom for rapid discharge. Also due to the influence of parasitic inductance and gate capacitance, undershoot will occur when the gate of the switching tube is discharged.
[0041] In order to solve the overshoot and undershoot problems, such as Figure 3 As shown, the prior art idea is to connect a resistor in series with the gate to weaken the oscillation through the resistor, thereby reducing overcharging and undershoot, but at the same time it will cause the gate of the switching device to slow down during the voltage rise and fall process, which is not conducive to high-frequency working environments and reduces the operating frequency of the system.
[0042] Based on this, the embodiment of the present invention provides a high-frequency gate driver chip for a switching device that can control overshoot and undershoot technology, and can adjust the amplitude of overshoot and undershoot caused by parasitic capacitance and gate capacitance when the switching device is turned on and off. At the same time, the embodiment of the present invention will not affect the driving ability of the driving circuit, and the rising edge when the switching device is turned on and the falling edge when it is turned off can still be maintained at the fastest level, which can not only solve the overshoot and undershoot problems when the gate voltage rises and falls, but also keep the change speed of the gate voltage as fast as possible when it rises and falls.
[0043] Reference Figure 1 , Figure 1 A schematic diagram of a high-frequency driving circuit based on a switching device provided in an embodiment of the present invention, referring to Figure 1 The high-frequency driving circuit includes a signal input module, a buffer module, a driving current dual-channel control module and a delay control module. The output end of the signal input module is connected to the input end of the buffer module, the first output end of the buffer module is connected to the first input end of the driving current dual-channel control module, the second output end of the buffer module is connected to the input end of the delay control module, and the output end of the delay control module is connected to the second input end of the driving current dual-channel control module, wherein:
[0044] The signal input module is used to obtain the pulse input signal and the enable signal, and output the pulse control signal;
[0045] It should be noted that, in some embodiments, the signal input module includes a first Schmitt trigger T1, a second Schmitt trigger T2 and a three-input NAND gate unit AND1, wherein the input end of the first Schmitt trigger is connected to the non-inverting input end of the pulse input signal, the input end of the second Schmitt trigger is connected to the inverting input end of the pulse input signal, the output end of the first Schmitt trigger is connected to the first input end of the three-input NAND gate unit, the output end of the second Schmitt trigger is connected to the second input end of the three-input NAND gate unit, the third input end of the three-input NAND gate unit is connected to the enable signal, and the output end of the three-input NAND gate unit is connected to the input end of the buffer module.
[0046] In some specific embodiments, the function of the input module of the embodiment of the present invention is to collect the input pulse signal, IN+ and IN- are respectively the in-phase input terminal and the inverting input terminal of the input signal pulse, and the EN terminal is the signal enable terminal. When the input pulse signal enters from IN+ or IN-, it passes through the first Schmitt trigger T1 or the second Schmitt trigger T2, flows into the three-input NAND gate unit AND1, and then the signal is output from the three-input NAND gate unit AND1 to enter the next buffer module.
[0047] The buffer module is used to obtain the pulse control signal and perform splitting processing to obtain a first pulse control signal and a second pulse control signal;
[0048] It should be noted that, in some embodiments, the buffer module includes a first inverter B0, a second inverter B1, a third inverter B2, a fourth inverter B3, a fifth inverter B4 and a sixth inverter B5, wherein the input end of the first inverter is connected to the output end of the three-input NAND gate unit, the first output end of the first inverter is connected to the input end of the second inverter, the second output end of the first inverter is connected to the input end of the third inverter, the output end of the second inverter is connected to the input end of the driving current dual-channel control module, the first output end of the third inverter is respectively connected to the input end of the fourth inverter and the delay control module, the output end of the fourth inverter is connected to the input end of the fifth inverter, the output end of the fifth inverter is connected to the input end of the sixth inverter, and the output end of the sixth inverter is connected to the input end of the driving current dual-channel control module.
[0049] In some specific embodiments, the module with buffer function will first pass the pulse signal transmitted by the three-input NAND gate unit AND1 through the first inverter B0 unit, and then divide the pulse signal into two paths, the first path signal enters the second inverter B1, and the second path signal enters the third inverter B2. The signal output by the second inverter B1 is used to control the common gate of the first transistor Q1 and the fourth transistor Q4. After the second path signal enters the third inverter B2, it passes through the fourth inverter B3, the fifth inverter B4 and the sixth inverter B5 units, and is connected to the common gate of the second transistor Q2 and the third transistor Q3. Since the transmission time of the signal in the two paths is different, the first transistor Q1 and the second transistor Q2, the third transistor Q3 and the fourth transistor Q4 can be turned on at the same time, or they can be turned on with a delay before and after. The delay time of the signal in the second inverter B1 of the first path is faster than the delay time in the second path. We can control the delay time of the signal between the third inverter B2, the fourth inverter B3, the fifth inverter B4 and the sixth inverter B5, and thus control the delay time between the first transistor Q1 and the second transistor Q2, and between the third transistor Q3 and the fourth transistor Q4.
[0050] The delay control module is used to obtain the first code value signal and the second code value signal to generate a delay control signal;
[0051] It should be noted that, in some embodiments, the delay control module includes a first thermometer code unit, a second thermometer code unit, a plurality of PMOS tubes, a plurality of NMOS tubes and a first capacitor, wherein the input end of the first thermometer code unit is connected to the first code value signal, the input end of the second thermometer code unit is connected to the second code value signal, the output end of the first thermometer code unit is connected to the gate of the PMOS tube, the output end of the second thermometer code unit is connected to the gate of the NMOS tube, the source of the PMOS tube, the drain of the NMOS tube, the output end of the third inverter and the input end of the fourth inverter are connected, the drain of the PMOS tube, the source of the NMOS tube and the first end of the first capacitor are connected, and the second end of the first capacitor is connected to the driving current dual-channel control module.
[0052] In some specific embodiments, in the delay control module, IN0-IN4 is a set of code values, which controls the OUT pin, i.e., the final output endpoint, when driving the rising edge of the switching device, and the opening time point of the second transistor Q2 is delayed after the time of the first transistor Q1. It also represents the amplitude of overshoot. The longer the delay, the higher the overshoot amplitude.
[0053] IN5-IN9 is another set of code values, which controls the gate falling edge of the OUT pin driving the switch device, and the opening time point of the third transistor Q3 is delayed after the fourth transistor Q4. It also represents the amplitude of the undershoot. The longer the delay, the higher the undershoot amplitude. By giving different input code values to IN0-IN9, the best delay time control is achieved, so that the best overshoot and undershoot amplitude can be obtained.
[0054] The driving current dual-channel control module is used to control the output of the first pulse control signal and the second pulse control signal according to the first pulse control signal and the second pulse control signal through the delay control signal to obtain a driving signal, and the driving signal includes a charging current driving signal and a discharging current driving signal.
[0055] It should be noted that, in some embodiments, the driving current dual-channel control module includes a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a first resistor and a second resistor, wherein the gate of the first MOS tube and the gate of the fourth MOS tube are connected to the output end of the second inverter, the source of the first MOS tube is connected to a high level, the drain of the first MOS tube, the first end of the first resistor and the source of the second MOS tube are connected, the gate of the second MOS tube, the gate of the third MOS tube and the output end of the sixth inverter are connected, the drain of the second MOS tube, the second end of the first resistor, the drain of the third MOS tube and the first end of the second resistor are connected and connected to the final output endpoint, the source of the third MOS tube, the second end of the second resistor and the drain of the fourth MOS tube are connected, and the source of the fourth MOS tube is connected to the second end of the first capacitor and grounded.
[0056] Furthermore, the driving current dual-channel control module also includes a charging current dual channel at the rising edge of the switching device gate and a discharging current dual channel at the falling edge of the switching device gate, wherein the charging current dual channel at the rising edge of the switching device gate is composed of a second MOS tube and a first resistor, and the discharging current dual channel at the falling edge of the switching device gate is composed of a third MOS tube and a second resistor.
[0057] In some specific embodiments, the driving current dual-channel control module is the last-stage driving circuit in the high-frequency driving circuit of the embodiment of the present invention, and includes four MOS tubes and two resistors, namely, the first resistor R1, the second resistor R2, the first transistor Q1, the second transistor Q2, the third transistor Q3 and the fourth transistor Q4. The second transistor Q2 and the first resistor R1 constitute a dual-channel charging current at the rising edge of the gate of the switching device. The third transistor Q3 and the second resistor R2 constitute a dual-channel discharge current at the falling edge of the gate of the switching device.
[0058] See also Figure 5The embodiment of the present application further provides a control method of a high-frequency driving circuit based on a switching device, which can realize the above-mentioned high-frequency driving circuit based on a switching device, and the method includes:
[0059] S100, obtaining a pulse input signal and an enable signal, and outputting a pulse control signal;
[0060] S200, acquiring a pulse control signal and performing splitting processing to obtain a first pulse control signal and a second pulse control signal;
[0061] S300, obtaining a first code value signal and a second code value signal, and generating a delay control signal;
[0062] It should be noted that the first code value signal is used to control the rising edge of the dual channels of the charging current, and the second code value signal is used to control the falling edge of the dual channels of the discharging current.
[0063] S400, according to the first pulse control signal and the second pulse control signal, and controlling the output of the first pulse control signal and the second pulse control signal through the delay control signal, to obtain a drive signal, wherein the drive signal includes a charging current drive signal and a discharging current drive signal;
[0064] It should be noted that, in some embodiments, when the driving signal is a charging current driving signal, the charging current driving signal charges the device to be charged through the first charging channel and the final output endpoint, the first charging channel includes a first MOS tube and a second MOS tube, until the gate of the first MOS tube and the gate of the second MOS tube reach a first preset charging voltage threshold, the charging current driving signal charges the device to be charged through the second charging channel and the final output endpoint, the second charging channel includes a first MOS tube and a first resistor, until the gate of the first MOS tube reaches a second preset charging voltage threshold, and charging is completed.
[0065] Specifically, Figure 4As shown, the OUT pin in the embodiment of the present invention, that is, the final output terminal, is connected to the gate of the switching device. The high-frequency driving circuit in the embodiment of the present invention charges the gate of the switching device through the OUT pin, and is further divided into two stages. In the first stage, when the gate voltage starts from 0V to 90% VDD, the current channel at this time is, starting from VDD, passing through the first transistor Q1, the second transistor Q2 and the parasitic inductance L, and finally reaching the gate to charge the gate capacitance. At this time, due to the lack of the influence of the series resistor, the speed of VDD charging the gate capacitance is very fast, and the speed of the gate voltage rising edge is pulled up with the maximum capacity of the driving circuit. When the gate voltage reaches 90% VDD, the second transistor Q2 is turned off, and the charging current is switched to the second channel, that is, from VDD through the first transistor Q1, the first resistor R1 and the parasitic inductance L, and finally reaches the gate. The current continues to charge the gate capacitance. Due to the existence of the first resistor R1 at this time, when the gate voltage rises to VDD, the overshoot generated by the oscillation will be suppressed by the first resistor R1. Therefore, the overshoot of the gate will not be significantly generated, and the rising and falling speeds of the gate voltage of the switching device can still be maintained at the fastest.
[0066] In some embodiments, when the driving signal is a discharge current driving signal, the discharge current driving signal performs discharge processing on the device to be discharged through a first discharge channel and a final output endpoint, and the first discharge channel includes a third MOS tube and a fourth MOS tube; until the gate of the third MOS tube and the gate of the fourth MOS tube reach a first preset discharge voltage threshold, the discharge current driving signal performs discharge processing on the device to be discharged through a second discharge channel and a final output endpoint, and the second discharge channel includes a fourth MOS tube and a second resistor; until the gate of the fourth MOS tube reaches a second preset discharge voltage threshold, the discharge is completed.
[0067] Specifically, Figure 4 As shown, the OUT pin in the embodiment of the present invention, i.e., the final output terminal, is also divided into two stages when discharging the gate of the switching device. In the first stage, when the gate voltage starts from VDDV to 10% VDD, the discharge channel of the gate current is, starting from the gate capacitor C, passing through the parasitic inductance L, the third transistor Q3 and the fourth transistor Q4 in sequence, and finally the gate current is discharged to the ground. At this time, due to the lack of the influence of the series resistor, the gate capacitor discharge speed is also very fast, and the speed of the gate voltage rising edge is pulled down at the maximum capacity of the driving circuit. When the gate voltage reaches 10% VDD, the third transistor Q3 is turned off, and the charging current is switched to the second channel, i.e., from the gate C through the parasitic inductance L, the second resistor R2 and the fourth transistor Q4, and finally reaches GND. At this time, the discharge current continues to discharge the gate capacitor, but due to the presence of the second resistor R2 at this time, when the gate voltage drops to GND, the undershoot generated by the oscillation will be suppressed by the second resistor R2, so the gate undershoot will not be significantly generated.
[0068] Further elaboration based on the application of the high-frequency driving circuit of the embodiment of the present invention, the high-frequency driving circuit of the embodiment of the present invention can be used in the transmitting module as a driving solution for the laser and gallium nitride to increase the operating frequency, improve the working reliability of gallium nitride, and improve the accuracy of the laser radar. The high-frequency driving circuit of the embodiment of the present invention can also be used in a switching power supply circuit operating at a high frequency, and is particularly suitable for application fields that are sensitive to gate overshoot and undershoot, such as switching power supply products in the field of household appliances such as televisions and refrigerators that use gallium nitride as a switching device.
[0069] The application of laser radar system is explained as follows: Figure 4 As shown, L1, L2 and L3 are parasitic inductances of the circuit board. The embodiment of the present invention drives the GaN switch device so that the GaN-connected laser can work in a narrow pulse, high frequency, and high power working mode. At the same time, the GaN device can work in a high reliability environment.
[0070] It can be understood that the contents of the above method embodiments are all applicable to the present circuit embodiment, the functions specifically implemented by the present circuit embodiment are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.
[0071] The preferred embodiments of the present invention are described above with reference to the accompanying drawings, but the scope of the rights of the present invention is not limited thereto. Any modification, equivalent substitution and improvement made by a person skilled in the art without departing from the scope and essence of the present invention should be within the scope of the rights of the present invention.
Claims
1. A high-frequency drive circuit based on a switching device, It is characterized in that The high-frequency driving circuit includes a signal input module, a buffer module, a driving current dual-channel control module and a delay control module, wherein the output end of the signal input module is connected to the input end of the buffer module, the first output end of the buffer module is connected to the first input end of the driving current dual-channel control module, the second output end of the buffer module is connected to the input end of the delay control module, and the output end of the delay control module is connected to the second input end of the driving current dual-channel control module, wherein: The signal input module is used to obtain a pulse input signal and an enable signal, and output a pulse control signal; The buffer module is used to obtain the pulse control signal and perform splitting processing to obtain a first pulse control signal and a second pulse control signal; Wherein, the buffer module includes a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter and a sixth inverter, wherein the input end of the first inverter is connected to the output end of the three-input NAND gate unit, the first output end of the first inverter is connected to the input end of the second inverter, the second output end of the first inverter is connected to the input end of the third inverter, the output end of the second inverter is connected to the input end of the driving current dual-channel control module, the first output end of the third inverter is respectively connected to the input end of the fourth inverter and the delay control module, the output end of the fourth inverter is connected to the input end of the fifth inverter, the output end of the fifth inverter is connected to the input end of the sixth inverter, and the output end of the sixth inverter is connected to the input end of the driving current dual-channel control module; The delay control module is used to obtain the first code value signal and the second code value signal to generate a delay control signal; Wherein, the delay control module includes a first thermometer code unit, a second thermometer code unit, a plurality of PMOS tubes, a plurality of NMOS tubes and a first capacitor, wherein the input end of the first thermometer code unit is connected to the first code value signal, the input end of the second thermometer code unit is connected to the second code value signal, the output end of the first thermometer code unit is connected to the gate of the PMOS tube, the output end of the second thermometer code unit is connected to the gate of the NMOS tube, the source of the PMOS tube, the drain of the NMOS tube, the output end of the third inverter and the input end of the fourth inverter are connected, the drain of the PMOS tube, the source of the NMOS tube and the first end of the first capacitor are connected, and the second end of the first capacitor is connected to the driving current dual-channel control module; The driving current dual-channel control module is used to control the output of the first pulse control signal and the second pulse control signal according to the first pulse control signal and the second pulse control signal through the delay control signal to obtain a driving signal, wherein the driving signal includes a charging current driving signal and a discharging current driving signal.
2. The high frequency driving circuit according to claim 1, It is characterized in that The signal input module includes a first Schmitt trigger, a second Schmitt trigger and a three-input NAND gate unit, wherein the input end of the first Schmitt trigger is connected to the non-inverting input end of the pulse input signal, the input end of the second Schmitt trigger is connected to the inverting input end of the pulse input signal, the output end of the first Schmitt trigger is connected to the first input end of the three-input NAND gate unit, the output end of the second Schmitt trigger is connected to the second input end of the three-input NAND gate unit, the third input end of the three-input NAND gate unit is connected to the enable signal, and the output end of the three-input NAND gate unit is connected to the input end of the buffer module.
3. The high frequency driving circuit according to claim 1, It is characterized in that The driving current dual-channel control module includes a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a first resistor and a second resistor, wherein the gate of the first MOS tube and the gate of the fourth MOS tube are connected to the output end of the second inverter, the source of the first MOS tube is connected to a high level, the drain of the first MOS tube, the first end of the first resistor and the source of the second MOS tube are connected, the gate of the second MOS tube and the gate of the third MOS tube are connected to the output end of the sixth inverter, the drain of the second MOS tube, the second end of the first resistor, the drain of the third MOS tube and the first end of the second resistor are connected and connected to a final output endpoint, the source of the third MOS tube, the second end of the second resistor and the drain of the fourth MOS tube are connected, and the source of the fourth MOS tube is connected to the second end of the first capacitor and grounded.
4. The high frequency driving circuit according to claim 3, It is characterized in that The driving current dual-channel control module also includes a charging current dual channel at the rising edge of the switching device gate and a discharging current dual channel at the falling edge of the switching device gate, wherein the charging current dual channel at the rising edge of the switching device gate is composed of the second MOS tube and the first resistor, and the discharging current dual channel at the falling edge of the switching device gate is composed of the third MOS tube and the second resistor.
5. A control method for a high-frequency drive circuit based on a switching device is applied to a high-frequency drive circuit based on a switching device as claimed in claim 1, It is characterized in that The method comprises: Obtain pulse input signal and enable signal, and output pulse control signal; Acquire the pulse control signal and perform splitting processing to obtain a first pulse control signal and a second pulse control signal; Acquire a first code value signal and a second code value signal to generate a delay control signal; According to the first pulse control signal and the second pulse control signal, and by controlling the output of the first pulse control signal and the second pulse control signal through the delay control signal, a driving signal is obtained, and the driving signal includes a charging current driving signal and a discharging current driving signal.
6. The method according to claim 5, It is characterized in that The first code value signal is used to control the rising edge of the dual channels of the charging current, and the second code value signal is used to control the falling edge of the dual channels of the discharging current.
7. The method according to claim 5, It is characterized in that When the driving signal is the charging current driving signal, it includes: The charging current driving signal performs charging processing on the device to be charged through the first charging channel and the final output endpoint, wherein the first charging channel includes a first MOS transistor and a second MOS transistor; Until the gate of the first MOS tube and the gate of the second MOS tube reach a first preset charging voltage threshold, the charging current driving signal charges the device to be charged through the second charging channel and the final output endpoint, and the second charging channel includes the first MOS tube and the first resistor; Charging is completed until the gate of the first MOS tube reaches a second preset charging voltage threshold.
8. The method according to claim 5, It is characterized in that When the driving signal is the discharge current driving signal, it includes: The discharge current driving signal performs discharge processing on the device to be discharged through the first discharge channel and the final output terminal, and the first discharge channel includes a third MOS tube and a fourth MOS tube; Until the gate of the third MOS tube and the gate of the fourth MOS tube reach a first preset discharge voltage threshold, the discharge current driving signal performs discharge processing on the device to be discharged through the second discharge channel and the final output terminal, and the second discharge channel includes the fourth MOS tube and the second resistor; The discharge is completed until the gate of the fourth MOS tube reaches the second preset discharge voltage threshold.