All common word line OTP memory circuit

Abstract

The invention discloses a fully common word line OTP memory circuit, and relates to integrated circuit technology. The invention comprises a decoder and N OTP memory units, wherein the OTP memory unit comprises a storage MOS tube, a selection MOS tube and a detection MOS tube; the first current connection end of the detection MOS tube is connected to the first bit line of the unit, and the decoder is a tree structure, and the tree structure comprises at least two subtree layers, each subtree comprises two branches, and the two branches are connected to a node, and a switch MOS tube is arranged between the end of each branch and the node; in two adjacent layers, the node of the upper subtree is connected to the end of the branch of the lower subtree, and the end of the branch of the top layer is connected to the first bit line of each OTP memory unit one by one; the gate of the switch MOS tube is led out through a connecting line. The circuit and operation of the invention are simpler than those of the prior art, and the cost and reliability are improved.

Description

Technical Field

[0001] The present invention relates to integrated circuit technology, in particular to OTP memory technology. Background Art

[0002] Chinese patent document CN114678054A discloses a method for reading and writing an OTP memory array. In the document, an OTP memory array is also disclosed. Figure 1 and Figure 2 In this document, the high-voltage related paths of all cells, such as WP, WB (WBH, WBL, etc.), can be globally connected and shared. The high-voltage paths do not require row selectors, so row selectors can be saved, but WS and WR still need row decoders, see Figure 4 Correspondingly, the programming state table is also relatively complex, and four states need to be considered, as shown in Table 1:

[0003] Table 1

[0004]

[0005] In Table 1, SW indicates that a word line is selected, SB indicates that a bit line is selected, UW indicates that a word line is not selected, and UB indicates that a bit line is not selected. Summary of the invention

[0006] The technical problem to be solved by the present invention is to provide a full common word line OTP memory circuit which does not require a row decoder and has better high voltage impact resistance.

[0007] The technical solution adopted by the present invention to solve the technical problem is that a full common word line OTP memory circuit includes a decoder and N OTP memory units, wherein the OTP memory unit includes a storage MOS tube, a selection MOS tube and a detection MOS tube; a first current connection end of the detection MOS tube is connected to a first bit line of the unit, a second current connection end is connected to a second bit line of the unit, and a control end is connected to a reference point; a current connection end of the storage MOS tube is connected to a reference point; a current connection end of the selection MOS tube is connected to a reference point, and another current connection end is connected to the first bit line of the unit; the decoder is a tree structure, and the tree structure includes at least two subtree layers, each subtree includes two branches, the two branches are connected to a node, and a switch MOS tube is arranged between the end of each branch and the node; in two adjacent layers, the node of the upper subtree is connected to the branch end of the lower subtree, and the branch end of the top layer is connected to the first bit line of each OTP memory unit in a one-to-one correspondence; the gate of the switch MOS tube is led out through a connecting line.

[0008] The decoder has an N-layer structure, where N is a preset natural number, and the Nth layer includes 2 parallel N A subtree.

[0009] The OTP memory unit further comprises a voltage-dividing MOS tube, and the voltage-dividing MOS tube is arranged between the storage MOS tube and the selection MOS tube.

[0010] The voltage-dividing MOS tube and the storage MOS tube are both intrinsic MOS tubes.

[0011] The gates of all the selection MOS tubes are connected to a common selection word line WS; the gates of all the storage MOS tubes are connected to a common storage word line WP; and the gates of all the voltage-dividing MOS tubes are connected to a common first voltage-dividing word line WB1.

[0012] The beneficial effects of the present invention include:

[0013] 1. The peripheral circuit does not need to be equipped with a high-voltage device for processing the 6.5V voltage of the unselected cell row line;

[0014] 2. The column-selected MOS tube also assumes the voltage-dividing function, eliminating the need for a first-level voltage-dividing tube. When writing, the column-selected MOS tube acts as a first-level voltage-dividing tube to isolate a portion of the high voltage.

[0015] 3. The present invention adopts a 1xN array, each memory cell uses a separate bit line (column line), and address selection is performed through the bit line. The row lines of all memory cells are shared, and no row line driver or row decoder is required.

[0016] 4. The programming operation is simpler and the programming table is simpler, with only two options: column selected and column unselected.

[0017] The circuit and operation of the present invention are simpler than those of the prior art, and the cost and reliability are improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a schematic diagram of the first storage unit structure of the prior art.

[0019] Figure 2 It is a schematic diagram of the storage unit structure of the second prior art.

[0020] Figure 3 It is a schematic diagram of a storage array of the first prior art.

[0021] Figure 4 It is a schematic diagram of a storage array of the second prior art.

[0022] Figure 5 It is a schematic diagram of the storage unit structure used in the present invention.

[0023] Figure 6 It is a schematic diagram of the overall structure of the present invention. DETAILED DESCRIPTION

[0024] See also Figure 5 The storage unit of the present invention adopts Figure 5 The structure shown in the Chinese patent document CN114678054A Figure 3 The storage cell array is in the form of 1 row and N columns. The column decoder adopts the decoder as a tree structure, and the tree structure includes at least two subtree layers.

[0025] Specifically, each subtree of the decoder includes two branches, the two branches are connected to the node, and a switch MOS tube is arranged between the end of each branch and the node; in two adjacent layers, the node of the upper subtree is connected to the end of the branch of the lower subtree, and the end of the branch of the top layer is connected to the first bit line of each OTP memory unit one by one; the gate of the switch MOS tube is led out through a connecting line.

[0026] See also Figure 6 ,A subtree consists of two branches and a trunk, and the connection point between the branches and the trunk is called a node. The branches have switching MOS tubes, and the nodes can be regarded as the trunk.

[0027] The decoder has an N-layer structure, where N is a preset natural number. The Nth layer includes 2 parallel N A subtree. Figure 6 A decoder with a 3-layer structure (N=3) is shown.

[0028] Figure 6 The structure of the OTP memory cell is shown in Figure 5 The OTP memory unit includes a voltage-dividing MOS transistor Twb1 disposed between the storage MOS transistor Twp and the selection MOS transistor Tws. The voltage-dividing MOS transistor and the storage MOS transistor are both intrinsic MOS transistors.

[0029] The gates of all selection MOS tubes are connected to a common selection word line WS, the gates of all storage MOS tubes are connected to a common storage word line WP, and the gates of all voltage-dividing MOS tubes are connected to a common first voltage-dividing word line WB1.

[0030] BR and BL are bit lines.

[0031] Table 2

[0032]

[0033] Table 2 is a table of programming operation voltages of the circuit of the present invention based on 110 nm technology.

[0034] Among them, SB means the bit line is selected, and UB means the bit line is not selected. A and B are the target units of the operation. Pulse is the pulse signal of clearing. Vsen is the preset detection level, "1.5 / float" means 1.5V or floating, and "0 / float" means the same.

[0035] Comparing Table 1 and Table 2, it can be seen that the unit of the present invention has only two states, the operation is simpler, and there is no row selection.

[0036] The significance of the present invention will be described in detail below.

[0037] First, as a kind of prior art, in Figure 3 As shown ( Figure 4 Similarly, when programming (writing) multi-row and multi-column storage cells, taking the programming of C cell as an example, the row is selected by raising the level of the row line WP2 of the row where the C cell is located, and the row line WP1 of the row where the unselected A cell is located cannot be raised. Therefore, it is necessary to use an external switch tube to decide whether to apply a high level, and the external switch tube must be able to withstand high voltage. With the present invention, the selection of the programming object can be achieved through column selection, and the row line WP is always at a high level without switching, and no row decoder is required. At the same time, compared with Figure 4 The prior art shown saves an external switch tube.

[0038] Secondly, the present invention properly solves the contradiction between GIDL leakage protection and chip circuit complexity.

[0039] GIDL leakage (gate-induced drain leakage) refers to the gate-induced drain leakage current, which is related to the voltage difference between the drain and the gate. For a 1.5V low-voltage tube, when the drain voltage is higher than the gate voltage by more than 2.5V, GIDL leakage will occur, which is harmful to the operation of the chip.

[0040] Figure 2 The cell array shown is Figure 4 shown. Figure 4In the case of WP=6.5V, two-stage voltage divider tubes are required to avoid GIDL leakage. Specifically, after the WP capacitor Cc of the C unit breaks down, the drain level of the first voltage divider tube Mbhc is 6.5v. In order to avoid GIDL leakage, the gate level should be as low as 4v; accordingly, the drain level of the second voltage divider tube Mblc should also be as low as 4v. If GIDL leakage does not occur, the gate level should be as low as 1.5v; accordingly, the source level of the second voltage divider tube Mblc is as low as 1.5v, and the source is connected to the g point of the detection MOS tube M0 in the C unit. The drain-gate voltage difference of the MOS tube (detection MOS tube) with the gate marked as g in the C unit is 1.5v, which is lower than the voltage difference of 2.5v required to generate GIDL. That is, two-stage voltage divider tubes must be used to avoid GIDL leakage.

[0041] And adopt Figure 6 The technology of the present invention is shown in FIG. 1 , because all detection MOS tubes (i.e. Figure 5 The gate voltage of the MOS tube marked as Tsen in the figure is 1.5v, and it can be turned off when BL=1.5V, without using Figure 2 The M4 tube in Figure 4 MOS tubes marked as Mblc and Mbla in FIG. Thus, each unit saves a voltage divider tube, and the complexity of the overall circuit and the chip area are greatly improved.

Claims

1. A fully common word line OTP memory circuit, comprising a decoder and N OTP memory units, N being a preset natural number, wherein the OTP memory unit comprises a storage MOS tube, a selection MOS tube and a detection MOS tube; a first current connection end of the detection MOS tube is connected to a first bit line of the unit, a second current connection end is connected to a second bit line of the unit, and a control end is connected to a reference point; a current connection end of the storage MOS tube is connected to a reference point; a current connection end of the selection MOS tube is connected to a reference point, and another current connection end is connected to a first bit line of the unit; It is characterized in that The OTP memory unit also includes a voltage-dividing MOS tube, which is arranged between the storage MOS tube and the selection MOS tube; the gates of all the selection MOS tubes are connected to a common selection word line WS; the gates of all the storage MOS tubes are connected to a common storage word line WP; the gates of all the voltage-dividing MOS tubes are connected to a common voltage-dividing word line WB1; the selection of the programming object can be realized by column selection, the row line WP is always at a high level without switching, and no row decoder is required; The decoder is a tree structure, which includes at least two subtree layers, each subtree includes two branches, the two branches are connected to the node, and a switch MOS tube is arranged between the end of each branch and the node; in two adjacent layers, the node of the upper subtree is connected to the end of the branch of the lower subtree, and the end of the branch of the top layer is connected to the first bit line of each OTP memory unit in a one-to-one correspondence; the gate of the switch MOS tube is led out through a connecting line; The column-select MOS tube also performs the voltage-dividing function, eliminating the need for a first-level voltage-dividing tube. When writing, the column-select MOS tube acts as a first-level voltage-dividing tube to isolate a portion of the high voltage. This solves the contradiction between GIDL leakage protection and chip circuit complexity.

2. The all-common-word-line OTP memory circuit according to claim 1, wherein: The decoder has an N-layer structure, where N is a preset natural number, and the Nth layer includes 2 parallel N A subtree.

3. The all-common-word-line OTP memory circuit according to claim 1 or 2, characterized in that: The voltage-dividing MOS tube and the storage MOS tube are both intrinsic MOS tubes.

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