A test structure, test method and test system for optical chip

Abstract

The present invention relates to the field of chip testing, specifically to a test structure, test method and test system for an optical chip, wherein the test structure comprises: a circuit board, on which a first substrate is arranged, an optical chip is arranged on the first substrate, the optical chip has a first surface, and the first surface is connected to the first substrate through an isolation guide layer; a plurality of test pins are arranged on the first surface, and the isolation guide layer comprises: an isolation layer for covering at least one test pin, and at least one opening is arranged on the isolation layer, the first end of the opening corresponds to at least one other test pin, an electric wire is arranged in the opening, and the second end of the opening is connected to a guide column connected to the electric wire; a first electric chip is arranged on the first substrate. The test structure can directly connect the optical chip to the substrate, greatly simplifying the preparation process; and the corresponding test method can use the structure to realize local testing of the optical chip, reducing the cost of batch testing.

Description

Technical Field

[0001] The present invention relates to the technical field of chip testing, and in particular to a testing structure, a testing method and a testing system for an optical chip. Background Art

[0002] With the continuous development of big data, artificial intelligence, telemedicine, the Internet of Things, e-commerce, and 5G communications, global data traffic has grown explosively. Lower-cost, more reliable, faster, and higher-density circuits are the goals pursued by integrated circuit packaging.

[0003] For example, the applicant has proposed a high-dimensional matrix optical chip, such as CN116736933A and CN117234276A, whose photon computing unit size is less than 100 μm. However, integrating higher density circuits on optical chips also places extremely high demands on the packaging structure design and testing process of optical chips.

[0004] Among them, for the packaging structure design of this high-dimensional matrix optical chip, the applicant proposed a hybrid packaging structure of optoelectronic chips based on 2.5D packaging technology (see CN117913084A). In order to ensure that the large-scale optical chip has sufficient channels to connect to the wiring layer, so as to realize electrical interconnection with a large number of electrical chips, its photosensitive area is set on the side (that is, the photosensitive area and the optical chip pad are respectively set on different sides), and the optical fiber array is horizontally coupled. In order to facilitate horizontal coupling and avoid the lower side of the optical fiber array after horizontal coupling from hitting the middle layer, the photosensitive area of ​​the large-scale optical chip (that is, the side where the optical interface is set) is extended out of the middle layer so that the optical fiber array is suspended in the air and has a certain gap with the middle layer; and by using a reinforcing layer to increase the thickness of the middle layer, the optical chip, the electrical chip and the middle layer are connected as a whole, thereby not only ensuring better connectivity, but also reducing the uneven stress or collision cracks (i.e. bump) of the middle layer (such as silicon interposer) caused by the center of gravity of the multi-layer structure formed due to the extension of the optical chip out of one side of the middle layer. crack), thereby reducing the risk of warping or cracking.

[0005] However, before packaging, it is also very important to test the quality of the optical chip. Therefore, before the optical chip is packaged or shipped, it is often necessary to perform a performance test on the pins set on it.

[0006] At present, the testing methods for optical chips include:

[0007] 1. Connect the chip to be tested to the substrate by wire bonding

[0008] For example, the invention with publication number CN116338425A proposes a chip testing method and a chip testing structure, including making a test chip, the test chip including a substrate, a test circuit arranged on the substrate and a test pin connected to the test circuit; making a solder pad on the surface of the chip to be tested; and then using a connecting wire to bond the solder pad to the corresponding test pin for testing.

[0009] 2. The indirect connection between the high-dimensional matrix optical chip and the substrate is achieved through an intermediate layer (such as a silicon interposer, Si Interposer), so that the high-density pins in the high-dimensional matrix optical chip can be rearranged and led out through the intermediate layer.

[0010] However, the intermediate layer connection scheme has a complex structure and is more difficult to process, especially when applied to high-dimensional matrix optical chip testing. Higher-density circuits will require more pins (or test pins or test paths) to be densely arranged on the optical chip to achieve signal input and output on the optical chip, which will greatly increase the difficulty of the testing process.

[0011] Therefore, there is an urgent need for a new testing process to perform performance testing on high-density optical chips. Summary of the invention

[0012] The purpose of the present invention is to provide a test structure, test method and test system for an optical chip, which can partially solve or alleviate the above-mentioned deficiencies in the prior art, simplify the test process and reduce the cost of batch testing.

[0013] In order to solve the above-mentioned technical problems, the present invention specifically adopts the following technical solutions:

[0014] A first aspect of the present invention is to provide a chip test structure, comprising:

[0015] Circuit boards;

[0016] A first substrate is provided on the circuit board via a first bonding structure, an optical chip is provided on the first substrate, the optical chip has a first surface, and the first surface is connected to the first substrate via an isolation guide layer; wherein a plurality of test pins are arranged at intervals on the first surface, the isolation guide layer comprises: an isolation layer, the isolation layer is used to cover at least one of the test pins, and the isolation layer is provided with at least one opening, a first end of the opening is provided corresponding to at least one other test pin, an electrical conductor is provided in the opening, the electrical conductor is connected to the corresponding test pin, and a guide column connected to the electrical conductor is provided at the second end of the opening, so as to realize electrical connection between the corresponding test pin and the first substrate;

[0017] A first electrical chip is also disposed on the first substrate, and the first electrical chip is connected to the first substrate via a second bonding structure;

[0018] A second substrate is also provided on the circuit board via a third bonding structure, and a second electrical chip is provided on the second substrate via a fourth bonding structure;

[0019] The first electrical chip is used to input a high-speed signal to the optical chip, and the second electrical chip is used to input a low-speed signal to the optical chip.

[0020] In some embodiments, it also includes:

[0021] An optical fiber array, the optical fiber array comprising: a cover plate and a V-groove, a GC interface is provided in the area of ​​the first surface protruding from the first substrate, and correspondingly, a first surface and a second surface are provided on the side of the V-groove close to the optical chip, the first surface is connected to the GC interface of the optical chip, and the second surface intersects with the plane where the end surface opposite to the first substrate is located; wherein, when the optical fiber array is working, the optical fiber first reaches the second surface, is refracted on the second surface, and then turns to be transmitted to the first surface, and enters the optical chip through the first surface and the GC interface.

[0022] In a second aspect, the present invention further provides a testing method, comprising the steps of:

[0023] S100 provides at least one optical chip to be tested, wherein the optical chip has a first surface, and a plurality of test pins are arranged on the first surface;

[0024] S101, respectively selecting a first test area and a second test area from the first surface, wherein the first test area and the second test area include a plurality of the test pins, and an overlap ratio of the test pins between the first test area and the second test area is less than a preset first ratio;

[0025] S102: testing the optical chip at least once to obtain test data sets of the first test area and the second test area respectively, wherein the test data sets include: output data corresponding to the test pins, and the output data include: connection status, and the connection status includes: connection and disconnection;

[0026] S103 obtains a result distribution index of the test area through the test data set, where the result distribution index includes one or more of the following:

[0027] A first indicator, the first indicator is the number of the test pins in a connected or disconnected state; a second indicator, the second indicator is the proportion of the test pins in a connected or disconnected state in the test area; a third indicator, the third indicator is the position distribution of the test pins in a connected or disconnected state in the test area;

[0028] S104: using a preset matching rule to determine whether the first result distribution index of the first test area matches the second result distribution index of the second test area, wherein when the difference between the first result distribution index and the second result distribution index falls within a preset threshold range, the matching rule considers that the first result distribution index and the second result distribution index match; if so, allowing step S105 to be executed;

[0029] S105: Select a recommended test area from the first test area and the second test area.

[0030] In some embodiments, when the result of S104 is no, the method further includes the following steps:

[0031] S106: selecting a third test area from the first surface, wherein the third test area includes a plurality of the test pins, and the number of the test pins in the third test area is greater than the number of the test pins in the first test area and the second test area, and the overlap ratio of the test pins in the third test area to the first test area and the second test area is less than a preset second ratio;

[0032] S107 obtains a test data set of the third test area;

[0033] S108 obtains a third result distribution index of the third test area through the corresponding test data set;

[0034] S109 uses preset matching rules to respectively determine whether the first result distribution index, the second result distribution index and the third result distribution index match each other; wherein, when the matching results of the first and second result distribution indicators are inconsistent, the test area that matches the third test area is selected as the recommended test area; when both the first and second result distribution indicators do not match the third test area, S106 is executed again to select a new third test area.

[0035] In some embodiments, the output data further includes: signal strength, and the signal strength includes: resistance and / or current magnitude. Correspondingly, before S105, the process further includes the following steps:

[0036] Calculating a uniformity index of the signal strength in at least one of the test areas; the uniformity index includes: the number of abnormal test pins, and the difference between the signal strength of the abnormal test pins and the average signal strength is greater than a preset first threshold;

[0037] Determining whether a difference between the two uniformity indicators is greater than a preset second threshold;

[0038] If not, proceed to S106, and if so, proceed to S105.

[0039] In some embodiments, the output data of one of the test pins is an average result of multiple tests.

[0040] In some embodiments, the corresponding test area is selected from the first surface using a set selection rule, wherein the selection rule is: multiple sub-areas are set on the first surface; a test area is selected from the first surface, and the proportion of the sub-areas included in the test area in the multiple sub-areas is greater than a preset third ratio.

[0041] In some embodiments, the first surface is connected to the first substrate through an isolation guide layer; wherein, a plurality of the test pins are arranged at intervals on the first surface, and the isolation guide layer includes: an isolation layer, the isolation layer is used to cover at least one of the test pins, and the isolation layer is provided with at least one opening, the first end of the opening is provided corresponding to at least one other test pin, and the second end of the opening is connected with a guide column to achieve electrical connection between the corresponding test pin and the first substrate.

[0042] Another aspect of the present invention further provides a chip testing system, comprising:

[0043] A first selection module is used to select a first test area and a second test area from a first surface of the optical chip, respectively, wherein a plurality of test pins are arranged on the first surface, the first test area and the second test area include a plurality of the test pins, and an overlap ratio of the test pins between the first test area and the second test area is less than a preset first ratio;

[0044] A first test data acquisition module is used to respectively acquire test data sets of the first test area and the second test area in at least one test process, wherein the test data sets include: output data corresponding to the test pin, and the output data includes: a connection state, wherein the connection state includes: connected and disconnected;

[0045] A first result acquisition module is used to acquire a result distribution index of the test area through the test data set, wherein the result distribution index includes one or more of the following: a first index, which is the number of the test pins in a connected or disconnected state; a second index, which is the proportion of the test pins in a connected or disconnected state in the test area; a third index, which is the position distribution of the test pins in a connected or disconnected state in the test area;

[0046] a first judgment module, configured to use a preset matching rule to judge whether a first result distribution index of the first test area matches a second result distribution index of the second test area, wherein when a difference between the first result distribution index and the second result distribution index falls within a preset threshold range, the matching rule considers that the first result distribution index and the second result distribution index match; if so, entering a recommendation module;

[0047] The recommendation module is used to select a recommended test area from the first test area and the second test area.

[0048] In some embodiments, it also includes:

[0049] A second selection module is used to select a third test area from the first surface, wherein the third test area includes a plurality of the test pins, and the number of the test pins in the third test area is greater than the number of the test pins in the first test area and the second test area, and the overlap ratio of the test pins in the third test area to the first test area and the second test area is less than a preset second ratio;

[0050] A second test data acquisition module, used to acquire a test data set of the third test area;

[0051] A second result acquisition module, used for acquiring a third result distribution index of the third test area through the corresponding test data set;

[0052] The second judgment module is used to use a preset matching rule to respectively judge whether the first result distribution index, the second result distribution index and the third result distribution index match each other; wherein, when the matching results of the first and second result distribution indicators are inconsistent, the test area matching the third test area is selected as the recommended test area; when both the first and second result distribution indicators do not match the third test area, the second selection module is used again to select a new third test area.

[0053] Beneficial technical effects:

[0054] Corresponding to the test of high-dimensional matrix optical chips, the present invention proposes a direct connection process between the optical chip and the substrate, that is, directly connecting the optical chip and the first substrate through an isolation guide layer, getting rid of the dependence on the intermediate layer, thereby significantly reducing the processing difficulty and cost of the test structure.

[0055] First, on the one hand, the present invention uses an isolation guide layer to locally guide and partially block the test pins on the high-dimensional matrix optical chip, thereby reducing the dimensionality of the dense pins corresponding to the high-dimensional matrix to a certain extent and simplifying the structure. On the other hand, the present invention also reserves a GC interface at a position where the first surface protrudes and hangs in the air by respectively protruding the isolation guide layer and the optical chip from the first substrate in sequence. Among them, when the optical chip and the first substrate are connected and processed, the partial suspension setting of the isolation guide layer can to a certain extent prevent materials such as glue from contaminating the reserved GC interface (for example, excess glue can stay in the suspended area under the isolation or guidance of the isolation layer, that is, it is restricted to approach the GC interface). Correspondingly, the end of the optical fiber array adopts a refractive surface design to cooperate with the first surface through the refraction of the second surface, so that the optical fiber is introduced into the interface at the lower end. In other words, with the help of the sequential protruding setting of the optical chip and the isolation guide layer, the output quality of the optical fiber signal can be improved and the accuracy of the detection result can be improved.

[0056] Furthermore, for this new test structure, the present invention also proposes a dimensionality reduction test method for screening test points based on key factors (such as the connectivity status of the pins), which can select typical representative test areas through pre-testing of local areas (such as the result distribution index obtained in the local area), thereby providing recommended local test areas for batch chip testing.

[0057] Furthermore, due to the isolation guide layer arrangement adopted in the present invention, the obtained test structure can accommodate chip design of ultra-high-dimensional matrix, that is, can complete the direct connection between highly dense test pins and the substrate.

[0058] At the same time, in order to improve the reliability of the selection of the test area in the dimensionality reduction test, the present invention also comprehensively evaluates the results of the test area from two limited dimensions: connectivity and signal strength distribution uniformity. Among them, connectivity can evaluate whether the test pin can be enabled, and signal strength can more finely evaluate whether the test pin has a large drift (such as whether it will affect the uniformity of the splitting ratio). Therefore, the comprehensive evaluation of limited dimensions such as connectivity and signal strength distribution uniformity can quickly screen out the test area to be recommended.

[0059] From another perspective, for application scenarios such as redundant design, the dimensionality reduction test structure proposed in the present invention is combined with the dimensionality reduction test method, which can also improve the tolerance of errors in the test results to a certain extent in the actual application process. For example, for optical chips with redundant designs, dimensionality reduction detection can be used to test only the working properties of its local area. If there are slight errors in the final test results under the dimensionality reduction test (for example, a small number of abnormal test pins are misjudged as normal), the redundant design can also eliminate the adverse effects of such slight errors on the test evaluation to a certain extent.

[0060] Alternatively, the dimensionality reduction test method proposed in the present invention is particularly suitable for fast and low-cost application classification of optical chips. Specifically, when the working properties of the global area of ​​the optical chip are good, the optical chip can be used normally, and when only local points in the local area of ​​the optical chip have abnormalities, the optical chip can also be used for dimensionality reduction (for example, when a 128*128 optical chip has some points that are abnormal, it can be reduced to a 64*64 optical chip) to improve the overall utilization of the optical chip and control production costs.

[0061] In this scenario of chip application classification, the use of dimensionality reduction testing methods can avoid global testing of the chip and improve testing efficiency. In addition, this application classification scenario can also weaken the minor errors that may be generated in local dimensionality reduction testing to a certain extent, thereby improving the reliability of dimensionality reduction test results to a certain extent. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, each element or part is not necessarily drawn according to the actual scale. Obviously, the drawings described below are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings without paying creative labor.

[0063] Figure 1 is a schematic diagram of a test structure in an exemplary embodiment of the present invention;

[0064] Figure 2 is a schematic structural diagram of an isolation guide layer in an exemplary embodiment of the present invention;

[0065] Figure 3 It is a schematic diagram of the connection structure between the optical fiber array and the optical chip in an exemplary embodiment of the present invention;

[0066] Figure 4The figure is a flowchart of the steps of a testing method in an exemplary embodiment of the present invention.

[0067] Summary of reference numerals:

[0068] 1 is a circuit board, 2 is a first bonding structure, 3 is a first substrate, 31 is an end face, 4 is an isolation guide layer, 41 is a PI layer, 41a is an opening, 42 is a copper column, 5 is an optical chip, 51 is a test pin, 52 is a GC interface, 6 is a third bonding structure, 7 is a second substrate, 8 is a first electrical chip, 9 is a second bonding structure, 10 is a second electrical chip, 11 is a fourth bonding structure, 12 is an optical fiber array, 121 is a cover plate, 122 is a V-groove, 122a is a first surface, and 122b is a second surface. DETAILED DESCRIPTION

[0069] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0070] Herein, suffixes such as "module", "component" or "unit" used to represent elements are only used to facilitate the description of the present invention, and have no specific meanings by themselves. Therefore, "module", "component" or "unit" can be used mixedly.

[0071] In this document, the terms "upper", "lower", "inner", "outer", "front", "back", "one end", "the other end" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0072] In this document, unless otherwise clearly specified and limited, the terms "installed", "provided with", "connected", etc. should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0073] Herein "and / or" includes any and all combinations of one or more of the associated listed items.

[0074] Herein, "plurality" means two or more than two, ie, it includes two, three, four, five, etc.

[0075] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0076] As used in this specification, the term "about" typically means + / - 5% of the stated value, more typically + / - 4% of the stated value, more typically + / - 3% of the stated value, more typically + / - 2% of the stated value, even more typically + / - 1% of the stated value, and even more typically + / - 0.5% of the stated value.

[0077] In this specification, some embodiments may be disclosed in a format of being in a range. It should be understood that this description of "being in a range" is only for convenience and brevity, and should not be interpreted as a rigid limitation on the disclosed range. Therefore, the description of the range should be considered to have specifically disclosed all possible sub-ranges and independent numerical values ​​within this range. For example, the description of the range 1-6 should be considered to have specifically disclosed sub-ranges such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6, etc., as well as individual numbers within this range, such as 1, 2, 3, 4, 5 and 6. Regardless of the breadth of the range, the above rules apply.

[0078] See also Figure 1-Figure 3 As shown, the present invention provides a chip testing structure suitable for application scenarios such as redundant design and dimensionality reduction detection.

[0079] Among them, redundant design means that when the actual application requirement of the optical chip is to have n*n pins, m*m pins can be set on the optical chip in the actual production process, where m>n. At this time, if x of the m*m pins are abnormal, but x≤m*mn*n, the optical chip can still meet the n*n design application requirements. In other words, redundant design means that the number of pins can be set on the optical chip higher than the actual application requirements.

[0080] Among them, dimensionality reduction detection refers to the performance testing of highly integrated optical chips (such as optical chips with 128*128 test pins) by selecting a limited number of sample points (i.e. pins).

[0081] It should be noted that in the prior art, optical chips need to complete performance testing before leaving the factory or being packaged. Usually, the pins can be indirectly connected to the substrate by setting an intermediate layer. However, since the pin density set on the high-dimensional matrix optical chip is very high, this intermediate layer connection solution is more difficult to process when applied to the high-dimensional matrix optical chip (such as higher cost and higher processing error). Moreover, when the matrix dimension of the optical chip is too high, it may even be impossible to complete the processing.

[0082] Corresponding to the testing of high-dimensional matrix optical chips, the present invention provides a chip testing technology that can achieve dimensionality reduction detection, that is, a chip testing structure and testing method to reduce the cost and difficulty of chip testing processing and detection.

[0083] From another perspective, this also enables the optical chip in the present invention to be designed with redundancy to a certain extent, thereby improving the tolerance for test errors to a certain extent, making the dimensionality reduction test scheme proposed in the present invention easier to implement and having practical application value.

[0084] Embodiment 1

[0085] The present invention provides a chip test structure, comprising:

[0086] Circuit board 1;

[0087] For example, in some embodiments, the circuit board 1 refers to a printed circuit board or a system integrated board.

[0088] A first substrate 3 is connected and arranged on the circuit board 1 through a first bonding structure 2, an optical chip 5 is arranged on the first substrate 3, and the optical chip 5 has a first surface, and the first surface is connected to the first substrate 3 through an isolation guide layer 4; wherein a plurality of test pins 51 (also referred to as pins in this document) are arranged at intervals on the first surface, and the isolation guide layer comprises: an isolation layer, the isolation layer is used to cover at least one of the test pins 51, and at least one opening is arranged on the isolation layer, a first end of the opening is arranged corresponding to at least one other test pin, and a guide column (such as a copper column) is connected and arranged at the second end of the opening to achieve electrical connection between the corresponding test pin and the first substrate 3;

[0089] That is to say, in some embodiments, a portion of the test pins are in a closed and isolated state (isolated by an isolation guide layer), and are non-conductively connected to the substrate, while another portion of the test pins are in a relatively open state (i.e., can be led out through openings), and are conductively connected to the substrate.

[0090] A first electrical chip 8 is also disposed on the first substrate 3, and the first electrical chip 8 is connected to the first substrate 3 via a second bonding structure 9;

[0091] The circuit board 1 is also connected to a second substrate 7 via a third bonding structure 6, and the second substrate 7 is connected to a second electrical chip 10 via a fourth bonding structure 11;

[0092] The first electrical chip is used to input a high-speed signal to the optical chip 5 , and the second electrical chip is used to input a low-speed signal to the optical chip 5 .

[0093] In this embodiment, the first and second electrical chips are integrated and independently connected to the optical chip 5 respectively to reduce the processing difficulty of the test structure. At the same time, the signal input division of the first and second electrical chips can meet the working requirements of signal input during the test.

[0094] Among them, integrated connection refers to setting the first electrical chip and the optical chip on the same substrate, and independent connection refers to setting the second electrical chip and the optical chip on different substrates respectively, and completing the electrical connection by setting the substrates on the same circuit board 1 (or two connected circuit boards).

[0095] In some embodiments, an electrical conductor is disposed in the opening, a first end of the electrical conductor is connected to the pin, and a second end of the electrical conductor is electrically connected to the substrate.

[0096] In some embodiments, N*N computing units are arranged on the optical chip, and one testing pin may be arranged corresponding to one computing unit.

[0097] Herein, the distinction criteria between high-speed signals and low-speed signals may depend on the frequency of the signal and the length of the transmission path.

[0098] For example, in some embodiments, when the transmission path length of a signal is less than about 1 / 6 of the signal wavelength, it can be considered a low-speed signal, whereas when the transmission path length is greater than or equal to about 1 / 6 of the signal wavelength, it can be considered a high-speed signal. In other words, if the rise time of a signal is less than six times the delay of its transmission line, the signal can be considered a high-speed signal.

[0099] For another example, in some embodiments, a signal with a frequency greater than 50 Mhz may be regarded as a high-speed signal, and correspondingly, a signal with a frequency less than or equal to 50 Mhz may be regarded as a low-speed signal.

[0100] For another example, in some embodiments, when the rising edge (or falling edge) time of a signal is less than 50 ps, ​​it can be considered as a high-speed signal.

[0101] For another example, in some embodiments, when a signal is transmitted along a transmission path and severe skin effect and ionization loss occur, it is considered to be a high-speed signal.

[0102] It is worth noting that in this embodiment, the optical chip 5 is directly connected to the first substrate 3 through the isolation guide layer, which eliminates the dependence on the intermediate layer, thereby significantly reducing the processing difficulty and cost of the test structure.

[0103] The process of connecting the optical chip 5 and the first substrate 3 may be:

[0104] 1) First, an isolation layer, preferably a PI layer 41, is covered on the first surface of the optical chip 5 to cover the multiple test pins on the first surface;

[0105] 2) etching the PI layer 41 by photolithography to etch openings with specific positions and numbers, wherein the first ends of the openings 41a correspond to the test pins, and the second ends of the openings 41a are provided with copper pillars 42;

[0106] 3) The optical chip 5 and the first substrate 3 are connected via copper pillars to electrically connect the local test pins to the first substrate.

[0107] In some embodiments, the PI layer refers to a polytetrafluoroethylene (PTFE) layer.

[0108] In some embodiments, it also includes:

[0109] An optical fiber array 12, the optical fiber array includes: a cover plate 121 and a V-groove 122, a GC interface 52 (also called: photosensitive port) is provided in the area of ​​the first surface protruding from the first substrate, and correspondingly, a first surface and a second surface are provided on the side of the V-groove close to the optical chip, the first surface is connected to the GC interface of the optical chip, and the second surface intersects with the plane where the end surface 31 opposite to the first substrate is located; wherein the optical fiber reaches the second surface, is refracted on the second surface, and then turned to be transmitted to the first surface, and enters the optical chip through the first surface.

[0110] The isolation guide layer 4 extends out of the first substrate 3 so that the isolation guide layer is partially suspended, and the first surface also extends out of the first substrate 3 so that the first chip 5 is suspended relative to the isolation guide layer and the first substrate, and a GC interface 52 is provided at the suspended portion of the first surface; correspondingly, a first surface 122a and a second surface 122b are provided at one end of the V-groove close to the optical chip 5 and the first substrate 3;

[0111] A first spacing is reserved between the end of the V-groove close to the first substrate (such as the intersection of the second surface 122b and the first surface 122a) and the end surface of the first substrate 3, and a second spacing is also reserved between the end of the V-groove and the isolation guide layer 4;

[0112] The applicant has noticed that during the processing of the high-dimensional matrix optical chip, its surface (such as the first surface, end surface, etc.) may be contaminated with impurities such as dust and glue due to processing reasons (such as isolation guide layer processing, circuit etching on the chip, etc.), and these impurities can easily affect the signal transmission quality between the GC interface and the optical fiber array. In response to this, the present invention proposes a bottom-coupled optical fiber array setting scheme.

[0113] For example, in this embodiment, the isolation guide layer and the optical chip are respectively protruded from the first substrate in sequence, so as to reserve a GC interface at a position protruding from the first surface. When the optical chip and the first substrate are connected and processed, the partial suspension of the isolation guide layer can, to a certain extent, prevent glue and other materials from contaminating the reserved GC interface (for example, excess glue can stay in the suspended area under the isolation or guidance of the isolation layer, that is, it is restricted from approaching the GC interface). Correspondingly, the end of the optical fiber array adopts a refractive surface design to cooperate with the first surface 122a through the refractive effect of the second surface 122b, so that the optical fiber is introduced into the GC interface at the lower end.

[0114] For example, in some embodiments, the spacing L1 of the optical chip 5 suspended relative to the isolation guide layer 4 is approximately 900 μm, the spacing L2 between one end of the isolation guide layer 4 suspended relative to the first substrate 3 and the nearest guide column is approximately 1206 μm, and the first substrate 3 has a second surface facing the isolation guide layer 4, and the spacing between the end of the second surface and the nearest guide column is approximately 1000 μm.

[0115] In some embodiments, the bonding structure refers to a conductive connection structure.

[0116] For example, in some embodiments, the bonding structure may be a metal bump or a solder bump.

[0117] For example, in some embodiments, the material of the metal bump may include one or a combination of copper and nickel, and the material of the solder bump may include one or a combination of copper, nickel, gold, tin and silver.

[0118] Embodiment 2

[0119] It is worth noting that the above test structure simplifies the processing difficulty on the one hand, and also provides a feasible exemplary implementation scheme for the dimensionality reduction test of optical chips on the other hand.

[0120] Correspondingly, the present invention also provides a chip testing method that can be applied to dimensionality reduction testing.

[0121] See also Figure 4 As shown, the present invention also provides a chip testing method (equivalent to a dimensionality reduction detection process), comprising the steps of:

[0122] S100 provides at least one optical chip to be tested, wherein the optical chip has a first surface, and a plurality of test pins are arranged on the first surface;

[0123] S101, respectively selecting a first test area and a second test area from the first surface, wherein the first test area and the second test area include a plurality of the test pins, and an overlap ratio of the test pins between the first test area and the second test area is less than a preset first ratio;

[0124] S102: testing the optical chip at least once to obtain test data sets of the first test area and the second test area respectively, wherein the test data sets include: output data corresponding to the test pins, and the output data include: connection status, and the connection status includes: connection and disconnection;

[0125] For example, in some embodiments, the test structure provided in Embodiment 1 can be used to test the first test area using at least one optical chip and to test the second test area using at least one optical chip, thereby obtaining a first test data set for the first test area and a second test data set for the second test area, respectively.

[0126] S103 obtains a result distribution index of the test area through the test data set, where the result distribution index includes one or more of the following:

[0127] A first indicator, the first indicator is the number of the test pins in a connected or disconnected state; a second indicator, the second indicator is the proportion of the test pins in a connected or disconnected state in the test area; a third indicator, the third indicator is the position distribution of the test pins in a connected or disconnected state in the test area;

[0128] For example, in some embodiments, multiple sub-areas can be evenly divided on the optical chip, and the test area can select sample points (i.e., test pins) evenly from the test pins in the multiple sub-areas. Specifically, the position distribution can be one or more of the following parameters: the number of abnormal areas, the coordinates of the abnormal areas.

[0129] For example, the number of test pins in the disconnected state in at least one sub-area is calculated respectively, and when the number is greater than a set first number, the area is considered to be an abnormal area. For another example, in some embodiments, when multiple abnormal areas are close to each other (such as when the distance is less than a set distance), the multiple abnormal areas can be marked as one abnormal area.

[0130] S104: using a preset matching rule to determine whether the first result distribution index of the first test area matches the second result distribution index of the second test area, wherein when the difference between the first result distribution index and the second result distribution index falls within a preset threshold range, the matching rule considers that the first result distribution index and the second result distribution index match; if so, allowing step S105 to be executed;

[0131] When the difference between two result distribution indicators falls within a preset threshold range, the matching rule considers that the two result distribution indicators match.

[0132] S105: Select a recommended test area from the first test area and the second test area.

[0133] For example, in some embodiments, if the difference between the first indicator of the first test area and the second test area is less than the set first threshold range, it is considered that the results of the first test area and the second test area match, and it can be preliminarily considered that the selection of the first and second test areas is reliable.

[0134] For another example, in some embodiments, when the difference between the number of abnormal regions in the first test area and the number of abnormal regions in the second test area is less than a set second threshold range, it is considered that the results of the first test area and the second test area match.

[0135] In some embodiments, the selected test area can be used to test the remaining multiple optical chips, and the test results corresponding to the test area can be used as the final test results of the optical chip. Alternatively, the test results of the test area can be used to predict the final test results of all areas in the optical chip.

[0136] In some embodiments, the test area refers to an area composed of test pins electrically connected to the substrate. That is to say, during the test process, corresponding openings are sequentially arranged on the isolation layer for the corresponding test pins in the test area, so that the electrical signal in the test pin can be transmitted to the substrate through the openings and the electrical wires and guide posts.

[0137] It is worth mentioning that for optical chips, especially high-dimensional matrix optical chips, the processing technology involved is very complex and the processing cost is very high. The slight deviations produced in the processing may have a significant impact on the performance of the chip, such as causing some pins to fail to work.

[0138] Therefore, in the traditional test scheme, the pins on the optical chip need to be tested globally, otherwise it is difficult to evaluate the performance of the optical chip as a whole. However, this global test scheme will not only further increase the difficulty of the process during the test phase, but also significantly increase the testing cost of batch chips.

[0139] In this regard, the present invention also proposes a dimensionality reduction detection process, which can select a typical representative test area through preliminary testing of the local area (such as the result distribution index obtained in the local area), thereby providing a recommended local area for batch chip testing.

[0140] Therefore, the local detection process of the present invention can simplify the structural processing difficulty of the detection structure on the one hand, and can also reduce the amount of data analysis in the test process on the other hand, thereby improving the test efficiency.

[0141] Furthermore, in some embodiments, when the result of S104 is no, the step of:

[0142] S106: selecting a third test area from the first surface, wherein the third test area includes a plurality of the test pins, and the number of the test pins in the third test area is greater than the number of the test pins in the first test area and the second test area, and the overlap ratio of the test pins in the third test area to the first test area and the second test area is less than a preset second ratio;

[0143] S107 obtains a test data set of the third test area;

[0144] S108 obtains a third result distribution index of the third test area through the corresponding test data set;

[0145] S109: using a preset matching rule to respectively determine whether the first result distribution index, the second result distribution index and the third result distribution index match each other; wherein, when the matching results of the first and second result distribution indicators are inconsistent, selecting a test area that matches the third test area as a recommended test area;

[0146] In some embodiments, when the first and second result distribution indicators do not match the third test area, S106 is executed again to select a new third test area.

[0147] Alternatively, in some embodiments, when the first and second result distribution indicators do not match the third test area, a corresponding prompt signal may be sent to a user (eg, an engineer) to suggest manual evaluation of the test area selection method.

[0148] In some embodiments, when the difference between the two result distribution indicators falls within a preset threshold range, the matching rule considers that the two result distribution indicators match. Specifically, the matching rule in S109 can refer to S104.

[0149] Further, in order to improve the reliability of the dimensionality reduction detection process, in some embodiments, the output data also includes: signal strength, and the signal strength includes: resistance and / or current magnitude. Correspondingly, before S105, the following steps are also included:

[0150] Calculating a uniformity index of the signal strength in at least one of the test areas; the uniformity index includes: the number of abnormal test pins, and the difference between the signal strength of the abnormal test pins and the average signal strength is greater than a preset first threshold;

[0151] Determining whether a difference between the two uniformity indicators is greater than a preset second threshold;

[0152] If yes, go to S106, if no, go to S105.

[0153] In this embodiment, when the signal connectivity (corresponding to the result distribution index) and the signal strength distribution uniformity index of the two test areas are the same or similar, it is considered that the currently selected test area has a high representativeness in the test process and can be used as a recommended test area. The final test area selection can be selected by the computer system based on the set rules, or randomly selected, or can also be manually selected by the user according to the final test area that meets the requirements.

[0154] That is, in order to improve the reliability of the selection of the test area in the dimensionality reduction test, this embodiment comprehensively evaluates the results of the test area from two limited dimensions: connectivity and signal strength distribution uniformity. Among them, connectivity can evaluate whether the test pin can be enabled, and signal strength can more finely evaluate whether the test pin has a large drift (such as whether it will affect the uniformity of the splitting ratio). Therefore, the comprehensive evaluation of limited dimensions such as connectivity and signal strength distribution uniformity can quickly screen out the test area to be recommended.

[0155] In this embodiment, it is preferred to first evaluate the connectivity, and then evaluate whether to calculate the signal strength distribution in combination with the connectivity, which can reduce the amount of necessary data calculation in the detection process to a certain extent.

[0156] From another perspective, in this embodiment, two or more test areas are comprehensively evaluated through large defects (such as connectivity) and small defects (such as properties such as sparse ratio uniformity). If the test results of the two test areas at both the large defect and small defect levels are relatively similar, it can be considered that the selected test area is appropriate and representative (or in other words, the current optical chip is suitable for this new type of dimensionality reduction test).

[0157] In some embodiments, the output data of one of the test pins is an average result of multiple tests.

[0158] For example, in some embodiments, when the output data is current, the current used in calculating the result distribution indicator is an average value of currents output from at least two tests.

[0159] For example, in some embodiments, in S101, multiple first test areas and multiple second test areas may be selected at one time, and an average result of multiple tests may be calculated as a result distribution indicator by setting rules (which may be set by the user).

[0160] For example, when the results of a test pin are all connected after y tests, its connectivity state is connected; when all its test results are disconnected, the corresponding connectivity state is disconnected; or, when the number of times the test pin is in the connected state in the test results is greater than the number of times it is disconnected, the result is output as connected; conversely, when the number of times the test pin is in the disconnected state in the test results is greater than the number of times it is connected, the result is output as disconnected.

[0161] Correspondingly, a test area whose result is closer to the average result may be selected from the plurality of first test areas as a recommended test area;

[0162] For example, taking the first test area as an example, multiple first test areas can be selected in S101, such as the first test area A1, the first test area A2, ... the first test area Ay, and the overlap ratio between the first test areas is greater than the first ratio. After testing the multiple first test areas, the average value of the first index or the second index of each first test area A1, the first test area A2, ... the first test area Ay is calculated respectively, and at least one first test area whose result distribution index is closest to the average value is selected as the recommended test area to be selected.

[0163] Likewise, multiple second test areas can be selected, and the selection rule of the second test area can be the same as that of the first test area.

[0164] In some embodiments, the corresponding test area is selected from the first surface using a set selection rule, wherein the selection rule is: multiple sub-areas are set on the first surface; a test area is selected from the first surface, and the proportion of the sub-areas included in the test area in the multiple sub-areas is greater than a preset third ratio.

[0165] For example, a sub-area may correspond to one or more computing units.

[0166] In some embodiments, the first surface is connected to the first substrate through an isolation guide layer; wherein, a plurality of the test pins are arranged at intervals on the first surface, and the isolation guide layer includes: an isolation layer, the isolation layer is used to cover at least one of the test pins, and the isolation layer is provided with at least one opening, the first end of the opening is provided corresponding to at least one other test pin, and the second end of the opening is connected with a guide column to achieve electrical connection between the corresponding test pin and the first substrate.

[0167] It can be understood that the test structure in this embodiment can adopt the test structure in any of the above embodiments.

[0168] It can be understood that the specific values ​​of the first, second or third ratio in this embodiment can be set by the user in combination with the test requirements.

[0169] Embodiment 3

[0170] Corresponding to the above-mentioned second embodiment, the present invention further provides a chip testing system, including:

[0171] A first selection module is used to select a first test area and a second test area from a first surface of the optical chip, respectively, wherein a plurality of test pins are arranged on the first surface, the first test area and the second test area include a plurality of the test pins, and an overlap ratio of the test pins between the first test area and the second test area is less than a preset first ratio;

[0172] A first test data acquisition module is used to respectively acquire test data sets of the first test area and the second test area in at least one test process, wherein the test data sets include: output data corresponding to the test pin, and the output data includes: a connection state, wherein the connection state includes: connected and disconnected;

[0173] A first result acquisition module is used to acquire a result distribution index of the test area through the test data set, wherein the result distribution index includes one or more of the following: a first index, which is the number of the test pins in a connected or disconnected state; a second index, which is the proportion of the test pins in a connected or disconnected state in the test area; a third index, which is the position distribution of the test pins in a connected or disconnected state in the test area;

[0174] a first judgment module, configured to use a preset matching rule to judge whether a first result distribution index of the first test area matches a second result distribution index of the second test area, wherein when a difference between the first result distribution index and the second result distribution index falls within a preset threshold range, the matching rule considers that the first result distribution index and the second result distribution index match; if so, entering a recommendation module;

[0175] The recommendation module is used to select a recommended test area from the first test area and the second test area.

[0176] In some embodiments, it also includes:

[0177] A second selection module is used to select a third test area from the first surface, wherein the third test area includes a plurality of the test pins, and the number of the test pins in the third test area is greater than the number of the test pins in the first test area and the second test area, and the overlap ratio of the test pins in the third test area to the first test area and the second test area is less than a preset second ratio;

[0178] A second test data acquisition module, used to acquire a test data set of the third test area;

[0179] A second result acquisition module, used for acquiring a third result distribution index of the third test area through the corresponding test data set;

[0180] The second judgment module is used to use a preset matching rule to respectively judge whether the first result distribution index, the second result distribution index and the third result distribution index match each other; wherein, when the matching results of the first and second result distribution indicators are inconsistent, the test area matching the third test area is selected as the recommended test area; when both the first and second result distribution indicators do not match the third test area, the second selection module is used again to select a new third test area.

[0181] In some embodiments, the output data further includes: signal strength, the signal strength includes: resistance and / or current magnitude, correspondingly, the system further includes

[0182] A verification module is used to calculate a uniformity index of the signal strength in at least one of the test areas before entering the recommendation module; the uniformity index includes: the number of abnormal test pins, and the difference between the signal strength of the abnormal test pins and the average signal strength is greater than a preset first threshold; determine whether the difference between the two uniformity indicators is greater than a preset second threshold; if not, enter the second selection module, and if so, enter the recommendation module.

[0183] It can be understood that the system in this embodiment can implement any of the above methods or steps, which will not be described in detail here.

[0184] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0185] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, a magnetic disk, or an optical disk), and includes a number of instructions for a computer terminal (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present invention.

[0186] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the enlightenment of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the purpose of the present invention and the claims, which all fall within the protection of the present invention.

Claims

1. A test structure for an optical chip, It is characterized in that include: Circuit board (1); A first substrate (3) is provided on the circuit board (1) via a first bonding structure (2), an optical chip (5) is provided on the first substrate (3), the optical chip (5) having a first surface, the first surface being connected to the first substrate (3) via an isolation guide layer; wherein a plurality of test pins (51) are arranged at intervals on the first surface, the isolation guide layer comprising: an isolation layer, the isolation layer being used to cover at least one of the test pins (51), and the isolation layer being provided with at least one opening, the first end of the opening being provided corresponding to at least one other test pin, an electric wire being provided in the opening, the electric wire being connected to the corresponding test pin, and a guide column connected to the electric wire being provided at the second end of the opening, so as to realize an electrical connection between the corresponding test pin and the first substrate (3); A first electrical chip (8) is also provided on the first substrate (3), and the first electrical chip (8) is connected to the first substrate (3) via a second bonding structure (9); The circuit board (1) is also provided with a second substrate (7) connected thereto via a third bonding structure (6), and the second substrate (7) is provided with a second electrical chip (10) connected thereto via a fourth bonding structure (11); The first electrical chip is used to input a high-speed signal to the optical chip (5), and the second electrical chip is used to input a low-speed signal to the optical chip (5).

2. The optical chip test structure according to claim 1, It is characterized in that Also includes: An optical fiber array (12), the optical fiber array comprising: a cover plate (121) and a V-groove (122), wherein a GC interface (52) is provided in an area of ​​the first surface protruding from the first substrate (3), and correspondingly, a first surface (122a) and a second surface (122b) are provided on a side of the V-groove close to the optical chip, wherein the first surface is connected to the GC interface of the optical chip, and the second surface intersects with a plane where an end surface (31) opposite to the first substrate is located; wherein when the optical fiber array is in operation, the optical fiber first reaches the second surface, is refracted on the second surface, and then is turned to be transmitted to the first surface, and enters the optical chip through the first surface and the GC interface.

3. A method for testing an optical chip, It is characterized in that Includes steps: S100 provides at least one optical chip to be tested, the optical chip having a first surface, the first surface being connected to a first substrate via an isolation guide layer, a plurality of test pins being arranged at intervals on the first surface, the isolation guide layer comprising: an isolation layer, the isolation layer being used to cover at least one of the test pins, and the isolation layer being provided with at least one opening, a first end of the opening being provided corresponding to at least one other test pin, an electric wire being provided in the opening, the electric wire being connected to the corresponding test pin, and a guide column connected to the electric wire being provided at the second end of the opening, so as to realize an electrical connection between the corresponding test pin and the first substrate; S101, respectively selecting a first test area and a second test area from the first surface, wherein the first test area and the second test area include a plurality of the test pins, and an overlap ratio of the test pins between the first test area and the second test area is less than a preset first ratio; S102: testing the optical chip at least once to obtain test data sets of the first test area and the second test area respectively, wherein the test data sets include: output data corresponding to the test pins, and the output data include: connection status, and the connection status includes: connection and disconnection; S103 obtains a result distribution index of the test area through the test data set, where the result distribution index includes one or more of the following: A first indicator, the first indicator is the number of the test pins in a connected or disconnected state; a second indicator, the second indicator is the proportion of the test pins in a connected or disconnected state in the test area; a third indicator, the third indicator is the position distribution of the test pins in a connected or disconnected state in the test area; S104: using a preset matching rule to determine whether the first result distribution index of the first test area matches the second result distribution index of the second test area, wherein when the difference between the first result distribution index and the second result distribution index falls within a preset threshold range, the matching rule considers that the first result distribution index and the second result distribution index match; if so, allowing step S105 to be executed; S105: Select a recommended test area from the first test area and the second test area.

4. A method for testing an optical chip according to claim 3, It is characterized in that When the result of S104 is no, the following steps are further included: S106: selecting a third test area from the first surface, wherein the third test area includes a plurality of the test pins, and the number of the test pins in the third test area is greater than the number of the test pins in the first test area and the second test area, and the overlap ratio of the test pins in the third test area to the first test area and the second test area is less than a preset second ratio; S107 obtains a test data set of the third test area; S108 obtains a third result distribution index of the third test area through the corresponding test data set; S109 uses preset matching rules to respectively determine whether the first result distribution indicator, the second result distribution indicator and the third result distribution indicator match each other; wherein, when the matching results of the first and second result distribution indicators are inconsistent, the test area that matches the third test area is selected as the recommended test area; when both the first and second result distribution indicators do not match the third test area, S106 is executed again to select a new third test area.

5. The method for testing an optical chip according to claim 3, It is characterized in that The output data also includes: signal strength, and the signal strength includes: resistance and / or current magnitude. Correspondingly, before S105, the following steps are also included: Calculating a uniformity index of the signal strength in at least one of the test areas; the uniformity index includes: the number of abnormal test pins, and the difference between the signal strength of the abnormal test pins and the average signal strength is greater than a preset first threshold; Determining whether a difference between the two uniformity indicators is greater than a preset second threshold; If yes, go to S106, if no, go to S105.

6. A method for testing an optical chip according to claim 5, It is characterized in that The output data of one of the test pins is an average result of multiple tests.

7. The method for testing an optical chip according to claim 3, It is characterized in that The corresponding test area is selected from the first surface using a set selection rule, wherein the selection rule is: multiple sub-areas are set on the first surface; a test area is selected from the first surface, and the proportion of the sub-areas included in the test area in the multiple sub-areas is greater than a preset third ratio.

8. A testing system for an optical chip, It is characterized in that The optical chip has a first surface, the first surface is connected to the first substrate through an isolation guide layer, a plurality of test pins are arranged at intervals on the first surface, the isolation guide layer comprises: an isolation layer, the isolation layer is used to cover at least one of the test pins, and at least one opening is provided on the isolation layer, a first end of the opening corresponds to at least one other test pin, an electric wire is provided in the opening, the electric wire is connected to the corresponding test pin, and a guide column connected to the electric wire is connected to the second end of the opening to achieve electrical connection between the corresponding test pin and the first substrate; the test system comprises: A first selection module is used to select a first test area and a second test area from a first surface of the optical chip, respectively, wherein a plurality of test pins are arranged on the first surface, the first test area and the second test area include a plurality of the test pins, and an overlap ratio of the test pins between the first test area and the second test area is less than a preset first ratio; A first test data acquisition module, used to respectively acquire test data sets of the first test area and the second test area in at least one test process, wherein the test data sets include: output data corresponding to the test pins, and the output data include: connection status, and the connection status includes: connection and disconnection; A first result acquisition module is used to acquire a result distribution index of the test area through the test data set, wherein the result distribution index includes one or more of the following: a first index, which is the number of the test pins in a connected or disconnected state; a second index, which is the proportion of the test pins in a connected or disconnected state in the test area; a third index, which is the position distribution of the test pins in a connected or disconnected state in the test area; a first judgment module, configured to use a preset matching rule to judge whether a first result distribution index of the first test area matches a second result distribution index of the second test area, wherein when a difference between the first result distribution index and the second result distribution index falls within a preset threshold range, the matching rule considers that the first result distribution index and the second result distribution index match; if so, entering a recommendation module; The recommendation module is used to select a recommended test area from the first test area and the second test area.

9. The optical chip testing system according to claim 8, It is characterized in that Also includes: A second selection module is used to select a third test area from the first surface, wherein the third test area includes a plurality of the test pins, and the number of the test pins in the third test area is greater than the number of the test pins in the first test area and the second test area, and the overlap ratio of the test pins in the third test area to the first test area and the second test area is less than a preset second ratio; A second test data acquisition module, used to acquire a test data set of the third test area; A second result acquisition module, used for acquiring a third result distribution index of the third test area through the corresponding test data set; The second judgment module is used to use a preset matching rule to respectively judge whether the first result distribution indicator, the second result distribution indicator and the third result distribution indicator match each other; wherein, when the matching results of the first and second result distribution indicators are inconsistent, the test area matching the third test area is selected as the recommended test area; when both the first and second result distribution indicators do not match the third test area, the second selection module is used again to select a new third test area.

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