High electron mobility transistor epitaxial wafer and preparation method thereof, HEMT

Abstract

The present invention relates to the field of optoelectronic technology, and discloses a high electron mobility transistor epitaxial wafer and a preparation method thereof, and a HEMT. The high electron mobility transistor epitaxial wafer comprises a substrate, on which a buffer layer, a channel layer, an insertion layer, a barrier layer, and a cap layer are sequentially arranged; the buffer layer comprises a BAlN layer, a BGaN layer, an AlGaN layer, and a SiN layer sequentially stacked on the substrate. The high electron mobility transistor epitaxial wafer provided by the present invention alleviates the lattice mismatch and thermal mismatch between the substrate and the epitaxial layer, releases the thermal stress of the epitaxial layer, improves the crystal quality of the grown epitaxial layer, reduces the leakage current of the power device, and increases the two-dimensional electron gas concentration of the channel layer, thereby improving the device performance.

Description

Technical Field

[0001] The present invention relates to the field of optoelectronic technology, and in particular to a high electron mobility transistor epitaxial wafer and a preparation method thereof, and a HEMT. Background Art

[0002] In order to meet the high-power and high-efficiency applications of the new generation of electronic devices and optoelectronic devices, the third-generation semiconductors based on GaN have made great progress in the past two decades and have gradually replaced traditional semiconductors such as Si, Ga, and As, especially in the preparation of high electron mobility transistors (HEMT) and light-emitting diodes (LED). GaN electronic devices can be used for efficient power conversion, high-frequency signal modulation, high-voltage controllable switches, and high-speed information processing. GaN-based materials have great application potential in the field of power and radio frequency electronic devices. At the same time, compared with traditional semiconductors, GaN-based materials show excellent radiation resistance, high temperature resistance and chemical stability, making them have the potential to work in harsh environments. Therefore, the gradual replacement of traditional Si and GaAs materials by high electron mobility transistor-based materials will play a positive role in the construction of wireless base stations, satellite communications, radar detection, power electronics, green energy and other livelihood and defense fields.

[0003] First, Si and Ga are prone to "melt-back etching" at high temperatures to form a Ga-Si eutectic alloy, which results in a large number of holes and pits on the epitaxial surface. GaN cannot nucleate and grow on the surface, which ultimately leads to epitaxial growth failure. Second, there is a large lattice mismatch between Si and GaN, and the crystal defect density is high. GaN grows epitaxially on the Si (111) crystal plane, which has an equivalent lattice constant of 0.3840nm and a lattice mismatch of up to 16.9% with the GaN (0002) plane. Such a large lattice mismatch will cause GaN to have a density of up to 5×10 9 cm -2 These threading dislocations can also form leakage channels in the LED chip, reducing the reliability of the device. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a high electron mobility transistor epitaxial wafer, which alleviates the lattice mismatch and thermal mismatch between the substrate and the epitaxial layer, releases the thermal stress of the epitaxial layer, improves the crystal quality of the grown epitaxial layer, reduces the leakage current of the power device, increases the two-dimensional electron gas concentration in the channel layer, and thus improves the device performance.

[0005] The technical problem to be solved by the present invention is also to provide a method for preparing a high electron mobility transistor epitaxial wafer, which has a simple process and can stably prepare a high electron mobility transistor epitaxial wafer with good luminous efficiency.

[0006] In order to solve the above technical problems, the present invention provides a high electron mobility transistor epitaxial wafer, comprising a substrate, on which a buffer layer, a channel layer, an insertion layer, a barrier layer, and a cap layer are sequentially arranged;

[0007] The buffer layer includes a BAlN layer, a BGaN layer, an AlGaN layer and a SiN layer sequentially stacked on the substrate.

[0008] In some embodiments, the thickness of the BAlN layer is 10 nm to 100 nm.

[0009] In some embodiments, the BGaN layer has a thickness of 10 nm to 100 nm.

[0010] In some embodiments, the B component of the BGaN layer gradually decreases from high to low along the BAlN layer toward the AlGaN layer.

[0011] In some embodiments, the AlGaN layer has a thickness of 10 nm to 100 nm.

[0012] In some embodiments, the Al component of the AlGaN layer gradually increases from low to high along the direction from the BGaN layer to the SiN layer.

[0013] In some embodiments, the SiN layer has a thickness of 1 nm to 50 nm.

[0014] To solve the above problems, the present invention also provides a method for preparing a high electron mobility transistor epitaxial wafer, comprising the following steps:

[0015] S1. Prepare substrate;

[0016] S2, depositing a buffer layer, a channel layer, an insertion layer, a barrier layer, and a cap layer on the substrate in sequence;

[0017] The buffer layer includes a BAlN layer, a BGaN layer, an AlGaN layer and a SiN layer sequentially stacked on the substrate.

[0018] In some embodiments, the growth temperature of the BAlN layer is 700° C. to 900° C. and the pressure is 50 torr to 500 torr;

[0019] The growth temperature of the BGaN layer is 700° C. to 900° C., and the pressure is 50 torr to 500 torr;

[0020] The growth temperature of the AlGaN layer is 700° C. to 900° C., and the pressure is 50 torr to 500 torr;

[0021] The growth temperature of the SiN layer is 900° C. to 1100° C., and the pressure is 50 torr to 500 torr.

[0022] Correspondingly, the present invention further provides a HEMT, wherein the HEMT comprises the above-mentioned high electron mobility transistor epitaxial wafer.

[0023] The implementation of the present invention has the following beneficial effects:

[0024] The high electron mobility transistor epitaxial wafer provided by the present invention has a buffer layer comprising a BAlN layer, a BGaN layer, an AlGaN layer and a SiN layer which are sequentially stacked on the substrate.

[0025] Among them, the BAlN layer provides nucleation points for the subsequent epitaxial layer growth, which is beneficial to the film formation and crystal quality improvement of GaN epitaxial materials, relieves the stress between the substrate and the epitaxial layer caused by lattice mismatch and thermal mismatch, and avoids Ga melt-back etching due to direct contact between Si atoms and Ga atoms at high temperature.

[0026] The BGaN layer reduces the lattice mismatch between the BAlN layer and the AlGaN layer, improves the overall crystal quality of the buffer layer, provides a flat nucleation surface for depositing the AlGaN layer, reduces the contact angle of its nucleation growth, and enables the island-like grown AlGaN grains to connect into a surface within a smaller thickness, thus transforming into two-dimensional epitaxial growth.

[0027] The AlGaN layer releases the thermal stress generated by the mismatch of thermal expansion coefficients in the epitaxial layer. In addition, the Al component gradually increases, and because of its small atomic radius, it can fill the void defects generated in the epitaxial layer and improve the crystal quality. And its two-dimensional structure provides a flat nucleation surface for the further growth of the three-dimensional GaN layer, reducing the contact angle of its nucleation growth.

[0028] The isolation layer SiN layer reduces the extension of line defects to the GaN channel layer, improves the crystal quality of the GaN channel layer, reduces the leakage current of the power device, increases the concentration of the two-dimensional electron gas in the channel layer, and thus improves the device performance.

[0029] In summary, the high electron mobility transistor epitaxial wafer provided by the present invention alleviates the lattice mismatch and thermal mismatch between the substrate and the epitaxial layer, releases the thermal stress of the epitaxial layer, improves the crystal quality of the grown epitaxial layer, reduces the leakage current of the power device, increases the two-dimensional electron gas concentration in the channel layer, and thus improves the device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 This is a schematic structural diagram of a high electron mobility transistor epitaxial wafer provided by the present invention. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention. In addition, it should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0032] In the description of the present invention, it is necessary to understand that the terms "length", "width", "up", "down", "left", "right", "horizontal", "top", "bottom", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0033] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0034] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or mutual communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0035] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0036] The disclosure below provides many different embodiments or examples to realize different structures of the present invention. In order to simplify the disclosure of the present invention, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present invention. In addition, the present invention can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed. In addition, the examples of various specific processes and materials provided by the present invention, but those of ordinary skill in the art can be aware of the application of other processes and / or the use of other materials.

[0037] In the present invention, "preferred" and "better" are only used to describe implementation methods or embodiments with better effects, and it should be understood that they do not constitute a limitation on the scope of protection of the present invention. In the present invention, the technical features described in an open manner include closed technical solutions composed of the listed features, and also include open technical solutions containing the listed features. In the present invention, when involving numerical ranges, unless otherwise specified, the two endpoints of the numerical range are included.

[0038] To solve the above problems, the present invention provides a high electron mobility transistor epitaxial wafer, such as Figure 1 As shown, it includes a substrate 100, on which a buffer layer 200, a channel layer 300, an insertion layer 400, a barrier layer 500, and a cap layer 600 are sequentially arranged;

[0039] The buffer layer 200 includes a BAlN layer 210 , a BGaN layer 220 , an AlGaN layer 230 , and a SiN layer 240 sequentially stacked on the substrate 100 .

[0040] The high electron mobility transistor epitaxial wafer provided by the present invention alleviates the lattice mismatch and thermal mismatch between the substrate and the epitaxial layer, releases the thermal stress of the epitaxial layer, improves the crystal quality of the grown epitaxial layer, reduces the leakage current of the power device, increases the two-dimensional electron gas concentration in the channel layer, and thus improves the device performance.

[0041] The specific structure of the buffer layer 200 is as follows:

[0042] In some embodiments, the thickness of the BAlN layer 210 is 10nm to 100nm; exemplary thicknesses of the BAlN layer 210 are 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, and 90nm, but are not limited to the above. The BAlN layer provides nucleation points for subsequent epitaxial layer growth, which is beneficial to the film formation and crystal quality improvement of GaN epitaxial materials, relieves stress caused by lattice mismatch and thermal mismatch between the substrate and the epitaxial layer, and avoids direct contact between Si atoms and Ga atoms at high temperatures to cause Ga melt-back etching.

[0043] In some embodiments, the thickness of the BGaN layer 220 is 10nm~100nm. Exemplary thicknesses of the BGaN layer 220 are 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, but are not limited to the above. In some embodiments, the B component of the BGaN layer 220 gradually decreases from high to low along the BAlN layer toward the AlGaN layer. The BGaN layer with a gradient B component can reduce the lattice mismatch between the BAlN layer and the AlGaN layer, improve the overall crystal quality of the buffer layer, provide a flat nucleation surface for depositing the AlGaN layer, reduce the contact angle of its nucleation growth, and enable the island-like grown AlGaN grains to be connected into a surface within a smaller thickness, transforming into two-dimensional epitaxial growth.

[0044] In some embodiments, the thickness of the AlGaN layer 230 is 10nm~100nm. Exemplary thicknesses of the AlGaN layer 230 are 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, but are not limited to the above. In some embodiments, the Al component of the AlGaN layer 230 gradually increases from low to high along the direction from the BGaN layer to the SiN layer. The AlGaN layer releases the thermal stress generated by the mismatch of the thermal expansion coefficient of the epitaxial layer. In addition, the Al component gradually increases because its atomic radius is small and can fill the void defects generated in the epitaxial layer, thereby improving the crystal quality. And its two-dimensional structure provides a flat nucleation surface for the further growth of a three-dimensional GaN layer, reducing the contact angle of its nucleation growth.

[0045] In some embodiments, the thickness of the SiN layer 240 is 1 nm to 50 nm. Exemplary thicknesses of the SiN layer 240 are 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, and 45 nm, but are not limited to the above. The isolation layer SiN layer reduces the extension of line defects to the GaN channel layer, improves the crystal quality of the GaN channel layer, reduces the leakage current of the power device, and increases the concentration of the two-dimensional electron gas in the channel layer, thereby improving the device performance.

[0046] Accordingly, the present invention provides a method for preparing a high electron mobility transistor epitaxial wafer, comprising the following steps:

[0047] S1, preparing a substrate 100;

[0048] In some embodiments, the substrate may be selected from a sapphire substrate, a silicon substrate, a silicon carbide substrate, and a gallium nitride substrate. Preferably, the substrate is a silicon substrate.

[0049] S2, depositing a buffer layer 200, a channel layer 300, an insertion layer 400, a barrier layer 500, and a cap layer 600 in sequence on the substrate 100;

[0050] The buffer layer 200 includes a BAlN layer 210 , a BGaN layer 220 , an AlGaN layer 230 , and a SiN layer 240 sequentially stacked on the substrate 100 .

[0051] Step S2 specifically includes the following steps:

[0052] S21 , depositing a buffer layer 200 on the substrate 100 .

[0053] In some embodiments, the growth temperature of the BAlN layer 210 is 700°C~900°C, and the pressure is 50torr~500torr; the growth temperature of the BGaN layer 220 is 700°C~900°C, and the pressure is 50torr~500torr; the growth temperature of the AlGaN layer 230 is 700°C~900°C, and the pressure is 50torr~500torr; the growth temperature of the SiN layer is 900°C~1100°C, and the pressure is 50torr~500torr.

[0054] S22 , depositing a channel layer 300 on the buffer layer 200 .

[0055] In some embodiments, the channel layer 300 is a GaN layer, the temperature of the reaction chamber is controlled at 1000°C to 1200°C, the pressure is 50 torr to 500 torr, N source and Ga source are introduced, and a GaN channel layer with a thickness of 0.5 nm to 5 μm is grown. The GaN channel layer provides a 2-DEG migration channel or path, and as the GaN thickness increases, the compressive stress is released through stacking faults, line defects are reduced, crystal quality is improved, and reverse leakage current is reduced.

[0056] S23 , depositing an insertion layer 400 on the channel layer 300 .

[0057] In some embodiments, the insertion layer 400 is an AlN insertion layer, the reaction chamber temperature is 700°C to 1100°C, the reaction chamber pressure is 100torr to 200torr, and the growth thickness is 0.5nm to 5nm. A very thin AlN layer is inserted between the AlGaN layer and the GaN layer, which increases the effective band step difference between the AlGaN layer and the GaN layer, prevents the penetration of the two-dimensional electron gas GaN layer, reduces the influence of alloy scattering, and thus improves the mobility of the two-dimensional electron gas.

[0058] S24 , depositing a barrier layer 500 on the insertion layer 400 .

[0059] In some embodiments, the barrier layer is an AlGaN barrier layer, the reaction chamber temperature is 800°C to 1200°C, the reaction chamber pressure is 100 torr to 200 torr, and the AlGaN barrier layer growth thickness is 5nm to 50nm. At the AlGaN / GaN interface, a heterojunction can be produced due to lattice matching. The bandgap width of AlGaN is greater than that of GaN. This gap in the bandgap width causes the heterojunction to form a broken band at the interface of the two materials. The electrons in the AlGaN layer will move toward the GaN side, and a triangular potential well will be formed on the surface of GaN. The electrons accumulated in the potential well are separated from the donors. Therefore, in the direction perpendicular to the two interfaces, the electrons are constrained on both sides and can only move in a thin layer parallel to the two interfaces. This thin layer of electrons is a two-dimensional electron gas.

[0060] S25 , depositing a cap layer 600 on the barrier layer 500 .

[0061] In some embodiments, the capping layer is a GaN capping layer, the reaction chamber temperature is 700°C to 1100°C, the reaction chamber pressure is 100 torr to 200 torr, and the growth thickness is 5nm to 50nm. The GaN capping layer increases the barrier height and reduces the gate leakage current.

[0062] Correspondingly, the present invention further provides a HEMT, wherein the HEMT comprises the above-mentioned high electron mobility transistor epitaxial wafer.

[0063] The present invention is further described below with specific embodiments:

[0064] Example 1

[0065] This embodiment provides a high electron mobility transistor epitaxial wafer, comprising a substrate, on which a buffer layer, a channel layer, an insertion layer, a barrier layer, and a cap layer are sequentially arranged;

[0066] The buffer layer includes a BAlN layer, a BGaN layer, an AlGaN layer and a SiN layer sequentially stacked on the substrate.

[0067] The thickness of the BAlN layer is 45 nm, and the B component is 0.3;

[0068] The thickness of the BGaN layer is 35 nm, and the B component gradually changes from 0.3 to 0.05 along the BAlN layer toward the AlGaN layer;

[0069] The thickness of the AlGaN layer is 50 nm, and the Al component gradually changes from 0.05 to 0.25 along the direction from the BGaN layer to the SiN layer;

[0070] The thickness of the SiN layer is 15 nm.

[0071] Example 2

[0072] This embodiment provides a high electron mobility transistor epitaxial wafer, comprising a substrate, on which a buffer layer, a channel layer, an insertion layer, a barrier layer, and a cap layer are sequentially arranged;

[0073] The buffer layer includes a BAlN layer, a BGaN layer, an AlGaN layer and a SiN layer sequentially stacked on the substrate.

[0074] The thickness of the BAlN layer is 35 nm, and the B component is 0.3;

[0075] The thickness of the BGaN layer is 30 nm, and the B component gradually changes from 0.3 to 0.05 along the BAlN layer toward the AlGaN layer;

[0076] The thickness of the AlGaN layer is 38 nm, and the Al component gradually changes from 0.05 to 0.25 along the direction from the BGaN layer to the SiN layer;

[0077] The thickness of the SiN layer is 15 nm.

[0078] Example 3

[0079] This embodiment provides a high electron mobility transistor epitaxial wafer, comprising a substrate, on which a buffer layer, a channel layer, an insertion layer, a barrier layer, and a cap layer are sequentially arranged;

[0080] The buffer layer includes a BAlN layer, a BGaN layer, an AlGaN layer and a SiN layer sequentially stacked on the substrate.

[0081] The thickness of the BAlN layer is 52 nm, and the B component is 0.3;

[0082] The thickness of the BGaN layer is 41 nm, and the B component gradually changes from 0.3 to 0.05 along the BAlN layer toward the AlGaN layer;

[0083] The thickness of the AlGaN layer is 65 nm, and the Al component gradually changes from 0.05 to 0.25 along the direction from the BGaN layer to the SiN layer;

[0084] The thickness of the SiN layer is 15 nm.

[0085] Example 4

[0086] This embodiment provides a high electron mobility transistor epitaxial wafer, comprising a substrate, on which a buffer layer, a channel layer, an insertion layer, a barrier layer, and a cap layer are sequentially arranged;

[0087] The buffer layer includes a BAlN layer, a BGaN layer, an AlGaN layer and a SiN layer sequentially stacked on the substrate.

[0088] The thickness of the BAlN layer is 45 nm, and the B component is 0.3;

[0089] The thickness of the BGaN layer is 35 nm, and the B component gradually changes from 0.3 to 0.05 along the BAlN layer toward the AlGaN layer;

[0090] The thickness of the AlGaN layer is 38 nm, and the Al component gradually changes from 0.05 to 0.25 along the direction from the BGaN layer to the SiN layer;

[0091] The thickness of the SiN layer is 22 nm.

[0092] Example 5

[0093] This embodiment provides a high electron mobility transistor epitaxial wafer, comprising a substrate, on which a buffer layer, a channel layer, an insertion layer, a barrier layer, and a cap layer are sequentially arranged;

[0094] The buffer layer includes a BAlN layer, a BGaN layer, an AlGaN layer and a SiN layer sequentially stacked on the substrate.

[0095] The thickness of the BAlN layer is 45 nm, and the B component is 0.3;

[0096] The thickness of the BGaN layer is 35 nm, and the B component gradually changes from 0.3 to 0.05 along the BAlN layer toward the AlGaN layer;

[0097] The thickness of the AlGaN layer is 50 nm, and the Al component gradually changes from 0.05 to 0.25 along the direction from the BGaN layer to the SiN layer;

[0098] The thickness of the SiN layer is 15 nm.

[0099] Example 6

[0100] This embodiment provides a high electron mobility transistor epitaxial wafer, comprising a substrate, on which a buffer layer, a channel layer, an insertion layer, a barrier layer, and a cap layer are sequentially arranged;

[0101] The buffer layer includes a BAlN layer, a BGaN layer, an AlGaN layer and a SiN layer sequentially stacked on the substrate.

[0102] The thickness of the BAlN layer is 45 nm, and the B composition is 0.35;

[0103] The thickness of the BGaN layer is 35 nm, and the B component gradually changes from 0.35 to 0.1 along the BAlN layer toward the AlGaN layer;

[0104] The thickness of the AlGaN layer is 50 nm, and the Al component gradually changes from 0.05 to 0.25 along the direction from the BGaN layer to the SiN layer;

[0105] The thickness of the SiN layer is 15 nm.

[0106] Example 7

[0107] This embodiment provides a high electron mobility transistor epitaxial wafer, comprising a substrate, on which a buffer layer, a channel layer, an insertion layer, a barrier layer, and a cap layer are sequentially arranged;

[0108] The buffer layer includes a BAlN layer, a BGaN layer, an AlGaN layer and a SiN layer sequentially stacked on the substrate.

[0109] The thickness of the BAlN layer is 45 nm, and the B composition is 0.25;

[0110] The thickness of the BGaN layer is 35 nm, and the B component gradually changes from 0.25 to 0.02 along the BAlN layer toward the AlGaN layer;

[0111] The thickness of the AlGaN layer is 50 nm, and the Al component gradually changes from 0.05 to 0.25 along the direction from the BGaN layer to the SiN layer;

[0112] The thickness of the SiN layer is 15 nm.

[0113] Example 8

[0114] This embodiment provides a high electron mobility transistor epitaxial wafer, comprising a substrate, on which a buffer layer, a channel layer, an insertion layer, a barrier layer, and a cap layer are sequentially arranged;

[0115] The buffer layer includes a BAlN layer, a BGaN layer, an AlGaN layer and a SiN layer sequentially stacked on the substrate.

[0116] The thickness of the BAlN layer is 45 nm, and the B component is 0.3;

[0117] The thickness of the BGaN layer is 35 nm, and the B component gradually changes from 0.3 to 0.05 along the BAlN layer toward the AlGaN layer;

[0118] The thickness of the AlGaN layer is 50 nm, and the Al component gradually changes from 0.05 to 0.35 along the direction from the BGaN layer to the SiN layer;

[0119] The thickness of the SiN layer is 15 nm.

[0120] Example 9

[0121] This embodiment provides a high electron mobility transistor epitaxial wafer, comprising a substrate, on which a buffer layer, a channel layer, an insertion layer, a barrier layer, and a cap layer are sequentially arranged;

[0122] The buffer layer includes a BAlN layer, a BGaN layer, an AlGaN layer and a SiN layer sequentially stacked on the substrate.

[0123] The thickness of the BAlN layer is 45 nm, and the B component is 0.3;

[0124] The thickness of the BGaN layer is 35 nm, and the B component gradually changes from 0.3 to 0.05 along the BAlN layer toward the AlGaN layer;

[0125] The thickness of the AlGaN layer is 50 nm, and the Al component gradually changes from 0.05 to 0.2 along the direction from the BGaN layer to the SiN layer;

[0126] The thickness of the SiN layer is 15 nm.

[0127] Comparative Example 1

[0128] This comparative example provides a high electron mobility transistor epitaxial wafer, which is different from Example 1 in that: the buffer layer thereof is not provided with a BAlN layer, and the rest is the same as Example 1.

[0129] Comparative Example 2

[0130] This comparative example provides a high electron mobility transistor epitaxial wafer, which is different from Example 1 in that: the buffer layer thereof is not provided with a BGaN layer, and the rest is the same as Example 1.

[0131] Comparative Example 3

[0132] This comparative example provides a high electron mobility transistor epitaxial wafer, which is different from Example 1 in that: the buffer layer thereof is not provided with an AlGaN layer, and the rest is the same as Example 1.

[0133] Comparative Example 4

[0134] This comparative example provides a high electron mobility transistor epitaxial wafer, which is different from Example 1 in that: the buffer layer thereof is not provided with a SiN layer, and the rest is the same as Example 1.

[0135] The high electron mobility transistor epitaxial wafers prepared in Example 1 to Example 9 and Comparative Example 1 to Comparative Example 4 were used to prepare HEMT devices. In the HEMT devices, performance such as the leakage current of the device buffer layer was tested.

[0136] Table 1 Performance test results of high electron mobility transistor epitaxial wafers obtained from Examples 1 to 9 and Comparative Examples 1 to 4

[0137]

[0138] Among them, XRD (002) data can characterize screw dislocations, and XRD (102) data can characterize mixed dislocations of screw dislocations and edge dislocations. The smaller the value of XRD (002) or XRD (102), the lower the dislocation density and the better the crystal quality. By comparing the test data of Example 1 to Example 9 and Comparative Example 1 to Comparative Example 4, it can be seen that the high electron mobility transistor epitaxial wafer provided by the present invention inserts a buffer layer with a specific structure. Under the above specific structure, the present invention can alleviate the lattice mismatch and thermal mismatch between the substrate and the epitaxial layer, release the thermal stress of the epitaxial layer, improve the crystal quality of the grown epitaxial layer, reduce the leakage current of the power device, and increase the concentration of the two-dimensional electron gas in the channel layer, thereby improving the device performance.

[0139] In the description of this specification, the description with reference to the terms "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0140] The above is a preferred embodiment of the invention. It should be pointed out that a person skilled in the art can make several improvements and modifications without departing from the principle of the invention. These improvements and modifications are also considered to be within the scope of protection of the invention.

Claims

1. A high electron mobility transistor epitaxial wafer, It is characterized in that It comprises a substrate, on which a buffer layer, a channel layer, an insertion layer, a barrier layer and a cap layer are sequentially arranged; The buffer layer comprises a BAlN layer, a BGaN layer, an AlGaN layer and a SiN layer sequentially stacked on the substrate; The Al component of the AlGaN layer gradually increases from low to high along the direction from the BGaN layer to the SiN layer.

2. The high electron mobility transistor epitaxial wafer according to claim 1, It is characterized in that The thickness of the BAlN layer is 10nm-100nm.

3. The high electron mobility transistor epitaxial wafer according to claim 1, It is characterized in that The thickness of the BGaN layer is 10nm-100nm.

4. The high electron mobility transistor epitaxial wafer according to claim 1, It is characterized in that The B component of the BGaN layer gradually decreases from high to low along the BAlN layer toward the AlGaN layer.

5. The high electron mobility transistor epitaxial wafer according to claim 1, It is characterized in that The thickness of the AlGaN layer is 10nm-100nm.

6. The high electron mobility transistor epitaxial wafer according to claim 1, It is characterized in that The thickness of the SiN layer is 1 nm to 50 nm.

7. A method for preparing a high electron mobility transistor epitaxial wafer according to any one of claims 1 to 6, It is characterized in that The following steps are involved: S1. Prepare substrate; S2, depositing a buffer layer, a channel layer, an insertion layer, a barrier layer, and a cap layer on the substrate in sequence; The buffer layer includes a BAlN layer, a BGaN layer, an AlGaN layer and a SiN layer sequentially stacked on the substrate.

8. The method for preparing a high electron mobility transistor epitaxial wafer according to claim 7, It is characterized in that The growth temperature of the BAlN layer is 700° C. to 900° C., and the pressure is 50 torr to 500 torr; The growth temperature of the BGaN layer is 700° C. to 900° C., and the pressure is 50 torr to 500 torr; The growth temperature of the AlGaN layer is 700° C. to 900° C., and the pressure is 50 torr to 500 torr; The growth temperature of the SiN layer is 900° C. to 1100° C., and the pressure is 50 torr to 500 torr.

9. A HEMT, It is characterized in that The HEMT comprises the high electron mobility transistor epitaxial wafer as claimed in any one of claims 1 to 6.

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