Image sampling system and medical-grade image sensor

Abstract

The present invention provides an image sampling system and a medical-grade image sensor, the image sampling system comprising: a pixel array, the pixel array having an exposure period; a plurality of reset voltage readout circuits, before the end of the exposure period, the reset voltage output circuit is electrically connected to the output end of the pixel array, and reads out the reset voltage signal of the pixel array, and the reset voltage readout circuit is floating outside the exposure period; a plurality of pixel voltage readout circuits, during the exposure period, the pixel voltage readout circuit is floating, and after the end of the exposure period, the pixel voltage readout circuit is electrically connected to the output end of the pixel array, and reads out the pixel voltage signal from the pixel array; and a voltage regulating module, electrically connected to the output end of the reset voltage readout circuit and the output end of the pixel voltage readout circuit, and outputs a differential signal of the pixel voltage signal and the reset voltage signal. The present invention can achieve high-precision signal sampling with relatively small integrated circuit resources.

Description

Technical Field

[0001] The present invention relates to the field of image sensing technology, and in particular to an image sampling system and a medical-grade image sensor. Background Art

[0002] Medical-grade image sensors can enter the human body and implement image sampling inside the human body, such as endoscopes. However, the realization of the functions of medical-grade image sensors depends on low-power, small-area image sensor chips. Due to power consumption and area limitations, the chip does not integrate column analog-to-digital conversion circuits. The gain error of medical-grade image sensors is large, resulting in large errors in the electrical signals actually obtained, making it difficult to achieve the clarity of consumer-grade image sensors.

[0003] Due to the lack of column analog-to-digital conversion circuits, pixel signals in the same row need to be stored and read out one by one. However, due to the leakage current of transistors, the method of reading out voltage signals in columns one after another will result in a shorter leakage current time for the column read out first and a longer leakage current time for the column read out later, so the image quality between different columns is uneven. In addition, capacitors occupy a large area of ​​integrated circuits, so it is difficult to balance the good sampling requirements and the area limitations of medical-grade image sensors. Therefore, the image quality of medical-grade image sensors is difficult to control. Summary of the invention

[0004] The purpose of the present invention is to provide an image sampling system and a medical-grade image sensor, which can achieve high-precision signal sampling with smaller integrated circuit resources and reduce the impact of leakage current on image sampling, thereby improving the imaging clarity of in-vivo sampling of medical-grade equipment.

[0005] In order to solve the above technical problems, the present invention is achieved through the following technical solutions:

[0006] The present invention provides an image sampling system, comprising:

[0007] A pixel array having an exposure period;

[0008] A plurality of reset voltage readout circuits, wherein before the exposure period ends, the reset voltage output circuit is electrically connected to the output terminal of the pixel array and reads out the reset voltage signal of the pixel array, and the reset voltage readout circuit is floating outside the exposure period;

[0009] a plurality of pixel voltage readout circuits, wherein the pixel voltage readout circuits are floating during the exposure period, and after the exposure period ends, the pixel voltage readout circuits are electrically connected to output terminals of the pixel array and read out pixel voltage signals from the pixel array; and

[0010] The voltage regulating module is electrically connected to the output end of the reset voltage readout circuit and the output end of the pixel voltage readout circuit, and outputs a differential signal of the pixel voltage signal and the reset voltage signal.

[0011] In one embodiment of the present invention, the voltage regulation module includes a fully differential amplifier, a first input terminal of the fully differential amplifier is electrically connected to the reset voltage readout circuit through a first column selection switch, and a second input terminal of the fully differential amplifier is electrically connected to the pixel voltage readout circuit through a second column selection switch.

[0012] In one embodiment of the present invention, the voltage regulation module includes a plurality of storage capacitors, which are electrically connected to the first output terminal or the second output terminal of the fully differential amplifier and receive the output charge of the fully differential amplifier, wherein some of the storage capacitors store pixel voltage data of the pixel array, and another part of the storage capacitors store reset voltage data of the pixel array.

[0013] In one embodiment of the present invention, the voltage regulating module includes a differential amplifier, a first input terminal of the differential amplifier is electrically connected to the storage capacitor and receives the reset voltage data, a second input terminal of the differential amplifier is electrically connected to the storage capacitor and receives the pixel voltage data, and an output terminal of the voltage regulating module outputs a differential signal of the pixel voltage data and the reset voltage data.

[0014] In one embodiment of the present invention, the first column selection switch and the second column selection switch are electrically connected to the same column circuit of the pixel array, and the first column selection switch and the second column selection switch are closed or opened at the same time.

[0015] In one embodiment of the present invention, the reset voltage readout circuit comprises:

[0016] a reset sampling capacitor, a first end of the reset sampling capacitor being electrically connected to the first column selection switch; and

[0017] A reset sampling switch, one end of which is electrically connected to the second end of the reset sampling capacitor, and the other end of which is electrically connected to the column circuit, wherein a plurality of the reset sampling switches are closed and opened before the end of the exposure period.

[0018] In one embodiment of the present invention, the pixel voltage readout circuit includes:

[0019] a pixel sampling capacitor, a first end of the pixel sampling capacitor being electrically connected to the second column selection switch; and

[0020] A pixel sampling switch, one end of which is electrically connected to the second end of the pixel sampling capacitor, and the other end of which is electrically connected to the column circuit, wherein the pixel sampling switch is closed after the exposure period ends.

[0021] In one embodiment of the present invention, the image sampling system includes a readout switch, one end of the readout switch is electrically connected to the reset sampling switch and the reset sampling capacitor, and one end of the readout switch is electrically connected to the pixel sampling switch and the pixel sampling capacitor. After the pixel sampling switch is closed, the readout switch is closed, and during the closing period of the readout switch, the column selection switches of the plurality of column circuits are closed and opened in sequence.

[0022] In an embodiment of the present invention, before the reset sampling switch is closed, the first column selection switch and the second column selection switch are closed, and after the pixel sampling switch is opened, the first column selection switch and the second column selection switch are opened.

[0023] The present invention provides a medical-grade image sensor, comprising:

[0024] An image sampling system as described above;

[0025] A signal conversion module is connected to the output end of the image sampling system and receives the differential signal output by the image sampling system. The signal conversion module outputs a digital signal after the differential signal is converted as the image data of the image sampling system.

[0026] The image processor is electrically connected to the output end of the signal conversion module and receives and processes the image data.

[0027] As described above, the present invention provides an image sampling system and a medical-grade image sensor, which can get rid of the influence of transistor leakage current on signal sampling, thereby reducing the imaging differences caused by leakage current in different readout column circuits. According to the image sampling system and medical-grade image sensor provided by the present invention, the analog gain of the image sampling system is only limited by the ratio of the coupling capacitance between the two-stage amplifier and the amplification capacitance of the second-stage amplifier, so the system analog gain is independent of the size of the sampling capacitor in the pixel array, thereby getting rid of the influence of the circuit area in the array limiting the size of the system analog gain. And according to the image sampling system and medical-grade image sensor provided by the present invention, it is possible to achieve double sampling of high-gain output signals and eliminate the offset voltage of the operational amplifier, thereby improving the accuracy of the circuit signal output and improving the image imaging accuracy and clarity.

[0028] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0030] Figure 1 FIG. 4 is a schematic diagram of the structure of an image sampling system in one embodiment of the present invention.

[0031] Figure 2 FIG. 4 is a schematic diagram of the structure of a pixel unit in an embodiment of the present invention.

[0032] Figure 3 FIG. 4 is a schematic diagram of the structure of an image sampling system in one embodiment of the present invention.

[0033] Figure 4 FIG. 4 is a schematic diagram of the structure of a reset voltage readout circuit and a pixel voltage readout circuit in one embodiment of the present invention.

[0034] Figure 5 Schematic diagram of the switch operation timing of the image sampling system in one embodiment of the present invention.

[0035] In the figure: 10, image sensor; 20, pixel array; 21, pixel unit; 30, row scanning circuit; 40, column readout circuit; 41, first output bus; 42, second output bus; 50, output module; 60, fully differential amplifier; 70, differential amplifier. DETAILED DESCRIPTION

[0036] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0037] Large-scale commercial image sensor chips include two categories: Charged Coupled Device (CCD) and Complementary Metal Oxide Semiconductor (CMOS) image sensor chips. The image sensor provided by the present invention is a CMOS image sensor. Compared with CCD sensors, CMOS image sensors have the characteristics of low power consumption, low cost and good compatibility with CMOS processes. They are not only used in the field of consumer electronics, such as miniature digital cameras, mobile phone cameras, camcorders and digital SLRs, but also in automotive electronics, monitoring, biotechnology and medicine. In medical-grade image sensors, the area of ​​the chip is extremely limited, and it is difficult to achieve good signal sampling. Therefore, the imaging accuracy of medical-grade image sensors is not high. Please refer to Figure 1 As shown, the image sensor 10 includes a plurality of pixel arrays 20, a row scanning circuit 30, a column readout circuit 40, and an output module 50. The row scanning circuit 30 completes the input of the control signal of each row of pixel units 21, so that the post-exposure signal conversion and readout of the pixel array 20 can be realized. The row scanning circuit 30 can select the pixel units 21 of the corresponding row, and then read out the exposure data of each column of the selected pixel units 21 column by column through the column readout circuit 40. The output module 50 is electrically connected to the column readout circuit 40, receives the signal of the column readout circuit 40 and outputs it. By analyzing and processing the exposure data, the image data is obtained, thereby forming the image information of the current exposure.

[0038] See also Figure 1 and Figure 2 As shown, in one embodiment of the present invention, the pixel array 20 includes a plurality of pixel units 21, and the plurality of pixel units 21 are distributed in an array along the row direction and the column direction. In this embodiment, the pixel unit 21 includes a photodiode PD and a plurality of working transistors. Among them, the photodiode PD is a photosensitive element, which can convert the light signal of the incident light into an electrical signal. The working transistor is connected to the photodiode PD to receive the electrical signal converted by the photodiode PD. Among them, the working transistor is a MOS tube. In this embodiment, the working transistor can be a reset transistor RX, a transfer transistor TX and a selection transistor SX. Among them, one end of the photodiode PD is grounded, and the other end is electrically connected to the drain of the transfer transistor TX. Among them, the source of the transfer transistor TX is electrically connected to the floating node FD. Among them, the drain of the reset transistor RX is electrically connected to the power supply end, and the source of the reset transistor RX is electrically connected to the floating node FD. The drain of the selection transistor SX is electrically connected to the floating node FD, and the source of the selection transistor SX is used for the charge V PIX. In the present embodiment, the gate of the reset transistor RX, the gate of the transfer transistor TX and the gate of the selection transistor SX are electrically connected to the row scanning circuit 30, and receive the control signal of the row scanning circuit 30. For example, when a high-level signal is received, the transistor is closed, when a low-level signal is received, the transistor is disconnected, and so on. It should be noted that according to the number of working transistors in a single pixel unit 21, the pixel unit 21 is divided into a multi-T pixel structure. In the present embodiment, the pixel unit 21 is, for example, a 3T pixel structure. In other embodiments of the present invention, the pixel unit 21 may also be a 4T pixel structure, a 6T pixel structure, and so on.

[0039] See also Figures 1 to 5 As shown, in one embodiment of the present invention, the image sampling system includes a pixel array 20, a plurality of reset voltage readout circuits, a plurality of pixel voltage readout circuits and a voltage regulating module. The pixel array 20 has an exposure period. The exposure period is a period of time for exposing the photodiode PD. During the exposure period, the reset voltage output circuit is electrically connected to the output end of the pixel array 20, and reads out the reset voltage signal of the pixel array 20. The output end of the pixel array 20 is the output end of the pixel unit 21. Outside the exposure period, the reset voltage readout circuit is in a floating state. The floating state is the off state of the on transistor or the on switch. After the exposure period, the pixel voltage readout circuit is electrically connected to the output end of the pixel array 20, and reads out the pixel voltage signal from the pixel array 20. During the exposure period, the pixel voltage readout circuit is in a floating state. After the pixel voltage readout circuit works, the voltage regulating module is electrically connected to the output end of the reset voltage readout circuit and the output end of the pixel voltage readout circuit, and outputs the differential signal of the adjusted pixel voltage signal and the reset voltage signal as accurate pixel data.

[0040] See also Figure 2 and Figure 5 As shown, in one embodiment of the present invention, when the transmission transistor TX receives a high level signal, the transmission transistor TX is closed. When the transmission transistor TX is closed, the charge in the photodiode PD can be conducted to the floating node FD through the transmission transistor TX. In this embodiment, the time interval from the disconnection of the transmission transistor TX to the closing and disconnection of the transmission transistor TX is t. Specifically, the exposure period is the time interval between two adjacent disconnections of the transmission transistor TX. Figure 5 As shown, the exposure period of the pixel unit 21 is t.

[0041] See also Figure 2 and Figure 5As shown, in one embodiment of the present invention, when the reset transistor RX receives a high level signal, the reset transistor RX is turned on, and at the same time, the charge data of the floating node FD is initialized. At the beginning of the exposure period, the reset transistor RX remains turned on, thereby maintaining the initialization state of the floating node FD. Before the exposure period ends, specifically, before the reset voltage readout circuit is electrically connected to the column circuit, the reset transistor RX receives a low level signal and is turned off. At this time, the reset voltage readout circuit is electrically connected to the column circuit, so that the reset voltage signal of the pixel unit 21 can be read out.

[0042] See also Figures 1 to 4 As shown, in one embodiment of the present invention, the pixel array 20 has a plurality of column circuits, wherein each column circuit is electrically connected to a different reset voltage readout circuit and a different pixel voltage readout circuit. In this embodiment, the image sampling system includes a first column selection switch S SEL1 and the second column selector switch S SEL2 , where the first column selector switch S SEL1 The second column selector switch S is electrically connected to the first input terminal of the voltage regulating module. SEL2 is electrically connected to the second input terminal of the voltage regulating module. SEL1 and the second column selector switch S SEL2 The first column selection switch S is electrically connected to the same column circuit of the pixel array 20. SEL1 and the second column selector switch S SEL2 Closed or opened simultaneously.

[0043] See also Figures 1 to 5 As shown, in one embodiment of the present invention, the column readout circuit 40 includes a first output bus 41 and a second output bus 42. The first column select switch S SEL1 The second column selection switch S is electrically connected to the first output bus 41, and the first output bus 41 is electrically connected to the first input terminal of the voltage regulating module. SEL2 The second output bus 42 is electrically connected to the second input terminal of the voltage regulating module. Figure 5 In S SEL Indicates the first column selection switch S SEL1 and the second column selector switch S SEL2 When the first column selector switch S SEL1 and the second column selector switch S SEL2 When a high level signal is received, the first column select switch S SEL1 and the second column selector switch S SEL2 When closed, the reset voltage readout circuit and the pixel voltage readout circuit are both electrically connected to the voltage regulating module, thereby outputting a reset voltage signal and a pixel voltage signal.

[0044] See also Figures 1 to 5 As shown, in one embodiment of the present invention, the reset voltage readout circuit includes a reset sampling capacitor C VR and reset sampling switch S VR Among them, the reset sampling capacitor C VR The first end of the first column select switch S SEL1 Electrical connection, reset sampling switch S VR One end of the reset sampling capacitor C VR The second end of the sampling switch is electrically connected to S VR The other end is electrically connected to the column circuit. Figure 5 As shown, when the pixel unit 21 is reset, the row scanning circuit 30 sends a reset signal to the reset transistor RX, turning on the reset transistor RX, thereby resetting the charge of the floating node FD to the initial state. During the exposure period, before the transfer transistor TX is closed, the reset sampling switch S is closed. VR The charge of the floating node FD is read out and stored in the reset sampling capacitor C. VR , as a reset voltage signal.

[0045] See also Figures 1 to 5 As shown, in one embodiment of the present invention, the pixel voltage readout circuit includes a pixel sampling capacitor C VS and pixel sampling switch S VS . Pixel sampling capacitor C VS The first end of the second column select switch S SEL2 Electrical connection. Pixel sampling switch S VS One end of the pixel sampling capacitor C VS The second end of the pixel sampling switch S VS The other end of is electrically connected to the column circuit. After the transmission transistor TX is closed, the pixel sampling switch S VS Closed, so that the current charge of the floating node FD is read out and stored in the pixel sampling capacitor C VS , as the pixel voltage signal.

[0046] See also Figures 1 to 5 As shown, in one embodiment of the present invention, the voltage regulating module includes a fully differential amplifier 60, and the first input end of the fully differential amplifier 60 is connected to the first column selection switch S SEL1 The second input terminal of the fully differential amplifier 60 is electrically connected to the reset voltage readout circuit through the second column select switch S SEL2 In this embodiment, the fully differential amplifier 60 includes a first input terminal V IP and the second input terminal V IN Among them, the first input terminal V IP The second input terminal VIN is the inverting input terminal. Among them, the first input terminal V IP The second input terminal V IN The fully differential amplifier 60 has a first reset switch S I , when the first reset switch S I The fully differential amplifier 60 enters the working state. In this embodiment, the fully differential amplifier 60 receives a signal, amplifies the signal and outputs the signal, thereby increasing the pixel voltage signal and the reset voltage signal.

[0047] See also Figures 1 to 5 As shown, in one embodiment of the present invention, the voltage regulating module includes a storage capacitor C C and differential amplifier 70. The storage capacitor C C One end of the storage capacitor C is electrically connected to the output end of the fully differential amplifier 60. C One end of is electrically connected to the input end of the differential amplifier 70. The electrical signal amplified by the fully differential amplifier 60 is stored in the storage capacitor C C In this embodiment, the differential amplifier 70 includes a second reset switch S II When the second reset switch S II The differential amplifier 70 is disconnected and enters the working state. In this embodiment, the positive input terminal of the differential amplifier 70 is electrically connected to the first output terminal of the full differential amplifier 60 and receives the pixel voltage signal. The negative input terminal of the differential amplifier 70 is electrically connected to the second output terminal of the full differential amplifier 60 and receives the reset voltage signal. In this embodiment, the storage capacitor C C There are 2, one of which is a storage capacitor C C The charge of the reset voltage signal is stored in the other storage capacitor C C The charge of the pixel voltage signal is stored in the storage capacitor C C The charge in the first reset switch S is input to the differential amplifier 70. After being processed by the differential amplifier 70, the differential amplifier 70 outputs a differential signal of the reset voltage signal and the pixel voltage signal. I and the second reset switch S II Alternately closed. Among them, the first reset switch S I Priority is given to closing the second reset switch S II Closed so that the reset voltage signal and the pixel voltage signal are amplified first and then processed by the differential amplifier 70.

[0048] See also Figures 1 to 5 As shown, in one embodiment of the present invention, the image sampling system includes a readout switch S R , read switch S R One end of the reset sampling switch SVR and reset sampling capacitor C VR Electrical connection, read switch S R One end of the pixel sampling switch S VS and pixel sampling capacitor C VS In this embodiment, the first reset switch S I Before closing, close the readout switch S R , so that the reset sampling capacitor C VR and pixel sampling capacitor C VS The upper plates of the pixels 20 are brought into the same potential, thereby ensuring that the differential amplifier 70 can obtain an accurate differential signal. The column circuits of the plurality of pixel arrays 20 output pixel voltage signals and reset voltage signals column by column.

[0049] In this embodiment, during the exposure period t, the first reset switch S I and the second reset switch S II Closed and lasts until the column selector switch S SEL Specifically, during the sampling phase, the column selection switch S SEL All are closed, the first output bus 41 and the second output bus 42 are fixed bias voltages, and the bias voltage value depends on the reset voltage value of the fully differential amplifier 60. VR When closed, the pixel reset voltage signal is sampled to the reset voltage sampling capacitor C VR If the signal sampling switch S VS When closed, the pixel voltage signal is sampled to the pixel voltage sampling capacitor C VS In the readout phase, reset the voltage sampling switch S VR and pixel voltage sampling switch S VS Open and read switch S R Close, select switch S SEL Specifically, any column circuit can be selected and the electrical signal of the column circuit can be read out, and the column selection switch S corresponding to the selected column circuit can be closed. SEL . The first reset switch S I and the second reset switch S II The full differential amplifier 60 and the differential amplifier 70 are alternately closed and reset. The control clocks of the full differential amplifier 60 and the differential amplifier 70 do not overlap, so that the voltage signal stored in the sampling capacitor is differentiated and amplified for output.

[0050] The present invention also provides a medical-grade image sensor, which includes an image sampling system, a signal conversion module and an image processor. The signal conversion module is connected to the output end of the image sampling system and receives the differential signal output by the image sampling system. The signal conversion module outputs a digital signal after the differential signal is converted as image data of the image sampling system. The image processor is electrically connected to the output end of the signal conversion module to receive and process the image data. In this embodiment, the image sampling system is located on a separate chip and can enter the human body together with the medical device to complete image sampling, while the signal conversion module and the image processor are located outside the chip. The present invention does not limit the structure and type of the signal conversion module and the image processor.

[0051] The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. An image sampling system, characterized in that: include: A pixel array having an exposure period; A plurality of reset voltage readout circuits, wherein before the exposure period ends, the reset voltage output circuit is electrically connected to the output terminal of the pixel array and reads out the reset voltage signal of the pixel array, and the reset voltage readout circuit is floating outside the exposure period, wherein the reset voltage readout circuit includes a reset sampling capacitor, and the reset sampling capacitor is used to store the reset voltage signal; a plurality of pixel voltage readout circuits, wherein the pixel voltage readout circuits are floated during the exposure period, and after the exposure period ends, the pixel voltage readout circuits are electrically connected to the output terminals of the pixel array and read out pixel voltage signals from the pixel array, wherein the pixel voltage readout circuits include pixel sampling capacitors, and the pixel sampling capacitors are used to store the pixel voltage signals; as well as A voltage regulating module, electrically connected to an output terminal of the reset voltage readout circuit and an output terminal of the pixel voltage readout circuit, and outputting a differential signal of the pixel voltage signal and the reset voltage signal; The voltage regulating module comprises: a fully differential amplifier, wherein a first input terminal of the fully differential amplifier is electrically connected to the reset voltage readout circuit via a first column selection switch, and a second input terminal of the fully differential amplifier is electrically connected to the pixel voltage readout circuit via a second column selection switch; a plurality of storage capacitors, the storage capacitors being electrically connected to the first output terminal or the second output terminal of the fully differential amplifier and receiving the output charge of the fully differential amplifier, wherein some of the storage capacitors store pixel voltage signals of the pixel array, and another part of the storage capacitors store reset voltage signals of the pixel array; a differential amplifier, wherein a first input terminal of the differential amplifier is electrically connected to the storage capacitor and receives the reset voltage signal, a second input terminal of the differential amplifier is electrically connected to the storage capacitor and receives the pixel voltage signal, and an output terminal of the voltage regulating module outputs a differential signal of the pixel voltage signal and the reset voltage signal; The fully differential amplifier comprises: a plurality of first amplifying capacitors, wherein a first end of the first amplifying capacitor is electrically connected to the reset sampling capacitor through the first column selecting switch, or is electrically connected to the pixel sampling capacitor through the second column selecting switch, and a second end of the first amplifying capacitor is electrically connected to the storage capacitor; a plurality of first reset switches, wherein the first reset switches are connected in parallel with the first amplifying capacitor, and when the first reset switches are disconnected, the fully differential amplifier receives and amplifies the signal, and outputs the reset voltage signal and the pixel voltage signal after the first amplification; The differential amplifier comprises: a plurality of second amplifying capacitors, wherein a first end of the second amplifying capacitor is electrically connected to the storage capacitor, and another end of the second amplifying capacitor is electrically connected to the output end of the differential amplifier; A plurality of second reset switches are connected in parallel with the second amplifying capacitor. When the second reset switch is disconnected, the differential amplifier receives and amplifies the signal and outputs a differential signal between the reset voltage signal and the pixel voltage signal after the second amplification.

2. An image sampling system according to claim 1, characterized in that: The first column selection switch and the second column selection switch are electrically connected to a same column circuit of the pixel array, and the first column selection switch and the second column selection switch are closed or opened at the same time.

3. An image sampling system according to claim 2, characterized in that: The reset voltage readout circuit comprises: a reset sampling capacitor, a first end of the reset sampling capacitor being electrically connected to the first column selection switch; and A reset sampling switch, one end of which is electrically connected to the second end of the reset sampling capacitor, and the other end of which is electrically connected to the column circuit, wherein a plurality of the reset sampling switches are closed and opened before the end of the exposure period.

4. An image sampling system according to claim 3, characterized in that: The pixel voltage readout circuit comprises: a pixel sampling capacitor, a first end of the pixel sampling capacitor being electrically connected to the second column selection switch; and A pixel sampling switch, one end of which is electrically connected to the second end of the pixel sampling capacitor, and the other end of which is electrically connected to the column circuit, wherein the pixel sampling switch is closed after the exposure period ends.

5. An image sampling system according to claim 4, characterized in that: The image sampling system includes a readout switch, one end of the readout switch is electrically connected to the reset sampling switch and the reset sampling capacitor, and one end of the readout switch is electrically connected to the pixel sampling switch and the pixel sampling capacitor. After the pixel sampling switch is closed, the readout switch is closed, and during the closing period of the readout switch, the column selection switches of the plurality of column circuits are closed and opened in sequence.

6. An image sampling system according to claim 5, characterized in that: Before the reset sampling switch is closed, the first column selection switch and the second column selection switch are closed, and after the pixel sampling switch is opened, the first column selection switch and the second column selection switch are opened.

7. A medical-grade image sensor, characterized in that: include: An image sampling system as claimed in claim 1; A signal conversion module is connected to the output end of the image sampling system and receives the differential signal output by the image sampling system. The signal conversion module outputs a digital signal after the differential signal is converted as the image data of the image sampling system. as well as The image processor is electrically connected to the output end of the signal conversion module and receives and processes the image data.

Images