A semiconductor capacitor, array and preparation method thereof

Abstract

The present application provides a semiconductor capacitor, an array and a method for preparing the same, wherein the semiconductor capacitor comprises a substrate, the substrate being a heavily doped semiconductor material; a first electrode plate, the first electrode plate being directly disposed on the back of the substrate; a first conductive layer, a first dielectric layer and a second electrode plate being sequentially stacked on the front of the substrate; wherein the resistivity of the first conductive layer is less than that of the substrate. The semiconductor capacitor, the array and the method for preparing the same provided by the present application can further reduce the equivalent series inductance of the capacitor when the product is miniaturized and has a high capacitance.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor capacitor, an array and a method for manufacturing the same. Background Art

[0002] Capacitors are commonly used passive components in integrated circuits. In RF applications, capacitors are often integrated with inductors and / or resistors to achieve filtering and tuning. In RF applications, equivalent series inductance (ESL) is one of the key parameters. The smaller the ESL, the higher the self-resonant frequency (SRF) of the capacitor, which ensures that the capacitor can work stably at a higher frequency.

[0003] By reducing the distance that the current flows in the electrode and increasing the cross-sectional area of ​​the current, the equivalent series inductance (ESL) can be effectively reduced. At present, the single-layer ceramic capacitor (SLC) with sintering process can achieve a smaller ESL due to its shorter current path and larger current cross-section. However, for SLC, it adopts a ceramic sintering process. When selecting a low dielectric constant medium such as the first type of ceramic medium (such as C0G material), its dielectric layer is thicker (generally greater than 100um), which makes it difficult to achieve a larger capacitance. As for the use of high dielectric constant media such as the second type of ceramic medium (such as X7R), although a larger capacitance can be achieved, its capacitance changes dramatically with temperature. At the same time, only using a high dielectric constant insulating layer to achieve a high capacitance of the capacitor will also lead to loss problems such as leakage of the capacitor, making it difficult to obtain high-performance capacitors overall.

[0004] The metal-oxide-semiconductor MOS capacitor made of semiconductor materials can use thinner dielectric materials to increase the capacitance, but because its capacitance changes directly with the voltage, it is difficult to determine its capacitance in the application. For MOS capacitors, it is best to make the capacitor work in the accumulation zone to obtain a stable capacitance and good high-frequency characteristics. Therefore, it is necessary to determine the operating voltage and substrate doping type according to the usage scenario. In the present invention, the semiconductor substrate is only used as a conductive substrate and does not contribute to the capacitance value. Therefore, any doping type (P-type or N-type) can be selected, and there is no limit on the operating voltage (as long as it works below the rated voltage). It can be seen that further research is needed to achieve high capacitance and reduce ESL on the basis of capacitor miniaturization. Summary of the invention

[0005] In order to solve the technical problem in the prior art that it is difficult to further reduce the equivalent series inductance of the capacitor when the product is miniaturized and has a high capacitance, the present invention provides the following technical solutions:

[0006] In a first aspect, the present application provides a semiconductor capacitor, the semiconductor capacitor comprising:

[0007] A substrate, which is a heavily doped semiconductor material;

[0008] A first electrode plate, the first electrode plate is directly disposed on the back side of the substrate;

[0009] A first conductive layer, a first dielectric layer and a second electrode plate are sequentially stacked on the front side of the substrate;

[0010] wherein the resistivity of the first conductive layer is smaller than that of the substrate;

[0011] The first electrode plate and the second electrode plate serve as the lead-out structure of the semiconductor capacitor, and the two are led outward from opposite directions.

[0012] Optionally, viewed from a plane perpendicular to the thickness direction of the substrate, at least one dimension of the second electrode plate is smaller than that of the first dielectric layer.

[0013] Optionally, viewed from a plane perpendicular to the thickness direction of the substrate, the first electrode plate and the second electrode plate have the same shape, and the first dielectric layer is retracted relative to the second electrode plate in at least one dimension, and the retracted space is filled by the second dielectric layer.

[0014] Optionally, the second dielectric layer has a height greater than that of the first dielectric layer.

[0015] Optionally, the second dielectric layer is directly sandwiched between the second electrode plate and the substrate.

[0016] Optionally, a second conductive layer is further included, and the second conductive layer is sandwiched between the second electrode plate and the first dielectric layer.

[0017] Optionally, a second dielectric layer is sandwiched between the second electrode plate and the first dielectric layer, and at least one through hole is opened in the second dielectric layer. The through hole is filled with a conductive metal material to connect the second electrode plate and the first dielectric layer.

[0018] Optionally, a third conductive layer is directly disposed on the first dielectric layer, the third conductive layer has a patterned morphology, and the third conductive layer is electrically connected to the second electrode plate through a through hole.

[0019] Optionally, the second dielectric layer is directly disposed between the first conductive layer and the second electrode plate, and the second dielectric layer contacts a side wall of the first dielectric layer.

[0020] Optionally, the material of the second conductive layer is different from that of the second electrode plate.

[0021] The second aspect of the present application provides a semiconductor capacitor array, the array comprising any semiconductor capacitor; and a connecting component for connecting multiple semiconductor capacitors; wherein the semiconductor capacitors are arranged vertically and / or horizontally; and multiple first external terminals and multiple second external terminals connected to the semiconductor capacitor array.

[0022] Optionally, the array is overall rectangular in shape when viewed from a plane perpendicular to the thickness of the substrate, and each first external terminal and each second external terminal are arranged on the long side of the rectangle.

[0023] The third aspect of the present application provides a method for preparing a semiconductor capacitor, the method comprising:

[0024] a substrate preparation step, preparing a substrate from a semiconductor material and introducing heavily doped impurities therein;

[0025] A first conductive layer preparation step, preparing a first conductive layer on a surface of one side of the substrate, wherein the resistivity of the first conductive layer is smaller than that of the substrate;

[0026] A first dielectric layer preparation step, growing a first dielectric layer material on the surface of the first conductive layer;

[0027] A second electrode plate preparation step, preparing the second electrode plate on the surface of the first dielectric layer;

[0028] A substrate thinning step, performing a thinning process on the side of the substrate opposite to the second electrode plate;

[0029] A first electrode plate preparation step, preparing a first electrode plate on the surface of the substrate exposed after the thinning process;

[0030] In the dicing and packaging step, a dicing process is performed, and the first electrode plate and the second electrode plate are directly used as lead-out structures of the semiconductor capacitor. The two are led outward from opposite directions and are respectively connected to external electrical contact structures.

[0031] Optionally, the second electrode plate preparation step includes a step of patterning the second electrode plate.

[0032] Optionally, the first dielectric layer preparation step includes a step of patterning the first dielectric layer;

[0033] And a second dielectric layer preparation step, after the patterned first dielectric layer, forming the second dielectric layer material and performing a planarization process.

[0034] Optionally, before the second electrode plate preparation step, the method further includes forming a second conductive material on the first dielectric layer.

[0035] Optionally, before the second electrode plate preparation step, the method further includes forming a second dielectric layer on the first dielectric layer, and then patterning the second dielectric layer to form a plurality of through holes penetrating the second dielectric layer.

[0036] Optionally, after the first dielectric layer preparation step is completed, a third conductive layer is directly prepared on the first dielectric layer, and then a second dielectric layer and a through hole formation step are performed, wherein the through hole is connected to the third conductive layer and the second electrode plate.

[0037] Optionally, after the preparation of the third conductive layer is completed, a patterning step is further included to form a pattern on the third conductive layer.

[0038] Optionally, after the preparation of the third conductive layer is completed, a patterning step is further included to form a pattern between the third conductive layer and the first dielectric layer; after the second dielectric layer is formed, it contacts the side wall of the first dielectric layer.

[0039] Compared with the prior art, the present invention has the following beneficial effects:

[0040] 1. The semiconductor capacitor for which protection is sought in the present invention avoids the formation of a metal-oxide-semiconductor (MOS) junction formed by direct contact between the dielectric layer and the semiconductor substrate by providing a first conductive layer, thereby structurally avoiding the change in electrical characteristics that makes it difficult to fix the capacitance value caused by the MOS capacitor effect, thereby maintaining the stability of the capacitor performance. At the same time, the first conductive layer can also increase the adhesion of the dielectric material on the substrate, ensuring that it can be firmly superimposed on the substrate, improving the reliability during the manufacturing process and the long-term stability of the device.

[0041] 2. The capacitor for which protection is sought in the present invention is based on semiconductor materials, rather than traditional capacitors based on ceramic materials, such as MLCC or SLC. The first dielectric layer in the capacitor structure is prepared by a semiconductor process and can be obtained by growth processes such as sputtering and deposition. It can reliably prepare nanoscale film layers with excellent uniformity. The reliability of the device can be improved by reducing the thickness of the first dielectric layer to obtain a high capacitance. At the same time, by using a heavily doped silicon substrate, which actually serves as a lead structure directly connected to the first electrode plate, it can reduce energy losses in the power supply and signal paths and improve the power handling capability of the capacitor in high-power applications.

[0042] 3. The capacitor for which protection is requested in the present invention can also easily control the specific capacitance. Specifically, from the perspective of a plane perpendicular to the thickness direction of the substrate, the second electrode plate is set to have at least one dimension smaller than the first dielectric layer, or the first dielectric layer sandwiched between the first electrode plate and the second electrode plate has a retracted morphology in at least one dimension. At this time, not only can the size of the capacitor be accurately controlled by changing the area of ​​the electrode plate or the first dielectric layer, but the path between the side of the second electrode plate and the side of the first conductive layer in the capacitor can also be increased to prevent the sandwiched first dielectric layer from being broken down by air, thereby improving the flexibility and reliability of the device as a whole.

[0043] 4. The semiconductor capacitors for which protection is sought in the present invention have the characteristic of a simpler subsequent mounting process. When discrete capacitors are assembled to a circuit board, conductive glue and other solvents with specific fluidity are often used to fix them to conduct electricity. When SLC capacitors are used, the amount of conductive sol used needs to be precisely controlled, otherwise too much conductive sol will overflow to the side of the dielectric layer of the SLC capacitor, resulting in drift of the actual capacitance value, easy breakdown and other problems. When applied to miniaturized devices, it will further lead to a sharp increase in the risk of device failure. In the present invention, the thickness of the substrate in the device structure is relatively large, and the thickness of the first electrode plate and the substrate located below has a greater tolerance thickness for the subsequent overflow of the conductive sol, making the subsequent mounting process more convenient. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 A structural diagram of a semiconductor capacitor provided for this application;

[0045] Figure 2 A schematic diagram of a modified embodiment of a semiconductor capacitor provided by the present application;

[0046] Figure 3 A structural diagram of another variant embodiment of the semiconductor capacitor provided in the present application;

[0047] Figure 4 A deformed structure diagram of a semiconductor capacitor provided in this application;

[0048] Figure 5 A deformed structure diagram of a semiconductor capacitor provided in this application;

[0049] Figure 6 A deformed structure diagram of a semiconductor capacitor provided in this application;

[0050] Figure 7 A structural diagram of a semiconductor capacitor shown as an exemplary embodiment of the present application;

[0051] Figure 8 A deformed structure diagram of a semiconductor capacitor provided in this application;

[0052] Fig. 9 A semiconductor capacitor array structure provided by the present application;

[0053] Fig.10 A top view of a semiconductor array shown in the present application;

[0054] Fig.11 A flow chart of a method for preparing a semiconductor capacitor provided in the present application.

[0055] Among them, 1-substrate; 2-first electrode plate; 3-first conductive layer;

[0056] 4 - first dielectric layer; 41 - first dielectric sublayer; 42 - first dielectric sublayer; 43 - first dielectric sublayer;

[0057] 5 - second electrode plate; 51 - one layer in the second electrode plate; 52 - two layers in the second electrode plate; 53 - three layers in the second electrode plate;

[0058] 6 - second dielectric layer; 7 - second conductive layer; 8 - through hole; 9 - third conductive layer. DETAILED DESCRIPTION

[0059] Here, exemplary embodiments are described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application.

[0060] The terms used in this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The singular forms of "a", "the" and "the" used in this application are also intended to include plural forms unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used in this article refers to and includes any or all possible combinations of one or more associated listed items.

[0061] It should be understood that although the terms first, second, third, etc. may be used in the present application to describe various information, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0062] Specific embodiments are given below to introduce the technical solution of the present application in detail.

[0063] Figure 1 The structure diagram of the semiconductor capacitor provided for this application. Please refer to Figure 1 , the semiconductor capacitor provided in this embodiment may include:

[0064] Substrate 1, which is a heavily doped semiconductor material;

[0065] A first electrode plate 2, directly disposed on the back side of the substrate 1;

[0066] A first conductive layer 3, a first dielectric layer 4 and a second electrode plate 5 are sequentially stacked on the front side of the substrate 1;

[0067] The resistivity of the first conductive layer 3 is smaller than that of the substrate 1 ; the first electrode plate 2 and the second electrode plate 5 serve as the lead-out structure of the semiconductor capacitor, and both are led outward from opposite directions.

[0068] It should be noted that the material of the substrate 1 can be a heavily doped semiconductor material (without limitation on the doping type), and specifically silicon, silicon germanium, gallium nitride, etc. can be selected. Preferably, heavily doped silicon is selected as the substrate material, which has a relatively low resistivity, less than 1 , which can be used as a conductor connected to the first electrode plate 2. Specifically, the heavily doped silicon substrate with low resistivity helps to improve the conductivity and reduce the resistance loss inside the capacitor, thereby improving the performance of the device. In addition, after the thickness of the silicon substrate is thinned, the thickness range is controlled between 50µm and 500µm. By thinning the substrate, the parasitic resistance in the capacitor can be further reduced, thereby improving the frequency response performance of the device. For example, in one embodiment, the thickness of the silicon substrate is set to 200µm.

[0069] Specifically, the first conductive layer 3, the first dielectric layer 4 and the second electrode plate 5 are stacked in sequence on the front side of the substrate 1. The first conductive layer 3 can avoid direct contact between the first dielectric layer 4 and the semiconductor substrate 1, and form a metal-oxide-semiconductor (MOS) junction, thereby structurally avoiding the degradation of electrical characteristics caused by the MOS capacitance effect, which makes it difficult to fix the capacitance value, thereby maintaining the stability of the capacitor performance. At the same time, the first conductive layer can also increase the adhesion of the dielectric material on the substrate, ensuring that the first conductive layer and subsequent stacking layers can be firmly prepared on the substrate, improving the reliability in the manufacturing process and the long-term stability of the device.

[0070] It should be noted that the first conductive layer 3 is made of a material with good conductivity, specifically, Ti, TiN, etc. At this time, the resistivity of the first conductive layer 3 is lower than that of the substrate 1, and a stable, low-resistance contact interface can be provided, thereby improving the bonding performance between the first dielectric layer 4 and the substrate 1, and can also effectively reduce the parasitic resistance and improve the overall performance of the capacitor.

[0071] It should also be noted that the material of the first dielectric layer 4 can be a dielectric material such as silicon nitride, silicon oxide, magnesium oxide, aluminum oxide, hafnium oxide, zirconium oxide, titanium oxide, tantalum oxide, or a multilayer film structure composed thereof. In addition, the thickness of the first dielectric layer 4 is determined by the capacitance value defined by the device, and the thinnest can reach the nanometer level.

[0072] Please continue to combine Figure 1It can be seen that the first electrode plate 2 and the second electrode plate 5 are respectively located on both sides of the substrate 1, wherein the materials of the first electrode plate 2 and the second electrode plate 5 can be the same or different materials can be selected. Both can be selected from materials with good conductive properties such as Ti, Ag, Ni, TiW, Au, TaN, etc., and two or more materials can be selected from them to form a multilayer film structure.

[0073] It should be noted that the first electrode plate 2 and the second electrode plate 5 serve as terminals for leading the capacitor outward. Specifically, the capacitor to be protected by the present invention can be directly fixed on the circuit board through the first electrode plate 2 by means of conductive colloid, solder, etc., and the second electrode plate 5 can be led outward by means of wirebond or the like.

[0074] The first electrode plate 2 and the second electrode plate 5 are led outward from opposite directions, which can simplify the layout on the circuit board, simplify the manufacturing process, make the capacitor easier to integrate into the overall circuit design, and reduce the electrical interference between different electrodes, thereby improving the electrical performance of the capacitor. In particular, the first electrode plate and the second electrode plate can be set to have the same shape, which helps to avoid distinguishing between positive and negative electrodes in the subsequent mounting process, thereby simplifying the mounting process.

[0075] Figure 2 This is a schematic diagram of a modified embodiment of the semiconductor capacitor provided by the present application. Please refer to Figure 2 , from the plane perpendicular to the thickness direction of the substrate 1, the second electrode plate 5 has at least one dimension that is smaller than the first dielectric layer 4. It should be noted that in this embodiment, the effective area of ​​the capacitor is changed by changing the size of the second electrode plate 5 to achieve the purpose of changing the capacitance value. In addition, the size of the second electrode plate 5 is smaller than the first dielectric layer 4, which actually forms the side of the first electrode plate 2 to shrink compared to the side of the first dielectric layer 4, which can increase the path between the side of the second electrode plate 5 and the side of the first conductive layer 3 below in the capacitor, and effectively avoid the first dielectric layer sandwiched therein from being broken down by air. It can be seen that in this embodiment, the reduced size of the second electrode plate 5 can conveniently and flexibly adjust the capacitance value and improve the reliability of the device. In addition, in actual applications, the shrinkage of the second electrode plate will form a different color relative to the edge of the chip, which is greatly different from the first electrode plate that has not been retracted, making it easier for the machine to identify the two-sided structure and reduce the difficulty of mounting.

[0076] Figure 3 For another modified embodiment structure diagram of the semiconductor capacitor provided in this application, please refer to Figure 3, viewed from a plane perpendicular to the thickness direction of the substrate 1, the first electrode plate 2 and the second electrode plate 5 have the same shape, and the first dielectric layer 4 is retracted in at least one dimension compared to the second electrode plate 5, and the space formed by the retraction is filled by the second dielectric layer 6. In practical applications, it can also be set that the second electrode plate 5 has at least one dimension smaller than the first dielectric layer 4 when viewed from a plane perpendicular to the thickness direction of the substrate 1. When the second electrode plate is retracted, a different color will be formed relative to the edge of the chip, which is greatly different from the first electrode plate that is not retracted, making it easier for the machine to identify the two-sided structure and reducing the difficulty of mounting.

[0077] It should also be noted that the first dielectric layer 4 is retracted relative to the second electrode plate 5 in at least one dimension, which means that the boundary portion of the first dielectric layer 4 does not completely fill the entire space between the first electrode plate 2 and the second electrode plate 5, and the unfilled space constitutes a retracted area relative to the first or second electrode plate. Furthermore, the second dielectric layer 6 is filled with the space in the retracted area. On the one hand, the dielectric constant of the second dielectric layer 6 can be selected to be different from that of the first dielectric layer 4. On the other hand, the second dielectric layer 6 can be used as a passivation layer to protect the edge of the first dielectric layer 4, protecting the first dielectric layer 4 from the external environment. In particular, when selecting the material of the second dielectric layer 6, a material with a smaller dielectric constant can be selected, such as silicon oxide, silicon nitride, etc.

[0078] Figure 4 Based on the application provided Figure 3 For the deformed structure diagram of the semiconductor capacitor shown in Figure 4 , the height of the second dielectric layer 6 is greater than that of the first dielectric layer 4, and the second dielectric layer 6 is directly sandwiched between the second electrode plate 5 and the substrate 1. It should be noted that the second dielectric layer 6 is directly sandwiched between the second electrode plate 5 and the substrate 1, and can cover both the first dielectric layer 4 and the first conductive layer 3, so as to provide more effective isolation protection for both. In addition, the second dielectric layer 6 is located between the second electrode plate 5 and the substrate 1, which can provide additional buffering and support, and help improve the stability of the capacitor.

[0079] In combination with the above content, it should also be noted that the dielectric constant of the second dielectric layer is smaller than that of the first dielectric layer, wherein the first dielectric layer has a higher dielectric constant and is generally used to increase the overall capacitance of the capacitor, and the second dielectric layer has a lower dielectric constant and can be used to fill the retracted part or as an additional insulating material.

[0080] Figure 5 Based on the application provided Figure 4 For the deformed structure diagram of the semiconductor capacitor shown in Figure 5 ,exist Figure 5The semiconductor capacitor shown also includes a second conductive layer 7, which is sandwiched between the second electrode plate 5 and the first dielectric layer 4. At this time, the second conductive layer 7 serves as an etching stop layer for planarization processes such as chemical mechanical polishing (CMP), and is also used to protect the first dielectric layer during the planarization process to avoid etching damage to the first dielectric layer and to prevent the risk of breakdown caused by excessive thinning of certain areas of the first dielectric layer, thereby ensuring the electrical performance and thickness uniformity of the first dielectric layer.

[0081] It should also be noted that the second conductive layer 7 and the second electrode plate 5 can be made of different materials to provide optimized performance for different electrical requirements. Specifically, the second conductive layer 7 can be made of one or more materials such as Ti, W, TiN, and Cu.

[0082] Figure 6 Based on the application provided Figure 4 For the deformed structure diagram of the semiconductor capacitor shown in Figure 6 ,exist Figure 6 The semiconductor capacitor shown in the figure not only has Figure 5 The second conductive layer 7 in the illustrated embodiment realizes protection of the top of the first dielectric layer 4 during the planarization process, and also simultaneously shrinks the second conductive layer 7, the first dielectric layer 4 and the first conductive layer 3 compared to the first electrode plate 2 and the second electrode plate 5, and the shrunk space is filled with the second dielectric layer 6, and the second conductive layer 7, the first dielectric layer 4 and the first conductive layer 3 are passivated and protected by the second dielectric layer 6.

[0083] Figure 7 The structure diagram of the semiconductor capacitor shown in an exemplary embodiment of the present application is shown in FIG. Figure 7 , which is different from the aforementioned capacitor structure, a second dielectric layer 6 is sandwiched between the second electrode plate 5 and the first dielectric layer 4, and at least one through hole 8 is opened in the second dielectric layer 6, and the through hole 8 is filled with a conductive material. In addition, the capacitor structure also includes a third conductive layer 9 directly contacted above the first dielectric layer, and the third conductive layer 9 has a patterned morphology. The third conductive layer is electrically connected to the second electrode plate through the conductive material in the through hole 8 to connect the second electrode plate 5 and the third conductive layer 9, wherein the material of the third conductive layer 9 may be different from that of the second electrode plate 5.

[0084] Specifically, this embodiment can not only control the effective area in the actual capacitor structure by the area of ​​the third conductive layer 9, but also prevent the etching of the through hole from having an adverse effect on the first dielectric layer 4. By setting a plurality of through holes, the area of ​​the actual contact between the second electrode plate 5 and the third conductive layer 9 can be controlled, thereby realizing flexible adjustment of the capacitance value. At the same time, by providing a plurality of through holes in the second dielectric layer 6, the uniformity of the process can be improved, and the process deviation caused by large-area etching or CMP during the processing process can be avoided, which affects the reliability and effectiveness of the device.

[0085] It should be noted that in this embodiment, it can also be arranged that, viewed from a plane perpendicular to the thickness direction of the substrate 1, the second electrode plate 5 has at least one dimension smaller than the first dielectric layer 4. When the second electrode plate is retracted, a different color will be formed relative to the edge of the chip, which is greatly different from the first electrode plate that is not retracted, making it easier for the machine to identify the two-sided structure and reducing the difficulty of mounting.

[0086] Figure 8 This application provides a basis for Figure 7 For the deformed structure diagram of the semiconductor capacitor shown in Figure 8 , compared to Figure 7 In the embodiment, Figure 8 The first dielectric layer is patterned with the third conductive layer 9, and the sidewalls of the two structures are passivated and protected by the second dielectric layer 6, thereby improving the overall device performance.

[0087] The semiconductor capacitor provided by the present application, in a first aspect, avoids the formation of a metal-oxide-semiconductor (MOS) junction formed by direct contact between the dielectric layer and the semiconductor substrate by setting a first conductive layer, thereby structurally avoiding the change in electrical characteristics that makes it difficult to fix the capacitance value caused by the MOS capacitor effect, thereby maintaining the stability of the capacitor performance. At the same time, the first conductive layer can also increase the adhesion of the dielectric material on the substrate, ensuring that it can be firmly superimposed on the substrate, improving the reliability during the manufacturing process and the long-term stability of the device.

[0088] On the second aspect, the capacitor for which protection is sought in the present invention is based on semiconductor materials, rather than traditional capacitors based on ceramic materials, such as MLCC or SLC. The first dielectric layer in the capacitor structure is prepared by a semiconductor process, and can be obtained by growth processes such as sputtering and deposition. A nanometer-scale film layer can be reliably prepared with excellent uniformity, and the reliability of the device can be improved by reducing the thickness of the first dielectric layer to obtain a high capacitance. At the same time, by using a heavily doped silicon substrate, which actually serves as a lead structure directly connected to the first electrode plate, the energy loss in the power supply and signal paths can be reduced, and the power handling capability of the capacitor in high-power applications can be improved.

[0089] On the third aspect, the capacitor for which protection is requested by the present invention can also easily control the specific capacitance. Specifically, from the plane perpendicular to the thickness direction of the substrate, the second electrode plate is set to have at least one dimension smaller than the first dielectric layer, or the first dielectric layer sandwiched between the first electrode plate and the second electrode plate has a retracted morphology in at least one dimension. At this time, not only can the size of the capacitor be accurately controlled by the change in the area of ​​the electrode plate or the first dielectric layer, but also the path between the side of the second electrode plate and the side of the first conductive layer in the capacitor can be increased to avoid the first dielectric layer sandwiched therein from being broken down by air, thereby improving the flexibility and reliability of the device as a whole.

[0090] Fourthly, the semiconductor capacitors for which protection is sought in the present invention have the characteristic of a simpler subsequent mounting process. When discrete capacitors are assembled to a circuit board, a solvent with specific fluidity, such as conductive glue, is often used to fix them to be conductive. When SLC capacitors are applied, the amount of conductive sol used needs to be precisely controlled, otherwise too much conductive sol will overflow to the side of the dielectric layer of the SLC capacitor, resulting in drift of the actual capacitance value, easy breakdown and other problems, and when applied to miniaturized devices, it will further lead to a sharp increase in the risk of device failure. In the present invention, the thickness of the substrate in the device structure is relatively large, and the thickness of the first electrode plate and the substrate located below has a greater tolerance thickness for the subsequent overflow of the conductive sol, making the subsequent mounting process more convenient.

[0091] Corresponding to the aforementioned semiconductor capacitor embodiments, the present application also provides a semiconductor capacitor array.

[0092] Fig. 9 An array structure formed by stacking a plurality of semiconductor capacitors as shown in an exemplary embodiment of the present application includes a connecting component for connecting the plurality of semiconductor capacitors; wherein the semiconductor capacitors are arranged vertically and / or horizontally; and a plurality of first external terminals and a plurality of second external terminals connected to the semiconductor capacitor array. Please refer to Fig. 9 In this embodiment, an array is formed by vertically stacking three capacitors, and the array as a whole is in the shape of a pyramid. The capacitor array structure is coated with multiple passivation layers, and each capacitor structure is connected through a plurality of through-hole and other connecting structures to form an external terminal connected to an external structure.

[0093] It should be noted that the vertical arrangement can increase the number of capacitors within a limited space and improve the integration; the horizontal arrangement facilitates the parallel connection of circuits and improves the current carrying capacity and signal transmission efficiency; the combined vertical and horizontal arrangement can be optimized according to the specific circuit design and space limitations to achieve the best performance and layout effect.

[0094] Fig.10 For a top view of the semiconductor array shown in this application, please refer to Fig.10, the array is overall rectangular in shape when viewed from a plane perpendicular to the thickness of the substrate, and each of the first external terminals and each of the second external terminals are arranged on the long sides of the rectangle. Fig.10 , from the long side, in any one of the first side and the second side, the first external terminal and the second external terminal are alternately arranged, and from the short side, the first external terminal and the second external terminal are arranged oppositely. At this time, the flow direction of the current in the semiconductor array is as follows Fig.10 As shown by the arrows, the currents in two adjacent cross sections flow in opposite directions, which can reduce or even offset the ESL.

[0095] Corresponding to the aforementioned semiconductor capacitor and array embodiments, the present application also provides a method for preparing a semiconductor capacitor.

[0096] Fig.11 For a flow chart of the method for preparing a semiconductor capacitor provided in this application, please refer to Fig.11 , methods include:

[0097] S1201, substrate preparation step, preparing a substrate from semiconductor material and introducing heavily doped impurities therein.

[0098] Specifically, heavily doped impurities are introduced into the semiconductor material to obtain the heavily doped semiconductor material. The process of introducing heavily doped impurities into the substrate can be found in the introduction of the related art, which will not be described in detail here.

[0099] S1202, a first conductive layer preparation step, preparing a first conductive layer on a surface of one side of the substrate, wherein the resistivity of the first conductive layer is smaller than that of the substrate.

[0100] It should be noted that the metal material can be deposited on the substrate surface by sputtering deposition in physical vapor deposition (PVD) technology, or the metal material can be evaporated and deposited on the substrate surface by electron beam evaporation or thermal evaporation. The first conductive layer can also be prepared by chemical vapor deposition (CVD) method.

[0101] S1203, a first dielectric layer preparation step, growing a first dielectric layer material on the surface of the first conductive layer.

[0102] Specifically, the first dielectric layer can be patterned after being prepared as needed. That is, the first dielectric layer preparation step includes the step of patterning the first dielectric layer; and the second dielectric layer preparation step, after the patterned first dielectric layer, depositing the second dielectric layer material and performing a planarization process. The planarization process can be chemical mechanical polishing (CMP). At this time, the second dielectric layer deposited later will cover the sidewalls of the first dielectric layer to provide sufficient passivation protection thereto.

[0103] Another process step of preparing the first dielectric layer also includes a step of patterning the first dielectric layer and the first conductive layer thereunder; and a second dielectric layer preparation step, after the patterned first dielectric layer, depositing the second dielectric layer material and performing a planarization process. At this time, the second dielectric layer deposited later will cover the sidewalls of the first dielectric layer and the first conductive layer to provide sufficient passivation protection for both.

[0104] In order to prevent the first dielectric layer from being damaged during the patterning process, the process of the first dielectric layer can also have another variation. Specifically, after the first dielectric layer material is prepared, a second conductive layer is formed directly on it. The thickness of the second conductive layer does not need to be very large, but it can be used as a protective layer for the first dielectric layer and an etching stop layer for the planarization process. At the same time, a conductive material with good contact characteristics with the first dielectric layer can be selected to prepare the second conductive layer to further enhance the overall contact performance of the device.

[0105] S1204, a second electrode plate preparation step, depositing a second electrode plate on the surface of the first dielectric layer.

[0106] Specifically, the second electrode plate may be patterned after being prepared as needed to form an indentation in at least one dimension compared to the underlying structure.

[0107] In another preparation process, before the second electrode plate preparation step, it also includes, after completing the first dielectric layer preparation step, preparing a third conductive layer directly above the first dielectric layer; then forming a second dielectric layer on the third conductive layer, and then patterning the second dielectric layer to form a plurality of through holes penetrating the second dielectric layer, and the through holes extend from the top to the third conductive layer.

[0108] Furthermore, as required, after the preparation of the third conductive layer is completed, a patterning step can be further included to form a pattern that is indented compared to the first dielectric layer. At this time, the patterned third conductive layer actually corresponds to the area of ​​the upper plate of the capacitor, so that the capacitance value can be flexibly controlled by controlling the area of ​​the third conductive layer. At this time, the second dielectric layer deposited later will cover the sidewalls of the first dielectric layer to provide a certain passivation protection thereto.

[0109] In practical applications, the third conductive layer and the first dielectric layer can be patterned together when patterning the third conductive layer as needed. At this time, the second dielectric layer deposited later will cover the side walls of the first dielectric layer and the first conductive layer to provide sufficient passivation protection for both.

[0110] S1205, substrate thinning step, performing a thinning process on the opposite side of the second electrode plate in the substrate.

[0111] It should be noted that substrate thinning can reduce the thickness of the substrate material, thereby reducing the equivalent series resistance and improving the electrical performance and response speed of the device.

[0112] S1206, a first electrode plate preparation step, preparing a first electrode plate on the exposed substrate surface after the thinning process.

[0113] It should also be noted that the step of forming the first electrode plate may be a typical process for forming a metal layer, and a material different from that of the second electrode plate may be selected.

[0114] S1207, a dicing and packaging step, performing a dicing process, wherein the first electrode plate and the second electrode plate are directly used as lead-out structures of the semiconductor capacitor, and the two are led outward from opposite directions and are respectively connected to external electrical contact structures.

[0115] In particular, the second dielectric layer involved in the aforementioned process is formed later, specifically, by patterning the first dielectric layer structure to form a recessed space, and then filling it. As those skilled in the art will know, the second dielectric layer can also be prepared by forming it first, that is, first growing the second dielectric layer and patterning it, and then growing the first conductive layer and / or the first dielectric layer and / or the second conductive layer in the recessed space as needed.

[0116] The method for preparing a semiconductor capacitor provided in the present application optimizes the conductivity of the electrode, the capacitance value of the capacitor, and the overall electrical performance by selecting appropriate materials and processes. Thinning the substrate helps to manage heat more effectively and prevent overheating problems. In addition, various steps ensure good adhesion of the electrode and reduce contact resistance. Reliable packaging is also provided, and the process steps are optimized to improve manufacturing consistency, stability, and production efficiency.

[0117] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A semiconductor capacitor, characterized in that: The semiconductor capacitor comprises: A substrate, wherein the substrate is a heavily doped semiconductor material; A first electrode plate, the first electrode plate is directly disposed on the back side of the substrate; A first conductive layer, a first dielectric layer and a second electrode plate are sequentially stacked on the front side of the substrate; the first conductive layer is directly arranged on the surface of the substrate, and the first dielectric layer is directly arranged on the surface of the first conductive layer; The resistivity of the first conductive layer is smaller than that of the substrate.

2. The semiconductor capacitor according to claim 1, wherein: Viewed from a plane perpendicular to the thickness direction of the substrate, at least one dimension of the second electrode plate is smaller than that of the first dielectric layer.

3. The semiconductor capacitor according to claim 1, wherein: Viewed from a plane perpendicular to the thickness direction of the substrate, the first electrode plate and the second electrode plate have the same shape, and the first dielectric layer is retracted relative to the second electrode plate in at least one dimension, and the retracted space is filled by the second dielectric layer.

4. The semiconductor capacitor according to claim 3, characterized in that: The second dielectric layer has a height greater than that of the first dielectric layer.

5. The semiconductor capacitor according to claim 4, characterized in that: The second dielectric layer is directly sandwiched between the second electrode plate and the substrate.

6. The semiconductor capacitor according to claim 4, characterized in that: The invention also includes a second conductive layer, wherein the second conductive layer is sandwiched between the second electrode plate and the first dielectric layer.

7. The semiconductor capacitor according to claim 1, wherein: A second dielectric layer is sandwiched between the second electrode plate and the first dielectric layer, and at least one through hole is opened in the second dielectric layer, and the through hole is filled with a conductive material; The method further includes: a third conductive layer directly disposed on top of the first dielectric layer in contact with the first dielectric layer, wherein the third conductive layer has a patterned morphology, and the third conductive layer is electrically connected to the second electrode plate through the through hole.

8. The semiconductor capacitor according to claim 7, characterized in that: The second dielectric layer is directly disposed between the first conductive layer and the second electrode plate, and the second dielectric layer contacts a side wall of the first dielectric layer.

9. The semiconductor capacitor according to claim 6, wherein: The material of the second conductive layer is different from that of the second electrode plate.

10. A semiconductor capacitor array, characterized in that: It comprises a plurality of semiconductor capacitors as described in any one of claims 1 to 9; and connecting components for connecting the plurality of semiconductor capacitors; wherein the semiconductor capacitors are arranged vertically and / or horizontally; and a plurality of first external terminals and a plurality of second external terminals connected to the semiconductor capacitor array.

11. The semiconductor capacitor array according to claim 10, characterized in that: The array is overall in a rectangular shape when viewed from a plane perpendicular to the thickness of the substrate, and each of the first external terminals and each of the second external terminals are arranged on the long sides of the rectangle.

12. A method for preparing a semiconductor capacitor, characterized in that: The method comprises, in sequence, a substrate preparation step, preparing the substrate from a semiconductor material and introducing heavily doped impurities therein; A first conductive layer preparation step, directly preparing a first conductive layer on a surface of one side of the substrate, wherein the resistivity of the first conductive layer is smaller than that of the substrate; A first dielectric layer preparation step, directly growing a first dielectric layer material on the surface of the first conductive layer; A second electrode plate preparation step, preparing a second electrode plate on the surface of the first dielectric layer; A substrate thinning step, performing a thinning process on the side of the substrate opposite to the second electrode plate; A first electrode plate preparation step, directly preparing a first electrode plate on the surface of the substrate exposed after the thinning process; In the dicing and packaging step, a dicing process is performed, wherein the first electrode plate and the second electrode plate are directly used as lead-out structures of the semiconductor capacitor, and the two are led outward from opposite directions and are respectively connected to external electrical contact structures.

13. The preparation method according to claim 12, characterized in that: The second electrode plate preparation step includes a step of patterning the second electrode plate.

14. The preparation method according to claim 12, characterized in that: The first dielectric layer preparation step includes a step of patterning the first dielectric layer; And a second dielectric layer preparation step, after the first dielectric layer is patterned, a second dielectric layer material is formed and a planarization process is performed.

15. The preparation method according to claim 14, characterized in that: Before the second electrode plate preparation step, the method further includes forming a second conductive material on the first dielectric layer.

16. The preparation method according to claim 12, characterized in that: Before the second electrode plate preparation step, the method further includes forming a second dielectric layer on the first dielectric layer, and then patterning the second dielectric layer to form a plurality of through holes penetrating the second dielectric layer.

17. The preparation method according to claim 16, characterized in that: After the first dielectric layer preparation step is completed, a third conductive layer is prepared directly on the first dielectric layer, and then the second dielectric layer and through hole formation step is performed, wherein the through hole is connected to the third conductive layer and the second electrode plate.

18. The preparation method according to claim 17, characterized in that: After the preparation of the third conductive layer is completed, a patterning step is further included to form a pattern on the third conductive layer.

19. The preparation method according to claim 17, characterized in that: After the preparation of the third conductive layer is completed, a patterning step is further included to form a pattern between the third conductive layer and the first dielectric layer; after the second dielectric layer is formed, it contacts the side wall of the first dielectric layer.

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