Instruction scheduling device and method

Abstract

The present application discloses an instruction scheduling device and method. The instruction scheduling device is used in a controller of a storage device. The controller is coupled to multiple flash memory chips through a first channel. The instruction scheduling device includes: an instruction cache unit, which caches various instructions adapted to multiple flash memory chips through multiple instruction queues; a remaining time calculation unit, which is used to calculate the remaining execution time of a DQ instruction that is currently transmitting data through a data bus of the first channel; an arbitration unit, which is used to take instructions from multiple instruction queues, compare the estimated execution time of one or more CA instructions with the remaining execution time, so as to determine a CA instruction that is preferentially executed by the CA execution unit. The device improves the probability of CA instructions and DQ instructions being executed in parallel by optimizing the behavior of CA instructions and DQ instructions being executed in parallel under the SCA interface, so that the DQ bus obtains higher utilization and higher data bandwidth.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to an instruction scheduling device and method. Background Art

[0002] Currently, many storage devices, such as USB flash memory, SD card, CF card, SSD, eMMC embedded storage card, UFS device, etc., use flash storage media (especially NAND storage media) as the main storage media, and it has gradually become the mainstream form. Compared with the traditional magnetic media storage, the performance has made a qualitative leap. The traditional flash interface protocol (ONFi or Toggle) used by such storage devices uses the same bus for command / address and data transmission. As the data transmission rate of the flash interface increases, the command / address transmission rate does not change, resulting in an increase in the proportion of command / address transmission time, which in turn leads to a bottleneck in the improvement of the data transmission bandwidth of the flash interface.

[0003] In order to solve the problem of improving the data transmission bandwidth of the traditional flash memory interface, the new flash memory interface protocol (for example, Separate Command Address, SCA for short) separates the command / address and data transmission and puts them on two different transmission buses, that is, CA instructions are placed on the command and address (CA) bus for transmission, and DQ instructions (that is, data to be written to or read from the flash memory storage medium) are placed on the data (DATA, also called DQ) bus for transmission.

[0004] refer to Figure 1 As shown, the CA instructions transmitted by the CA bus 11 include CA instructions A to CA instructions D, and the data transmitted by the DQ bus 12 are DATA1 and DATA2 (DATA1 and DATA2 correspond to one DQ instruction respectively). According to the SCA protocol, before the data DATA1 is transmitted, the data transmission start mark SCE is sent through the CA bus 11, and after the transmission of DATA1 is completed, the data transmission end mark SCT is sent through the CA bus 11, and the data DATA2 is processed in the same way. However, it can be seen from the figure that the CA instructions and the DQ instructions cannot be perfectly executed in parallel in actual execution, which will waste part of the bandwidth utilization of the DQ bus. Summary of the invention

[0005] In view of this, an embodiment of the present disclosure provides an instruction scheduling device and method to improve the bandwidth utilization of a DQ bus.

[0006] According to a first aspect of an embodiment of the present disclosure, there is provided an instruction scheduling device, which is applied to a controller of a storage device, wherein the controller is coupled to a plurality of flash memory chips through a first channel, wherein the first channel includes a CA bus and a DQ bus, and the instruction scheduling device includes:

[0007] An instruction cache unit, which caches various instructions adapted to the multiple flash memory chips respectively through multiple instruction queues;

[0008] A remaining time calculation unit, used to calculate the remaining execution time of the DQ instruction currently performing data transmission through the data bus;

[0009] The arbitration unit is used to take instructions from the multiple instruction queues respectively, compare the estimated execution time of one or more CA instructions that can be executed in parallel with the DQ instruction with the remaining execution time, so as to determine a target CA instruction to be executed preferentially via the CA bus.

[0010] Optionally, the arbitration unit further compares the estimated execution time of each of one or more CA instructions that can be executed in parallel with the DQ instruction with the remaining execution time plus the additional compensation time to determine a target CA instruction to be executed preferentially via the CA bus.

[0011] Optionally, when there are multiple CA instructions whose expected execution times are all less than the remaining execution time, or when there are multiple CA instructions whose expected execution times are all less than the remaining execution time plus the additional compensation time, the arbitration unit selects the CA instruction with the highest priority as the target CA instruction according to a predetermined priority logic.

[0012] Optionally, the arbitration unit determines whether to add the remaining execution time to the additional compensation time for comparison according to whether the current scenario satisfies a certain condition.

[0013] Optionally, the remaining time calculation unit pre-stores a compensation schedule, and determines the additional compensation time by querying the compensation schedule.

[0014] Optionally, the additional compensation time is defined for various DQ instructions respectively; and / or, the estimated execution time is defined for various CA instructions respectively.

[0015] Optionally, the remaining time calculation unit calculates the remaining execution time by monitoring the transmitted data of the DQ instruction currently performing data transmission.

[0016] According to a second aspect of an embodiment of the present disclosure, a controller of a storage device is provided, comprising the instruction scheduling apparatus described above.

[0017] According to a third aspect of an embodiment of the present disclosure, there is provided a storage device, comprising: a coupled controller and a flash memory storage medium, wherein the controller is the controller described above.

[0018] According to a fourth aspect of an embodiment of the present disclosure, there is provided an instruction scheduling method for a controller of a storage device, wherein the controller is coupled to a plurality of flash memory chips respectively through a first channel, wherein the first channel includes a CA bus and a DQ bus, and the instruction scheduling method includes:

[0019] Taking out a plurality of instructions from a plurality of instruction queues respectively, wherein the plurality of instruction queues respectively correspond to instructions cached and adapted to a plurality of flash memory chips under the first channel;

[0020] Obtaining the remaining execution time of a DQ instruction currently performing data transmission through the data bus;

[0021] The estimated execution time of each of one or more CA instructions that can be executed in parallel with the DQ instruction among the plurality of instructions is compared with the remaining execution time plus the additional compensation time to determine a target CA instruction that is preferentially executed via the CA bus.

[0022] The instruction scheduling method and device provided by the embodiments of the present disclosure improve the probability of parallel execution of CA instructions and DQ instructions by optimizing the behavior of parallel execution of CA instructions and DQ instructions under the SCA interface, thereby achieving higher utilization and higher data bandwidth of the DQ bus. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0024] Figure 1 This is an example diagram of the CA bus and DQ bus;

[0025] Figure 2 is a schematic block diagram of an exemplary host system;

[0026] Figure 3 is a schematic diagram of the structure of an instruction scheduling device provided by an embodiment of the present disclosure;

[0027] Figures 4 to 7 An example diagram of parallel transmission of CA bus and DQ bus is given;

[0028] Figure 8 A flowchart of an instruction scheduling method provided by an embodiment of the present disclosure is shown;

[0029] Fig. 9 A flowchart of an instruction scheduling method provided by another embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0030] The present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown.

[0031] The present invention is described below based on embodiments, but the present invention is not limited to these embodiments. In the detailed description of the present invention below, some specific details are described in detail. It is possible for a person skilled in the art to fully understand the present invention without the description of these details. In order to avoid confusing the essence of the present invention, known methods, processes, flows, components and circuits are not described in detail.

[0032] Unless the context clearly requires otherwise, the words "include", "comprising" and the like throughout the specification and claims should be interpreted as inclusive rather than exclusive or exhaustive; that is, as "including but not limited to". In the description of the present invention, it should be understood that the terms "first", "second", etc. are used for descriptive purposes only and are not to be understood as indicating or implying relative importance. In addition, in the description of the present invention, unless otherwise specified, "plurality" means two or more.

[0033] Figure 2 is a schematic block diagram of an exemplary host system 100. The host system 100 is, for example, a personal computer, a notebook computer, or a server.

[0034] The host system 100 includes a host device 110 (e.g., a computer system including a main processor and a memory) and a storage device. The host device 110 may issue a host command to the storage device so that the storage device manages the data stored in the storage device according to the command. For example, the host device 110 may be communicatively connected to the storage device (e.g., through the host interface 121) and issue various commands (e.g., READ, WRITE, UNMAP, REASSIGNBLOCK, TRIM, etc.) to the storage device. The storage device may store, update, read and / or otherwise manage host data according to the address range prompted by the command. Once the command is executed, the storage device may transmit a response to the host device 110, indicating that the command has been successfully completed.

[0035] The storage device is composed of a controller 120 and a storage medium 130. The controller 120 parses the host command and converts the host command into an instruction adapted to the storage medium 130, then executes the instruction and feeds back the instruction result to the host device 110. The controller 120 is composed of various hardware and software, such as a (micro)processor, a cache unit such as SRAM and DRAM, and an interface circuit, and the software is a series of software programs that complete management functions, including but not limited to data reading and writing, bad block management, wear leveling, garbage collection, power failure recovery, and write balancing technology.

[0036] The storage medium 130 is used to store data. There are multiple channels (such as CH0 and CH1) between the controller 120 and the storage medium 130. The controller 120 and the storage medium 130 exchange data through each channel.

[0037] At present, the mainstream storage medium 130 is flash memory storage medium (especially NAND storage medium). Usually, each channel (such as CH0 or CH1 in the figure) is coupled to N (N is 2, 4, 8, etc.) flash memory chips, and the controller 120 needs to operate the corresponding flash memory chips through each channel. When the SCA protocol is used as the flash memory interface protocol, each channel includes two buses: DQ bus and CA bus. The controller 120 executes DQ instructions through the DQ bus to write or read data to the flash memory chip, and executes CA instructions through the CA bus to perform command / address operations on the flash memory chip.

[0038] In order to achieve higher utilization and higher transmission bandwidth of the DQ bus, the embodiment of the present disclosure provides an instruction scheduling device disposed in the controller 120. Figure 3 A schematic structural diagram of the instruction scheduling device 200 is shown.

[0039] like Figure 3 As shown, the instruction scheduling device 200 includes a host interface 201, a command parser 202, an instruction cache unit 203, an arbitration unit 204, a remaining time calculation unit 206, a data path 205, a CA instruction execution unit 207, and a DQ instruction execution unit 208. For the convenience of description, only flash memory chips DIE0 to DIEn coupled to the controller 120 through the same channel are shown in the figure, and the same channel includes a CA bus 11 and a DQ bus 12.

[0040] The host interface 201 is used to receive host commands from the host device 110 and to transmit data with the host device 110. The host command is, for example, a write command to write data to the flash storage medium 130, a read command to read data from the flash storage medium, a query command to check the execution status of the write command or the read command, etc. The interface protocol adopted by the host interface 201 determines the various command types and formats. For example, when UPIU (UFS Protocol Information Units) is adopted as the interface protocol, the transmitted UPIU packet is composed of multiple parts such as a header and a data payload. The header provides information such as the interaction type, length, and attributes, and the data payload provides the specific content of the command or data.

[0041] The command parser 202 parses the received host command, converts it into an instruction compatible with the flash memory chip, and stores the instruction in the instruction cache unit 203. Flash memory chips of different products support different instruction sets. For example, for "write operation", different flash memory chip products have different instruction formats, so the command parser 202 is required to convert the received host command. The command parser 202 can convert one host command into multiple instructions compatible with the flash memory chip, or multiple host commands into multiple instructions compatible with the flash memory chip. The embodiment of the present disclosure does not impose specific restrictions on the correspondence between the host command and the number of instructions compatible with the flash memory chip.

[0042] Based on the SCA protocol, the command parser 202 classifies the instructions adapted to the flash memory chip into CA instructions and DQ instructions. CA instructions are generally operation instructions related to the configuration of the flash memory chip, such as instructions for reading the status of the flash memory chip and instructions for modifying the status of the registers on the flash memory chip. DQ instructions are generally instructions related to the data stored on the flash memory chip, such as reading or writing data to the flash memory chip.

[0043] The command parser 202 can also obtain the estimated execution time of each fetched CA instruction, and store the estimated execution time and the corresponding CA instruction in the instruction cache unit. T1 to t6 in the figure represent the estimated execution time of the corresponding CA instruction. The command parser 202 can also obtain the total amount of each DQ instruction to be transmitted, and store the total amount and the corresponding DQ instruction in the instruction cache unit. L1 to L3 in the figure represent the total amount of the corresponding DQ instruction to be transmitted.

[0044] In some embodiments, the command parser 202 maintains multiple first-in-first-out instruction queues for multiple flash memory chips in the instruction cache unit 203, which are used to store CA instructions and DQ instructions adapted to each flash memory chip respectively. The figure shows (n+1) instruction queues corresponding to the flash memory chips DIE0 to DIEn respectively.

[0045] The arbitration unit 204 takes instructions from the multiple instruction queues, arbitrates one or more CA instructions, and sends the selected CA instructions to the CA instruction execution unit 207 for execution. At the same time, the arbitration unit 204 sends one or more DQ instructions to the DQ instruction execution unit 208 through the data path 205 for data transmission. Here, the data path 205 is similar to the data cache unit. The data to be written to the flash memory chip is first placed in the data path 205, and then taken away in sequence by the DQ instruction execution unit 208. The data read in sequence from the flash memory chip is first placed in the data path 205 by the DQ instruction execution unit 208, and then transmitted to the host device 110.

[0046] The remaining time calculation unit 206 is used to calculate the remaining execution time of the DQ instruction currently performing data transmission through the DQ bus 12. Specifically, the total amount of data to be transmitted by the DQ instruction currently performing data transmission is obtained through the arbitration unit 204, and then the remaining execution time is calculated by monitoring the data change amount of the data path 205, but the embodiment of the present disclosure does not specifically limit the calculation method.

[0047] The arbitration unit 204 may arbitrate one or more CA instructions taken from multiple instruction queues as follows: first, one or more CA instructions that can be executed in parallel with the DQ instruction currently performing data transmission through the DQ bus 12 are selected from these one or more CA instructions, and then the estimated execution time of each of these one or more CA instructions is compared with the remaining execution time of the DQ instruction currently performing data transmission to determine a target CA instruction to be executed preferentially through the CA bus 11.

[0048] The following is based on Figures 4 to 7 The priority arbitration of the arbitration unit 204 is described exemplarily. In the following examples, it is assumed that the CA instructions taken out from each instruction queue can be transmitted in parallel with the currently performed data.

[0049] refer to Figure 4As shown, at the current time point, data DATA1 is being transmitted on the DQ bus 12, CA instructions A and CA instructions B have completed execution, CA instructions C and CA instructions D are taken out from the two instruction queues respectively, and the remaining execution time of data DATA1 is less than the estimated execution time of CA instruction C and greater than the estimated execution time of CA instruction D. Then, according to the arbitration of the arbitration unit 204, at the current time point, CA instruction D is preferentially sent to the CA bus for execution.

[0050] refer to Figure 5 As shown, at the current time point, data DATA1 is being transmitted on the DQ bus 12, CA instruction A has been executed, CA instruction C and CA instruction D are taken out from the two instruction queues respectively, and the remaining execution time of data DATA1 is less than the estimated execution time of CA instruction C and CA instruction D. Then, according to the arbitration of the arbitration unit 204, at the current time point, the arbitration unit 204 will compensate for an additional period of time, that is, add an additional time length to the remaining execution time, and then compare it with the estimated execution time of CA instruction C and CA instruction D. Since the estimated execution time of CA instruction C is less than the remaining execution time plus the compensation time, and the estimated execution time of CA instruction D is greater than the remaining execution time plus the compensation time, the arbitration unit 204 will give priority to sending CA instruction C to the CA bus for execution. In other cases, assuming that there are multiple CA instructions, and the estimated execution time of each CA instruction is less than the remaining execution time plus the compensation time, the CA instruction with the highest priority can be selected for priority execution according to the pre-defined priority logic. For example, if Figure 5 If the estimated execution time of CA instruction C and CA instruction D are both less than the remaining execution time plus the compensation time, the CA instruction with a larger (or smaller) estimated execution time can be selected for priority execution.

[0051] refer to Figure 6 As shown in FIG. 1 , if more CA instructions are taken out in the current scenario (for example, the number of CA instructions is greater than the set threshold) and / or the remaining execution time of the DQ bus data transmission is short (for example, the remaining execution time is less than the set threshold), then the following method is adopted: Figure 5 The approach of adding extra compensation time will have a relatively high benefit.

[0052] refer to Figure 7 As shown, when the remaining execution time of the DQ bus data transmission is long, no additional compensation time is added to the remaining execution time of the DQ bus (in this case, if compensation is forced, it will cause the DQ bus and the CA204 bus to not be executed in parallel for a part of the time), so that the remaining CA instructions and the data transmission command of the next DQ instruction are executed in parallel.

[0053] comprehensive Figures 4 to 7As can be seen from the example, the arbitration unit 204 first gives priority to executing the CA instruction whose estimated execution time is less than the remaining execution time of the DQ instruction currently being transmitted. If there are multiple such CA instructions, the CA instruction with the highest priority is selected for priority execution according to the pre-defined priority logic; secondly, for the CA instructions whose estimated execution time is greater than the remaining execution time of the DQ instruction currently being transmitted, it is determined whether the remaining execution time of the DQ instruction currently being transmitted is less than the set threshold, then additional compensation time is added, and the CA instruction whose estimated execution time is less than the remaining execution time of the DQ instruction currently being transmitted plus the compensation time is preferentially executed. If there are multiple such CA instructions, the CA instruction with the highest priority is selected for priority execution according to the pre-defined priority logic.

[0054] In some embodiments, different compensation times are specified for different DQ instructions. In practice, a compensation time table may be stored in a cache unit of the controller to store additional compensation times for various DQ instructions, as shown in Table 1.

[0055] DQ instruction type Compensation time 4KB random read data 15ns Page read 0 Page write 0

[0056] It should be noted that the instruction scheduling device 200 may not include the original components of the controller (such as the host interface, command parser, CA instruction execution unit and DQ instruction execution unit, etc.), and the above embodiment can be implemented by reusing the original components.

[0057] Accordingly, the embodiment of the present disclosure also provides an instruction scheduling method, which is applied to a controller of a storage device, and the controller is coupled to multiple flash memory chips through a first channel. The instruction scheduling method can be implemented as a software program or a combination of a software program and hardware logic. Figure 8 and Fig. 9 A flowchart of an embodiment of the instruction scheduling method is given respectively. Figure 8 The flowchart includes the following steps.

[0058] In step S801, multiple instructions are taken out from multiple instruction queues respectively. Figure 2 As shown, the command parser 202 parses and converts the received host command into various instructions adapted to the flash memory chip, and stores the various instructions into the instruction queue corresponding to each flash memory chip.

[0059] In step S802, the remaining execution time of the DQ instruction currently transmitting data on the data bus of the first channel is obtained. Specifically, the remaining execution time can be calculated by the ratio of the data transmitted on the data bus of the first channel to the total amount of data to be transmitted by the DQ instruction and the transmission rate of the data bus of the first channel.

[0060] In step S803, the estimated execution time and the remaining execution time of one or more CA instructions that can be executed in parallel with the DQ instruction are compared to determine a target CA instruction that is preferentially executed via the CA bus of the first channel. Figures 4 to 7 In addition, this step can store the estimated execution time of various CA instructions through a pre-stored query table, and then obtain the estimated execution time of the corresponding CA instruction by querying the table.

[0061] Fig. 9 The flowchart is relative to Figure 8 More details are provided, including the following steps.

[0062] Step S901 is initialization, including defining additional compensation time for different DQ instructions.

[0063] Step S902 is to monitor the execution of the CA instruction.

[0064] Step S903 is to obtain the CA instruction waiting to be executed from the instruction queue.

[0065] Step S904 is to determine whether a DQ instruction is currently being executed. If yes, step S905 is executed; if not, step S910 is executed.

[0066] Step S905 is to select a CA instruction that does not conflict with the currently executed DQ instruction (can be executed in parallel) from the CA instructions output in step S903. For example, the NAND protocol stipulates that when the same LUN (Logical Unit Number) is executing DQ data transmission, some CA commands of the same LUN cannot be executed in parallel with it.

[0067] Step S906 is to determine whether there is a CA instruction that can be executed in parallel with the current DQ instruction. If so, execute step S908; if not, execute step S902.

[0068] Step S907 is to query the remaining execution time of the current DQ instruction and the additional compensation time defined by the DQ instruction.

[0069] Step S908 is to determine whether there is a CA instruction whose estimated execution time is less than or equal to the remaining execution time of the current DQ instruction (or less than or equal to the remaining execution time of the DQ instruction + compensation time). If so, execute step S909; if not, execute step S902.

[0070] Step S909 is to select the CA instruction with the highest priority from among the multiple CA instructions that meet the conditions and execute it first.

[0071] Step S910 is to determine whether there is a DQ instruction waiting to be executed when there is no DQ instruction currently being executed. If yes, step S911 is executed; if not, step S912 is executed.

[0072] In step S911, the DQ instruction is executed preferentially.

[0073] In step S912 , when there is no DQ instruction currently being executed and no DQ instruction waiting to be executed, the CA instruction with the highest priority is selected from among all CA instructions waiting to be executed and is executed first.

[0074] The instruction scheduling method and device provided according to the embodiments of the present disclosure improve the probability of parallel execution of CA instructions and DQ instructions by optimizing the behavior of parallel execution of CA instructions and DQ instructions under the SCA interface, thereby achieving higher utilization and higher data bandwidth of the DQ bus.

[0075] According to the embodiments of the present invention as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. An instruction scheduling device, applied to a controller of a storage device, wherein the controller is coupled to a plurality of flash memory chips through a first channel, wherein the first channel includes a CA bus and a DQ bus, and the instruction scheduling device include: An instruction cache unit, which caches various instructions adapted to the multiple flash memory chips respectively through multiple instruction queues; A remaining time calculation unit, used to calculate the remaining execution time of the DQ instruction currently performing data transmission through the DQ bus; The arbitration unit is used to take out instructions from the multiple instruction queues respectively, and compare the estimated execution time of one or more CA instructions that can be executed in parallel with the DQ instruction with the remaining execution time to determine a target CA instruction to be executed preferentially via the CA bus, so as to increase the probability of the CA instruction being executed in parallel with the DQ instruction.

2. The instruction scheduling device according to claim 1, in, The arbitration unit further compares the estimated execution time of each of one or more CA instructions that can be executed in parallel with the DQ instruction with the remaining execution time plus the additional compensation time to determine a target CA instruction to be executed preferentially via the CA bus.

3. The instruction scheduling device according to claim 2, in, When there are multiple CA instructions whose expected execution times are all less than the remaining execution time, or when there are multiple CA instructions whose expected execution times are all less than the remaining execution time plus the additional compensation time, the arbitration unit selects the CA instruction with the highest priority as the target CA instruction according to a predetermined priority logic.

4. The instruction scheduling device according to claim 2, in, The arbitration unit determines whether to add the remaining execution time to the additional compensation time for comparison according to whether the current scenario meets certain conditions.

5. The instruction scheduling device according to claim 2, in, The remaining time calculation unit pre-stores a compensation schedule, and determines the additional compensation time by querying the compensation schedule.

6. The instruction scheduling device according to claim 2, in, The additional compensation time is defined for each DQ instruction respectively; and / or, the estimated execution time is defined for each CA instruction respectively.

7. The instruction scheduling device according to claim 1, in, The remaining time calculation unit calculates the remaining execution time by monitoring the transmitted data of the DQ instruction currently performing data transmission.

8. A controller of a storage device, comprising the instruction scheduling device according to any one of claims 1 to 7.

9. A storage device, include: A coupled controller and a flash storage medium, wherein the controller is the controller as claimed in claim 8.

10. A method for scheduling instructions, for use in a controller of a storage device, wherein the controller is coupled to a plurality of flash memory chips through a first channel, wherein the first channel includes a CA bus and a DQ bus, and the method for scheduling instructions include: Taking out a plurality of instructions from a plurality of instruction queues respectively, wherein the plurality of instruction queues respectively correspond to instructions cached and adapted to a plurality of flash memory chips under the first channel; Obtaining the remaining execution time of a DQ instruction currently performing data transmission through the DQ bus; The estimated execution time of one or more CA instructions among the multiple instructions that can be executed in parallel with the DQ instruction is compared with the remaining execution time to determine a target CA instruction to be executed preferentially via the CA bus, so as to increase the probability of the CA instruction being executed in parallel with the DQ instruction.

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