A method and device for processing multi-asynchronous chip test signals

Abstract

The present invention discloses a method and device for processing multiple asynchronous chip test signals, the processing method comprising the following steps: based on a pre-test of a target chip, a chip test signal group is obtained, wherein the chip test signal group comprises at least two asynchronous chip test signals; each chip test signal is subjected to a region conversion process to form a corresponding signal vector set; based on a signal asynchronous processing strategy, each signal vector set is processed to give a chip test sequence; and the chip test result is determined by comparative analysis of each chip test sequence. The present invention mainly processes chip test signals with inconsistent timing in batches, thereby improving chip test efficiency and accuracy.

Description

Technical Field

[0001] The invention belongs to the technical field of chip testing, and in particular relates to a method and device for processing multiple asynchronous chip test signals. Background Art

[0002] Testing is an indispensable part of the development, production and use of integrated circuits. ATE-based testing is a widely used method in today's integrated circuit industry, which has the advantages of high efficiency and good consistency.

[0003] In IC testing, digital signal testing is the basis, and functional testing is the foundation of data signal testing. By inputting a series of stimulus signals, the output signal is tested at the output end to see if it meets expectations. General functional testing is based on timing requirements, inputting drive signals, and finally completing the determination of IC functions by real-time sampling, comparison and judgment of device outputs.

[0004] For example, patent CN115792582A provides a chip testing method, device and equipment, the method includes: obtaining the chip model data of the chip to be tested; if it is determined that the chip to be tested belongs to the target model according to the chip model data, then executing the model test scheme corresponding to the target model for the chip to be tested, and outputting the test result of the chip to be tested; wherein, the model test scheme includes a parallel test scheme obtained by functional unit analysis of the chip; functional unit analysis includes confirming the parallel test scheme based on the test time required for each functional unit in the chip and the interference of parallel tests between each functional unit. The scheme formulates a parallel test scheme with the best test results based on the interference of each functional unit during parallel testing, which can ensure the shortest total test time and correct test data.

[0005] For example, patent CN115980553A provides a mass production test method based on a digital ATE test machine, including: according to the test requirements of the chip, the final ATE test machine model is confirmed through test cost analysis, and the FPGA is initialized; the SYNCframe chip is confirmed through the FPGA interface, the Serdes signal output by the chip is decoded and the PRBS test is performed, and the FPGA feeds back the pass / fail signal to the ATE; after the test passes, the ADC data is collected and converted by the FPGA, the ATE and the FPGA perform handshake interaction, and the SNR parameter value of the ADC is collected. The ATE sets and compares the limit values ​​of the received parameter values, thereby outputting the test data of the parameter and determining whether it is within the chip parameter indicator range, and finally feeding back the test completion signal to the FPGA, and the FPGA returns to the initialization waiting state.

[0006] However, in batch testing, there are timing inconsistencies, such as Figure 1As shown, it is impossible to perform batch analysis and processing on the output signals, which seriously affects the test efficiency.

[0007] Therefore, how to perform batch processing on test signals with inconsistent timing to improve chip testing efficiency and accuracy is an urgent problem to be solved by those skilled in the art. Summary of the invention

[0008] In view of the defects existing in the above-mentioned prior art, the present invention provides a method and device for processing multiple asynchronous chip test signals, and the processing method includes the following steps: based on the pre-test of the target chip, a chip test signal group is obtained, wherein the chip test signal group includes at least two asynchronous chip test signals; each chip test signal is subjected to region conversion processing to form a corresponding signal vector set; based on the difference processing strategy of the asynchronous signal, each signal vector set is processed to give a chip test series; by comparing and analyzing each chip test series, the chip test result is determined. The present invention mainly performs batch processing on chip test signals with inconsistent timing, thereby improving the efficiency and accuracy of chip testing.

[0009] In a first aspect, the present invention provides a method for processing a multi-asynchronous chip test signal, characterized in that the method specifically comprises the following steps:

[0010] Based on a pre-test of the target chip, a chip test signal group is obtained, wherein the chip test signal group includes at least two asynchronous chip test signals;

[0011] Performing region conversion processing on each chip test signal to form a corresponding signal vector set;

[0012] Based on the signal asynchronous processing strategy, each signal vector set is processed to give a chip test sequence;

[0013] The chip test results are determined by comparing and analyzing the test series of each chip.

[0014] Furthermore, the chip test signal includes an analog signal and / or a digital signal.

[0015] Furthermore, each chip test signal is subjected to region conversion processing to form a corresponding signal vector set, which specifically includes the following steps:

[0016] Based on the test cycle, each chip test signal is cut to form multiple waveforms;

[0017] Combined with the hash algorithm, each waveform is converted into a vector to form a corresponding signal vector set.

[0018] Furthermore, each waveform is converted into a vector by combining the hash algorithm, including:

[0019] Preprocessing each waveform, wherein the preprocessing includes denoising and normalization;

[0020] Define typical features for transformation, extract typical features of each waveform, and construct a feature vector group, wherein the typical feature of each waveform corresponds to each feature vector of the feature vector group;

[0021] The characteristic vector is processed by a preset hash function to give a signal vector.

[0022] Furthermore, the feature vector is processed by a preset hash function, which is specifically expressed as follows:

[0023]

[0024] Among them, s i is the i-th signal vector, c is the hash constant, e i is the i-th eigenvector, mod is the modulus calculation, and X is the amplitude of the hash map.

[0025] Furthermore, based on the signal asynchronous processing strategy, each signal vector set is processed to provide a chip test sequence, which specifically includes the following steps:

[0026] Define the order of each signal vector in the signal vector set, and give the first sequence number corresponding to each signal vector;

[0027] Based on the first sequence number and in combination with a predefined signal vector combination method, each signal vector is combined to form a plurality of corresponding signal vector groups;

[0028] In combination with the counting analysis of the signal vectors in each signal vector group, an initial output value of the signal vector group is defined, and a second sequence number corresponding to each signal vector group is marked;

[0029] Based on the second sequence number and according to a predefined signal asynchronous processing method, initial output values ​​corresponding to each signal vector group are aggregated to form an initial output value cluster;

[0030] The chip test series is determined by analyzing the fluctuation of the initial output values ​​in each initial output value cluster.

[0031] Furthermore, the definition of the signal vector combination method is specifically expressed as:

[0032]

[0033] Among them, C1 is the signal vector combination, i is the first order number, f() is the comparison function, N is a non-zero constant, s i is the ith signal vector, s i-1is the i-1th signal vector;

[0034] The definition of signal asynchronous processing is specifically expressed as follows:

[0035]

[0036] Among them, C 2,p is the pth initial output value cluster, p is the serial number of the initial output value cluster, k j is the number of initial output values ​​in the jth initial output value cluster, For the The initial output value, For the The initial output value, For the The initial output value.

[0037] Furthermore, the chip test series is specifically expressed as:

[0038]

[0039] Among them, C3 is the chip test series, D() is the fluctuation analysis function, C 2,1 is the first initial output value cluster, C 2,p is the pth initial output value cluster, C 2,M is the Mth initial output value cluster.

[0040] Further, a comparative analysis of the test series of each chip shows that the chip test meets the following requirements:

[0041]

[0042] Among them, C 3,r is the test sequence for the rth chip, is the qth chip test data in the rth chip test sequence, C 3,u is the test sequence of the uth chip, is the qth chip test data in the u chip test sequence, G() is the proportional function, Y is the total number of chip test sequences, and T is the length of each chip test sequence.

[0043] In a second aspect, the present invention further provides a device for processing multiple asynchronous chip test signals, which uses the above-mentioned method for processing multiple asynchronous chip test signals, specifically comprising:

[0044] A collection unit, used for acquiring a chip test signal group based on a pre-test of a target chip, wherein the chip test signal group includes at least two asynchronous chip test signals;

[0045] The chip test signal analysis unit is used to perform region conversion processing on each chip test signal to form a corresponding signal vector set; based on the signal asynchronous processing strategy, each signal vector set is processed to give a chip test sequence;

[0046] The chip test signal processing unit is used to determine the chip test result by comparing and analyzing the test data series of each chip.

[0047] The present invention provides a method and device for processing multi-asynchronous chip test signals, which at least have the following beneficial effects:

[0048] (1) The present invention mainly processes test signals with inconsistent timing in batches, thereby improving chip testing efficiency and accuracy.

[0049] (2) On the basis of ensuring accurate analysis of chip test signals, the present invention cuts and hashes complex waveform signals to provide a signal vector set, which can simplify the analysis process and make signal analysis more efficient. At the same time, in the multi-stage test process, the signal vector determined by the hash value can also be used to check the consistency of the test signal to ensure the reliability of each chip test signal.

[0050] (3) For the processing of multiple asynchronous signals, the standardized transformation of multiple asynchronous signals is achieved by combining the order of signal vectors, the combination of signal vectors, the order of signal vector groups, the clustering method of initial output values ​​generated by signal vector groups, and the fluctuation analysis within the initial output value cluster. Then, a unified comparative analysis is performed on the chip test series after the standardized transformation, and the test results of the chip functional characteristics are given. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 A waveform diagram of an asynchronous chip test signal in the prior art;

[0052] Figure 2 A schematic flow chart of a method for processing multi-asynchronous chip test signals provided by the present invention;

[0053] Figure 3 A schematic diagram of a flow chart of performing region conversion processing on each chip test signal to form a corresponding signal vector set according to an embodiment of the present invention;

[0054] Figure 4 An example diagram of two asynchronous chip test signals provided by the present invention;

[0055] Figure 5 A schematic flow chart of a chip test sequence is provided for processing each signal vector set based on a signal asynchronous processing strategy in an embodiment of the present invention;

[0056] Figure 6 An example diagram of the signal vector group and initial output value delineation provided by the present invention;

[0057] Figure 7 A schematic diagram of the architecture of a device for processing multiple asynchronous chip test signals provided by the present invention. DETAILED DESCRIPTION

[0058] In order to better understand the above technical solution, the above technical solution will be described in detail below in conjunction with the accompanying drawings and specific implementation methods. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0059] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. The singular forms "a", "said" and "the" used in the embodiments of the present invention and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings, and "multiple" generally includes at least two.

[0060] It should also be noted that the term "includes", "comprising" or any other variation thereof is intended to cover non-exclusive inclusion, so that a commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprising a ..." do not exclude the existence of other identical elements in the commodity or device including the elements.

[0061] As a key step in detecting the functional integrity of the chip, the automatic tester ATE automatically completes the test project to verify whether the chip, integrated circuit, etc. can work normally according to the design specifications. ATE testing can provide test stimuli with complex timing based on the simulation waveforms of the chip and integrated circuit in the design stage. Based on the test stimuli with complex timing, direct current (DC) signals, alternating current (AC) signals, digital signals, analog signals and other tests can be performed. The type of chip test is related to the type of chip, integrated circuit and application scenario.

[0062] Generally speaking, functional testing of the target chip often requires multiple measurements to obtain multiple test signals at different times. However, multiple test signals cannot return corresponding test data at the same time point (different timing). That is, there is a periodic offset between the test signals, making it impossible to directly analyze the situation where the output waveforms of multiple measurements of the same chip are not synchronized.

[0063] To this end, it is necessary to set up a batch processing strategy for asynchronous signals, parse each test output waveform, and determine the functional integrity of the chip based on the chip test signal.

[0064] like Figure 2 As shown, the present invention provides a method for processing a multi-asynchronous chip test signal, which specifically includes the following steps:

[0065] Based on a pre-test of the target chip, a chip test signal group is obtained, wherein the chip test signal group includes at least two asynchronous chip test signals;

[0066] Performing region conversion processing on each chip test signal to form a corresponding signal vector set;

[0067] Based on the signal asynchronous processing strategy, each signal vector set is processed to give a chip test sequence;

[0068] The chip test results are determined by comparing and analyzing the test series of each chip.

[0069] The present invention mainly performs batch processing on chip test signals with inconsistent timing, thereby improving chip test efficiency and accuracy.

[0070] Chip test signals include analog signals, and / or digital signals, and of course mixed signals. Generally speaking, chip test signals are synthesized by test timing and test vectors, and contain both timing and vector information. Pre-testing of the target chip can ensure the quality of the chip and integrated circuit (IC) products, including testing of various parameters of the chip, which can be DC parameter testing, AC parameter testing, or functional testing, etc., and no further restrictions are made here.

[0071] Testing the target chip requires stimulating the chip at a specific voltage or logic level and following precise timing to simulate the actual working environment of the chip.

[0072] Chip test signals have obvious periodicity, usually showing characteristics related to clock cycle, data transmission and circuit response time. At the same time, clear jumps (or fluctuating waveforms) can also be found in chip test signals. These jumps and waveforms correspond to changes in logic states. Based on the measurement and analysis of chip test signals, the performance of the chip under stimulation can be demonstrated.

[0073] In batch testing, there is a situation of inconsistent timing, and the output signals cannot be analyzed and processed in batches, which seriously affects the test efficiency. The present invention processes each asynchronous signal by setting a difference processing strategy, and obtains the corresponding chip test series respectively. By analyzing and comparing each chip test series, the functional integrity of the target chip is determined.

[0074] like Figure 3 As shown, each chip test signal is subjected to region conversion processing to form a corresponding signal vector set, which specifically includes the following steps:

[0075] Based on the test cycle, each chip test signal is cut to form multiple waveforms;

[0076] Combined with the hash algorithm, each waveform is converted into a vector to form a corresponding signal vector set.

[0077] Combined with the hash algorithm, each waveform is converted into a vector, including:

[0078] Preprocessing each waveform, wherein the preprocessing includes denoising and normalization;

[0079] Define typical features for transformation, extract typical features of each waveform, and construct a feature vector group, wherein the typical feature of each waveform corresponds to each feature vector of the feature vector group;

[0080] The characteristic vector is processed by a preset hash function to give a signal vector.

[0081] Among them, the feature vector is processed by a preset hash function, which is specifically expressed as:

[0082]

[0083] Among them, s i is the i-th signal vector, c is the hash constant, e i is the i-th eigenvector, mod is the modulus calculation, and X is the amplitude of the hash map.

[0084] The hash constant and the amplitude of the hash mapping need to be determined according to different application scenarios, and no specific limitation is made here. For example, in a certain embodiment, the hash constant c can select the commonly used prime number 31, and the amplitude of the hash mapping can select 100, that is, mapping in the range of [0-100].

[0085] In one embodiment, if Figure 4 As shown, two asynchronous chip test signals are subjected to regional conversion processing, and then the characteristic vector is converted into data 1 and 0 to obtain a signal vector set, that is, Figure 4 The first test signal output and the second test signal output in . Among them, 1 and 0 can represent a high level and a low level respectively.

[0086] On the basis of ensuring accurate analysis of chip test signals, complex waveform signals are cut and hashed to give a signal vector set, which can simplify the analysis process and make signal analysis more efficient. At the same time, in the multi-stage test process, the signal vector determined by the hash value can also be used to check the consistency of the test signal to ensure the reliability of each chip test signal.

[0087] like Figure 5 As shown, based on the signal asynchronous processing strategy, each signal vector set is processed to give a chip test sequence, which specifically includes the following steps:

[0088] Define the order of each signal vector in the signal vector set, and give the first sequence number corresponding to each signal vector;

[0089] Based on the first sequence number and in combination with a predefined signal vector combination method, each signal vector is combined to form a plurality of corresponding signal vector groups;

[0090] In combination with the counting analysis of the signal vectors in each signal vector group, an initial output value of the signal vector group is defined, and a second sequence number corresponding to each signal vector group is marked;

[0091] Based on the second sequence number and according to a predefined signal asynchronous processing method, initial output values ​​corresponding to each signal vector group are aggregated to form an initial output value cluster;

[0092] The chip test series is determined by analyzing the fluctuation of the initial output values ​​in each initial output value cluster.

[0093] For the processing of multiple asynchronous signals, the standardized transformation of multiple asynchronous signals is achieved by combining the order of signal vectors, the combination of signal vectors, the order of signal vector groups, the clustering method of initial output values ​​generated by signal vector groups, and the fluctuation analysis within the initial output value cluster. Then, a unified comparative analysis is performed on the chip test series after the standardized transformation, and the test results of the chip functional characteristics are given.

[0094] The definition of signal vector combination method is specifically expressed as:

[0095]

[0096] Among them, C1 is the signal vector combination, i is the first order number, f() is the comparison function, N is a non-zero constant, s i is the ith signal vector, s i-1 is the i-1th signal vector.

[0097] In the above embodiment, the first test signal output is used as a signal vector set, and each signal vector is defined with a first sequence number, and a notation such as ①, ②, ③, etc. is used. According to the first sequence number and the signal vector combination mode, the signal vector combination of the first test signal output is defined. Figure 6 As shown, the dashed box in the first test signal output defines a signal vector group formed by combining various signal vectors.

[0098] The signal vectors in each signal vector group are counted and counted, which can be simple superposition or other methods. After the statistics, the initial output value of the corresponding signal vector group is given, and the second sequence number of the corresponding signal vector group and the initial output value is given at the same time. Among them, the initial output value can be Arabic numerals, or other numbers or letters; the marking method of the second sequence number is in Figure 6 Roman numerals are used in the numbering, for example, Ⅰ, Ⅱ, Ⅲ, Ⅳ, etc.

[0099] After the second sequence number and the initial output value are determined, the initial output value is aggregated according to the definition of the signal asynchronous processing method to form an initial output value cluster. The definition of the signal asynchronous processing method is specifically expressed as:

[0100]

[0101] Among them, C 2,p is the pth initial output value cluster, p is the serial number of the initial output value cluster, k j is the number of initial output values ​​in the jth initial output value cluster, For the The initial output value, For the The initial output value, For the The initial output value.

[0102] The length of the initial output value cluster is determined according to different chip test types or chip test signal forms, and can be in the form of fixed length or regular length. Here, no further limitation is made on the specific length. The fixed length can be in the form of 2 adjacent initial output values ​​as a cluster, or 3 adjacent initial output values ​​as a cluster; the regular length can be in the form of increasing length or decreasing length, such as the first initial output value cluster is 2 adjacent initial output values, the second initial output value cluster is 3 adjacent initial output values, and so on, all initial output values ​​are aggregated into an initial output value cluster.

[0103] According to the length definition of the initial output value cluster, the initial output values ​​corresponding to each signal vector group can be aggregated. Afterwards, the fluctuation analysis of each initial output value of each initial output value cluster can be performed to obtain a standardized chip test series.

[0104] Specifically, the chip test series is expressed as:

[0105]

[0106] Among them, C3 is the chip test series, D() is the fluctuation analysis function, C 2,1 is the first initial output value cluster, C 2,p is the pth initial output value cluster, C 2,M is the Mth initial output value cluster.

[0107] A fluctuation analysis is performed on each initial output value in each initial output value cluster. The fluctuation analysis may be performed by calculating the fluctuation difference of the initial output values, or by calculating the standard deviation, variance, etc. of each initial output value.

[0108] exist Figure 6 In the method, two adjacent initial output values ​​of fixed length are used as a cluster. The fluctuation analysis of each initial output value in each initial output value cluster adopts the calculation method of continuous fluctuation difference. The chip test data is given by comparing the continuous fluctuation difference with the preset fluctuation value. Taking the first initial output value cluster as an example, the initial output value II-initial output value I in the first initial output value cluster is compared with the preset fluctuation value to form the first chip test data. By analogy, the second chip test data is determined, and so on, until all chip test data are completed to obtain the chip test series. The preset fluctuation value can be a constant. The specific value of the constant is not limited. It can be 0 or other values.

[0109] By processing each signal vector set as above, corresponding chip test series are obtained. At this time, the chip test series is a standardized series after signal asynchronous processing. Comparative analysis of each chip test series can realize chip performance analysis.

[0110] Taking the two chip test sequences r and u in the chip test sequence with a total of Y asynchronous signals as an example, the comparative analysis of each chip test sequence is explained. The chip test meets the requirements and meets the following conditions:

[0111]

[0112] Among them, C 3,r is the test sequence for the rth chip, is the qth chip test data in the rth chip test sequence, C 3,u is the test sequence of the uth chip, is the qth chip test data in the u chip test sequence, G() is the proportional function, Y is the total number of chip test sequences, and T is the length of each chip test sequence.

[0113] The proportional function is to determine that there is a proportional relationship between the chip test series corresponding to each asynchronous signal. Therefore, it can be considered that although the chip test signal has a timing asynchrony problem, the performance characteristics of the chip test reflected are consistent. The specific type and form of the proportional function can be a direct proportional function, an inverse proportional function, a linear function, etc., as long as it can describe the existence of a proportional relationship. No specific limitation is made here.

[0114] like Figure 7 As shown, the present invention also provides a processing device for multiple asynchronous chip test signals, which adopts the processing method for multiple asynchronous chip test signals as mentioned above, specifically comprising:

[0115] A collection unit, used for acquiring a chip test signal group based on a pre-test of a target chip, wherein the chip test signal group includes at least two asynchronous chip test signals;

[0116] The chip test signal analysis unit is used to perform region conversion processing on each chip test signal to form a corresponding signal vector set; based on the difference processing strategy of asynchronous signals, each signal vector set is processed to give a chip test sequence;

[0117] The chip test signal processing unit is used to determine the chip test result by comparing and analyzing the test data series of each chip.

[0118] The present invention also provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements any one of the above-mentioned methods for processing multi-asynchronous chip test signals when executing the computer program.

[0119] Specifically, a computer device may include one or more processing devices, such as one or more central processing units (CPUs), each of which may implement one or more hardware threads. A computer device may also include any storage resource for storing any type of information such as code, settings, data, etc. Without limitation, for example, a storage resource may include any one or more combinations of the following: any type of RAM, any type of ROM, a flash memory device, a hard disk, an optical disk, etc. More generally, any storage resource may use any technology to store information.

[0120] Further, any storage resource may provide volatile or non-volatile retention of information. Further, any storage resource may represent a fixed or removable component of a computer device. In one case, when a processing device executes an associated instruction stored in any storage resource or a combination of storage resources, the computer device may perform any operation of the associated instruction. The computer device also includes one or more drive mechanisms for interacting with any storage resource, such as a hard disk drive mechanism, an optical disk drive mechanism, etc.

[0121] The computer device may also include an input / output module (I / O) for receiving various inputs (via input devices) and for providing various outputs (via output devices). A specific output mechanism may include a presentation device and an associated graphical user interface (GUI). In other embodiments, the input / output module (I / O), input devices, and output devices may not be included, and the computer device may be used only as a computer device in a network. The computer device may also include one or more network interfaces for exchanging data with other devices via one or more communication links. One or more communication buses couple the components described above together.

[0122] The communication link may be implemented in any manner, for example, through a local area network, a wide area network (e.g., the Internet), a point-to-point connection, etc., or any combination thereof. The communication link may include any combination of hardwired links, wireless links, routers, gateway functions, name servers, etc., governed by any protocol or combination of protocols.

[0123] The beneficial effects obtained by the above-mentioned equipment and devices are consistent with the beneficial effects obtained by the above-mentioned methods, and will not be described in detail in the embodiments of this specification.

[0124] The present invention provides a method and device for processing multi-asynchronous chip test signals, which at least have the following beneficial effects:

[0125] (1) The present invention mainly processes test signals with inconsistent timing in batches, thereby improving chip testing efficiency and accuracy.

[0126] (2) On the basis of ensuring accurate analysis of chip test signals, the present invention cuts and hashes complex waveform signals to provide a signal vector set, which can simplify the analysis process and make signal analysis more efficient. At the same time, in the multi-stage test process, the signal vector determined by the hash value can also be used to check the consistency of the test signal to ensure the reliability of each chip test signal.

[0127] (3) For the processing of multiple asynchronous signals, the standardized transformation of multiple asynchronous signals is achieved by combining the order of signal vectors, the combination of signal vectors, the order of signal vector groups, the clustering method of initial output values ​​generated by signal vector groups, and the fluctuation analysis within the initial output value cluster. Then, a unified comparative analysis is performed on the chip test series after the standardized transformation, and the test results of the chip functional characteristics are given.

[0128] Although preferred embodiments of the present invention have been described, additional changes and modifications may be made to these embodiments by those skilled in the art once the basic inventive concepts are known. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention. Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A method for processing multi-asynchronous chip test signals, characterized in that: The specific steps include: Based on a pre-test of the target chip, a chip test signal group is obtained, wherein the chip test signal group includes at least two asynchronous chip test signals; Based on the test cycle, each chip test signal is cut to form multiple waveforms; Preprocessing each waveform, wherein the preprocessing includes denoising and normalization; Define typical features for transformation, extract typical features of each waveform, and construct a feature vector group, wherein the typical feature of each waveform corresponds to each feature vector of the feature vector group; The feature vector is processed by a preset hash function to give a signal vector, thereby forming a corresponding signal vector set; Define the order of each signal vector in the signal vector set, and give the first sequence number corresponding to each signal vector; Based on the first sequence number and in combination with a predefined signal vector combination method, each signal vector is combined to form a plurality of corresponding signal vector groups; In combination with the counting analysis of the signal vectors in each signal vector group, an initial output value of the signal vector group is defined, and a second sequence number corresponding to each signal vector group is marked; Based on the second sequence number and according to a predefined signal asynchronous processing method, initial output values ​​corresponding to each signal vector group are aggregated to form an initial output value cluster; By analyzing the fluctuation of the initial output values ​​in each initial output value cluster, the chip test series is determined, wherein the definition of the signal vector combination method is specifically expressed as: ; Where C1 is the signal vector combination, i is the first order number, f() is the comparison function, N is a non-zero constant, s i is the ith signal vector, s i-1 is the i-1th signal vector; The definition of signal asynchronous processing is specifically expressed as follows: ； Among them, C 2,p is the pth initial output value cluster, p is the serial number of the initial output value cluster, k j is the number of initial output values ​​in the jth initial output value cluster, For the The initial output value, For the The initial output value, For the Initial output value; The chip test results are determined by comparing and analyzing the test series of each chip.

2. The method for processing multi-asynchronous chip test signals as claimed in claim 1, characterized in that: The chip test signal includes an analog signal and / or a digital signal.

3. The method for processing multi-asynchronous chip test signals as claimed in claim 1, characterized in that: The feature vector is processed by the preset hash function, which is specifically expressed as: ； Among them, s i is the i-th signal vector, c is the hash constant, e i is the i-th eigenvector, mod is the modulus calculation, and X is the amplitude of the hash map.

4. The method for processing multi-asynchronous chip test signals as claimed in claim 1, characterized in that: The chip test sequence is specifically expressed as: ； Among them, C3 is the chip test series, D() is the fluctuation analysis function, C 2,1 is the first initial output value cluster, C 2,p is the pth initial output value cluster, C 2,M is the Mth initial output value cluster.

5. The method for processing multi-asynchronous chip test signals as claimed in claim 1, characterized in that: Comparative analysis of the test series of each chip shows that the chip test meets the following requirements: ； Among them, C 3,r is the test sequence for the rth chip, is the qth chip test data in the rth chip test sequence, C 3,u is the test sequence of the uth chip, is the qth chip test data in the u chip test sequence, G() is the proportional function, Y is the total number of chip test sequences, and T is the length of each chip test sequence.

6. A processing device for multiple asynchronous chip test signals, characterized in that: The method for processing a multi-asynchronous chip test signal according to any one of claims 1 to 5 specifically comprises: A collection unit, used for acquiring a chip test signal group based on a pre-test of a target chip, wherein the chip test signal group includes at least two asynchronous chip test signals; The chip test signal analysis unit is used to perform region conversion processing on each chip test signal to form a corresponding signal vector set; based on the signal asynchronous processing strategy, each signal vector set is processed to give a chip test sequence; The chip test signal processing unit is used to determine the chip test result by comparing and analyzing the test data series of each chip.

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