A red light VCSEL chip and its manufacturing method

Abstract

The present invention relates to the field of LED technology, and specifically to a red light VCSEL chip and a method for manufacturing the same. The red light VCSEL chip comprises a GaAs substrate, a GaAs transition layer, a bottom reflector, an N-type semiconductor layer, a multi-quantum well active layer, a P-type semiconductor layer, a GaP window layer, a transparent conductive layer, a monitoring layer, and a top dielectric stack reflector arranged in sequence from bottom to top; the GaP window layer comprises a GaP extension layer and a GaP contact layer arranged in sequence, the GaP extension layer comprises a non-roughened area and a roughened area surrounding the non-roughened area, the GaP contact layer is arranged in the non-roughened area, and the GaP contact layer is at least partially embedded in the transparent conductive layer; an aluminum oxide isolation layer is arranged between the roughened area and the transparent conductive layer. The structure of the present application can effectively improve the conversion efficiency of short-wavelength red light VCSEL and improve reliability.

Description

Technical Field

[0001] The present invention relates to the field of VCSEL technology, and in particular to a red light VCSEL chip and a manufacturing method thereof. Background Art

[0002] Red VCSEL chips are a type of vertical cavity surface emitting laser chips with ultra-low power consumption and high efficiency. They are mainly used in fiber optic communications, laser display, optical sensing and other fields. In the field of consumer electronics, red VCSEL chips have been widely used in proximity sensing, ToF, 3D structured light, AR / VR, face recognition, medical beauty, etc. In the future, with the further development of technology, red VCSEL chips are expected to play an important role in more emerging fields. Due to its unique working principle and structural design, red VCSEL chips have excellent performance in power consumption and efficiency, and are widely used in low-power equipment occasions. Red VCSEL chips face many challenges in the production process, especially the production of short-wavelength red VCSELs is particularly difficult, mainly because the inherent defects of AlGaInP used in the red active area material lead to limited band gap, which seriously limits the luminous efficiency and temperature characteristics of the device. In order to solve this problem, it is very necessary to improve the epitaxial design and select materials with high reflectivity and high luminous efficiency to achieve high conversion efficiency and high reliability. Summary of the invention

[0003] The purpose of the present invention is to provide a red light VCSEL chip and a manufacturing method thereof, which can effectively improve the conversion efficiency of short-wavelength red light VCSEL and improve the reliability.

[0004] In order to solve the above problems, the technical solution provided by the present invention is:

[0005] The first aspect of the present invention is to provide a red light VCSEL chip, comprising a GaAs substrate, a GaAs transition layer, a bottom reflector, an N-type semiconductor layer, a multi-quantum well active layer, a P-type semiconductor layer, a GaP window layer, a transparent conductive layer, a monitoring layer and a top dielectric stack reflector arranged in sequence from bottom to top;

[0006] The GaP window layer includes a GaP extension layer and a GaP contact layer arranged in sequence, the GaP extension layer includes a non-roughened area and a roughened area surrounding the non-roughened area, the GaP contact layer is arranged to cover the surface of the non-roughened area, and the GaP contact layer is at least partially embedded in the transparent conductive layer;

[0007] An aluminum oxide partition layer is arranged between the roughened area and the transparent conductive layer.

[0008] Furthermore, a back insulating layer is provided on the surface of the GaAs substrate away from the GaAs transition layer, the back insulating layer is made of SiN, the thickness of the back insulating layer is 4000 angstroms to 6000 angstroms, and an AlGaAs thermal conductive layer is provided between the GaAs transition layer and the bottom reflector.

[0009] Furthermore, the monitoring layer is prepared from titanium pentoxide; the top dielectric stack reflector is made of titanium pentoxide and silicon oxide alternately grown and stacked, with the number of growth pairs being 5 to 10 pairs;

[0010] The bottom reflector is made of AlAs and AlGaAs that are alternately grown and stacked, and the number of growth pairs is 40 to 50 pairs.

[0011] Furthermore, the chip is provided with a first step and a second step in sequence from top to bottom on the outer side around it;

[0012] The first step is etched from the upper surface of the chip to the upper surface of the transparent conductive layer;

[0013] The second step is etched from the upper surface of the transparent conductive layer to the upper surface of the N-type semiconductor layer.

[0014] Further, the chip further comprises an electrode group, wherein the electrode group comprises an N bonding wire electrode, a P connecting electrode and a P bonding wire electrode;

[0015] The N-type bonding wire electrode is arranged on the first side surface of the step surface of the second step, and the lower surface of the N-type bonding wire electrode is in direct contact with the upper surface of the N-type semiconductor layer;

[0016] The P bonding wire electrode is arranged on the surface of the second side of the step surface of the second step, and there is no electrical connection between the P bonding wire electrode and the N-type semiconductor layer;

[0017] The P connection electrode covers the entire step surface of the first step, the entire vertical surface of the second step, and the surface of the second side of the step surface of the second step;

[0018] Among them, the P connection electrode includes a P-side semiconductor contact portion, a P connection portion and a P welding wire contact portion connected in sequence; the P-side semiconductor contact portion is arranged on the step surface of the first step, and the lower surface of the P-side semiconductor contact portion is in direct contact with the upper surface of the transparent conductive layer; the P connection portion is arranged on the vertical surface of the second step, and no electrical connection is generated between the P connection portion and the vertical surface of the second step; the P welding wire contact portion is arranged on the surface of the second side of the step surface of the second step, and the P welding wire contact portion is in direct contact with the P welding wire electrode.

[0019] Further, the preparation material of the P connection electrode is Cr, Ti, Ni, Pt and Au arranged in sequence, and the thickness of the P connection electrode is 2500 angstroms;

[0020] The materials used to prepare the P welding wire electrode and the N welding wire electrode are Ti, Ni, Pt and Au arranged in sequence, and the thickness of the P welding wire electrode and the N welding wire electrode is 20000 angstroms.

[0021] Furthermore, the chip further comprises a passivation layer, which directly covers the surface of the top dielectric stack reflector and other regions on the surfaces of the first step and the second step except for the N-wire electrode and the P-side semiconductor contact portion.

[0022] Furthermore, the raw material used for preparing the GaP contact layer is Mg / C co-doped GaP, and the doping concentration is 5E19cm -3 , the thickness of the GaP contact layer is 15nm to 25nm;

[0023] The thickness of the GaP extension layer is 40nm to 60nm;

[0024] Furthermore, the thickness of the aluminum oxide barrier layer is 50 angstroms to 200 angstroms.

[0025] Another aspect of the present invention is to provide a method for manufacturing the above-mentioned red light VCSEL chip, the manufacturing method comprising:

[0026] S1. Provide a GaAs substrate as an epitaxial structure growth substrate, and sequentially grow a GaAs transition layer, a bottom reflector, an N-type semiconductor layer, a multi-quantum well active layer, a P-type semiconductor layer, a GaP extension layer and a GaP contact layer on the GaAs substrate;

[0027] S2. On the epitaxial wafer, an organic solution cleaning method is used, a positive resist overlay method is used, and a GaP roughening solution is used to remove the GaP contact layer material on the roughened area, and the bottom GaP extension layer is roughened;

[0028] S3, using organic solution cleaning, negative resist overprinting, electron beam evaporation, and negative resist stripping to form an aluminum oxide isolation layer in the roughened area;

[0029] S4, cleaning the wafer with a mixture of weak alkaline ammonia and water, and depositing a transparent conductive layer on the surface of the wafer by sputtering;

[0030] S5, using an organic cleaning method, an optical film evaporator to evaporate the monitoring layer and the top medium stack reflector;

[0031] S6, using positive resist overprinting to produce a second step pattern, and etching to the surface of the N-type semiconductor layer by ICP etching to stop forming the second step; further using positive resist overprinting to produce a first step pattern, and etching to the surface of the transparent conductive layer by ICP etching to stop forming the first step;

[0032] S7, cleaning the wafer with an organic solution, depositing a passivation layer by PECVD, making a conductive channel pattern by a positive photoresist, and etching away the passivation layer material in the conductive channel pattern by ICP;

[0033] S8, using an organic solution cleaning method, a negative resist overlay method, electron beam evaporation, and negative resist stripping to produce a P connection electrode; further using an organic solution cleaning method, a negative resist overlay method, electron beam evaporation, and negative resist stripping to produce a P welding wire electrode and an N welding wire electrode;

[0034] S9, thinning the GaAs substrate by mechanical grinding, and performing CMP polishing, cleaning the back side by an organic solution, and forming a back side insulating layer by electron beam evaporation;

[0035] S10. Finally, the chips are cut and separated at a fixed interval to form VCESL single chips and tested and AOI sorted.

[0036] Compared with the prior art, the present invention has the following beneficial effects:

[0037] 1. In this application, the epitaxial material and structure of the red light VCSEL chip are improved, the highly doped GaP contact layer above the roughened area is etched away and the surface is roughened, and then an aluminum oxide barrier layer is provided to fully cover the roughened area, which can jointly constrain the current and destroy the mirror reflection that may be formed inside the structure, perform optical constraints, and improve the light extraction efficiency of the device. The aluminum oxide barrier layer can also improve the adhesion effect of the roughened surface and the transparent conductive layer, and improve the stability and reliability of the device.

[0038] 2. The laser cavity length must be an integer multiple of the wavelength to ensure stable oscillation of the laser in the cavity. The laser cavity length determines the wavelength of the laser emission. By adding a monitoring layer, the thickness of the top dielectric stack reflector can be adjusted in real time according to the actual vapor deposition thickness of the monitoring layer to strengthen the control of the cavity length, which is conducive to real-time adjustment of the cavity length so that the cavity length matches the wavelength.

[0039] 3. Through the design of the above step structure and electrode group, the etching of the first step and the second step can further limit the current of the chip and limit light leakage. The P wire electrode is introduced to the second step to facilitate wire bonding, while the structure is stable and reliable. Since there is heat generation caused by the current passing through the GaAs substrate side and the oscillation loss of photons in the cavity, the heat generated by the chip during use can be effectively conducted by introducing an AlGaAs thermal conductive layer in the epitaxial structure.

[0040] 4. The red light VCSEL chip manufacturing method provided in this application can obtain a device with high light efficiency and high reliability, and the processing process is simple and the cost is low. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0042] Figure 1 This is a schematic diagram of the epitaxial structure of a red light VCSEL chip shown in some embodiments of the present application;

[0043] Figure 2 This is a structural schematic diagram of a red light VCSEL chip epitaxial structure forming a coarsening area as shown in some embodiments of the present application;

[0044] Figure 3 A schematic structural diagram of another perspective of a roughened area formed in the epitaxial structure of a red light VCSEL chip shown in some embodiments of the present application;

[0045] Figure 4 A schematic diagram of the structure of the red light VCSEL chip epitaxial structure forming a monitoring layer and a top dielectric stack reflector as shown in some embodiments of the present application;

[0046] Figure 5 A schematic diagram of a structure in which a first step and a second step are formed in an epitaxial structure of a red light VCSEL chip as shown in some embodiments of the present application;

[0047] Figure 6 This is a schematic diagram of the structure of a red light VCSEL chip shown in some embodiments of the present application;

[0048] Figure 7 This is a schematic structural diagram of a red light VCSEL chip from another perspective shown in some embodiments of the present application;

[0049] Description of the drawings: 1. GaAs substrate; 2. GaAs transition layer; 3. bottom reflector; 4. N-type semiconductor layer; 5. multi-quantum well active layer; 6. P-type semiconductor layer; 7. GaP window layer; 71. GaP extension layer; 711. non-roughened area; 712. roughened area; 72. GaP contact layer; 9. aluminum oxide isolation layer; 10. transparent conductive layer; 11. monitoring layer; 12. AlGaAs thermal conductive layer; 13. top dielectric stack reflector; 14. passivation layer; 15. P connection electrode; 151. P-side semiconductor contact; 152. P connection; 153. P welding wire contact; 161. N welding wire electrode; 162. P welding wire electrode; 17. back insulating layer; 18. first step; 19. second step. DETAILED DESCRIPTION

[0050] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. The following description of at least one exemplary embodiment is actually only illustrative and is by no means intended to limit the present application and its application or use. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0051] Unless otherwise specifically stated, the relative arrangement, numerical expressions and numerical values ​​of the parts and steps set forth in these embodiments do not limit the scope of the present application. At the same time, it should be understood that, for ease of description, the sizes of the various parts shown in the accompanying drawings are not drawn according to the actual proportional relationship. The technology, method and equipment known to those of ordinary skill in the relevant field may not be discussed in detail, but in appropriate cases, the technology, method and equipment should be considered as a part of the authorization specification. In all examples shown and discussed here, any specific value should be interpreted as being merely exemplary, rather than as a limitation. Therefore, other examples of exemplary embodiments may have different values. It should be noted that similar reference numerals and letters represent similar items in the following drawings, so that once a certain item is defined in an accompanying drawing, it does not need to be further discussed in subsequent drawings.

[0052] In the description of the present application, it should be understood that the use of terms such as "first" and "second" to limit components is only for the convenience of distinguishing the corresponding components. Unless otherwise stated, the above terms have no special meaning and therefore cannot be understood as limiting the scope of protection of the present application.

[0053] In the description of the present application, it should be understood that the directions or positional relationships indicated by directional words such as "front, back, up, down, left, right", "lateral, vertical, perpendicular, horizontal" and "top, bottom" are usually based on the directions or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description. Unless otherwise specified, these directional words do not indicate or imply that the device or element referred to must have a specific direction or be constructed and operated in a specific direction, and therefore cannot be understood as limiting the scope of protection of the present application; the directional words "inside and outside" refer to the inside and outside relative to the contours of each component itself.

[0054] The present application is further described in detail below with reference to specific embodiments:

[0055] Example 1

[0056] The red light VCSEL chip provided in this embodiment, Figure 6 This is a schematic diagram of the structure of a red light VCSEL chip shown in some embodiments of the present application (the front side is the light emitting side); Figure 7 This is a schematic diagram of the structure of the red light VCSEL chip from another perspective shown in some embodiments of the present application; specifically, the structure provided by the present application is as follows, please refer to Figure 6 and Figure 7 A red light VCSEL chip comprises a GaAs substrate 1, a GaAs transition layer 2, a bottom reflector 3, an N-type semiconductor layer 4, a multi-quantum well active layer 5, a P-type semiconductor layer 6, a GaP window layer 7, a transparent conductive layer 10, a monitoring layer 11 and a top dielectric stack reflector 13 arranged in sequence from bottom to top; the GaP window layer 7 comprises a GaP extension layer 71 and a GaP contact layer 72 arranged in sequence, the GaP extension layer 71 comprises a non-roughened area 711 and a roughened area 712 surrounding the non-roughened area 711, and the GaP contact layer 72 covers the surface of the non-roughened area 711 (see the structure for details). Figure 3 ), and the GaP contact layer 72 is at least partially embedded in the transparent conductive layer 10; an aluminum oxide partition layer 9 is provided between the roughened area 712 and the transparent conductive layer 10.

[0057] The red light VCSEL chip in the present application can be used to confine the current and destroy the specular reflection that may be formed inside the structure by etching away the highly doped GaP contact layer 72 above the roughened area 712 and roughening the surface, and then the aluminum oxide barrier layer 9 is fully covered on the roughened area 712, so as to perform optical confinement. The aluminum oxide barrier layer 9 can also improve the adhesion effect of the roughened surface and the transparent conductive layer 10, thereby improving the stability and reliability of the device.

[0058] Because the laser cavity length must be an integer multiple of the wavelength to ensure stable oscillation of the laser in the cavity, the laser cavity length determines the wavelength of the laser emission. By adding the monitoring layer 11, the thickness of the top dielectric stack reflector 13 can be adjusted in real time according to the actual vapor deposition thickness of the monitoring layer 11 to strengthen the control of the cavity length, which is conducive to real-time adjustment of the cavity length so that the cavity length matches the wavelength.

[0059] As a preferred embodiment, a back insulating layer 17 is provided on the surface of the GaAs substrate 1 away from the GaAs transition layer 2. The back insulating layer 17 is made of SiN and has a thickness of 4000 angstroms to 6000 angstroms.

[0060] In the red light VCSEL chip structure provided by the present application, there is a situation on the GaAs substrate 1 side where the current generates heat and the photons oscillate and lose in the cavity, causing the device to heat up. As a preferred embodiment, an AlGaAs heat-conducting layer 12 is further provided between the GaAs transition layer 2 and the bottom reflector 3. By introducing the AlGaAs heat-conducting layer 12 into the epitaxial structure, the heat generated during the use of the chip can be effectively conducted.

[0061] As a preferred embodiment, the monitoring layer 11 is made of titanium pentoxide; the top dielectric stack reflector 13 uses titanium pentoxide and silicon oxide alternately grown and stacked, with a growth pair number of 5 to 10 pairs; the bottom reflector 3 uses AlAs and AlGaAs alternately grown and stacked, with a growth pair number of 40 to 50 pairs.

[0062] As a preferred embodiment, please combine Figure 5 The first step 18 and the second step 19 are sequentially arranged around the outer side of the chip from top to bottom; the first step 18 is etched from the upper surface of the chip to the upper surface of the transparent conductive layer 10; the second step 19 is etched from the upper surface of the transparent conductive layer 10 to the upper surface of the N-type semiconductor layer 4.

[0063] As a preferred embodiment, please combine Figure 6 and Figure 7The chip further comprises an electrode group, the electrode group comprising an N welding wire electrode 161, a P connection electrode 15 and a P welding wire electrode 162; the N welding wire electrode 161 is arranged on the first side surface of the step surface of the second step 19, and the lower surface of the N welding wire electrode 161 is in direct contact with the upper surface of the N-type semiconductor layer 4; the P welding wire electrode 162 is arranged on the surface of the second side of the step surface of the second step 19, and there is no electrical connection between the P welding wire electrode 162 and the N-type semiconductor layer 4; the P connection electrode 15 covers the entire step surface of the first step 18, the entire vertical surface of the second step 19 and the surface of the second side of the step surface of the second step 19 (which can limit the side light emission and improve the stability of the VCSEL side wall structure); wherein the P connection electrode 15 comprises a plurality of electrodes connected in sequence. The P-side semiconductor contact portion 151, the P-connecting portion 152 and the P-welding wire contact portion 153 are connected; the P-side semiconductor contact portion 151 is arranged on the step surface of the first step 18, and the lower surface of the P-side semiconductor contact portion 151 is in direct contact with the upper surface of the transparent conductive layer 10; the P-connecting portion 152 is arranged on the vertical surface of the second step 19, and no electrical connection is generated between the P-connecting portion 152 and the vertical surface of the second step 19; the P-welding wire contact portion 153 is only arranged on the surface of the second side of the step surface of the second step 19, and the P-welding wire contact portion 153 is in direct contact with the P-welding wire electrode 162 to ensure the electrical connection between the P-welding wire electrode 162 and the transparent conductive layer 10, and no electrical connection is generated between the P-welding wire electrode 162 and the N-type semiconductor layer 4.

[0064] It should be noted that the "first side" and "second side" described in the above embodiments are kept at a certain position on the chip to facilitate wire bonding operations and insulation. As a specific setting example, the above "first side" and "second side" are respectively located at the left and right ends of the chip.

[0065] The present application adopts the above step structure and electrode group design, wherein the etching of the first step 18 and the second step 19 can further limit the current of the chip and limit light leakage. The P wire electrode 162 is introduced to the second step 19 to facilitate wire bonding, while the structure is stable and highly reliable.

[0066] As a preferred embodiment, the preparation material of the P connection electrode 15 is Cr, Ti, Ni, Pt and Au arranged in sequence, and the thickness of the P connection electrode 15 is 2500 angstroms; the preparation materials of the P welding wire electrode 162 and the N welding wire electrode 161 are Ti, Ni, Pt and Au arranged in sequence, and there is no special restriction on the thickness of the P welding wire electrode 162 and the N welding wire electrode 161, and it can be set with reference to the thickness of a conventional red light VCSEL chip, for example, it can be set to 20000 angstroms.

[0067] As a preferred embodiment, the chip further includes a passivation layer 14, which directly covers the surface of the top dielectric stack reflector 13 and other areas on the surface of the first step 18 and the second step 19 except the N-wire electrode 161 and the P-side semiconductor contact 151.

[0068] As a preferred embodiment, the GaP contact layer 72 is made of Mg / C co-doped GaP with a doping concentration of 5E19cm -3 The thickness of the GaP contact layer 72 is 15 nm to 25 nm; the thickness of the GaP extension layer 71 is 40 nm to 60 nm; and the thickness of the aluminum oxide isolation layer 9 is 50 angstroms to 200 angstroms.

[0069] The area directly above the GaP contact layer 72 serves as the light emitting area of ​​the red light VCSEL, so the shape of the GaP contact layer 72 can be set according to the shape of a conventional red light VCSEL light emitting hole. Preferably, the shape of the GaP contact layer 72 is circular.

[0070] From the above, it can be seen that the red light VCSEL chip provided in the embodiment of the present application has the following advantages:

[0071] 1. In this application, the epitaxial material and structure of the red light VCSEL chip are improved, the highly doped GaP contact layer above the roughened area is etched away and the surface is roughened, and then an aluminum oxide barrier layer is provided to fully cover the roughened area, which can jointly constrain the current and destroy the mirror reflection that may be formed inside the structure, perform optical constraints, and improve the light extraction efficiency of the device. The aluminum oxide barrier layer can also improve the adhesion effect of the roughened surface and the transparent conductive layer, and improve the stability and reliability of the device.

[0072] 2. The laser cavity length must be an integer multiple of the wavelength to ensure stable oscillation of the laser in the cavity. The laser cavity length determines the wavelength of the laser emission. By adding a monitoring layer, the thickness of the top dielectric stack reflector can be adjusted in real time according to the actual vapor deposition thickness of the monitoring layer to strengthen the control of the cavity length, which is conducive to real-time adjustment of the cavity length so that the cavity length matches the wavelength.

[0073] 3. Through the design of the above step structure and electrode group, the etching of the first step and the second step can further limit the current of the chip and limit light leakage. The P wire electrode is introduced to the second step to facilitate wire bonding, while the structure is stable and reliable. Since there is heat generation caused by the current passing through the GaAs substrate side and the oscillation loss of photons in the cavity, the heat generated by the chip during use can be effectively conducted by introducing an AlGaAs thermal conductive layer in the epitaxial structure.

[0074] Example 2

[0075] Please combine Figure 1 to Figure 7 This embodiment provides a method for manufacturing a red light VCSEL chip, the manufacturing method comprising:

[0076] Step 1: Please combine Figure 1 , Figure 1 Schematic diagram of the epitaxial structure of a red light VCSEL chip shown in some embodiments of the present application; a GaAs substrate 1 is provided as an epitaxial structure growth substrate, and a GaAs transition layer 2, an AlGaAs thermal conductive layer 12, a bottom reflector 3, an N-type semiconductor layer 4, a multi-quantum well active layer 5, a P-type semiconductor layer 6, a GaP extension layer 71 and a GaP contact layer 72 are sequentially grown on the GaAs substrate 1;

[0077] The GaAs substrate 1 preferably has a 10° off-angle and a thickness of 625 μm; the GaAs transition layer 2 preferably has a thickness of 200 nm; the bottom reflector 3 preferably has an AlAs / AlGaAs stacked layer with a pair number of 40 to 50 pairs; the N-type semiconductor layer 4, the multi-quantum well active layer 5, and the P-type semiconductor layer 6 preferably have a thin AlGaInP light-emitting structure with a thickness of 200 nm, which is easy to manufacture chip steps; the N-type semiconductor layer 4 is doped with Si, and the doping concentration is 2E17 cm -3 ~4E17cm -3 ; The P-type semiconductor layer 6 is doped with Mg, with a doping concentration of 4E17cm -3 ~8E17cm -3 The thickness of the GaP extension layer 71 is preferably 50 nm, the thickness of the GaP contact layer 72 is preferably 20 nm, and the doping element of the GaP contact layer 72 is Mg / C co-doped, and the doping concentration is 5E19cm -3 ; The thickness of the AlGaAs thermal conductive layer 12 is 100 nm;

[0078] Step 2: Please combine Figure 2 and Figure 3 , Figure 2 This is a structural schematic diagram of a red light VCSEL chip epitaxial structure forming a coarsening area as shown in some embodiments of the present application; Figure 3 Another perspective structural diagram of the roughened area formed in the epitaxial structure of the red light VCSEL chip shown in some embodiments of the present application; on the epitaxial wafer, the GaP contact layer 72 material on the roughened area 712 is removed by using an organic solution cleaning method and a positive resist overlay method, and the bottom GaP extension layer 71 is roughened by using a GaP roughening solution; the roughening depth is 20nm to 30nm;

[0079] Please combine the following steps 3 to 5 Figure 4 , Figure 4A schematic diagram of the structure of the red light VCSEL chip epitaxial structure forming a monitoring layer and a top dielectric stack reflector as shown in some embodiments of the present application;

[0080] Step 3: using organic solution cleaning, negative resist overprinting, electron beam evaporation, and negative resist stripping, to form an aluminum oxide isolation layer 9 in the roughened area 712 for insulation and current blocking; preferably, the thickness of the aluminum oxide isolation layer 9 is 100 angstroms;

[0081] Step 4: Clean the wafer with a mixture of weak alkaline ammonia and water, and deposit a transparent conductive layer 10 on the wafer surface by sputtering. The thickness of the transparent conductive layer 10 is not particularly limited and can be set with reference to the thickness of a conventional VCSEL; preferably, the thickness of the transparent conductive layer 10 is 400nm to 500nm.

[0082] Step 5: Using an organic cleaning method, an optical film evaporator evaporates the monitoring layer 11 and the top dielectric stack reflector 13; preferably, the monitoring layer 11 is made of titanium pentoxide, and the top dielectric stack reflector 13 adopts an 8-pair alternating structure of titanium pentoxide and silicon oxide. Since the laser cavity length determines the wavelength of laser emission, the monitoring layer 11 is increased with titanium pentoxide, mainly based on the actual evaporated thickness of the monitoring layer 11, and the thickness of the top dielectric stack reflector 13 is adjusted in real time to strengthen the control of the cavity length (the cavity length refers to the thickness from the top dielectric stack reflector 13 to the bottom reflector 3);

[0083] Step 6: Please combine Figure 5 , Figure 5 A schematic diagram of the structure of the red light VCSEL chip epitaxial structure forming the first step and the second step shown in some embodiments of the present application; a second step 19 pattern is produced by positive resist overlay, and the second step 19 is stopped by ICP etching until the surface of the N-type semiconductor layer 4 is etched, the ICP etching power is 800W, the pressure is 50mTOrr, the BCl3 flow rate is 35sccm, the Cl2 flow rate is 10sccm, the N2 flow rate is 15sccm, and the surface photoresist is removed by a stripping solution; a first step 18 pattern is further produced by positive resist overlay, and the first step 18 is stopped by ICP etching until the surface of the transparent conductive layer 10 is etched, the ICP etching power is 800W, the pressure is 50mTOrr, the BCl3 flow rate is 35sccm, the Cl2 flow rate is 10sccm, the N2 flow rate is 15sccm, and the surface photoresist is removed by a stripping solution;

[0084] Please combine the following steps 7 to 10 Figure 6 and Figure 7 , Figure 6 This is a schematic diagram of the structure of a red light VCSEL chip shown in some embodiments of the present application; Figure 7This is a schematic structural diagram of a red light VCSEL chip from another perspective shown in some embodiments of the present application;

[0085] Step seven, clean the wafer with an organic solution, deposit a passivation layer 14 by PECVD, make a conductive channel pattern with a positive photoresist, and etch away the passivation layer 14 material in the conductive channel pattern by ICP; preferably, the passivation layer 14 is made of SiN and the deposition temperature is 280°C.

[0086] Step 8: Using an organic solution cleaning method, a negative resist overlay method, an electron beam evaporation method, and a negative resist stripping method to manufacture a P connection electrode 15; further using an organic solution cleaning method, a negative resist overlay method, an electron beam evaporation method, and a negative resist stripping method to manufacture a P welding wire electrode 162 and an N welding wire electrode 161; preferably, the thickness of the P connection electrode 15 is 2500 angstroms, and includes Cr / Ti / Ni / Pt / Au metal materials in sequence; the thickness of the P welding wire electrode 162 and the N welding wire electrode 161 is 20000 angstroms, and includes Ti / Ni / Pt / Au metal materials in sequence;

[0087] Step 9: Thin the GaAs substrate 1 by mechanical grinding, perform CMP polishing, clean the back surface by organic solution, and form a back insulating layer 17 by electron beam evaporation; preferably, the back insulating layer 17 is made of SiN with a thickness of 5000 angstroms;

[0088] Step 10. Finally, the chips are cut and separated at a fixed interval to form VCESL single chips and tested and AOI sorted.

[0089] From the above, it can be seen that the method for manufacturing the red light VCSEL chip provided in the embodiment of the present application has the following advantages: the red light VCSEL chip manufactured by this invention has high efficiency, high device reliability, simple processing and low cost. Since the method for manufacturing the red light VCSEL chip provided in the embodiment of the present application obtains the red light VCSEL chip in the above embodiment 1, it also has the advantages of the red light VCSEL chip in the above embodiment 1, which will not be described in detail here.

[0090] For content not described in this embodiment, please refer to the relevant description in the rest of this application.

[0091] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present application and not to limit it. Although the present application has been described in detail with reference to the preferred embodiments, ordinary technicians in the relevant field should understand that the specific implementation methods of the present application can still be modified or some technical features can be replaced by equivalents, which should all be included in the scope of the technical solution requested for protection in this application.

Claims

1. A red light VCSEL chip, characterized in that: It includes a GaAs substrate, a GaAs transition layer, a bottom reflector, an N-type semiconductor layer, a multi-quantum well active layer, a P-type semiconductor layer, a GaP window layer, a transparent conductive layer, a monitoring layer and a top dielectric stack reflector which are arranged in sequence from bottom to top; The GaP window layer includes a GaP extension layer and a GaP contact layer arranged in sequence, the GaP extension layer includes a non-roughened area and a roughened area surrounding the non-roughened area, the GaP contact layer is arranged to cover the surface of the non-roughened area, and the GaP contact layer is at least partially embedded in the transparent conductive layer; An aluminum oxide partition layer is provided between the roughened area and the transparent conductive layer; The chip is provided with a first step and a second step in sequence from top to bottom on the outer side around the chip; The first step is etched from the upper surface of the chip to the upper surface of the transparent conductive layer; The second step is etched from the upper surface of the transparent conductive layer to the upper surface of the N-type semiconductor layer; The chip further comprises an electrode group, wherein the electrode group comprises an N bonding wire electrode, a P connecting electrode and a P bonding wire electrode; The N-type bonding wire electrode is arranged on the first side surface of the step surface of the second step, and the lower surface of the N-type bonding wire electrode is in direct contact with the upper surface of the N-type semiconductor layer; The P bonding wire electrode is arranged on the surface of the second side of the step surface of the second step, and there is no electrical connection between the P bonding wire electrode and the N-type semiconductor layer; The P connection electrode covers the entire step surface of the first step, the entire vertical surface of the second step, and the surface of the second side of the step surface of the second step; Among them, the P connection electrode includes a P-side semiconductor contact portion, a P connection portion and a P welding wire contact portion connected in sequence; the P-side semiconductor contact portion is arranged on the step surface of the first step, and the lower surface of the P-side semiconductor contact portion is in direct contact with the upper surface of the transparent conductive layer; the P connection portion is arranged on the vertical surface of the second step, and no electrical connection is generated between the P connection portion and the vertical surface of the second step; the P welding wire contact portion is arranged on the surface of the second side of the step surface of the second step, and the P welding wire contact portion is in direct contact with the P welding wire electrode.

2. A red light VCSEL chip according to claim 1, characterized in that: A back insulating layer is arranged on the surface of the GaAs substrate away from the GaAs transition layer. The back insulating layer is made of SiN and has a thickness of 4000 angstroms to 6000 angstroms. An AlGaAs thermal conductive layer is arranged between the GaAs transition layer and the bottom reflector.

3. A red light VCSEL chip according to claim 1, characterized in that: The monitoring layer is made of titanium pentoxide; the top dielectric stack reflector is made of titanium pentoxide and silicon oxide that are alternately grown and stacked, with the number of growth pairs being 5 to 10 pairs; The bottom reflector is made of AlAs and AlGaAs that are alternately grown and stacked, and the number of growth pairs is 40 to 50 pairs.

4. The red light VCSEL chip according to claim 1, characterized in that: The P connection electrode is made of materials including Cr, Ti, Ni, Pt and Au arranged in sequence, and the thickness of the P connection electrode is 2500 angstroms; The materials used to prepare the P welding wire electrode and the N welding wire electrode are Ti, Ni, Pt and Au arranged in sequence, and the thickness of the P welding wire electrode and the N welding wire electrode is 20000 angstroms.

5. The red light VCSEL chip according to claim 1, characterized in that: The chip further includes a passivation layer, which directly covers the surface of the top dielectric stack reflector and other regions on the surfaces of the first step and the second step except for the N-wire electrode and the P-side semiconductor contact portion.

6. The red light VCSEL chip according to claim 1, characterized in that: The raw material used for the preparation of the GaP contact layer is Mg / C co-doped GaP, and the doping concentration is 5E19cm -3 , the thickness of the GaP contact layer is 15nm to 25nm; The thickness of the GaP extension layer is 40nm-60nm.

7. The red light VCSEL chip according to claim 1, characterized in that: The thickness of the aluminum oxide barrier layer is 50 angstroms to 200 angstroms.

8. A method for manufacturing a red light VCSEL chip according to any one of claims 1 to 7, characterized in that: The production method comprises: S1. Provide a GaAs substrate as an epitaxial structure growth substrate, and sequentially grow a GaAs transition layer, a bottom reflector, an N-type semiconductor layer, a multi-quantum well active layer, a P-type semiconductor layer, a GaP extension layer and a GaP contact layer on the GaAs substrate; S2. On the epitaxial wafer, an organic solution cleaning method is used, a positive resist overlay method is used, and a GaP roughening solution is used to remove the GaP contact layer material on the roughened area, and the bottom GaP extension layer is roughened; S3, using organic solution cleaning, negative resist overprinting, electron beam evaporation, and negative resist stripping to form an aluminum oxide isolation layer in the roughened area; S4, cleaning the wafer with a mixture of weak alkaline ammonia and water, and depositing a transparent conductive layer on the surface of the wafer by sputtering; S5, using an organic cleaning method, an optical film evaporator to evaporate the monitoring layer and the top medium stack reflector; S6, using positive resist overprinting to produce a second step pattern, and etching to the surface of the N-type semiconductor layer by ICP etching to stop forming the second step; further using positive resist overprinting to produce a first step pattern, and etching to the surface of the transparent conductive layer by ICP etching to stop forming the first step; S7, cleaning the wafer with an organic solution, depositing a passivation layer by PECVD, making a conductive channel pattern by a positive photoresist, and etching away the passivation layer material in the conductive channel pattern by ICP; S8, using an organic solution cleaning method, a negative resist overlay method, electron beam evaporation, and negative resist stripping to produce a P connection electrode; further using an organic solution cleaning method, a negative resist overlay method, electron beam evaporation, and negative resist stripping to produce a P welding wire electrode and an N welding wire electrode; S9, thinning the GaAs substrate by mechanical grinding, and performing CMP polishing, cleaning the back side by an organic solution, and forming a back side insulating layer by electron beam evaporation; S10. Finally, the chips are cut and separated at a fixed interval to form VCESL single chips and tested and AOI sorted.

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