Method for preparing passivation contact region based on ion implantation, passivation contact cell and preparation method thereof

Abstract

The invention provides a method for preparing a passivation contact region based on an ion implantation technology, which comprises the following steps of: fully crystallizing polycrystalline silicon subjected to chemical vapor deposition, doping the polycrystalline silicon through ion implantation of boron or phosphorus, and activating doped atoms of the implanted boron or phosphorus by adopting rapid heat treatment to obtain the passivation contact region. And the doped boron or phosphorus is controlled to enter the silicon substrate less. According to the method, a boron or phosphorus doping distribution curve close to an ideal design passivation contact region can be obtained by combining boron or phosphorus ion implantation and a rapid heat treatment technology, so that a high-quality hole passivation contact region and an electron passivation contact region can be obtained. On the basis, the invention also discloses a method for preparing the passivated contact battery by adopting the method and the correspondingly obtained passivated contact battery.

Description

Technical Field

[0001] The invention belongs to the field of solar cells, and mainly provides a method for preparing a passivation contact area based on ion implantation technology, and provides a corresponding passivation contact cell and a preparation method thereof. Background Art

[0002] Photovoltaic power generation is green and environmentally friendly, can be sustainable, can solve the energy and environmental crisis of mankind, and has an important strategic position in the future energy development. The development of high-efficiency, low-cost solar cells is the key to promoting the stable and rapid development of the photovoltaic power generation industry. Among all types of solar cells, crystalline silicon solar cells have the fastest development in application, the most mature industrial technology, and the highest market share due to their high photoelectric conversion efficiency, stable performance, and low manufacturing cost. Among them, crystalline silicon solar cells with passivated contact structures (referred to as passivated contact cells) can achieve extremely excellent surface passivation, selective passage of photogenerated carriers, and one-dimensional efficient collection through tunneling silicon oxide and doped polycrystalline silicon, and have very high photoelectric conversion efficiency. At present, TOPCon (Tunnel Oxide and Passivated Contact) passivated contact cells with n-type silicon as substrate have been popularized in industrial production.

[0003] The core structure of the passivation contact cell is the passivation contact region, including the hole passivation contact region and the electron passivation contact region. The ideally designed passivation contact region is expected to achieve: 1) as high a doping concentration of boron or phosphorus as possible in doped (boron or phosphorus) polysilicon, 2) as high a doping concentration of boron or phosphorus as possible at the doped polysilicon / tunneling silicon oxide interface, 3) as low a doping concentration of boron or phosphorus as possible in the silicon substrate, and 4) high-quality tunneling silicon oxide.

[0004] From the perspective of obtaining the ideal doping distribution of boron or phosphorus in the passivation contact area, the conventional doping technology currently used, including furnace tube thermal diffusion, or chemical vapor deposition of boron and phosphorus doping sources combined with furnace tube heat treatment, has the following disadvantages: 1) The surface doping concentration is limited by the solid solubility of the doping temperature. When a high doping concentration is required, a high temperature and time for doping source deposition and redistribution are often required. As a result, the doping of boron or phosphorus will inevitably enter the silicon substrate more, thereby seriously increasing the Auger recombination in the silicon substrate. When more boron or phosphorus atoms pass through the ultra-thin tunneling silicon oxide, a large number of pinholes will also be formed, thereby seriously reducing the interface passivation quality of the tunneling silicon oxide. In particular, for the hole passivation contact area, high temperature (especially above 1000°C) and long-term heat treatment will cause more doped boron atoms to redistribute into the silicon substrate, which will cause more dislocation defects in the silicon substrate, thereby causing more lattice distortion. The higher the temperature, the higher the degree of crystal silicon distortion. Moreover, high temperature and long-term heat treatment will also reduce the bulk minority carrier diffusion length of the silicon substrate. 2) To reduce Auger recombination, it is necessary to reduce the amount of boron and phosphorus doping that enters the silicon substrate, which requires reducing the temperature and time of doping source deposition and redistribution, which will inevitably weaken the field passivation effect of doped polysilicon, thereby reducing the ability of the passivation contact area to extract and transmit majority carriers. 3) Using traditional doping technology, a doping distribution curve similar to the Gaussian or residual error function distribution is obtained in polysilicon. The doping concentration of boron or phosphorus gradually decreases with the increasing depth into the polysilicon layer. The highest doping concentration occurs at the outermost surface of the polysilicon layer, and the lowest doping concentration occurs at the tunneling silicon oxide / polysilicon interface. Since the doping concentration of boron or phosphorus at the interface is crucial to the strength of the field passivation effect of doped polysilicon, a lower doping concentration of boron or phosphorus at the interface will result in a weaker field passivation effect, thereby weakening the ability to extract photogenerated carriers. 4) Since the doping concentration of boron diffusion is more dependent on the solid solubility limit of boron in polysilicon at a certain temperature, it is not easy to obtain a concentration higher than 1·10 on the polysilicon surface and in the polysilicon layer even if a long-term high-temperature heat treatment above 1000°C is used. 20 cm -3 The boron doping concentration makes it difficult for the hole passivation contact region prepared by boron diffusion to obtain a strong field passivation effect.

[0005] The above shortcomings prevent the performance of the passivation contact area from being fully utilized, which restricts the further improvement of the conversion efficiency of the passivation contact cell. Therefore, developing high-quality hole and electron passivation contact areas with or close to ideal doping distribution curves is very critical to improving the photoelectric conversion efficiency of the passivation contact cell and can promote its further development in industrialization. Summary of the invention

[0006] In order to solve the above problems, the present invention provides a method for preparing a passivation contact area based on ion implantation technology. First, the chemical vapor deposited polysilicon is fully crystallized, and then the polysilicon is doped by ion implantation of boron or phosphorus, and then rapid thermal treatment is used to activate the implanted boron or phosphorus doping atoms, and the doped boron or phosphorus is controlled to enter the silicon substrate less. This method can obtain a doping distribution curve of boron or phosphorus in the passivation contact area close to the ideal design by combining boron or phosphorus ion implantation and rapid thermal treatment technology, so that high-quality hole passivation contact areas and electron passivation contact areas can be obtained. Based on this, the present invention also discloses a method for preparing a passivation contact battery using the above method and the corresponding passivation contact battery.

[0007] A first aspect of the present invention provides a method for preparing a passivation contact region based on ion implantation, comprising:

[0008] providing a silicon substrate;

[0009] Preparing tunneling silicon oxide on the surface of the silicon substrate;

[0010] Preparing intrinsic polysilicon or intrinsic amorphous silicon on the tunneling silicon oxide, and then raising the ambient temperature of the intrinsic polysilicon or the intrinsic amorphous silicon to 800-900° C. to fully crystallize the intrinsic polysilicon, or first crystallizing the intrinsic amorphous silicon into intrinsic polysilicon and then fully crystallizing the intrinsic amorphous silicon;

[0011] Doping the fully crystallized intrinsic polysilicon by ion implantation of boron or phosphorus;

[0012] The activation of boron or phosphorus doping and its redistribution within the intrinsic polysilicon are accomplished by rapid thermal processing.

[0013] The second aspect of the present invention provides a method for preparing a passivated contact cell, wherein the passivated contact region of the passivated contact cell is prepared by the method described in the first aspect of the present invention.

[0014] The third aspect of the present invention provides a passivation contact battery, which has a passivation contact region including a hole passivation contact region and / or an electron passivation contact region; the passivation contact region is prepared by the method for preparing a passivation contact region based on ion implantation described in the first aspect of the present invention.

[0015] When the passivation contact region is a hole passivation contact region, the boron doping concentration on the outer surface of the boron-doped polysilicon is not less than 1.10 20 cm -3 , the boron doping concentration at the boron-doped polysilicon / tunneling silicon oxide interface is not less than 5·10 19 cm -3, and the difference between the boron doping concentration on the outer surface of the boron-doped polysilicon and the boron doping concentration at the interface of the boron-doped polysilicon / tunneling silicon oxide is less than 10% of the boron doping concentration on the outer surface of the boron-doped polysilicon; when the passivation contact region is an electronic passivation contact region, the phosphorus doping concentration on the outer surface of the phosphorus-doped polysilicon is not less than 1·10 20 cm -3 , the phosphorus doping concentration at the phosphorus-doped polysilicon / tunneling silicon oxide interface is not less than 1·10 20 cm -3 , and the difference between the phosphorus doping concentration on the outer surface of the phosphorus-doped polysilicon and the phosphorus doping concentration at the phosphorus-doped polysilicon / tunneling silicon oxide interface is less than 50% of the phosphorus doping concentration on the outer surface of the phosphorus-doped polysilicon.

[0016] When the passivation contact region is a hole passivation contact region, for a silicon substrate with a bulk resistivity of 0.5-10Ω·cm:

[0017] When the thickness of the boron-doped polysilicon is in the range of 0-50nm, the absolute value of the slope of the change in the logarithm of the boron doping concentration versus the depth into the silicon substrate from the boron-doped polysilicon / tunneling silicon oxide interface to the point where the boron doping concentration in the silicon substrate is equal to the intrinsic doping concentration of the silicon substrate is greater than or equal to 12.6μm -1 ;

[0018] When the thickness of the boron-doped polysilicon is in the range of 50-200nm, the absolute value of the slope of the change in the logarithm of the boron doping concentration versus the depth into the silicon substrate from the boron-doped polysilicon / tunneling silicon oxide interface to the point where the boron doping concentration in the silicon substrate is equal to the intrinsic doping concentration of the silicon substrate is greater than or equal to 15.8μm -1 ;

[0019] The thickness of the boron-doped polysilicon is in the range of 200-500nm, and the absolute value of the slope of the change in the logarithm of the boron doping concentration versus the depth into the silicon substrate from the boron-doped polysilicon / tunneling silicon oxide interface to the point where the boron doping concentration in the silicon substrate is equal to the intrinsic doping concentration of the silicon substrate is greater than or equal to 21.1μm -1 ;

[0020] When the passivation contact region is an electronic passivation contact region, for a silicon substrate with a bulk resistivity of 0.5-10Ω·cm:

[0021] When the thickness of phosphorus-doped polysilicon is in the range of 0-50nm, the absolute value of the slope of the change in the logarithm of the phosphorus doping concentration versus the depth into the silicon substrate from the phosphorus-doped polysilicon / tunneling silicon oxide interface to the point where the phosphorus doping concentration in the silicon substrate is equal to the intrinsic doping concentration of the silicon substrate is greater than or equal to 13.8μm -1 ;

[0022] When the thickness of phosphorus-doped polysilicon is in the range of 50-200nm, the absolute value of the slope of the change in the logarithm of the phosphorus doping concentration versus the depth into the silicon substrate from the phosphorus-doped polysilicon / tunneling silicon oxide interface to the point where the phosphorus doping concentration in the silicon substrate is equal to the intrinsic doping concentration of the silicon substrate is greater than or equal to 17.3μm -1 ;

[0023] When the thickness of phosphorus-doped polysilicon is in the range of 200-500nm, the absolute value of the slope of the change in the logarithm of the phosphorus doping concentration versus the depth into the silicon substrate from the phosphorus-doped polysilicon / tunneling silicon oxide interface to the point where the phosphorus doping concentration in the silicon substrate is equal to the intrinsic doping concentration of the silicon substrate is greater than or equal to 23.1μm -1 .

[0024] The present invention has the following beneficial effects

[0025] (1) The present invention provides a method for preparing a passivation contact region based on ion implantation technology. The doping of ion implantation is not limited by solid solubility, so a higher doping concentration of boron or phosphorus in the passivation contact region can be achieved. Through rapid thermal treatment, on the basis of achieving good activation of doped boron or phosphorus atoms, the doped boron or phosphorus atoms can be well controlled to enter the silicon substrate less. The lower thermal treatment budget can also significantly reduce the pinholes caused by boron or phosphorus doping in tunneling silicon oxide, significantly reduce the dislocation defects and lattice distortion caused by doped boron atoms to the silicon substrate, and also obtain a longer silicon substrate minority carrier diffusion length.

[0026] This method can obtain a passivation contact region with a near-ideal doping distribution, namely: 1) a higher doping concentration of boron or phosphorus in the doped polysilicon layer and at the doped polysilicon / tunneling silicon oxide interface, and 2) a steep decrease in the doping concentration of boron or phosphorus occurs when entering the silicon substrate from the doped polysilicon / tunneling silicon oxide interface, thereby preventing more boron or phosphorus doping atoms from entering the silicon substrate. Therefore, the prepared passivation contact cell can obtain a better field passivation effect of the passivation contact region, thereby effectively enhancing the extraction and transmission capabilities of majority carriers; can significantly reduce the Auger recombination caused by boron or phosphorus doping to the silicon substrate; can obtain high-quality tunneling silicon oxide interface passivation, thereby more efficiently suppressing the recombination of minority carriers.

[0027] Therefore, the method for preparing the passivation contact region based on ion implantation technology provided by the present invention can obtain high-quality hole passivation contact region and electron passivation contact region, and can achieve better photoelectric conversion efficiency of the passivation contact battery.

[0028] (2) Furthermore, the present invention also provides a passivated contact cell with a localized passivation contact area on the front electrode area of ​​the cell. This structural design can avoid the use of a passivation contact structure on the entire front surface of the cell, thereby solving the drawbacks of high optical parasitic absorption coefficient and high optical loss of doped polysilicon, and further improving the photocurrent and photoelectric conversion efficiency of the cell. Accordingly, the present invention also provides a method based on masked boron-phosphorus ion implantation combined with rapid thermal treatment to prepare such a passivated contact cell with a localized passivation contact area on the front of the cell, which can prepare precise and high-quality local hole or electron passivation contact areas, while obtaining excellent cell conversion efficiency, and also making the cell preparation process simpler.

[0029] (3) The present invention uses rapid heat treatment to perform annealing of ion implanted boron or phosphorus doping in the passivation contact area. The heat treatment time is short, which can improve the battery production capacity and help reduce the battery production cost.

[0030] (4) The passivated contact cell prepared by the ion implantation and rapid thermal treatment method provided by the present invention is suitable for n-type or p-type silicon substrates, can effectively improve the photoelectric conversion efficiency of TOPCon cells and PERC cells, has a simple cell structure, and a simple and practical preparation process, and is suitable for industrial applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 . Schematic diagram of the structure of a passivated contact battery prepared based on the method of the present invention (double-sided structure, with uniform passivated contact areas on both the front and back sides of the battery, Example 2).

[0032] Among them, 1 is n-type or p-type silicon substrate, 2 is tunneling silicon oxide, 3 is phosphorus-doped polysilicon, 4 is boron-doped polysilicon, 5 is silicon nitride on the front of the battery, 6 is silicon nitride on the back of the battery, 7 is the front electrode of the battery, and 8 is the back electrode of the battery. In the above, 2 and 3 form the electron passivation contact area, and 2 and 4 form the hole passivation contact area. Note: The front of the battery can also be boron-doped polysilicon, and accordingly, the back of the battery can also be phosphorus-doped polysilicon.

[0033] Figure 2 .Schematic diagram of the structure of an n-type passivated contact cell prepared based on the method of the present invention in Example 1.

[0034] Among them, 1 is the n-type silicon substrate, 2 is the tunneling silicon oxide, 3 is phosphorus-doped polysilicon, 4 is boron-doped polysilicon, 5 is the silicon nitride on the front of the battery, 6 is the silicon nitride on the back of the battery, 7 is the front electrode of the battery, and 8 is the back electrode of the battery. Above, 2 and 3 form the localized electron passivation contact area on the front of the battery, and 2 and 4 form the uniform hole passivation contact area on the entire back of the battery.

[0035] Figure 3-a. The boron doping distribution curve of the hole passivation contact area prepared by the method of the present invention is simulated using TCADSUPREM (for details on specific boron injection and RTP process parameters, see Example 1-Step 5).

[0036] Figure 3-b . Boron doping distribution curve of the hole passivation contact area prepared by furnace tube boron diffusion method, simulated by TCAD SUPREM (for details of specific boron diffusion process parameters, please see the notes in Example 1-Step 5).

[0037] Figure 4-a . The phosphorus doping distribution curve of the electronic passivation contact area prepared by the method of the present invention is simulated using TCADSUPREM (for details on specific phosphorus injection and RTP process parameters, see Example 1-Step 10).

[0038] Figure 4-b . The phosphorus doping distribution curve of the electronic passivation contact area prepared by the furnace tube phosphorus diffusion method was simulated using TCAD SUPREM (for details on the specific phosphorus diffusion process parameters, please see the notes in Example 1-Step 10).

[0039] Figure 5-a . The phosphorus doping distribution curve of the electronic passivation contact area prepared by the method of the present invention is simulated using TCADSUPREM (for details on specific phosphorus injection and RTP process parameters, see Example 2).

[0040] Figure 5-b . The phosphorus doping distribution curve of the electronic passivation contact area prepared by the furnace tube phosphorus diffusion method was simulated using TCAD SUPREM (for details on the specific phosphorus diffusion process parameters, please see the notes in Example 2). DETAILED DESCRIPTION

[0041] For a better understanding of the present invention, the present invention will be further described below in conjunction with specific embodiments and drawings. Obviously, the embodiments described are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present invention.

[0042] The present invention provides a method for preparing a passivation contact region based on ion implantation technology, which adopts a method of boron or phosphorus ion implantation combined with rapid thermal treatment to prepare a hole passivation contact region or an electron passivation contact region, and specifically comprises the following steps:

[0043] Step 1. Select a silicon substrate. Generally, single crystal silicon is selected, and the substrate doping type can be n-type (doped with phosphorus) or p-type (doped with boron).

[0044] Step 2: The surface of the silicon substrate is polished or a velvet surface with a random pyramid morphology is prepared. The specific preparation method is not limited. For example, a wet chemical etching method using an alkali or acid solution can be used.

[0045] Step 3. Prepare tunneling silicon oxide on the surface of the silicon substrate. The specific preparation method is not limited, and thermal oxidation, chemical vapor deposition, ozone oxidation, wet chemical oxidation, etc. can be used.

[0046] Step 4. Prepare intrinsic polysilicon on the tunneling silicon oxide and complete the full crystallization of the intrinsic polysilicon. The specific preparation method is not limited. Generally, the preparation can be carried out by chemical vapor deposition.

[0047] Typically, it can be prepared by low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD). First, LPCVD or PECVD is used to prepare intrinsic polycrystalline silicon or intrinsic amorphous silicon of the target thickness. Generally, the LPCVD deposition temperature is 580-680°C, and the PECVD deposition temperature is 400-500°C. Then, the temperature is gradually increased to 800-900°C in the deposition chamber of the chemical vapor deposition equipment. During this heating process, the prepared intrinsic polycrystalline silicon can be more fully crystallized; during this heating process, the prepared intrinsic amorphous silicon can be crystallized from amorphous silicon to polycrystalline silicon, and sufficient crystallization is completed during this heating process. The heating rate is generally 5-10°C / minute, and the atmosphere is an inert gas. Since the polysilicon has been fully crystallized during the above-mentioned heating process, after the temperature rises to 800-900°C, the constant temperature time and the cooling rate are not limited; generally, the temperature can be directly cooled at a rate of 5-15°C / minute, and the atmosphere is an inert gas.

[0048] Step 5. Doping the intrinsic polysilicon with boron or phosphorus by ion implantation, and then using rapid thermal processing (RTP) to complete the activation of the boron or phosphorus doping and redistribution in the intrinsic polysilicon. By designing the process parameters of ion implantation and rapid thermal processing in conjunction, a doping distribution curve of boron or phosphorus in the polysilicon layer that meets the target design is achieved.

[0049] Ion implantation of boron or phosphorus in intrinsic polysilicon may be performed by n times (n is greater than or equal to 1) of ion implantation. Generally, in order to more accurately obtain the desired doping distribution curve of boron or phosphorus, the energy and dose of each ion implantation in multiple ion implantations will be different. The specific process parameters of each ion implantation are not limited. Generally, for ion implantation of boron or phosphorus, the energy is 500eV-500keV and the dose is 5·10 14 -5.10 16 cm -2The ion implantation inclination angle can be 0 degrees (parallel to the normal direction of the silicon substrate surface) or a certain inclination angle, typically 0.1-10 degrees. The temperature range of the silicon substrate during the ion implantation process is generally 0-100°C, typically, the room temperature of 25°C is selected.

[0050] The specific method of rapid thermal processing is not limited, including spike annealing, halogen lamp annealing, laser annealing, or flash annealing. For ion implantation of boron doping, the peak temperature of rapid thermal processing is 900-1100°C, the annealing time at the peak temperature is 5-150 seconds, the heating rate is 100-250°C / second, the cooling rate is 150-200°C / minute, and the atmosphere is an inert gas such as nitrogen. For ion implantation of phosphorus doping, the peak temperature of rapid thermal processing is 800-1000°C, the annealing time at the peak temperature is 5-150 seconds, the heating rate is 100-250°C / second, the cooling rate is 150-200°C / minute, and the atmosphere is an inert gas such as nitrogen.

[0051] It can be understood that in the case where a localized hole or electron passivation contact area on the front of the battery needs to be prepared, the doping of boron or phosphorus can be carried out by masked ion implantation, that is, by setting a mask in the ion implantation process to achieve localized ion implantation of the silicon substrate. Among them, for the area with the mask, the ion implantation is blocked by the mask, so that the silicon substrate cannot be doped; for the area without the mask, the silicon substrate can be doped by ion implantation. The process parameters for boron and phosphorus ion implantation and rapid thermal treatment are selected as above. The ion implantation mask can be made of materials such as graphite or ceramics.

[0052] It should also be noted that in the present invention, expressions such as "A1-A2", "A1 to A2" and other related numerical ranges all include the two endpoint values ​​of A1 and A2.

[0053] Furthermore, the present invention can also apply the above-mentioned method for preparing the passivation contact region to prepare the hole passivation contact region or the electron passivation contact region of the passivation contact battery.

[0054] Furthermore, the present invention also provides a passivated contact battery. The passivated contact battery can be a double-sided structure or an IBC structure. The hole passivation contact region or the electron passivation contact region is prepared by the above method, and the preparation of other structural parts of the battery can be achieved by conventional technical methods.

[0055] The substrate material used in the passivation contact cell is silicon material (referred to as silicon substrate or silicon wafer). Generally, single crystal silicon is selected, and the substrate doping type can be n-type (phosphorus-doped) or p-type (boron-doped).

[0056] The passivation contact cell has at least one of a hole passivation contact region or an electron passivation contact region. The hole passivation contact region is composed of tunneling silicon oxide and boron-doped polysilicon (acceptor doping), and the electron passivation contact region is composed of tunneling silicon oxide and phosphorus-doped polysilicon (donor doping). In the present application, the hole passivation contact region and the electron passivation contact region are collectively referred to as the passivation contact region, and the boron-doped polysilicon and the phosphorus-doped polysilicon are collectively referred to as doped polysilicon.

[0057] The passivation contact area can be uniform over the entire surface ( Figure 1 ), or it can be localized (referred to as local passivation contact area). Figure 2 As shown, the local passivation contact area is generally arranged directly below the electrode area on the front (or back) side of the battery, the electrode area unit and the local passivation contact area unit have the same shape and geometric center, and the area (i.e., size) of the electrode area unit is less than or equal to the area (i.e., size) of the local passivation contact area unit.

[0058] The thickness of the tunneling silicon oxide is 1.2-1.6 nm, and the refractive index is 1.45-1.5, but is not limited thereto.

[0059] For the uniform passivation contact area on the entire front of the battery, the thickness of the doped polysilicon is 5-100nm. For the local passivation contact area directly below the electrode area on the front of the battery, the thickness of the doped polysilicon is 5-500nm. For the passivation contact area on the back of the battery, the thickness of the doped polysilicon is 5-500nm.

[0060] In the hole passivation contact region, the boron doping concentration on the outer surface of the boron-doped polysilicon (the side away from the silicon substrate) is not less than 1.10 20 cm -3 , the typical range is 1·10 20 -5.10 20 cm -3 The boron doping concentration at the boron-doped polysilicon / tunneling silicon oxide interface is not less than 5·10 19 cm -3 , the typical range is 5·10 19 -5.10 20 cm -3 . Preferably, the boron doping concentration on the outer surface of the boron-doped polysilicon is slightly higher than the boron doping concentration at the interface of the boron-doped polysilicon / tunneling silicon oxide, and this concentration difference is as small as possible. Typically, the difference between the boron doping concentration on the outer surface of the boron-doped polysilicon and the boron doping concentration at the interface of the boron-doped polysilicon / tunneling silicon oxide is less than 10% of the boron doping concentration on the outer surface of the boron-doped polysilicon.

[0061] like Figure 3-a As shown, at the boron atomic concentration (1 / cm 3) as the ordinate and depth (μm) as the abscissa, the boron doping concentration decreases sharply as it goes deeper into the silicon substrate from the boron-doped polysilicon / tunneling silicon oxide interface, and quickly drops below the intrinsic doping concentration of the silicon substrate. For commonly used n-type or p-type silicon substrates with a bulk resistivity of 0.5 to 10Ω·cm, the specific slope (in μm -1 ) range is as follows:

[0062] (1) For boron-doped polysilicon with a thickness in the range of 0-50 nm, the absolute value of the slope of the logarithm of the change in the boron doping concentration versus the depth into the silicon substrate from the boron-doped polysilicon / tunneling silicon oxide interface to the point where the boron doping concentration in the silicon substrate is equal to the intrinsic doping concentration of the silicon substrate (as can be seen from the figure, the slope is a negative number, the same below) is greater than or equal to 12.6 μm -1 Typically, the absolute value of the slope is greater than or equal to 34.5 μm -1 .

[0063] (2) For boron-doped polysilicon with a thickness in the range of 50-200 nm, the absolute value of the slope of the logarithm of the change in the boron doping concentration versus the depth into the silicon substrate from the boron-doped polysilicon / tunneling silicon oxide interface to the point where the boron doping concentration in the silicon substrate is equal to the intrinsic doping concentration of the silicon substrate is greater than or equal to 15.8 μm -1 Typically, the absolute value of the slope is greater than or equal to 43.1 μm -1 .

[0064] (3) For boron-doped polysilicon with a thickness in the range of 200-500 nm, the absolute value of the slope of the logarithm of the change in the boron doping concentration versus the depth into the silicon substrate from the boron-doped polysilicon / tunneling silicon oxide interface to the point where the boron doping concentration in the silicon substrate is equal to the intrinsic doping concentration of the silicon substrate is greater than or equal to 21.1 μm -1 Typically, the absolute value of the slope is greater than or equal to 57.5 μm -1 .

[0065] In the electronic passivation contact region, the phosphorus doping concentration on the outer surface of the phosphorus-doped polysilicon (the side away from the silicon substrate) is not less than 1.10 20 cm -3 , the typical range is 1·10 20 -1·10 21 cm -3 The phosphorus doping concentration at the phosphorus-doped polysilicon / tunneling silicon oxide interface is not less than 1·10 20 cm -3 , the typical range is 1·10 20 -5.10 20 cm -3. Preferably, the phosphorus doping concentration on the outer surface of the multi-phosphorus-doped crystalline silicon is slightly higher than the phosphorus doping concentration at the phosphorus-doped polysilicon / tunneling silicon oxide interface, and this concentration difference is as small as possible. Typically, the difference between the phosphorus doping concentration on the outer surface of the phosphorus-doped polysilicon and the phosphorus doping concentration at the phosphorus-doped polysilicon / tunneling silicon oxide interface is less than 50% of the phosphorus doping concentration on the outer surface of the phosphorus-doped polysilicon.

[0066] like Figure 4-a As shown in Figure 2, at the phosphorus atomic concentration (1 / cm 3 ) as the ordinate and depth (μm) as the abscissa, the phosphorus doping concentration decreases sharply as it goes deeper into the silicon substrate from the phosphorus-doped polysilicon / tunneling silicon oxide interface, and quickly drops below the intrinsic doping concentration of the silicon substrate. For commonly used n-type or p-type silicon substrates with a bulk resistivity of 0.5 to 10Ω·cm, the specific slope (in μm -1 ) range is as follows:

[0067] (1) For phosphorus-doped polysilicon with a thickness in the range of 0-50 nm, the absolute value of the slope of the logarithm of the change in phosphorus doping concentration versus the depth into the silicon substrate from the phosphorus-doped polysilicon / tunneling silicon oxide interface to the point where the phosphorus doping concentration in the silicon substrate is equal to the intrinsic doping concentration of the silicon substrate (as can be seen from the figure, the slope is a negative number, the same below) is greater than or equal to 13.8 μm -1 Typically, the absolute value of the slope is greater than or equal to 53.8 μm -1 .

[0068] (2) For phosphorus-doped polysilicon with a thickness in the range of 50-200 nm, the absolute value of the slope of the change in the logarithm of the phosphorus doping concentration versus the depth into the silicon substrate from the phosphorus-doped polysilicon / tunneling silicon oxide interface to the point where the phosphorus doping concentration in the silicon substrate is equal to the intrinsic doping concentration of the silicon substrate is greater than or equal to 17.3 μm -1 Typically, the absolute value of the slope is greater than or equal to 66.3 μm -1 .

[0069] (3) For phosphorus-doped polysilicon with a thickness in the range of 200-500 nm, the absolute value of the slope of the change in the logarithm of the phosphorus doping concentration versus the depth into the silicon substrate from the phosphorus-doped polysilicon / tunneling silicon oxide interface to the point where the phosphorus doping concentration in the silicon substrate is equal to the intrinsic doping concentration of the silicon substrate is greater than or equal to 23.1 μm -1 Typically, the absolute value of the slope is greater than or equal to 86.1 μm -1 .

[0070] The front and back of the cell both have a layer of silicon nitride as an auxiliary passivation layer. The silicon nitride on the front of the cell also plays an anti-reflection role. The silicon nitride on the front of the cell has a thickness of 60-80nm and a refractive index of 1.9-2.1. The silicon nitride on the back of the cell has a thickness of 60-200nm and a refractive index of 1.9-2.2.

[0071] The hole passivation contact area or the electron passivation contact area of ​​the passivation contact battery has a corresponding metallized electrode. The material of the electrode is not limited, and generally, silver is used.

[0072] The technical solution of the present invention is further explained below in conjunction with specific embodiments.

[0073] Example 1 The method based on boron-phosphorus ion implantation combined with rapid thermal processing described in the present invention is used to prepare an n-type passivated contact battery with a local electronic passivation contact area on the front side of the battery. Figure 2 As shown, the battery has a double-sided structure, specifically including: an n-type silicon substrate 1, a tunneling silicon oxide 2, phosphorus-doped polysilicon 3, boron-doped polysilicon 4, silicon nitride 5 on the front side of the battery, silicon nitride 6 on the back side of the battery, a front electrode 7, and a back electrode 8.

[0074] A local electronic passivation contact area is used below the positive electrode area of ​​the battery. Both the positive electrode unit of the battery and the local electronic passivation contact area unit use a grid line pattern. The line width of the positive electrode unit of the battery is 20μm, and the spacing between two adjacent grid line electrode units (the distance between the axis lines) is 1000μm. The line width of the local electronic passivation contact area unit is 100μm, and the spacing between two adjacent grid line units is 1000μm. The other areas on the front of the battery are n-type silicon substrates. The back of the battery uses a uniform hole passivation contact area on the entire surface.

[0075] The specific battery preparation method is as follows:

[0076] Step 1. Select a 182mm*182mm n-type single crystal silicon wafer with a body resistivity of 1.0Ω·cm.

[0077] Step 2. Use sodium hydroxide solution to polish and etch the n-type silicon wafer to remove the damaged layer on the surface of the silicon wafer. One side is defined as the front side of the battery, and phosphorus doping is performed later. In the subsequent battery preparation, the front side of the battery will be textured in an appropriate step. Correspondingly, the other side is defined as the back side of the battery, and boron doping is performed later.

[0078] Step 3. Prepare tunneling silicon oxide on the back of the silicon wafer using a thermal oxidation method. The thickness is 1.3 nm and the refractive index is 1.46.

[0079] Step 4. Use LPCVD to prepare intrinsic polysilicon on the back of the cell with a thickness of 250nm. The deposition pressure is 13.33Pa, the temperature is 630℃, and the process gas is SiH 4 , the protective gas is argon. After the intrinsic polysilicon deposition is completed, the pressure of the deposition chamber is restored to 1 atmosphere, and then the temperature is raised to 850℃, the heating rate is 7℃ / minute, so that the polysilicon is more fully crystallized, and then the temperature is directly lowered, the cooling rate is 7℃ / minute, and the nitrogen atmosphere. In this step, very little intrinsic polysilicon is plated around the front of the battery, and it is mainly produced in a very narrow range at the edge of the front. This effect can be eliminated later by wet chemical etching.

[0080] Step 5. Boron doping is performed on the intrinsic polysilicon layer by ion implantation of boron and rapid thermal processing. The boron implantation energy is 20 keV and the dose is 6·10 15 cm -2 , the injection angle is 7 degrees, and the temperature of the silicon wafer substrate is room temperature 25°C. Peak RTP annealing is adopted, the peak temperature is 1080°C, the annealing time at the peak temperature is 20 seconds, the heating rate is 220°C / second, the cooling rate is 200°C / minute, and the nitrogen atmosphere is used.

[0081] like Figure 3-a As shown in the figure, the boron doping distribution curve of the hole passivation contact region has the following characteristics: the boron doping concentration (activated, i.e., net doping in the figure, the same below) on the outermost surface of the 250nm polysilicon layer is 1.8·10 20 cm -3 , the boron doping concentration at the polysilicon / tunneling silicon oxide interface is 1.8·10 20 cm -3 As the depth from the polysilicon / tunneling silicon oxide interface to the silicon substrate deepens, the boron doping concentration decreases sharply and quickly drops below the intrinsic doping concentration of n-type silicon; specifically, from the boron-doped polysilicon / tunneling silicon oxide interface to the point where the boron doping concentration in the silicon substrate is equal to the intrinsic doping concentration of n-type silicon, the absolute value of the slope of the logarithm of the change in the boron doping concentration versus the depth into the silicon substrate is 70.2μm. -1 .

[0082] Note: For comparison, Figure 3-b The following is a graph showing the deposition of 250nm amorphous silicon by LPCVD followed by furnace tube boron tribromide (BBr 3) boron diffusion prepared by boron diffusion. Boron diffusion uses commonly used process parameters and takes into account the highest possible boron doping concentration in polysilicon and the lowest possible boron doping concentration in the silicon substrate. Specifically, borosilicate glass is deposited at 950°C for 60 minutes and then redistributed at 1000°C for 30 minutes. During the heat treatment of boron diffusion, the amorphous silicon deposited by LPCVD also completes the crystallization from amorphous silicon to polysilicon and achieves full crystallization.

[0083] like Figure 3-b As shown in the figure, the boron doping distribution curve of the hole passivation contact region has the following characteristics: the boron doping concentration on the outermost surface of the 250nm polysilicon layer is 6.4·10 19 cm -3 , the boron doping concentration at the polysilicon / tunneling silicon oxide interface is 6.4·10 19 cm -3 In the process of going deeper into the silicon substrate from the polysilicon / tunneling silicon oxide interface, the boron doping concentration does not decrease sharply, but gradually decreases to below the intrinsic doping concentration of n-type silicon; specifically, from the boron-doped polysilicon / tunneling silicon oxide interface to the point where the boron doping concentration in the silicon substrate is equal to the intrinsic doping concentration of n-type silicon, the absolute value of the slope of the change in the logarithm of the boron doping concentration versus the depth into the silicon substrate is 11.7μm -1 .

[0084] pass Figure 3-a and 3-b A comparative analysis shows that, compared with the furnace tube boron diffusion method, the hole passivation contact area prepared by the method combining ion implantation and rapid thermal treatment of the present invention has a higher boron doping concentration on the polysilicon surface and the polysilicon / tunneling silicon oxide interface, and the boron doping entering the n-type silicon substrate is also significantly reduced. For furnace tube boron diffusion, if the boron doping concentration in polysilicon is increased by adjusting the boron diffusion process parameters (deposition temperature and time, redistribution temperature and time, gas flow rate, etc.), it will inevitably cause more boron doping to enter the silicon substrate. Furthermore, since the doping concentration of boron diffusion is more dependent on the solid solubility limit of boron in polysilicon at a certain temperature, it is not easy to obtain a boron doping concentration higher than 1·10 on the polysilicon surface and in the polysilicon layer even if a long-term high-temperature heat treatment above 1000°C is used. 20 cm -3 The boron doping concentration is reduced, thereby reducing the field passivation effect of the hole passivation contact area prepared by boron diffusion. Therefore, the method of the present invention is used to prepare the hole passivation contact area, which can effectively enhance the field passivation effect of the hole passivation contact area and significantly reduce the Auger recombination caused by boron doping to the silicon substrate, thereby effectively improving the performance of the hole passivation contact area.

[0085] Step 6. Use the chain In-line APCVD method to prepare a layer of silicon oxide on the back of the battery, with a thickness of 40nm and a refractive index of 1.46. This layer of silicon oxide is used as a protective layer on the back of the battery, which can effectively protect and prevent the impact on the back of the battery during subsequent battery preparation.

[0086] Step 7. First, a mixed solution of nitric acid and hydrofluoric acid is used in combination with a single-sided water-floating wet etching method to etch away the small amount of boron-doped polysilicon that is doped around the edge of the front side of the battery. In the mixed solution of nitric acid and hydrofluoric acid, the mass concentration of nitric acid is 40%, the mass concentration of hydrofluoric acid is 4%, the solution temperature is 7°C, and the etching time is 2-3 minutes. Then, a hydrofluoric acid solution is used in combination with a single-sided water-floating wet etching method to etch away the silicon oxide that is plated around the front side of the battery. The hydrofluoric acid concentration is 1%, and the etching time is 30-60 seconds. In this step of wet chemical etching, the APCVD SiO 2 It provides good protection for the back of the battery.

[0087] Step 8. Prepare tunneling silicon oxide on the front side of the silicon wafer using a thermal oxidation method. The thickness is 1.3 nm and the refractive index is 1.46.

[0088] Step 9. Use LPCVD method to prepare intrinsic polysilicon on the front of the battery with a thickness of 250nm. The deposition pressure is 13.33Pa, the temperature is 630℃, and the process gas is SiH 4 , the protective gas is argon. After the intrinsic polysilicon deposition is completed, the pressure in the deposition chamber is restored to 1 atmosphere, and then the temperature is raised to 830°C at a rate of 7°C / min to make the polysilicon more fully crystallized, and then the temperature is directly lowered at a rate of 7°C / min in a nitrogen atmosphere.

[0089] Step 10. Use masked phosphorus ion implantation and rapid thermal treatment to locally dope the intrinsic polysilicon in the local electronic passivation contact design area on the front of the battery. The phosphorus implantation energy is 30keV and the dose is 7.10 15 cm -2 , the injection angle is 7 degrees, and the silicon wafer substrate temperature is room temperature 25°C. The phosphorus implantation process mask pattern is consistent with the design pattern of the front local electron passivation contact area given above. Peak RTP annealing is adopted, the peak temperature is 975°C, the annealing time at the peak temperature is 30 seconds, the heating rate is 220°C / second, the cooling rate is 200°C / minute, and the nitrogen atmosphere is used.

[0090] like Figure 4-a As shown in the figure, the phosphorus doping distribution curve of the electronic passivation contact region has the following characteristics: the phosphorus doping concentration on the outermost surface of the 250nm polysilicon layer is 1.7·10 20 cm -3, the phosphorus doping concentration at the polysilicon / tunneling silicon oxide interface is 1.7·10 20 cm -3 . As the depth from the polysilicon / tunneling silicon oxide interface to the silicon substrate deepens, the phosphorus doping concentration decreases sharply and quickly drops below the intrinsic doping concentration of n-type silicon; specifically, from the phosphorus-doped polysilicon / tunneling silicon oxide interface to the point where the phosphorus doping concentration in the silicon substrate is equal to the intrinsic doping concentration of n-type silicon, the absolute value of the slope of the change in the logarithm of the phosphorus doping concentration versus the depth into the silicon substrate is 226.8μm -1 .

[0091] Note: For comparison, Figure 4-b The following is a graph showing the deposition of 250nm amorphous silicon by LPCVD followed by the use of furnace tube phosphorus oxychloride (POCl 3 ) prepared by phosphorus diffusion. Phosphorus diffusion uses common process parameters, and takes into account the need to obtain a sufficiently high phosphorus doping concentration in polysilicon and a minimum phosphorus doping concentration in the silicon substrate. Specifically, phosphorus silicon glass is deposited at 850°C for 60 minutes, and then redistributed at 885°C for 35 minutes. During the heat treatment of phosphorus diffusion, the amorphous silicon deposited by LPCVD also completes the crystallization from amorphous silicon to polysilicon and achieves full crystallization.

[0092] like Figure 4-b As shown in the figure, the phosphorus doping distribution curve of the electronic passivation contact region has the following characteristics: the phosphorus doping concentration on the outermost surface of the 250nm polysilicon layer is 1.3·10 20 cm -3 , the phosphorus doping concentration at the polysilicon / tunneling silicon oxide interface is 1.3·10 20 cm -3 In the process of going deeper into the silicon substrate from the polysilicon / tunneling silicon oxide interface, the phosphorus doping concentration does not decrease sharply, but gradually decreases to below the intrinsic doping concentration of n-type silicon; specifically, from the phosphorus-doped polysilicon / tunneling silicon oxide interface to the point where the phosphorus doping concentration in the silicon substrate is equal to the intrinsic doping concentration of n-type silicon, the absolute value of the slope of the change in the logarithm of the phosphorus doping concentration versus the depth into the silicon substrate is 58.9μm -1 .

[0093] pass Figure 4-a and 4-bComparative analysis shows that, compared with the furnace tube phosphorus diffusion method, the electronic passivation contact area prepared by the method combining ion implantation and rapid thermal treatment of the present invention has a higher phosphorus doping concentration on the polysilicon surface and the polysilicon / tunneling silicon oxide interface, and the phosphorus doping entering the n-type silicon substrate is also significantly reduced. For furnace tube phosphorus diffusion, if the phosphorus doping concentration in polysilicon is increased by adjusting the phosphorus diffusion process parameters (deposition temperature and time, redistribution temperature and time, gas flow rate, etc.), it is inevitable that phosphorus doping will enter the silicon substrate more. Therefore, the electronic passivation contact area prepared by the method of the present invention can effectively enhance the field passivation effect of the electronic passivation contact area, and also effectively reduce the Auger recombination brought by phosphorus doping to the silicon substrate, so that the performance of the electronic passivation contact area can be effectively improved.

[0094] Step 11. Prepare a layer of silicon nitride on the front of the battery by PECVD method, with a thickness of 70nm and a refractive index of 2.0. On the one hand, this layer of silicon nitride is used as a protective layer on the front of the battery, which can effectively protect and prevent the impact on the front of the battery in the subsequent battery preparation. On the other hand, this layer of silicon nitride also serves as a protective layer for the local electronic passivation contact area on the front of the battery during the process of chemical etching to form the local electronic passivation contact area in steps 13 and 14.

[0095] Step 12. Use a mixed solution of nitric acid and hydrofluoric acid combined with a single-sided water-floating wet etching method to etch away a small amount of phosphorus-doped polysilicon that is doped around the edge of the back of the battery. In the mixed solution of nitric acid and hydrofluoric acid, the mass concentration of nitric acid is 40%, the mass concentration of hydrofluoric acid is 4%, the solution temperature is 7°C, and the etching time is 1-2 minutes. In this step, the silicon nitride prepared in step 11 plays a good protective role on the front of the battery. Through this step of chemical etching, electrical insulation isolation is also completed between the front and back of the battery.

[0096] Step 13. Use screen printing chemical etching slurry to etch away all the silicon nitride on the front side of the battery except for the local electronic passivation contact area. BES etching slurry, which contains a certain concentration of phosphate, can etch silicon nitride. The pattern of the screen printing screen is consistent with the design pattern of the local electronic passivation contact area on the front of the battery given above. After screen printing the slurry, it is heated to 350-400°C on a heating plate and left to stand for 1-2 minutes. The silicon nitride in the area where the chemical slurry is printed is etched away. Then, a 50°C hydrochloric acid solution combined with ultrasonic cleaning is used to clean the residual Merck slurry on the surface of the silicon wafer.

[0097] Step 14. First, use a single-sided water-floating KOH solution polishing and etching method to etch away the intrinsic polysilicon and tunneling silicon oxide in the non-local electronic passivation contact area on the front of the battery. The mass concentration of the KOH solution is 5%, the temperature is 75-80°C, and the etching time is 300-360 seconds. Next, use a single-sided water-floating KOH solution etching method to texturize the non-local electronic passivation contact area on the front of the battery, so that the area forms a random pyramid-shaped velvet surface. The mass concentration of the KOH solution is 2%, the temperature is 70°C, and the etching time is 5-6 minutes. In the above alkaline solution etching, the silicon nitride directly above the local electronic passivation contact area on the front of the battery plays a good protective role in this local electronic passivation contact area.

[0098] Then, hydrofluoric acid solution was used to passivate the silicon nitride in the local electronic contact area on the front of the battery and the APCVD SiO2 on the back. 2 The concentration of hydrofluoric acid is 5%, and the etching and cleaning time is 10-15 minutes.

[0099] Step 15. A layer of silicon nitride is prepared on the front of the cell by PECVD as a passivation anti-reflection film with a thickness of 75nm and a refractive index of 2.0. This layer of silicon nitride also serves as a buffer barrier layer for the metallization of the screen-printed silver paste in the subsequent step 17 to ensure that the silver paste can be confined within the phosphorus-doped polysilicon layer as much as possible after rapid thermal treatment and sintering, and as little as possible enter the silicon substrate by diffusing through the phosphorus-doped polysilicon and tunneling silicon oxide.

[0100] Step 16. Prepare a layer of silicon nitride on the back of the battery by PECVD method, with a thickness of 80nm and a refractive index of 2.0. This layer of silicon nitride serves as an auxiliary passivation layer on the back of the battery to enhance the working stability of the battery in extreme applications (especially high humidity and high temperature). In addition, this layer of silicon nitride also serves as a buffer barrier layer for screen printing metallization in the subsequent step 17 to ensure that the silver paste can be confined as much as possible within the boron-doped polysilicon layer after rapid thermal treatment and sintering, and as little as possible overdiffusion through the boron-doped polysilicon and tunneling silicon oxide into the silicon substrate.

[0101] Step 17. Metallize the front and back of the battery by screen printing silver paste and rapid heat treatment sintering. Among them, the screen printing on the front of the battery needs to be aligned: that is, the electrode area on the front of the battery and the local electronic passivation contact area are aligned. The grid line width of the silver electrode on the front of the battery is 20μm and the spacing is 1000μm. The silver electrode on the back of the battery adopts a grid line pattern with a line width of 35μm and a spacing of 1000μm. The actual peak temperature of sintering is 720-750℃, the time at the peak temperature is 2-4 seconds, and the compressed air atmosphere.

[0102] At this point, the preparation of the n-type double-sided passivated contact cell is completed.

[0103] Example 2 The method based on boron-phosphorus ion implantation combined with rapid thermal processing described in the present invention is used to prepare a p-type passivated contact battery with uniform passivation contact areas on the front and back sides of the battery.

[0104] like Figure 1 As shown, the battery has a double-sided structure, specifically including: a p-type silicon substrate 1 (bulk resistivity is 1.0Ω·cm), a tunneling silicon oxide 2, phosphorus-doped polysilicon 3, boron-doped polysilicon 4, silicon nitride 5 on the front side of the battery, silicon nitride 6 on the back side of the battery, a front electrode 7 of the battery, and a back electrode 8 of the battery.

[0105] In order to reduce the negative effect of the high optical parasitic absorption coefficient of the doped polysilicon on the front of the battery, the front of the battery uses 10nm phosphorus-doped polysilicon and 1.5nm tunneling silicon oxide to form an electron passivation contact area. The hole passivation contact area on the back of the battery is the same as in Example 1, using 250nm boron-doped polysilicon and 1.3nm tunneling silicon oxide. Other battery parameters are also the same as in Example 1.

[0106] In the preparation of the battery, phosphorus ion implantation combined with rapid thermal treatment is used to prepare a uniform electronic passivation contact area on the entire front surface of the battery. The phosphorus implantation energy is 1 keV and the dose is 5·10 15 cm -2 , the implantation angle is 7 degrees, and the silicon wafer substrate temperature is room temperature 25°C. Peak RTP annealing is adopted, the peak temperature is 925°C, the annealing time at the peak temperature is 20 seconds, the heating rate is 220°C / second, the cooling rate is 200°C / minute, and the nitrogen atmosphere is used.

[0107] like Figure 5-a As shown in the figure, the phosphorus doping distribution curve of the electron passivation contact region has the following characteristics: the phosphorus doping concentration on the outermost surface of the 10 nm polysilicon layer is 1.8·10 20 cm -3 , the phosphorus doping concentration at the polysilicon / tunneling silicon oxide interface is 1·10 20 cm -3 As the depth from the polysilicon / tunneling silicon oxide interface to the silicon substrate increases, the phosphorus doping concentration decreases sharply and quickly drops below the intrinsic doping concentration of p-type silicon. Specifically, from the phosphorus-doped polysilicon / tunneling silicon oxide interface to the point where the phosphorus doping concentration in the silicon substrate is equal to the intrinsic doping concentration of p-type silicon, the absolute value of the slope of the change in the logarithm of the phosphorus doping concentration versus the depth into the silicon substrate is 191.2μm. -1 .

[0108] Note: For comparison, Figure 5-b The results show that after LPCVD deposition of 10nm amorphous silicon, phosphorus oxychloride (POCl 3) prepared by phosphorus diffusion. Phosphorus diffusion uses common process parameters, and takes into account the need to obtain a sufficiently high phosphorus doping concentration in polysilicon and a minimum phosphorus doping concentration in the silicon substrate. Specifically, phosphorus silicon glass is deposited at 880°C for 45 minutes, and then redistributed at 880°C for 15 minutes. During the heat treatment of phosphorus diffusion, the amorphous silicon deposited by LPCVD also completes the crystallization from amorphous silicon to polysilicon and achieves full crystallization.

[0109] like Figure 5-b As shown in the figure, the phosphorus doping distribution curve of the electron passivation contact region has the following characteristics: the phosphorus doping concentration on the outermost surface of the 10 nm polysilicon layer is 1.2·10 20 cm -3 , the phosphorus doping concentration at the polysilicon / tunneling silicon oxide interface is 7.5·10 19 cm -3 In the process of going deeper into the silicon substrate from the polysilicon / tunneling silicon oxide interface, the phosphorus doping concentration does not decrease sharply, but gradually decreases to below the intrinsic doping concentration of p-type silicon; specifically, from the phosphorus-doped polysilicon / tunneling silicon oxide interface to the point where the phosphorus doping concentration in the silicon substrate is equal to the intrinsic doping concentration of p-type silicon, the absolute value of the slope of the change in the logarithm of the phosphorus doping concentration versus the depth into the silicon substrate is 33.6μm -1 .

[0110] pass Figure 5-a and 5-b Comparative analysis shows that due to the high optical parasitic absorption coefficient of the doped polysilicon on the front of the battery, in order to reduce this negative effect, the thickness of the phosphorus-doped polysilicon on the front of the battery should be as thin as possible. In this case, for the preparation of the electronic passivation contact area on the front of the battery, the method of combining ion implantation and rapid thermal treatment of the present invention has more obvious advantages than the furnace tube phosphorus diffusion method, which is specifically reflected in two aspects:

[0111] 1) The electronic passivation contact area prepared by the method of the present invention has a higher phosphorus doping concentration on the polysilicon surface and the polysilicon / tunneling silicon oxide interface, and the phosphorus doping entering the n-type silicon substrate is also significantly reduced. For furnace tube phosphorus diffusion, if the phosphorus doping concentration in polysilicon is increased by adjusting the phosphorus diffusion process parameters, it is inevitable that more phosphorus doping will enter the silicon substrate. In the case of thin phosphorus-doped polysilicon on the front side of the battery, Auger recombination will be more significant. Therefore, the method of the present invention can more effectively enhance the field passivation effect of the electronic passivation contact area, and can also more significantly reduce the Auger recombination caused by phosphorus doping to the silicon substrate, so that the performance of the electronic passivation contact area can be more effectively improved.

[0112] 2) The electronic passivation contact area on the front side of the battery is prepared by the method of the present invention, and the window for adjusting the process parameters is wider.

[0113] The other battery preparation steps of this embodiment are similar to those in Embodiment 1 and will not be described in detail.

[0114] Finally, it should be noted that although the embodiments of the present invention are described above in conjunction with the accompanying drawings, the present invention is not limited to the above-mentioned specific embodiments and application fields. The above-mentioned specific embodiments are merely illustrative and instructive, and are used to help understand the method of the present invention and its core idea, but are not restrictive. Under the guidance of this specification, ordinary technicians in this field can also make many forms of changes, improvements and equivalent implementations in the specific implementation methods and application scopes without departing from the scope of protection of the principles of the present invention and the claims, which should also be regarded as the protection scope of the present invention.

Claims

1. A method for preparing a passivation contact region based on ion implantation, characterized in that: include: providing a silicon substrate; Preparing tunneling silicon oxide on the surface of the silicon substrate; Preparing intrinsic polysilicon or intrinsic amorphous silicon on the tunneling silicon oxide, and then raising the ambient temperature of the intrinsic polysilicon or the intrinsic amorphous silicon to 800-900° C. to fully crystallize the intrinsic polysilicon, or first crystallizing the intrinsic amorphous silicon into intrinsic polysilicon and then fully crystallizing the intrinsic amorphous silicon; Doping the fully crystallized intrinsic polysilicon by ion implantation of boron or phosphorus; The activation of boron or phosphorus doping and its redistribution within the intrinsic polysilicon are accomplished by rapid thermal processing.

2. The method according to claim 1, characterized in that Intrinsic polysilicon or intrinsic amorphous silicon is prepared on the tunneling silicon oxide, and then the ambient temperature of the intrinsic polysilicon or intrinsic amorphous silicon is increased to 800-900°C, specifically comprising: preparing intrinsic polysilicon or intrinsic amorphous silicon on the tunneling silicon oxide by chemical vapor deposition; when the chemical vapor deposition is LPCVD, the deposition temperature is 580-680°C; when the chemical vapor deposition is PECVD, the deposition temperature is 400-500°C; raising the temperature in the deposition chamber of the chemical vapor deposition equipment to 800-900°C; the heating rate is 5-10°C / minute, and the atmosphere is an inert gas.

3. The method according to claim 1, characterized in that The number of ion implantations is greater than or equal to one; if greater than one, the energy and dose of each ion implantation are different; the energy of the ion implantation is 500eV-500keV, and the dose is 5·10 14 -5.10 16 cm -2 ; The ion implantation inclination angle is 0 degree or 0.1-10 degrees; The temperature of the silicon substrate during the ion implantation process is 0-100°C.

4. The method according to claim 1, characterized in that For ion implantation boron doping, the peak temperature of the rapid thermal treatment is 900-1100° C., the annealing time at the peak temperature is 5-150 seconds, the heating rate is 100-250° C. / second, the cooling rate is 150-200° C. / minute, and the atmosphere is an inert gas; For ion implantation phosphorus doping, the peak temperature of the rapid thermal treatment is 800-1000°C, the annealing time at the peak temperature is 5-150 seconds, the heating rate is 100-250°C / second, the cooling rate is 150-200°C / minute, and the atmosphere is an inert gas.

5. The method according to any one of claims 1 to 4, characterized in that: When the passivation contact region is a localized hole or electron passivation contact region, a masked ion implantation method is used to perform localized boron or phosphorus doping on the fully crystallized intrinsic polysilicon.

6. A method for preparing a passivated contact battery, characterized in that: The passivation contact region of the passivation contact cell is prepared by the method according to any one of claims 1 to 5.

7. A passivated contact battery, characterized in that: The passivation contact region comprises a hole passivation contact region and / or an electron passivation contact region; the passivation contact region is prepared by the method for preparing a passivation contact region based on ion implantation as claimed in any one of claims 1 to 5.

8. The passivation contact region according to claim 7, characterized in that: When the passivation contact region is a hole passivation contact region, the boron doping concentration on the outer surface of the boron-doped polysilicon is not less than 1.10 20 cm -3 , the boron doping concentration at the boron-doped polysilicon / tunneling silicon oxide interface is not less than 5·10 19 cm -3 , and the difference between the boron doping concentration on the outer surface of the boron-doped polysilicon and the boron doping concentration at the interface of the boron-doped polysilicon / tunneling silicon oxide is less than 10% of the boron doping concentration on the outer surface of the boron-doped polysilicon; When the passivation contact region is an electronic passivation contact region, the phosphorus doping concentration on the outer surface of the phosphorus-doped polysilicon is not less than 1.10 20 cm -3 , the phosphorus doping concentration at the phosphorus-doped polysilicon / tunneling silicon oxide interface is not less than 1·10 20 cm -3 , and the difference between the phosphorus doping concentration on the outer surface of the phosphorus-doped polysilicon and the phosphorus doping concentration at the phosphorus-doped polysilicon / tunneling silicon oxide interface is less than 50% of the phosphorus doping concentration on the outer surface of the phosphorus-doped polysilicon.

9. The passivation contact region according to claim 8, characterized in that: When the passivation contact region is a hole passivation contact region, for a silicon substrate with a bulk resistivity of 0.5-10Ω·cm: When the thickness of the boron-doped polysilicon is in the range of 0-50nm, the absolute value of the slope of the change in the logarithm of the boron doping concentration versus the depth into the silicon substrate from the boron-doped polysilicon / tunneling silicon oxide interface to the point where the boron doping concentration in the silicon substrate is equal to the intrinsic doping concentration of the silicon substrate is greater than or equal to 12.6μm -1 ; When the thickness of the boron-doped polysilicon is in the range of 50-200nm, the absolute value of the slope of the change in the logarithm of the boron doping concentration versus the depth into the silicon substrate from the boron-doped polysilicon / tunneling silicon oxide interface to the point where the boron doping concentration in the silicon substrate is equal to the intrinsic doping concentration of the silicon substrate is greater than or equal to 15.8μm -1 ; The thickness of the boron-doped polysilicon is in the range of 200-500nm, and the absolute value of the slope of the change in the logarithm of the boron doping concentration versus the depth into the silicon substrate from the boron-doped polysilicon / tunneling silicon oxide interface to the point where the boron doping concentration in the silicon substrate is equal to the intrinsic doping concentration of the silicon substrate is greater than or equal to 21.1μm -1 ; When the passivation contact region is an electronic passivation contact region, for a silicon substrate with a bulk resistivity of 0.5-10Ω·cm: When the thickness of phosphorus-doped polysilicon is in the range of 0-50nm, the absolute value of the slope of the change in the logarithm of the phosphorus doping concentration versus the depth into the silicon substrate from the phosphorus-doped polysilicon / tunneling silicon oxide interface to the point where the phosphorus doping concentration in the silicon substrate is equal to the intrinsic doping concentration of the silicon substrate is greater than or equal to 13.8μm -1 ; When the thickness of phosphorus-doped polysilicon is in the range of 50-200nm, the absolute value of the slope of the change in the logarithm of the phosphorus doping concentration versus the depth into the silicon substrate from the phosphorus-doped polysilicon / tunneling silicon oxide interface to the point where the phosphorus doping concentration in the silicon substrate is equal to the intrinsic doping concentration of the silicon substrate is greater than or equal to 17.3μm -1 ; When the thickness of phosphorus-doped polysilicon is in the range of 200-500nm, the absolute value of the slope of the change in the logarithm of the phosphorus doping concentration versus the depth into the silicon substrate from the phosphorus-doped polysilicon / tunneling silicon oxide interface to the point where the phosphorus doping concentration in the silicon substrate is equal to the intrinsic doping concentration of the silicon substrate is greater than or equal to 23.1μm -1 .

10. The passivation contact region according to claim 8, characterized in that: When the passivation contact region is a hole passivation contact region, the boron doping concentration on the outer surface of the boron-doped polysilicon is 1·10 20 -5.10 20 cm -3 The boron doping concentration at the boron-doped polysilicon / tunneling silicon oxide interface is 5·10 19 -5.10 20 cm -3 ; And, for silicon substrates with bulk resistivity between 0.5 and 10 Ω·cm: When the thickness of the boron-doped polysilicon is in the range of 0-50nm, the absolute value of the slope of the change in the logarithm of the boron doping concentration versus the change in the depth into the silicon substrate from the boron-doped polysilicon / tunneling silicon oxide interface to the point where the boron doping concentration in the silicon substrate is equal to the intrinsic doping concentration of the silicon substrate is greater than or equal to 34.5μm -1 ; When the thickness of the boron-doped polysilicon is in the range of 50-200nm, the absolute value of the slope of the change in the logarithm of the boron doping concentration versus the change in the depth into the silicon substrate from the boron-doped polysilicon / tunneling silicon oxide interface to the point where the boron doping concentration in the silicon substrate is equal to the intrinsic doping concentration of the silicon substrate is greater than or equal to 43.1μm -1 ; The thickness of the boron-doped polysilicon is in the range of 200-500nm, and the absolute value of the slope of the change in the logarithm of the boron doping concentration versus the depth into the silicon substrate from the boron-doped polysilicon / tunneling silicon oxide interface to the point where the boron doping concentration in the silicon substrate is equal to the intrinsic doping concentration of the silicon substrate is greater than or equal to 57.5μm -1 ; When the passivation contact region is an electronic passivation contact region, the phosphorus doping concentration on the outer surface of the phosphorus-doped polysilicon is 1·10 20 -1·10 21 cm -3 The phosphorus doping concentration at the phosphorus-doped polysilicon / tunneling silicon oxide interface is 1·10 20 -5.10 20 cm -3 ; And, for silicon substrates with bulk resistivity between 0.5 and 10 Ω·cm: The thickness of phosphorus-doped polysilicon is in the range of 0-50nm, and the absolute value of the slope of the change in the logarithm of the phosphorus doping concentration versus the depth into the silicon substrate from the phosphorus-doped polysilicon / tunneling silicon oxide interface to the point where the phosphorus doping concentration in the silicon substrate is equal to the intrinsic doping concentration of the silicon substrate is greater than or equal to 53.8μm -1 ; The thickness of the phosphorus-doped polysilicon is in the range of 50-200 nm, and the absolute value of the slope of the change in the logarithm of the phosphorus doping concentration versus the depth into the silicon substrate from the phosphorus-doped polysilicon / tunneling silicon oxide interface to the point where the phosphorus doping concentration in the silicon substrate is equal to the intrinsic doping concentration of the silicon substrate is greater than or equal to 66.3 μm -1 ; The thickness of the phosphorus-doped polysilicon is in the range of 200-500nm, and the absolute value of the slope of the change in the logarithm of the phosphorus doping concentration versus the depth into the silicon substrate from the phosphorus-doped polysilicon / tunneling silicon oxide interface to the point where the phosphorus doping concentration in the silicon substrate is equal to the intrinsic doping concentration of the silicon substrate is greater than or equal to 86.1μm -1 .

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