Semiconductor structure and forming method thereof

Abstract

The invention provides a semiconductor structure and a forming method thereof, and the method comprises the steps: providing a substrate which is internally provided with an IO region and a core region, and the IO region and the core region are disposed at an interval; forming an IO well region in the IO region; forming an IO gate dielectric layer, wherein the IO gate dielectric layer covers the IO well region; forming a core well region in the core region; and forming a core gate dielectric layer, wherein the core gate dielectric layer covers the core well region. According to the technical scheme, the electrical performance of the semiconductor structure can be improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] As the size of logic circuit devices continues to shrink, input-output (IO) devices and core devices need to coexist in a unit space to meet the increasingly complex circuit design requirements.

[0003] How to improve the electrical performance of logic circuit devices is an issue worth discussing. Summary of the invention

[0004] In view of this, an embodiment of the present invention provides a semiconductor structure and a method for forming the same, which can improve the electrical performance of the semiconductor structure.

[0005] To solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure. The method for forming a semiconductor structure includes: Providing a substrate, wherein the substrate has an IO area and a core area, and the IO area and the core area are spaced apart; forming an IO well region in the IO region; forming an IO gate dielectric layer, wherein the IO gate dielectric layer covers the IO well region; forming a core well region within the core region; A core gate dielectric layer is formed, and the core gate dielectric layer covers the core well region.

[0006] Optionally, forming an IO well region in the IO region comprises the steps of: forming a patterned first mask layer, wherein the first mask layer covers the IO region and the core region and exposes the IO well region; The IO well region is doped using the first mask layer as a mask to obtain the IO well region.

[0007] Optionally, forming the IO gate dielectric layer comprises the steps of: forming an IO gate dielectric material layer, wherein the IO gate dielectric material layer covers the IO region and the core region; forming a patterned second mask layer, wherein the second mask layer covers the IO gate dielectric material layer and exposes the IO gate dielectric material layer above the core well region; The IO gate dielectric material layer above the core well region is removed using the second mask layer as a mask to obtain an IO gate dielectric layer.

[0008] Optionally, the process for forming the IO gate dielectric layer is a thermal oxidation process.

[0009] Optionally, forming a core well region in the core region comprises the steps of: forming a patterned third mask layer, wherein the third mask layer exposes the core well region; The core well region is doped using the third mask layer as a mask to obtain the core well region.

[0010] Optionally, the process for forming the core gate dielectric layer is an ISSG process.

[0011] Optionally, before forming the core gate dielectric layer, the forming method further comprises the steps of: The substrate is annealed.

[0012] Optionally, the forming method further comprises the steps of: forming a first IO source-drain doping region and a second IO source-drain doping region in the IO well region, wherein the first IO source-drain doping region and the second IO source-drain doping region are located at two sides of the IO gate dielectric layer; A first core source-drain doping region and a second core source-drain doping region are formed in the core well region, wherein the first core source-drain doping region and the second core source-drain doping region are located at two sides of the core gate dielectric layer.

[0013] Optionally, the doping type of the core well region is consistent with that of the IO well region, and the doping concentration of the core well region is lower than that of the IO well region.

[0014] Optionally, the thickness of the core gate dielectric layer is less than the thickness of the IO gate dielectric layer.

[0015] Optionally, after providing the substrate and before forming the IO well region in the IO region, the forming method further comprises the steps of: An isolation structure is formed in the substrate, and the isolation structure is suitable for isolating the IO area and the core area.

[0016] Optionally, forming the isolation structure comprises the steps of: forming an isolation groove on a surface of the substrate; forming a first isolation layer of an isolation structure on the side and bottom of the isolation trench; A second isolation layer of an isolation structure is formed on the surface of the first isolation layer to obtain an isolation structure.

[0017] To solve the above technical problems, an embodiment of the present invention provides a semiconductor structure. The semiconductor structure includes: A substrate, wherein the substrate has an IO region and a core region, the IO region and the core region are arranged at intervals, wherein the IO region has an IO well region, and the core region has a core well region; An IO gate dielectric layer, wherein the IO gate dielectric layer covers the IO well region; A core gate dielectric layer covers the core well region.

[0018] Optionally, the IO well region has a first IO source-drain doping region and a second IO source-drain doping region, wherein the first IO source-drain doping region and the second IO source-drain doping region are located on both sides of the IO gate dielectric layer; The core well region has a first core source-drain doping region and a second core source-drain doping region, wherein the first core source-drain doping region and the second core source-drain doping region are located at two sides of the core gate dielectric layer.

[0019] Optionally, the doping type of the core well region is consistent with that of the IO well region, and the doping concentration of the core well region is lower than that of the IO well region.

[0020] Optionally, the thickness of the core gate dielectric layer is less than the thickness of the IO gate dielectric layer.

[0021] Optionally, the substrate surface has an isolation groove; the semiconductor structure further comprises: The isolation structure is located in the isolation groove and is suitable for isolating the IO area and the core area.

[0022] Optionally, the isolation structure includes: A first isolation layer, the first isolation layer covers the side surface and the bottom surface of the isolation groove; The second isolation layer is located in the isolation groove and covers the first isolation layer.

[0023] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages: In the semiconductor formation method provided by the embodiment of the present invention, compared with the case where the IO gate dielectric layer is formed after the core well region, the IO gate dielectric layer is formed before the core well region, which can reduce the influence of the formation process of the IO gate dielectric layer on the subsequently formed core well region, and avoid the redistribution of the doping concentration in the core well region caused by the formation process of the IO gate dielectric layer, thereby improving the electrical performance of the semiconductor structure.

[0024] Furthermore, compared with the furnace tube process, the ISSG process grows the core gate dielectric layer faster and has a shorter process time. Therefore, compared with the furnace tube process, forming the core gate dielectric layer through the ISSG process can improve the problem of doping concentration redistribution in the IO well region caused by the formation of the core gate dielectric layer.

[0025] Furthermore, the thickness of the core gate dielectric layer is less than that of the IO gate dielectric layer, and the core gate dielectric layer adopts the ISSG process with a faster formation speed, which can reduce the process time of the core gate dielectric layer and further improve the problem of doping concentration redistribution in the IO well region caused by the formation of the core gate dielectric layer.

[0026] Furthermore, in the process of first forming the IO well region, since the doping concentration of the IO well region is higher than that of the core well region, the degree of change of the doping concentration redistribution is smaller, and it can withstand a longer redistribution time. In the process of later forming the core well region, since the doping concentration of the core well region is lower, the degree of change of the doping concentration redistribution is greater, and it can withstand a shorter time for doping concentration redistribution. By setting up the core well region to be formed later, it can better meet the actual situation of the semiconductor structure's tolerance to doping concentration redistribution time, thereby achieving a better balance and further improving the electrical performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions of the embodiments of this specification, the drawings required for use in the embodiments of this specification or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0028] Figure 1 is a flow chart of a method for forming a semiconductor structure in an embodiment of the present invention; Figures 2 to 5 It is a schematic cross-sectional structure diagram corresponding to each step in a method for forming a semiconductor structure in an embodiment of the present invention.

[0029] Description of reference numerals: A substrate 100, an IO well region 110, a core well region 120, a first IO source-drain doping region 130, a second IO source-drain doping region 140, a first core source-drain doping region 150, and a second core source-drain doping region 160; Isolation structure 200, first isolation layer 210, second isolation layer 220; IO gate dielectric layer 310, IO gate dielectric material layer 311, IO gate layer 320, IO sidewall 330; Core gate dielectric layer 410, core gate layer 420, core sidewall spacer 430; A first mask layer A1, a second mask layer A2, and a third mask layer A3. DETAILED DESCRIPTION

[0030] As can be seen from the background technology, how to improve the electrical performance of logic circuit devices is an issue worth discussing.

[0031] In a specific application scenario, a logic circuit device has an input-output (IO) device and a core device, and the electrical performance of the logic circuit device is related to the electrical performance of the IO device and the core device.

[0032] In order to solve the above technical problems, in an embodiment of the present invention, a substrate is provided, wherein the substrate has an IO region and a core region; an IO well region is formed in the IO region; an IO gate dielectric layer is formed, and the IO gate dielectric layer covers the IO well region; a core well region is formed in the core region; a core gate dielectric layer is formed, and the core gate dielectric layer covers the core well region. By adopting the above technical solution, compared with the case where the IO gate dielectric layer is formed after the core well region and the IO gate dielectric layer is formed before the core well region, the influence of the formation process of the IO gate dielectric layer on the subsequently formed core well region can be reduced, and the doping concentration redistribution in the core well region caused by the formation process of the IO gate dielectric layer can be avoided, thereby improving the electrical performance of the semiconductor structure.

[0033] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0034] Reference Figure 1 , Figure 1 A flow chart of a method for forming a semiconductor structure in an embodiment of the present invention is shown. The method for forming a semiconductor structure may include steps S11 to S15: Step S11: providing a substrate, wherein the substrate has an IO area and a core area, and the IO area and the core area are spaced apart; Step S12: forming an IO well region in the IO region; Step S13: forming an IO gate dielectric layer, wherein the IO gate dielectric layer covers the IO well region; Step S14: forming a core well region in the core region; Step S15: forming a core gate dielectric layer, wherein the core gate dielectric layer covers the core well region.

[0035] The following combination Figures 2 to 5 The above-mentioned formation method is explained.

[0036] Figures 2 to 5 It is a schematic cross-sectional structure diagram corresponding to each step in a method for forming a semiconductor structure in an embodiment of the present invention.

[0037] Reference Figure 2 , providing a substrate 100.

[0038] Specifically, the substrate 100 is used to provide a process platform for the subsequent formation of a semiconductor structure.

[0039] The substrate 100 may be a silicon substrate, or the material of the substrate 100 may also include germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium. The substrate 100 may also be a silicon substrate on an insulator or a germanium substrate on an insulator, or a substrate on which an epitaxial layer (Epitaxylayer, Epilayer) is grown.

[0040] In some embodiments, the substrate 100 may have an input-output (IO) region and a core region, wherein the IO region is used to form an IO device, and the core region is used to form a core device.

[0041] It should be pointed out that core devices are devices responsible for performing core functions such as calculation, data processing and control; IO devices, also known as interface devices, are devices responsible for exchanging data with external devices and providing input and output functions.

[0042] In some embodiments, the IO region may be located between the core region and an outer side of the substrate 100 , for example, may be located between the core region and an outer side of the chip.

[0043] Continue to refer to Figure 2 , an isolation structure 200 is formed in the substrate 100 .

[0044] Specifically, the isolation structure 200 can achieve electrical isolation between the regions on both sides thereof. For example, the IO region and the core region can be spaced apart by the isolation structure 200, so that electrical isolation can be achieved between the IO region and the core region.

[0045] Specifically, the isolation structure 200 includes a first isolation layer 210 and a second isolation layer 220; the formation of the isolation structure 200 may include the steps of: forming an isolation groove (not shown) on the surface; forming the first isolation layer 210 of the isolation structure 200 on the side and bottom of the isolation groove, and forming the second isolation layer 220 of the isolation structure 200 on the surface of the first isolation layer 210.

[0046] In some embodiments, the isolation trench may be formed by using an isotropic etching process; or, may be formed by using an anisotropic etching process.

[0047] In some embodiments, the first isolation layer 210 may be an oxide layer formed by a thermal oxidation process.

[0048] Specifically, the first isolation layer 210 is used to isolate the substrate 100 from the second isolation layer 220 , so as to reduce damage to the substrate 100 during the subsequent process of forming the second isolation layer 220 .

[0049] In some embodiments, the material of the second isolation layer 220 may be silicon dioxide.

[0050] In some embodiments, the second isolation layer 220 may be formed by an isotropic deposition process; or, may be formed by an anisotropic deposition process.

[0051] In some embodiments, the size of the opening of the isolation trench is larger than the size of the bottom surface of the isolation trench.

[0052] Specifically, during the formation of the second isolation layer 220, the size of the opening of the isolation groove is larger than the size of the bottom surface of the isolation groove, which can reduce the probability of the second isolation layer 220 at the opening of the isolation groove prematurely cutting off the space at the opening of the isolation groove, thereby reducing the probability of gaps appearing in the second isolation layer 220.

[0053] The size is used to indicate the size, for example, the size of the cross-sectional area, or the size of the width. The direction of the width may be, for example, parallel to the direction of carrier flow.

[0054] Continue to refer to Figure 2 , an IO well region 110 is formed in the IO region. Specifically, the step of forming the IO well region 110 may include: forming a patterned first mask layer A1, the first mask layer A1 covers the IO region and the core region and exposes the IO well region 110; using the first mask layer A1 as a mask, doping the IO well region 110 to obtain the IO well region 110.

[0055] Specifically, the first mask layer A1 covers the core region and part of the IO region and exposes the surface of the substrate 100 where the IO well region 110 is located, and can protect the covered area from being doped while doping the IO well region 110 to obtain the IO well region 110.

[0056] In some embodiments, the IO well region 110 may be doped using multiple rounds of ion implantation processes, for example, three rounds of ion implantation processes.

[0057] Specifically, the three rounds of ion implantation intensities of the IO well region 110 are sequentially enhanced, wherein the first round of ion implantation is used to adjust the threshold voltage of the subsequently formed IO device; the second round of ion implantation is used to reduce the probability of punch-through between the source region and the drain region of the subsequently formed IO device; and the third round of ion implantation is used to reduce the parasitic resistance at the bottom of the IO well region 110.

[0058] In some embodiments, when performing the first round of ion implantation on the IO well region 110 , the ion implantation energy used may be 10 keV to 40 keV, for example, 15 keV to 20 keV.

[0059] In some embodiments, when performing the second round of ion implantation on the IO well region 110 , the ion implantation energy used may be 200 keV to 500 keV, for example, 200 keV to 400 keV.

[0060] In some embodiments, when the third round of ion implantation is performed on the IO well region 110 , the ion implantation energy used may be 400 keV to 1000 keV, for example, 400 keV to 800 keV.

[0061] In some embodiments, when ion implantation is performed on the IO well region 110, the ion implantation dose may be 5.0E 12 cm 2 To 1.8E 13 cm 2 For example, it can be 7.0E 12 cm 2 To 1.5E 13 cm 2 .

[0062] In some embodiments, the doping type of the IO well region 110 may be P-type doping or N-type doping.

[0063] It should be noted that, in the following description, P-type doping may be used as an example for explanation, but it does not constitute a limitation on the specific doping type used in the IO well region 110 .

[0064] In some embodiments, the doping ions of the IO well region 110 may be boron ions.

[0065] Reference Figure 3 and Figure 4 , forming an IO gate dielectric layer 310.

[0066] Specifically, the step of forming the IO gate dielectric layer 310 may include: forming an IO gate dielectric material layer 311, the IO gate dielectric material layer 311 covers the IO region and the core region; forming a patterned second mask layer A2, the second mask layer A2 covers the IO gate dielectric material layer 311 and exposes the IO gate dielectric material layer 311 above the core well region 120; using the second mask layer A2 as a mask, removing the IO gate dielectric material layer 311 above the core well region 120 to obtain the IO gate dielectric layer 310, wherein the IO gate dielectric layer 310 covers the IO region.

[0067] In some embodiments, the process for forming the IO gate dielectric layer 310 may be a thermal oxidation process, such as a furnace tube process.

[0068] Specifically, in the thermal oxidation process, the surface of the IO region and the surface of the core region are oxidized to obtain the IO gate dielectric material layer 311 .

[0069] In some embodiments, the IO gate dielectric material layer 311 above the core well region 120 may be removed by using an anisotropic etching process, such as plasma etching.

[0070] Specifically, the anisotropic ion etching process can control the shape and characteristics of the removed IO gate dielectric material layer 311 , thereby improving the size and position accuracy of the obtained IO gate dielectric layer 310 .

[0071] Continue to refer to Figure 4 , a core well region 120 is formed in the core region.

[0072] Specifically, the step of forming the core well region 120 may include: forming a patterned third mask layer A3, the third mask layer A3 exposing the core well region 120; and doping the core well region 120 using the third mask layer A3 as a mask to obtain the core well region 120.

[0073] Specifically, the third mask layer A3 covers the IO gate dielectric layer 310, the IO region exposed by the IO gate dielectric layer 310, and a portion of the core region, and exposes the surface of the substrate 100 in the region where the core well region 120 is located, while doping the core well region 120 to obtain the core well region 120, it can also protect the covered area from being doped.

[0074] In some embodiments, the core well region 120 may be doped using a multi-round ion implantation process, wherein the number of ion implantations in the core well region 120 is consistent with that in the IO well region 110. For example, three rounds of ion implantation may be used.

[0075] Specifically, the intensity of the three rounds of ion implantation in the core well region 120 is enhanced sequentially, wherein the first round of ion implantation is used to adjust the threshold voltage of the core device subsequently formed; the second round of ion implantation is used to reduce the probability of punch-through between the source region and the drain region of the core device subsequently formed; and the third round of ion implantation is used to reduce the parasitic resistance at the bottom of the core well region 120.

[0076] In some embodiments, when performing the first round of ion implantation on the core well region 120 , the ion implantation energy used may be 4.0 keV to 8.0 keV, for example, 5.0 keV to 7.0 keV.

[0077] In some embodiments, the first round of ion implantation energy of the core well region 120 may be less than the first round of ion implantation energy of the IO well region 110 .

[0078] In some embodiments, when performing the second round of ion implantation on the core well region 120 , the ion implantation energy used may be 200 keV to 500 keV, for example, 200 keV to 400 keV.

[0079] In some embodiments, the second round ion implantation energy of the core well region 120 may be consistent with the second round ion implantation energy of the IO well region 110 .

[0080] In some embodiments, when the third round of ion implantation is performed in the core well region 120 , the ion implantation energy used may be 400 keV to 1000 keV, for example, 400 keV to 800 keV.

[0081] In some embodiments, the third round of ion implantation energy of the core well region 120 may be consistent with the third round of ion implantation energy of the IO well region 110 .

[0082] In some embodiments, the ion implantation dose of the core well region 120 may be less than the ion implantation dose of the IO well region 110. For example, when the ion implantation is performed on the core well region 120, the ion implantation dose may be 4.0 E 12 cm 2 To 1.1E 13 cm 2 For example, it can be 5.0 E 12 cm 2 To 1.0 E 13 cm 2 .

[0083] Specifically, the doping concentration of the core well region 120 may be lower than the doping concentration of the IO well region 110 .

[0084] In some embodiments, the doping type of the core well region 120 may be P-type doping or N-type doping.

[0085] It should be noted that in the following description, the doping type of the core well region 120 may be consistent with the doping type of the IO well region 110 as an example for explanation, but it does not constitute a limitation on the specific doping type used in the core well region 120.

[0086] In some embodiments, the doping ions of the core well region 120 may be boron ions.

[0087] It should be pointed out that the temperature of the thermal oxidation process is usually between 800 and 1200 degrees, which means that during the process of forming the IO gate dielectric layer 310, the semiconductor structure is in a high temperature environment, and the IO well region 110 has a phenomenon of doping concentration redistribution. Compared with the formation sequence of the core well region 120 prior to the IO well region 110, in the embodiment of this specification, the formation sequence of the IO gate dielectric layer 310 prior to the core well region 120 can reduce the influence of the formation process of the IO gate dielectric layer 310 on the core well region 120, avoid the doping concentration redistribution in the core well region 120 caused by the formation process of the IO gate dielectric layer 310, and thus improve the electrical performance of the semiconductor structure.

[0088] Continue to refer to Figure 4 , the substrate 100 is annealed.

[0089] Specifically, the annealing process can repair the damage of the IO well region 110 and the core well region 120 , activate the doping ions therein, improve their electrical properties, and control the doping distribution therein.

[0090] Continue to refer to Figure 4 , forming a core gate dielectric layer 410.

[0091] Specifically, the step of forming the core gate dielectric layer 410 may include: forming a patterned fourth mask layer (not shown), the fourth mask layer exposing the core well region 120; using the fourth mask layer as a mask to form the core gate dielectric layer 410, the core gate dielectric layer 410 covering the core well region 120.

[0092] Specifically, the fourth mask layer covers the IO gate dielectric layer 310, the IO region exposed by the IO gate dielectric layer 310, and a portion of the core region, and exposes the surface of the substrate 100 in the region where the core well region 120 is located, so as to form the core gate dielectric layer 410 in the core well region 120 while avoiding the formation of the core gate dielectric layer 410 on the surface of the region covered by the fourth mask layer.

[0093] In some embodiments, the core gate dielectric layer 410 may be formed by an in situ steam generation (ISSG) process.

[0094] It should be pointed out that compared with the furnace tube process, the ISSG process grows the core gate dielectric layer 410 faster and has a shorter process time, which means that compared with the furnace tube process forming the core gate dielectric layer 410, the time for the redistribution of the doping concentration in the IO well region 110 during the process of forming the core gate dielectric layer 410 through the ISSG process is shorter, and therefore the impact on the doping concentration redistribution in the IO well region 110 caused by the formation of the core gate dielectric layer 410 is relatively small.

[0095] In some embodiments, the thickness of the core gate dielectric layer 410 is less than the thickness of the IO gate dielectric layer 310 .

[0096] Specifically, the thickness of the core gate dielectric layer 410 is less than the thickness of the IO gate dielectric layer 310, and the core gate dielectric layer 410 adopts the ISSG process with a faster formation speed, which can reduce the process time of the core gate dielectric layer 410 and further improve the problem of doping concentration redistribution in the IO well region 110 caused by the formation process of the core gate dielectric layer 410.

[0097] Compared with another process of "first forming the core well region 120 and the core gate dielectric layer 410, and then forming the IO well region 110 with a higher doping concentration", in the embodiment of the present invention, "first forming the IO well region 110 and the IO gate dielectric layer 310, and then forming the core well region 120" results in at least the following two differences: (1) the order of formation is different; (2) the relationship between the doping concentrations of the core well region and the IO well region is different.

[0098] It should be pointed out that at the same time and in the same high-temperature environment, in each of the above-mentioned processes, the degree of change of the doping concentration redistribution in the region is related to the doping concentration in the region. For example, the higher the doping concentration in the region, the smaller the degree of change of the doping concentration redistribution in the region at the same time and in the same high-temperature environment; wherein the actual doping concentration distribution in the region has a difference with the theoretical doping concentration distribution, and the degree of change of the doping concentration redistribution in the region refers to: the ratio of the difference to the theoretical doping concentration distribution. In other words, the higher the doping concentration in the region, the smaller the ratio, and the smaller the degree of change of the doping concentration redistribution in the region.

[0099] Therefore, in the embodiment of the present invention, in the process of first forming the IO well region 110, since the doping concentration of the IO well region 110 is higher than that of the core well region 120, the degree of change of the doping concentration redistribution is smaller, and it can withstand a longer redistribution time. In the process of later forming the core well region 120, since the doping concentration of the core well region 120 is relatively small, the degree of change of the doping concentration redistribution is greater, and it can withstand a shorter time for doping concentration redistribution. By setting up the later formation of the core well region 120, it can better meet the actual situation of the semiconductor structure to withstand the time of doping concentration redistribution, so that a better balance can be achieved, and the electrical performance of the semiconductor structure can be further improved.

[0100] Reference Figure 5 , forming an IO gate structure.

[0101] Specifically, the IO gate structure may include: an IO gate dielectric layer 310, an IO gate layer 320 and an IO sidewall 330. The steps of forming the IO gate structure may include: forming the IO gate layer 320 on the IO gate dielectric layer 310; forming the IO sidewall 330 on both sides of the IO gate layer 320 and the IO gate dielectric layer 310, wherein the IO sidewall 330 covers the surface of the IO well region 110 on both sides of the IO gate dielectric layer 310.

[0102] Specifically, the IO gate layer 320 is used to achieve electrical connection with other interconnect structures later; the IO sidewall 330 is used to protect the sidewalls of the IO gate layer 320 and the IO gate dielectric layer 310 .

[0103] In some embodiments, the IO gate layer 320 may be a polysilicon (Ploy-Si) layer, or the material of the IO gate layer 320 may also include one or more of titanium nitride, tantalum nitride, tantalum, titanium, titanium aluminide, tungsten, aluminum, titanium silicon nitride, and titanium aluminum carbide.

[0104] In some embodiments, the IO gate layer 320 may include an IO work function layer (not shown in the figure) and an IO electrode layer (not shown in the figure) located on the IO work function layer, wherein the IO work function layer is used to adjust the threshold voltage of the transistor. In other embodiments, the IO gate layer 320 may also include only the IO work function layer.

[0105] In some embodiments, the IO spacer 330 may be a single-layer structure or a stacked-layer structure.

[0106] In some embodiments, the material of the IO spacer 330 may include one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride.

[0107] Continue to refer to Figure 5 , forming a core gate structure.

[0108] Specifically, the core gate structure may include: a core gate dielectric layer 410, a core gate layer 420 and a core side wall 430. The steps of forming the core gate structure may include: forming a core gate layer 420 on the core gate dielectric layer 410; forming a core side wall 430 on both sides of the core gate layer 420 and the core gate dielectric layer 410, wherein the core side wall 430 covers the surface of the core well region 120 on both sides of the core gate dielectric layer 410.

[0109] Specifically, the core gate layer 420 is used to achieve electrical connection with other interconnect structures later; the core sidewall spacer 430 is used to protect the sidewalls of the core gate layer 420 and the core gate dielectric layer 410 .

[0110] In some embodiments, the core gate layer 420 may be a polysilicon layer, or the material of the core gate layer 420 may also include one or more of titanium nitride, tantalum nitride, tantalum, titanium, titanium aluminide, tungsten, aluminum, titanium silicon nitride, and titanium aluminum carbide.

[0111] In some embodiments, the material of the core gate layer 420 is consistent with the material of the IO gate layer 320 .

[0112] In some embodiments, the core gate layer 420 may include a core work function layer (not shown in the figure) and a core electrode layer (not shown in the figure) located on the core work function layer, wherein the core work function layer is used to adjust the threshold voltage of the transistor. In other embodiments, the core gate layer 420 may also include only the core work function layer.

[0113] In some embodiments, the core spacer 430 may be a single-layer structure or a stacked-layer structure.

[0114] In some embodiments, the material of the core spacer 430 may include one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon nitride oxide, boron nitride, and boron carbonitride.

[0115] In some embodiments, the material of the core spacer 430 is consistent with the material of the IO gate layer 320 .

[0116] In some embodiments, the core gate layer 420 and the IO gate layer 320 may be formed in various orders. For example, the IO gate layer 320 may be formed during the process of forming the core gate layer 420. For example, the IO gate layer 320 may be formed before forming the core gate layer 420.

[0117] In some embodiments, the core spacer 430 and the IO spacer 330 may be formed in various orders. For example, the IO spacer 330 may be formed during the process of forming the core spacer 430. For example, the IO spacer 330 may be formed before forming the core spacer 430.

[0118] Continue to refer to Figure 5 , forming a first IO source-drain doping region 130 and a second IO source-drain doping region 140.

[0119] Specifically, the step of forming the first IO source-drain doping region 130 and the second IO source-drain doping region 140 may include: doping the IO well region 110 exposed on both sides of the IO gate structure to obtain the first IO source-drain doping region 130 and the second IO source-drain doping region 140, wherein one of the first IO source-drain doping region 130 and the second IO source-drain doping region 140 is used as the source region of the IO device, and the other is used as the drain region of the IO device.

[0120] In some embodiments, the first IO source-drain doping region 130 and the second IO source-drain doping region 140 have the same doping type, and both are different from the doping type of the IO well region 110. For example, the doping type of the first IO source-drain doping region 130 and the second IO source-drain doping region 140 is N-type doping, and the IO well region 110 is P-type doping.

[0121] In some embodiments, the IO device may be an NMOS device or a PMOS device.

[0122] Continue to refer to Figure 5 , forming a first core source-drain doping region 150 and a second core source-drain doping region 160 .

[0123] Specifically, the steps of forming a first core source-drain doping region 150 and a second core source-drain doping region 160 may include: doping the core well region 120 exposed on both sides of the core gate structure to obtain a first core source-drain doping region 150 and a second core source-drain doping region 160, wherein one of the first core source-drain doping region 150 and the second core source-drain doping region 160 is used as a source region of the core device, and the other is used as a drain region of the core device.

[0124] In some embodiments, the first core source-drain doping region 150 and the second core source-drain doping region 160 have the same doping type, and both are different from the doping type of the core well region 120. For example, the doping type of the first core source-drain doping region 150 and the second core source-drain doping region 160 is N-type doping, and the core well region 120 is P-type doping.

[0125] In some embodiments, the core device may be an NMOS device or a PMOS device.

[0126] In some embodiments, the type of the IO device is consistent with the type of the core device.

[0127] In some embodiments, the operating voltage of the IO device is higher than the operating voltage of the core device.

[0128] In an embodiment of the present invention, a semiconductor structure may also be provided. Figures 2 to 5 The semiconductor structure includes: a substrate 100, an IO gate dielectric layer 310 and a core gate dielectric layer 410, wherein the substrate has an IO region and a core region, the IO region and the core region are arranged at intervals, the IO region has an IO well region 110, and the core region has a core well region 120; the IO gate dielectric layer 310 covers the IO well region 110; and the core gate dielectric layer 410 covers the core well region 120.

[0129] Furthermore, the IO well region may include a first IO source / drain doping region 130 and a second IO source / drain doping region 140 , wherein the first IO source / drain doping region 130 and the second IO source / drain doping region 140 are located at two sides of the IO gate dielectric layer 310 .

[0130] Furthermore, the core well region 120 may have a first core source / drain doping region 150 and a second core source / drain doping region 160 , wherein the first core source / drain doping region 150 and the second core source / drain doping region 160 are located on both sides of the core gate dielectric layer 410 .

[0131] Furthermore, the doping type of the core well region 120 may be consistent with that of the IO well region 110 , and the doping concentration of the core well region 120 may be lower than that of the IO well region 110 .

[0132] Furthermore, the thickness of the core gate dielectric layer 410 may be smaller than the thickness of the IO gate dielectric layer 310 .

[0133] Furthermore, the substrate surface may have an isolation groove.

[0134] Furthermore, the semiconductor structure may further include an isolation structure 200 , which is located in the isolation trench and is suitable for isolating the IO region and the core region.

[0135] Furthermore, the isolation structure 200 may include a first isolation layer 210 , and the first isolation layer 210 covers the side surface and the bottom surface of the isolation trench.

[0136] Furthermore, the isolation structure 200 may further include a second isolation layer 220 , where the second isolation layer 220 is located in the isolation trench and covers the first isolation layer 210 .

[0137] It should be noted that the semiconductor structure in the embodiment of the present invention can be formed by the formation method described in the above embodiment, or by other formation methods. For the specific description of the semiconductor structure in the embodiment of the present invention, reference can be made to the corresponding description in the above embodiment, and this embodiment will not be repeated here.

[0138] It is understandable that the term "and / or" in this article is only a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article indicates that the associated objects before and after are in an "or" relationship.

[0139] It is understood that the "multiple" mentioned herein refers to two or more than two. The first, second, third, fourth, etc. descriptions in the embodiments of the present application are only used for illustration and distinction of the described objects, and have no order, nor do they represent any special limitation on the number of devices in the embodiments of the present application, and cannot constitute any limitation on the embodiments of the present application.

[0140] It can be understood that the above describes multiple implementation schemes provided by the embodiments of the present invention, and the various optional methods introduced in each implementation scheme can be combined and cross-referenced with each other without conflict, thereby extending a variety of possible implementation schemes, which can all be considered as the implementation schemes disclosed and open to the public by the present invention.

[0141] Although the embodiments of the present invention are disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, wherein the substrate has an IO region and a core region, and the IO region and the core region are spaced apart; forming an IO well region in the IO region; forming an IO gate dielectric layer, wherein the IO gate dielectric layer covers the IO well region; forming a core well region within the core region; A core gate dielectric layer is formed, wherein the core gate dielectric layer covers the core well region.

2. The forming method according to claim 1, characterized in that: Forming an IO well region in the IO region comprises the steps of: forming a patterned first mask layer, wherein the first mask layer covers the IO region and the core region and exposes the IO well region; The IO well region is doped using the first mask layer as a mask to obtain the IO well region.

3. The forming method according to claim 1, characterized in that: The IO gate dielectric layer is formed, comprising the steps of: forming an IO gate dielectric material layer, wherein the IO gate dielectric material layer covers the IO region and the core region; forming a patterned second mask layer, wherein the second mask layer covers the IO gate dielectric material layer and exposes the IO gate dielectric material layer above the core well region; The IO gate dielectric material layer above the core well region is removed using the second mask layer as a mask to obtain the IO gate dielectric layer.

4. The forming method according to claim 1, characterized in that: The process for forming the IO gate dielectric layer is a thermal oxidation process.

5. The forming method according to claim 1, characterized in that: Forming a core well region in the core region comprises the steps of: forming a patterned third mask layer, wherein the third mask layer exposes the core well region; The core well region is doped using the third mask layer as a mask to obtain the core well region.

6. The forming method according to claim 1, characterized in that: The process for forming the core gate dielectric layer is an ISSG process.

7. The forming method according to claim 1, characterized in that: Before forming the core gate dielectric layer, the method further comprises the following steps: The substrate is annealed.

8. The forming method according to claim 1, characterized in that: Also includes the steps: forming a first IO source-drain doping region and a second IO source-drain doping region in the IO well region, wherein the first IO source-drain doping region and the second IO source-drain doping region are located on both sides of the IO gate dielectric layer; A first core source-drain doping region and a second core source-drain doping region are formed in the core well region, wherein the first core source-drain doping region and the second core source-drain doping region are located at two sides of the core gate dielectric layer.

9. The forming method according to claim 1, characterized in that: The doping type of the core well region is consistent with that of the IO well region, and the doping concentration is less than that of the IO well region.

10. The forming method according to claim 1, characterized in that: The thickness of the core gate dielectric layer is less than the thickness of the IO gate dielectric layer.

11. The forming method according to claim 1, characterized in that: After providing the substrate and before forming the IO well region in the IO region, the method further includes the following steps: An isolation structure is formed in the substrate, wherein the isolation structure is suitable for isolating the IO region and the core region.

12. The forming method according to claim 11, characterized in that: The isolation structure is formed, comprising the steps of: forming an isolation groove on the surface of the substrate; forming a first isolation layer of the isolation structure on the side and bottom surfaces of the isolation trench; A second isolation layer of the isolation structure is formed on the surface of the first isolation layer to obtain the isolation structure.

13. A semiconductor structure, characterized in that: include: A substrate, wherein the substrate has an IO region and a core region, the IO region and the core region are arranged at intervals, wherein the IO region has an IO well region, and the core region has a core well region; An IO gate dielectric layer, wherein the IO gate dielectric layer covers the IO well region; A core gate dielectric layer covers the core well region.

14. The semiconductor structure according to claim 13, characterized in that: The IO well region has a first IO source-drain doping region and a second IO source-drain doping region, wherein the first IO source-drain doping region and the second IO source-drain doping region are located on both sides of the IO gate dielectric layer; The core well region has a first core source-drain doping region and a second core source-drain doping region, wherein the first core source-drain doping region and the second core source-drain doping region are located on both sides of the core gate dielectric layer.

15. The semiconductor structure according to claim 13, characterized in that The doping type of the core well region is consistent with that of the IO well region, and the doping concentration is less than that of the IO well region.

16. The semiconductor structure according to claim 13, characterized in that The thickness of the core gate dielectric layer is less than the thickness of the IO gate dielectric layer.

17. The semiconductor structure according to claim 13, characterized in that The substrate surface has an isolation groove; the semiconductor structure further includes: An isolation structure is located in the isolation groove and is suitable for isolating the IO area and the core area.

18. The semiconductor structure according to claim 17, characterized in that: The isolation structure comprises: a first isolation layer, wherein the first isolation layer covers the side surface and the bottom surface of the isolation groove; A second isolation layer is located in the isolation groove and covers the first isolation layer.

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