High-performance charge pump circuit for high-side driving

Abstract

The invention discloses a high-performance charge pump circuit for high-side driving. The high-performance charge pump circuit comprises an oscillator circuit, a dead zone generation circuit and a charge pump circuit, the oscillator circuit is used for generating a periodically changing square wave signal as a clock signal CLK of the dead zone generation circuit; the dead zone generation circuit processes the CLK signals and generates clock signals with certain dead zone time in pairs; the charge pump circuit controls on and off of a switch tube through a signal generated by the dead zone generation circuit to control charging or discharging of a capacitor, charges are accumulated, and voltage pumping is achieved. According to the charge pump circuit, under the control of the dead zone generation circuit, the switch tube is repeatedly turned on and turned off to control charging or discharging of the capacitor, voltage pumping, high conversion efficiency, small loss and small output ripple are achieved, and under the action of the voltage-regulator tube, the output voltage is fixed at a numerical value, and stable output is achieved. The power consumption is low, the conversion efficiency is high, the output ripple is small and stable, and the output voltage is not too high.

Description

Technical Field

[0001] The present invention relates to a high-side gate driving technology in an integrated circuit driving system, and in particular to a charge pump technology for high-side gate driving. Background Art

[0002] Charge pumps based on switched capacitor technology are widely used in boost circuit modules in various chips due to their excellent characteristics of low cost, low electromagnetic interference and high power efficiency. For example, a stepper motor driver chip drives an H-bridge high-end power tube. When the high-end power tube in the H-bridge is turned on, the source voltage is close to the drain voltage. At this time, in order to fully turn on the power tube, a voltage higher than the system power supply needs to be generated to connect to the gate of the power tube. In this case, a charge pump circuit is needed to meet the circuit requirements; when the high-side power switch chip drives the high-side power tube, the charge pump can raise the gate voltage to above the power supply voltage to ensure that the power switch tube can be turned on normally; when the three-phase bridge driver chip drives the brushless motor, in order to ensure that the high-side power switch tube is fully turned on, the charge pump is also required to generate a voltage higher than the system power supply. Therefore, the charge pump circuit is widely used, but it is still valuable to design a high-performance charge pump circuit with high conversion efficiency, low power consumption and small output ripple.

[0003] like Figure 1 The figure shows the traditional oscillator and charge pump circuit structure. Figure 1 As shown in a, although the structure of the three-stage ring oscillator is very simple, its performance is greatly reduced. Not only does the power consumption increase, but the circuit's anti-noise ability is poor, and it is often accompanied by many glitches. Moreover, the frequency of the pulse is controlled by the delay of the inverter, so the frequency is very large. Figure 1 b shows the equivalent model of Dickson charge pump. The disadvantage of traditional Dickson charge pump is that it cannot avoid the loss of threshold voltage. As the number of stages increases, the loss of threshold voltage becomes more and more serious. Therefore, as the number of stages increases, the conversion efficiency also decreases significantly. Another disadvantage is that the clock is used to directly drive the capacitor. The charge pump circuit generally has a large output current. In order to reduce the output ripple, a larger capacitor is generally used. In this way, direct clock drive will have certain limitations on the clock's driving ability. Summary of the invention

[0004] In view of the deficiencies in the prior art, the present invention provides a high-performance charge pump circuit for high-side driving.

[0005] The oscillator in the present invention controls the clock frequency at 4 MHZ, which can make the charge pump output to high voltage quickly without causing excessive power consumption, while reducing ripple to achieve stable output; the introduction of the dead zone generation circuit ensures that the switch tubes will not be turned on at the same time, thereby causing the charge reflux phenomenon, greatly increasing the conversion efficiency of the charge pump.

[0006] The technical solution adopted by the present invention is specifically as follows:

[0007] A high-performance charge pump circuit for high-side driving comprises an oscillator circuit, a dead zone generating circuit and a charge pump circuit; the oscillator circuit is used to generate a periodically changing square wave signal as a clock signal CLK of the dead zone generating circuit; the dead zone generating circuit processes the CLK signal to generate clock signals with certain dead zone times between each other; the charge pump circuit controls the charging or discharging of a capacitor by controlling the opening and closing of a switch tube through a signal generated by the dead zone generating circuit, accumulates charge and realizes voltage pumping.

[0008] Furthermore, the oscillator circuit includes a first PMOS tube MP1, a second PMOS tube MP2, a third PMOS tube MP3, a fourth PMOS tube MP4, a fifth PMOS tube MP5, and a sixth PMOS tube MP6; a first NMOS tube MN1, a second NMOS tube MN2, a third NMOS tube MN3, a fourth NMOS tube MN4, a fifth NMOS tube MN5, a sixth NMOS tube MN6, and a seventh NMOS tube MN7; a first zener diode Z1; a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4; a first inverter INV1, a second inverter INV2, a third inverter INV3, and a first variable capacitor C1.

[0009] The substrate ends of the first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are connected to the ground GND; the substrate ends of the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6 are connected to the power supply VDD. One end of the first resistor R1, the source end of the first PMOS transistor MP1, the source end of the second PMOS transistor MP2, the source end of the third PMOS transistor MP3 and the source end of the fourth PMOS transistor MP4 are connected to the power supply VDD; the anode of the first voltage stabilizing diode Z1, one end of the second resistor R2, one end of the third resistor R3, the source end of the fifth NMOS transistor MN5, one end of the first variable capacitor C1, the source end of the sixth NMOS transistor MN6 and the source end of the seventh NMOS transistor MN7 are connected to the ground GND. The gate and drain of the first NMOS tube MN1 are connected to the gate of the second NMOS tube MN2 and the other end of the first resistor R1; the source of the first NMOS tube MN1 is connected to the cathode of the first voltage stabilizing diode Z1; the source of the second NMOS tube MN2 is connected to the other end of the second resistor R2; the first NMOS tube MN1 and the second NMOS tube MN2 form a current mirror link. The drain and gate of the first PMOS tube MP1 are connected to the gate of the second PMOS tube MP2, the third PMOS tube MP3, the fourth PMOS tube MP4 and the drain of the second NMOS tube MN2; the first PMOS tube MP1, the second PMOS tube MP2, the third PMOS tube MP3, the fourth PMOS tube MP4 form a current mirror link.

[0010] The drain end of the second PMOS tube MP2 is connected to the drain end of the third NMOS tube MN3 and the gate end of the fourth NMOS tube MN4. The drain end of the third PMOS tube MP3 is connected to the drain end of the fourth NMOS tube MN4 and the input end of the first inverter INV1. The drain end of the fourth PMOS tube MP4 is connected to the source ends of the fifth PMOS tube MP5 and the sixth PMOS tube MP6. The source end of the third NMOS tube MN3 is connected to the source end of the fourth NMOS tube MN4 and the other end of the third resistor R3. The gate end of the third NMOS tube MN3 is connected to the drain end of the fifth NMOS tube MN5, the other end of the first variable capacitor C1, the drain end of the fifth PMOS tube MP5 and the drain end of the sixth NMOS tube MN6. The input end of the third inverter INV3 is connected to the EN end; the output end of the third inverter INV3 is connected to the gate end of the fifth NMOS tube MN5. The output end of the first inverter INV1 is connected to the input end of the second inverter INV2 and the gate end of the sixth PMOS tube MP6; the output end of the second inverter INV2, i.e., the CLK end, is connected to the gate end of the fifth PMOS tube MP5. The drain end of the sixth PMOS tube MP6 is connected to one end of the fourth resistor R4; the other end of the fourth resistor R4 is connected to the gate end and the drain end of the seventh NMOS tube MN7 and the gate end of the sixth NMOS tube MN6; the sixth NMOS tube MN6 and the seventh NMOS tube MN7 form a current mirror link.

[0011] Furthermore, the dead zone generating circuit includes a first NAND gate NAND1, a second NAND gate NAND2, a third NAND gate NAND3, a fourth inverter INV4, a fifth inverter INV5, a sixth inverter INV6 and a seventh inverter INV7.

[0012] The input end of the fourth inverter INV4 is the charge pump control signal IN end, the output end of the fourth inverter INV4 is connected to the input end of the first NAND gate NAND1, and the other input end of the first NAND gate NAND1 is connected to the oscillator output clock signal CLK end. The output end of the first NAND gate NAND1 is connected to the input end of the fifth inverter INV5 and the input end of the second NAND gate NAND2; the output end of the third NAND gate NAND3 is connected to the other input end of the second NAND gate NAND2 and the input end of the seventh inverter INV7. The output end of the fifth inverter INV5 is connected to the input end of the third NAND gate NAND3; the output end of the second NAND gate NAND2 is connected to the other input end of the third NAND gate NAND3 and the input end of the sixth inverter INV6. The output end of the third NAND gate NAND3 is the CLK1 end, the output end of the sixth inverter INV6 is the CLK2 end, the output end of the second NAND gate NAND2 is the CLK3 end, and the output end of the seventh inverter INV7 is the CLK4 end.

[0013] Furthermore, the charge pump circuit includes a second capacitor C2, a third capacitor C3, an output capacitor Cout, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, a first NPN transistor Q1, a second NPN transistor Q2, a third NPN transistor Q3, a second Zener diode Z2, a third Zener diode Z3, a fourth Zener diode Z4, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, an eighth NMOS transistor MN8 and a ninth NMOS transistor MN9.

[0014] The gate ends of the seventh PMOS tube MP7, the eighth NMOS tube MN8, the eighth PMOS tube MP8 and the ninth NMOS tube MN9 are respectively connected to the four output ends CLK1, CLK2, CLK3 and CLK4 of the dead zone generating circuit. The source end of the seventh PMOS tube MP7 is connected to the power supply VDD; the drain end of the eighth NMOS tube MN8 is connected to the drain end of the seventh PMOS tube MP7 and one end of the third capacitor C3; the source end of the eighth NMOS tube MN8 is connected to the ground GND. The source end of the eighth PMOS tube MP8 is connected to the power supply VDD; the drain end of the ninth NMOS tube MN9 is connected to the drain end of the eighth PMOS tube MP8 and one end of the second capacitor C2; the source end of the ninth NMOS tube MN9 is connected to the ground GND. The other end of the second capacitor C2 is connected to one end of the sixth resistor R6; the third capacitor C3 is connected to one end of the fifth resistor R5. The other end of the sixth resistor R6 is connected to the two ends of the eighth resistor R8, the base and collector of the second NPN tube Q2 and the emitter of the third NPN tube Q3. The other end of the fifth resistor R5 is connected to both ends of the seventh resistor R7 and the base of the first NPN tube Q1. The emitter of the first NPN tube Q1 is connected to the charge pump output terminal HB; the collector of the first NPN tube Q1 is connected to the emitter of the second NPN tube Q2. The base and collector of the third NPN tube Q3 are connected to one end of the ninth resistor R9; the other end of the ninth resistor R9 is connected to the floating ground terminal HS. The cathode of the second voltage zener diode Z2 is connected to the charge pump output terminal HB; the anode of the second voltage zener diode Z2 is connected to the cathode of the third voltage zener diode Z3; the anode of the third voltage zener diode Z3 is connected to the cathode of the fourth voltage zener diode Z4; the anode of the fourth voltage zener diode Z4 is connected to one end of the tenth resistor R10; the other end of the tenth resistor R10 is connected to the floating ground terminal HS. One end of the output capacitor Cout is connected to the charge pump output terminal HB; the other end of the output capacitor Cout is connected to the floating ground terminal HS.

[0015] The beneficial effects of the present invention are as follows:

[0016] The charge pump circuit of the present invention is controlled by the dead zone generating circuit, and the switch tube is repeatedly turned on and off to control the charging or discharging of the capacitor, so as to realize voltage pumping, high conversion efficiency, low loss, small output ripple, and under the action of the voltage regulator tube, the output voltage is fixed at a value and the output is stable. Compared with the traditional oscillator and charge pump circuit, the present invention has low power consumption, high conversion efficiency, small and stable output ripple, and the output voltage is not too high. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a structural diagram of a traditional ring oscillator and Dickson charge pump circuit.

[0018] Figure 2 It is an overall principle diagram of an embodiment of the present invention.

[0019] Figure 3 1 is a circuit diagram of an oscillator circuit according to an embodiment of the present invention.

[0020] Figure 4 It is a circuit diagram of a dead zone generating circuit and a charge pump circuit according to an embodiment of the present invention.

[0021] Figure 5 It is a working waveform diagram of the oscillator according to an embodiment of the present invention.

[0022] Figure 6 1 and 2 are the output waveforms when the IN terminal of the dead zone generating circuit according to the embodiment of the present invention is at a high level.

[0023] Figure 7 It is a working waveform diagram of the dead zone generating circuit according to an embodiment of the present invention.

[0024] Figure 8 1 is a charge pump operating waveform diagram according to an embodiment of the present invention. DETAILED DESCRIPTION

[0025] The specific implementation of the present invention will be described in more detail below in conjunction with the schematic diagram. The advantages and features of the present invention will become clearer based on the following description. It should be noted that the drawings are all in a very simplified form and are not in exact proportions, and are only used to facilitate and clearly assist in explaining the purpose of the embodiments of the present invention.

[0026] like Figure 2 As shown, the present invention provides a high-performance charge pump circuit for high-side driving, comprising an oscillator circuit, a dead zone generating circuit and a charge pump circuit; the oscillator circuit is used to generate a periodically changing square wave signal as a clock signal CLK of the dead zone generating circuit; the dead zone generating circuit processes the CLK signal to generate clock signals with certain dead zone times between each other; the charge pump circuit controls the charging or discharging of the capacitor by controlling the opening and closing of the switch tube through the signal generated by the dead zone generating circuit, accumulates the charge, and realizes voltage pumping.

[0027] Oscillator Section

[0028] like Figure 3 The oscillator circuit shown in the figure includes a first PMOS tube MP1, a second PMOS tube MP2, a third PMOS tube MP3, a fourth PMOS tube MP4, a fifth PMOS tube MP5, and a sixth PMOS tube MP6; a first NMOS tube MN1, a second NMOS tube MN2, a third NMOS tube MN3, a fourth NMOS tube MN4, a fifth NMOS tube MN5, a sixth NMOS tube MN6, and a seventh NMOS tube MN7; a first voltage zener diode Z1; a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4; a first inverter INV1, a second inverter INV2, a third inverter INV3 and a first variable capacitor C1.

[0029] The substrate ends of the first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are connected to the ground GND; the substrate ends of the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6 are connected to the power supply VDD. One end of the first resistor R1, the source end of the first PMOS transistor MP1, the source end of the second PMOS transistor MP2, the source end of the third PMOS transistor MP3 and the source end of the fourth PMOS transistor MP4 are connected to the power supply VDD; the anode of the first voltage stabilizing diode Z1, one end of the second resistor R2, one end of the third resistor R3, the source end of the fifth NMOS transistor MN5, one end of the first variable capacitor C1, the source end of the sixth NMOS transistor MN6 and the source end of the seventh NMOS transistor MN7 are connected to the ground GND. The gate and drain of the first NMOS tube MN1 are connected to the gate of the second NMOS tube MN2 and the other end of the first resistor R1; the source of the first NMOS tube MN1 is connected to the cathode of the first voltage stabilizing diode Z1; the source of the second NMOS tube MN2 is connected to the other end of the second resistor R2; the first NMOS tube MN1 and the second NMOS tube MN2 form a current mirror link. The drain and gate of the first PMOS tube MP1 are connected to the gate of the second PMOS tube MP2, the third PMOS tube MP3, the fourth PMOS tube MP4 and the drain of the second NMOS tube MN2; the first PMOS tube MP1, the second PMOS tube MP2, the third PMOS tube MP3, the fourth PMOS tube MP4 form a current mirror link.

[0030] The drain end of the second PMOS tube MP2 is connected to the drain end of the third NMOS tube MN3 and the gate end of the fourth NMOS tube MN4. The drain end of the third PMOS tube MP3 is connected to the drain end of the fourth NMOS tube MN4 and the input end of the first inverter INV1. The drain end of the fourth PMOS tube MP4 is connected to the source ends of the fifth PMOS tube MP5 and the sixth PMOS tube MP6. The source end of the third NMOS tube MN3 is connected to the source end of the fourth NMOS tube MN4 and the other end of the third resistor R3. The gate end of the third NMOS tube MN3 is connected to the drain end of the fifth NMOS tube MN5, the other end of the first variable capacitor C1, the drain end of the fifth PMOS tube MP5 and the drain end of the sixth NMOS tube MN6. The input end of the third inverter INV3 is connected to the EN end; the output end of the third inverter INV3 is connected to the gate end of the fifth NMOS tube MN5. The output end of the first inverter INV1 is connected to the input end of the second inverter INV2 and the gate end of the sixth PMOS tube MP6; the output end of the second inverter INV2, i.e., the CLK end, is connected to the gate end of the fifth PMOS tube MP5. The drain end of the sixth PMOS tube MP6 is connected to one end of the fourth resistor R4; the other end of the fourth resistor R4 is connected to the gate end and the drain end of the seventh NMOS tube MN7 and the gate end of the sixth NMOS tube MN6; the sixth NMOS tube MN6 and the seventh NMOS tube MN7 form a current mirror link.

[0031] In the oscillator circuit, the EN terminal is an enable signal, which is valid when the EN terminal is at a high level, that is, the oscillator works when the EN terminal is at a high level; the CLK terminal is the oscillator output signal; the CLK oscillation frequency is changed by changing the capacitance of the first variable capacitor C1.

[0032] When EN is at a low level, the output of the third inverter INV3 is at a high level, so that the fifth NMOS tube MN5 is turned on, the gate voltage of the third NMOS tube MN3 is pulled down, the third NMOS tube MN3 is turned off, so that the gate voltage of the fourth NMOS tube MN4 is pulled high, the fourth NMOS tube MN4 is turned on, and the input of the first inverter INV1 is pulled low; then the output of the second inverter INV2, that is, the CLK output end, is at a low level, and the fifth PMOS tube MP5 is turned on, the sixth PMOS tube MP6 is turned off, and the oscillator does not work.

[0033] When EN turns to a high level, the output of the third inverter INV3 is a low level, so that the fifth NMOS tube MN5 is turned off. At this time, the current copied by the current mirror passes through the fifth PMOS tube MP5 to charge the first variable capacitor C1 below. At this time, the size of the capacitor charged is the bias current; when the voltage of the first variable capacitor C1 rises to the threshold voltage of the third NMOS tube MN3, the third NMOS tube MN3 is turned on, and the gate voltage of the fourth NMOS tube MN4 is pulled down, the fourth NMOS tube MN4 is turned off, the input of the first inverter INV1 becomes a high level, and the output of the second inverter INV2, that is, the CLK end, is a high level; at this time, the fifth PMOS tube MP5 is turned off, and the sixth PMOS tube M P6 is turned on, and the first capacitor C1 is discharged through the sixth PMOS tube MN6. At this time, the magnitude of the capacitor discharge is the bias current copied by the current mirror. After the discharge is lower than the threshold voltage of the third NMOS tube MN3, the third NMOS tube MN3 is turned off, and the gate voltage of the fourth NMOS tube MN4 is raised. The fourth NMOS tube MN4 is turned on, so that the input of the first inverter INV1 becomes a low level, and the output of the second inverter INV2, that is, the CLK end, is also a low level. At this time, the fifth PMOS tube MP5 is turned on, and the sixth PMOS tube MP6 is turned off. The current charges the first variable capacitor C1 through the fifth PMOS tube MP5, and this cycle is repeated to generate a periodically changing square wave signal.

[0034] like Figure 5 The figure shows the working waveform of the oscillator. It can be seen that when the enable terminal EN is high, the CLK terminal outputs a periodically changing square wave signal with a clock frequency of 4MHZ.

[0035] Dead zone generation and charge pump section

[0036] like Figure 4 The dotted line box on the left is a dead zone generating circuit, and the charge pump circuit on the right is shown.

[0037] The dead zone generating circuit comprises a first NAND gate NAND1, a second NAND gate NAND2, a third NAND gate NAND3, a fourth inverter INV4, a fifth inverter INV5, a sixth inverter INV6 and a seventh inverter INV7; wherein the IN terminal is a charge pump control signal, which is valid at a low level; the CLK terminal is a clock signal output by an upper oscillator, and CLK1, CLK2, CLK3 and CLK4 are respectively the four output terminals of the dead zone generating circuit.

[0038] The input end of the fourth inverter INV4 is the charge pump control signal IN end, the output end of the fourth inverter INV4 is connected to the input end of the first NAND gate NAND1, and the other input end of the first NAND gate NAND1 is connected to the oscillator output clock signal CLK end. The output end of the first NAND gate NAND1 is connected to the input end of the fifth inverter INV5 and the input end of the second NAND gate NAND2; the output end of the third NAND gate NAND3 is connected to the other input end of the second NAND gate NAND2 and the input end of the seventh inverter INV7. The output end of the fifth inverter INV5 is connected to the input end of the third NAND gate NAND3; the output end of the second NAND gate NAND2 is connected to the other input end of the third NAND gate NAND3 and the input end of the sixth inverter INV6. The output end of the third NAND gate NAND3 is the CLK1 end, the output end of the sixth inverter INV6 is the CLK2 end, the output end of the second NAND gate NAND2 is the CLK3 end, and the output end of the seventh inverter INV7 is the CLK4 end.

[0039] The charge pump circuit includes a second capacitor C2, a third capacitor C3, an output capacitor Cout, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, a first NPN transistor Q1, a second NPN transistor Q2, a third NPN transistor Q3, a second voltage zener diode Z2, a third voltage zener diode Z3, a fourth voltage zener diode Z4, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, an eighth NMOS transistor MN8 and a ninth NMOS transistor MN9; wherein the VDD terminal is a power supply, the GND terminal is grounded, the HS is a floating terminal, and the HB is a charge pump output terminal.

[0040] The gate ends of the seventh PMOS tube MP7, the eighth NMOS tube MN8, the eighth PMOS tube MP8 and the ninth NMOS tube MN9 are respectively connected to the four output ends CLK1, CLK2, CLK3 and CLK4 of the dead zone generating circuit. The source end of the seventh PMOS tube MP7 is connected to the power supply VDD; the drain end of the eighth NMOS tube MN8 is connected to the drain end of the seventh PMOS tube MP7 and one end of the third capacitor C3; the source end of the eighth NMOS tube MN8 is connected to the ground GND. The source end of the eighth PMOS tube MP8 is connected to the power supply VDD; the drain end of the ninth NMOS tube MN9 is connected to the drain end of the eighth PMOS tube MP8 and one end of the second capacitor C2; the source end of the ninth NMOS tube MN9 is connected to the ground GND. The other end of the second capacitor C2 is connected to one end of the sixth resistor R6; the third capacitor C3 is connected to one end of the fifth resistor R5. The other end of the sixth resistor R6 is connected to the two ends of the eighth resistor R8, the base and collector of the second NPN tube Q2 and the emitter of the third NPN tube Q3. The other end of the fifth resistor R5 is connected to both ends of the seventh resistor R7 and the base of the first NPN tube Q1. The emitter of the first NPN tube Q1 is connected to the charge pump output terminal HB; the collector of the first NPN tube Q1 is connected to the emitter of the second NPN tube Q2. The base and collector of the third NPN tube Q3 are connected to one end of the ninth resistor R9; the other end of the ninth resistor R9 is connected to the floating ground terminal HS. The cathode of the second voltage zener diode Z2 is connected to the charge pump output terminal HB; the anode of the second voltage zener diode Z2 is connected to the cathode of the third voltage zener diode Z3; the anode of the third voltage zener diode Z3 is connected to the cathode of the fourth voltage zener diode Z4; the anode of the fourth voltage zener diode Z4 is connected to one end of the tenth resistor R10; the other end of the tenth resistor R10 is connected to the floating ground terminal HS. One end of the output capacitor Cout is connected to the charge pump output terminal HB; the other end of the output capacitor Cout is connected to the floating ground terminal HS.

[0041] When the IN terminal is at a high level, the fourth inverter INV4 outputs a low level. No matter how CLK changes, the output of the first NAND gate NAND1 is always at a high level, the output of the fifth inverter INV5 is at a low level, the output of the third NAND gate NAND3 is at a high level, and the output of the seventh inverter INV7 is at a low level. Then the output of the second NAND gate NAND2 is at a low level, and the output of the sixth inverter INV6 is at a high level. The outputs of CLK1 to CLK4 are respectively: high, high, low, and low. Then the seventh PMOS tube MP7 is turned off, the eighth NMOS tube MN8 is turned on, and one end of the third capacitor C3 is pulled down to the ground. The eighth PMOS tube MP8 is turned on, the ninth NMOS tube MN9 is turned off, and one end of the second capacitor C2 is raised to the power supply voltage, and the charge pump does not work.

[0042] like Figure 6 Shown is the operating waveform of the oscillator output clock signal CLK and the four outputs of the dead zone generating circuit when the IN terminal is at a high level.

[0043] When the IN terminal is at a low level, the output of the fourth inverter INV4 is at a high level, and the output of the first NAND gate NAND1 changes with the change of the CLK signal. When CLK is at a high level, the output of the first NAND gate NAND1 is at a low level, and when CLK is at a low level, the output of the first NAND gate NAND1 is at a high level. When the output of the first NAND gate NAND1 is at a low level, the output of the fifth inverter INV5 is at a high level, the output of the second NAND gate NAND2 is at a high level, the output of the third NAND gate NAND3 is at a low level, the output of the seventh inverter INV7 is at a high level, and the output of the sixth inverter INV6 is at a low level, then the outputs of CLK1 to CLK4 are low, low, high, and high respectively; at this time, the seventh PMOS tube MP7 is turned on, the eighth NMOS tube MN8 is turned off, and one end of the third capacitor C3 is raised to the power supply voltage; the eighth PMOS tube MP8 is turned off, the ninth NMOS tube MN9 is turned on, and one end of the second capacitor C2 is pulled down to the ground. When CLK turns to a low level, the output of the first NAND gate NAND1 turns to a high level, and the output states of CLK1 to CLK4 are consistent with the above description, namely: high, high, low, low; at this time, the seventh PMOS tube MP7 is turned off, the eighth NMOS tube MN8 is turned on, and one end of the third capacitor C3 is pulled down to the ground; the eighth PMOS tube MP8 is turned on, the ninth NMOS tube MN9 is turned off, and one end of the second capacitor C2 is raised to the power supply voltage. With the periodic change of the square wave signal at the oscillator output CLK end, the four outputs of the dead zone generation circuit also change periodically, and the second capacitor C2 and the third capacitor C3 are repeatedly charged and discharged, so that the output capacitor Cout voltage is raised. In order to prevent the output voltage from being too high, three voltage regulator diodes are connected between the output end and the floating ground, so that the output voltage can only be higher than the floating ground voltage by a fixed value. When it is further raised, these voltage regulator diodes will be reversely conducted, so that the output voltage will not be too high.

[0044] The working principle of the dead zone generation circuit is as follows:

[0045] When the IN terminal is at a low level, after the CLK signal changes from a low level to a high level, the output of the first NAND gate NAND1 changes to a low level, and the output of the second NAND gate NAND2 is at a high level. The output of the second NAND gate NAND2 changes the CLK2 terminal to a low level first through the sixth inverter INV6, and changes the CLK1 terminal to a low level after passing through the third NAND gate NAND3. The delay of the third NAND gate NAND3 is greater than that of the sixth inverter INV6, so that the CLK2 terminal changes to a low level first, the eighth NMOS tube MN8 is turned off first, the CLK1 terminal changes to a low level again, and the seventh PMOS tube MP7 is turned on later, so as to avoid the switch tubes being turned on at the same time; similarly, the output of the second NAND gate NAND2, i.e., the CLK3 terminal, is at a high level first, and then changes the CLK4 terminal to a high level after passing through the third NAND gate NAND3 and the seventh inverter INV7, so the eighth PMOS tube MP8 is turned off first, and the ninth NMOS tube MN9 is turned on later, so as to avoid the switch tubes being turned on at the same time. When CLK changes from a high level to a low level, the output of the first NAND gate NAND1 is a high level, and the output of the fifth inverter INV5 is a low level. The output of the third NAND gate NAND3 is first changed to a high level. The output of the third NAND gate NAND3 first changes the CLK4 terminal to a low level through the seventh inverter INV7, and changes the CLK3 terminal to a low level through the second NAND gate NAND2. The delay of the second NAND gate NAND2 is greater than that of the seventh inverter INV7, so that the CLK4 terminal is first at a low level, the ninth NMOS tube MN9 is first turned off, the CLK3 terminal is then at a low level, and the eighth PMOS tube MP8 is then turned on, so as to avoid the switch tubes being turned on at the same time; similarly, the output of the third NAND gate NAND3, that is, the CLK1 terminal, is first at a high level, and the output of the third NAND gate NAND3 changes the CLK2 terminal to a high level after passing through the second NAND gate NAND2 and the sixth inverter INV6, so the seventh PMOS tube MP7 is first turned off, and the ninth NMOS tube MN9 is then turned on, so as to avoid the switch tubes being turned on at the same time.

[0046] The introduction of the dead zone generation circuit can avoid the switch tubes being turned on at the same time, causing charge reverse flow, and at the same time greatly increases the conversion efficiency of the charge pump.

[0047] like Figure 7 The waveforms shown are those of the dead zone generating circuit when it is working, which are the waveforms of CLK, CLK1, CLK2, CLK3, and CLK4. There is a dead zone between CLK1 and CLK2, and between CLK3 and CLK4, which prevents the switches from being turned on at the same time.

[0048] like Figure 8 The waveform shown is when the charge pump is working. The low level of IN is effective. After IN becomes low level, the charge pump starts to work. When the power supply voltage VDD = 12V, HS = 0V, the temperature is 25℃, there is no load, and under the tt process angle, the HB output is 17V, and the output ripple is only 11mV.

[0049] The above contents are further detailed descriptions of the present invention in combination with specific / preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, they can also make several substitutions or modifications to these described embodiments without departing from the concept of the present invention, and these substitutions or modifications should be regarded as belonging to the protection scope of the present invention.

[0050] Parts of the present invention that are not described in detail belong to the well-known technologies of those skilled in the art.

Claims

1. A high performance charge pump circuit for high side driving, characterized in that: It includes an oscillator circuit, a dead zone generating circuit and a charge pump circuit; the oscillator circuit is used to generate a periodically changing square wave signal as a clock signal CLK of the dead zone generating circuit; the dead zone generating circuit processes the CLK signal to generate clock signals with certain dead zone times between each other; the charge pump circuit controls the charging or discharging of the capacitor by controlling the opening and closing of the switch tube through the signal generated by the dead zone generating circuit, accumulates the charge, and realizes voltage pumping.

2. A high performance charge pump circuit for high side driving according to claim 1, characterized in that: The oscillator circuit includes a first PMOS tube MP1, a second PMOS tube MP2, a third PMOS tube MP3, a fourth PMOS tube MP4, a fifth PMOS tube MP5, and a sixth PMOS tube MP6; a first NMOS tube MN1, a second NMOS tube MN2, a third NMOS tube MN3, a fourth NMOS tube MN4, a fifth NMOS tube MN5, a sixth NMOS tube MN6, and a seventh NMOS tube MN7; a first voltage zener diode Z1; a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4; a first inverter INV1, a second inverter INV2, a third inverter INV3, and a first variable capacitor C1; The substrate terminals of the first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are connected to the ground GND; the substrate terminals of the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6 are connected to the power supply VDD; one end of the first resistor R1, the source end of the first PMOS transistor MP1, the source end of the second PMOS transistor MP2, the source end of the third PMOS transistor MP3 and the source end of the fourth PMOS transistor MP4 are connected to the power supply VDD; the anode of the first voltage stabilizing diode Z1, one end of the second resistor R2, one end of the third resistor R3, the source end of the fifth NMOS transistor MN5, one end of the first variable capacitor C1, the source end of the sixth NMOS transistor MN6 and the source end of the seventh NMOS transistor MN7 are connected ground GND; the gate and drain of the first NMOS tube MN1 are connected to the gate of the second NMOS tube MN2 and the other end of the first resistor R1; the source of the first NMOS tube MN1 is connected to the cathode of the first voltage stabilizing diode Z1; the source of the second NMOS tube MN2 is connected to the other end of the second resistor R2; the first NMOS tube MN1 and the second NMOS tube MN2 form a current mirror link; the drain and gate of the first PMOS tube MP1 are connected to the gate of the second PMOS tube MP2, the third PMOS tube MP3, the fourth PMOS tube MP4 and the drain of the second NMOS tube MN2; the first PMOS tube MP1, the second PMOS tube MP2, the third PMOS tube MP3, the fourth PMOS tube MP4 form a current mirror link; The drain end of the second PMOS tube MP2 is connected to the drain end of the third NMOS tube MN3 and the gate end of the fourth NMOS tube MN4; the drain end of the third PMOS tube MP3 is connected to the drain end of the fourth NMOS tube MN4 and the input end of the first inverter INV1; the drain end of the fourth PMOS tube MP4 is connected to the source ends of the fifth PMOS tube MP5 and the sixth PMOS tube MP6; the source end of the third NMOS tube MN3 is connected to the source end of the fourth NMOS tube MN4 and the other end of the third resistor R3; the gate end of the third NMOS tube MN3 is connected to the drain end of the fifth NMOS tube MN5, the other end of the first variable capacitor C1, the drain end of the fifth PMOS tube MP5 and the input end of the sixth NMOS tube MP6. The output end of the third inverter INV3 is connected to the gate end of the fifth NMOS tube MN5; the output end of the first inverter INV1 is connected to the input end of the second inverter INV2 and the gate end of the sixth PMOS tube MP6; the output end of the second inverter INV2, i.e., the CLK end, is connected to the gate end of the fifth PMOS tube MP5; the drain end of the sixth PMOS tube MP6 is connected to one end of the fourth resistor R4; the other end of the fourth resistor R4 is connected to the gate end and the drain end of the seventh NMOS tube MN7 and the gate end of the sixth NMOS tube MN6; the sixth NMOS tube MN6 and the seventh NMOS tube MN7 form a current mirror link.

3. A high performance charge pump circuit for high side driving according to claim 2, characterized in that: In the oscillator circuit, the EN terminal is an enable signal, which is valid when the EN terminal is at a high level, that is, the oscillator works when the EN terminal is at a high level; the CLK terminal is the oscillator output signal; the CLK oscillation frequency is changed by changing the capacitance of the first variable capacitor C1; When EN is at a low level, the output of the third inverter INV3 is at a high level, so that the fifth NMOS tube MN5 is turned on, the gate voltage of the third NMOS tube MN3 is pulled down, and the third NMOS tube MN3 is turned off, so that the gate voltage of the fourth NMOS tube MN4 is pulled high, and the fourth NMOS tube MN4 is turned on, so that the input of the first inverter INV1 is pulled low; then the output of the second inverter INV2, that is, the CLK output end, is at a low level, and the fifth PMOS tube MP5 is turned on, the sixth PMOS tube MP6 is turned off, and the oscillator does not work; When EN turns to a high level, the output of the third inverter INV3 is a low level, so that the fifth NMOS tube MN5 is turned off. At this time, the current copied by the current mirror passes through the fifth PMOS tube MP5 to charge the first variable capacitor C1 below. At this time, the size of the capacitor charged is the bias current; when the voltage of the first variable capacitor C1 rises to the threshold voltage of the third NMOS tube MN3, the third NMOS tube MN3 is turned on, and the gate voltage of the fourth NMOS tube MN4 is pulled down, the fourth NMOS tube MN4 is turned off, the input of the first inverter INV1 becomes a high level, and the output of the second inverter INV2, that is, the CLK end, is a high level; at this time, the fifth PMOS tube MP5 is turned off, and the sixth PMOS tube M P6 is turned on, and the first capacitor C1 is discharged through the sixth PMOS tube MN6. At this time, the magnitude of the capacitor discharge is the bias current copied by the current mirror. After the discharge is lower than the threshold voltage of the third NMOS tube MN3, the third NMOS tube MN3 is turned off, and the gate voltage of the fourth NMOS tube MN4 is raised. The fourth NMOS tube MN4 is turned on, so that the input of the first inverter INV1 becomes a low level, and the output of the second inverter INV2, that is, the CLK end, is also a low level. At this time, the fifth PMOS tube MP5 is turned on, and the sixth PMOS tube MP6 is turned off. The current charges the first variable capacitor C1 through the fifth PMOS tube MP5, and this cycle is repeated to generate a periodically changing square wave signal.

4. A high performance charge pump circuit for high side driving according to claim 1 or 2, characterized in that: The dead zone generating circuit comprises a first NAND gate NAND1, a second NAND gate NAND2, a third NAND gate NAND3, a fourth inverter INV4, a fifth inverter INV5, a sixth inverter INV6 and a seventh inverter INV7; The input end of the fourth inverter INV4 is the charge pump control signal IN end, the output end of the fourth inverter INV4 is connected to the input end of the first NAND gate NAND1, and the other input end of the first NAND gate NAND1 is connected to the oscillator output clock signal CLK end; the output end of the first NAND gate NAND1 is connected to the input end of the fifth inverter INV5 and the input end of the second NAND gate NAND2; the output end of the third NAND gate NAND3 is connected to the other input end of the second NAND gate NAND2 and the input end of the seventh inverter INV7; the output end of the fifth inverter INV5 is connected to the input end of the third NAND gate NAND3; the output end of the second NAND gate NAND2 is connected to the other input end of the third NAND gate NAND3 and the input end of the sixth inverter INV6; the output end of the third NAND gate NAND3 is the CLK1 end, the output end of the sixth inverter INV6 is the CLK2 end, the output end of the second NAND gate NAND2 is the CLK3 end, and the output end of the seventh inverter INV7 is the CLK4 end.

5. A high performance charge pump circuit for high side driving according to claim 4, characterized in that: The charge pump circuit includes a second capacitor C2, a third capacitor C3, an output capacitor Cout, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, a first NPN transistor Q1, a second NPN transistor Q2, a third NPN transistor Q3, a second voltage zener diode Z2, a third voltage zener diode Z3, a fourth voltage zener diode Z4, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, an eighth NMOS transistor MN8 and a ninth NMOS transistor MN9; The gate ends of the seventh PMOS tube MP7, the eighth NMOS tube MN8, the eighth PMOS tube MP8 and the ninth NMOS tube MN9 are respectively connected to the four output ends CLK1, CLK2, CLK3 and CLK4 of the dead zone generating circuit; the source end of the seventh PMOS tube MP7 is connected to the power supply VDD; the drain end of the eighth NMOS tube MN8 is connected to the drain end of the seventh PMOS tube MP7 and one end of the third capacitor C3; the source end of the eighth NMOS tube MN8 is connected to the ground GND; the source end of the eighth PMOS tube MP8 is connected to the power supply VDD; the drain end of the ninth NMOS tube MN9 is connected to the drain end of the eighth PMOS tube MP8 and one end of the second capacitor C2; the source end of the ninth NMOS tube MN9 is connected to the ground GND; the other end of the second capacitor C2 is connected to one end of the sixth resistor R6; the third capacitor C3 is connected to one end of the fifth resistor R5; the other end of the sixth resistor R6 is connected to both ends of the eighth resistor R8, the second NPN tube Q 2 and the emitter of the third NPN tube Q3; the other end of the fifth resistor R5 is connected to the two ends of the seventh resistor R7 and the base of the first NPN tube Q1; the emitter of the first NPN tube Q1 is connected to the charge pump output terminal HB; the collector of the first NPN tube Q1 is connected to the emitter of the second NPN tube Q2; the base and collector of the third NPN tube Q3 are connected to one end of the ninth resistor R9; the other end of the ninth resistor R9 is connected to the floating ground terminal HS; the cathode of the second zener diode Z2 is connected to the charge pump output terminal HB; the anode of the second zener diode Z2 is connected to the cathode of the third zener diode Z3; the anode of the third zener diode Z3 is connected to the cathode of the fourth zener diode Z4; the anode of the fourth zener diode Z4 is connected to one end of the tenth resistor R10; the other end of the tenth resistor R10 is connected to the floating ground terminal HS; one end of the output capacitor Cout is connected to the charge pump output terminal HB; the other end of the output capacitor Cout is connected to the floating ground terminal HS.

6. A high performance charge pump circuit for high side driving according to claim 5, characterized in that: When the IN terminal is at a high level, the fourth inverter INV4 outputs a low level. No matter how CLK changes, the output of the first NAND gate NAND1 is always at a high level, the output of the fifth inverter INV5 is at a low level, the output of the third NAND gate NAND3 is at a high level, and the output of the seventh inverter INV7 is at a low level. Then the output of the second NAND gate NAND2 is at a low level, and the output of the sixth inverter INV6 is at a high level. The outputs of CLK1 to CLK4 are respectively: high, high, low, and low. Then the seventh PMOS tube MP7 is turned off, the eighth NMOS tube MN8 is turned on, and one end of the third capacitor C3 is pulled down to the ground. The eighth PMOS tube MP8 is turned on, the ninth NMOS tube MN9 is turned off, and one end of the second capacitor C2 is raised to the power supply voltage, and the charge pump does not work. When the IN terminal is at a low level, the output of the fourth inverter INV4 is at a high level, and the output of the first NAND gate NAND1 changes with the change of the CLK signal. When CLK is at a high level, the output of the first NAND gate NAND1 is at a low level, and when CLK is at a low level, the output of the first NAND gate NAND1 is at a high level; when the output of the first NAND gate NAND1 is at a low level, the output of the fifth inverter INV5 is at a high level, the output of the second NAND gate NAND2 is at a high level, the output of the third NAND gate NAND3 is at a low level, the output of the seventh inverter INV7 is at a high level, and the output of the sixth inverter INV6 is at a low level, then the outputs of CLK1 to CLK4 are respectively is low, low, high, high; at this time, the seventh PMOS tube MP7 is turned on, the eighth NMOS tube MN8 is turned off, and one end of the third capacitor C3 is raised to the power supply voltage; the eighth PMOS tube MP8 is turned off, the ninth NMOS tube MN9 is turned on, and one end of the second capacitor C2 is pulled down to the ground; when CLK turns to a low level, the output of the first NAND gate NAND1 turns to a high level, and the output states of CLK1 to CLK4 are respectively: high, high, low, low; at this time, the seventh PMOS tube MP7 is turned off, the eighth NMOS tube MN8 is turned on, and one end of the third capacitor C3 is pulled down to the ground; the eighth PMOS tube MP8 is turned on, the ninth NMOS tube MN9 is turned off, and one end of the second capacitor C2 is raised to the power supply voltage; As the square wave signal at the oscillator output CLK terminal changes periodically, the four outputs of the dead zone generating circuit also change periodically. The second capacitor C2 and the third capacitor C3 are repeatedly charged and discharged, causing the output capacitor Cout voltage to rise. In order to prevent the output voltage from being too high, three voltage zener diodes are connected between the output terminal and the floating ground, so that the output voltage can only be a fixed value higher than the floating ground voltage. When it rises further, these voltage zener diodes will conduct in the reverse direction, so that the output voltage will not be too high.

7. A high performance charge pump circuit for high side driving according to claim 6, characterized in that: The working principle of the dead zone generation circuit is as follows: When the IN terminal is at a low level, after the CLK signal changes from a low level to a high level, the output of the first NAND gate NAND1 changes to a low level, and the output of the second NAND gate NAND2 is a high level. The output of the second NAND gate NAND2 changes the CLK2 terminal to a low level first through the sixth inverter INV6, and changes the CLK1 terminal to a low level after passing through the third NAND gate NAND3. The delay of the third NAND gate NAND3 is greater than the sixth inverter INV6, so that the CLK2 terminal changes to a low level first, the eighth NMOS tube MN8 is turned off first, the CLK1 terminal changes to a low level again, and the seventh PMOS tube MP7 is turned on later to avoid the switch tubes being turned on at the same time; similarly, the output of the second NAND gate NAND2, that is, the CLK3 terminal, is first at a high level, and then changes the CLK4 terminal to a high level after passing through the third NAND gate NAND3 and the seventh inverter INV7, so the eighth PMOS tube MP8 is turned off first, and the ninth NMOS tube MN9 is turned on later to avoid the switch tubes being turned on at the same time; when CLK changes from a high level When it turns to a low level, the output of the first NAND gate NAND1 is a high level, and the output of the fifth inverter INV5 is a low level. The output of the third NAND gate NAND3 is first changed to a high level. The output of the third NAND gate NAND3 first changes the CLK4 end to a low level through the seventh inverter INV7, and changes the CLK3 end to a low level through the second NAND gate NAND2. The delay of the second NAND gate NAND2 is greater than that of the seventh inverter INV7, so that the CLK4 end is first at a low level, the ninth NMOS tube MN9 is first turned off, the CLK3 end is then at a low level, and the eighth PMOS tube MP8 is then turned on to avoid the switch tubes being turned on at the same time; similarly, the output of the third NAND gate NAND3, that is, the CLK1 end, is first at a high level, and the output of the third NAND gate NAND3 changes the CLK2 end to a high level after passing through the second NAND gate NAND2 and the sixth inverter INV6, so the seventh PMOS tube MP7 is first turned off, and the ninth NMOS tube MN9 is then turned on to avoid the switch tubes being turned on at the same time.

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