Deep hypothermia CMOS temperature sensor

Abstract

The invention relates to a deep hypothermia CMOS (complementary metal oxide semiconductor) temperature sensor, which is characterized in that on the basis of a quasi-linear relation between a threshold voltage and a temperature of a thick oxygen PMOS (P-channel Metal Oxide Semiconductor) device under deep hypothermia, current of the thick oxygen PMOS device under three different specific biases is extracted and arithmetic operation is carried out on the current to obtain a linear function about the threshold voltage of the thick oxygen PMOS device, so that temperature sensing under the deep hypothermia is realized. Compared with the prior art, the invention has the advantages of digital quantity output, small volume, compatibility with CMOS (Complementary Metal-Oxide-Semiconductor Transistor) process and the like.

Description

Technical Field

[0001] The invention relates to the field of CMOS temperature sensors, and in particular to a deep low temperature CMOS temperature sensor. Background Art

[0002] Temperature sensors can be roughly divided into two types: discrete and integrated.

[0003] Discrete temperature sensors rely on discrete components to achieve temperature sensing. One of their major drawbacks is that their output is analog. Therefore, when you want to obtain temperature information in digital form, you need to provide an external analog-to-digital converter. In addition, this type of temperature sensor also has the disadvantages of being large in size and incompatible with CMOS technology.

[0004] Integrated temperature sensors mainly refer to temperature sensors that use CMOS technology to integrate temperature sensing devices, digital readout circuits, and bias circuits on the same silicon chip, also known as CMOS temperature sensors. This type of temperature sensor can output digital temperature information by itself, so it can communicate directly with external digital circuits, reducing deployment costs.

[0005] For temperature measurement within the industrial temperature range (-40 to +125°C), CMOS temperature sensors are usually the main choice due to their advantages such as small size, high accuracy, easy integration, and digital output. They have been widely used in many scenarios such as system-on-chip, industrial Internet of Things, and wireless sensor networks.

[0006] For temperature measurements far from the industrial temperature range, existing CMOS temperature sensors are not competent, and only discrete temperature sensors such as thermocouples and resistance temperature detectors can be used. Such temperature sensors require external analog-to-digital converters to provide digital temperature information, so the deployment cost is high. In addition, such temperature sensors are difficult to use for on-chip temperature detection due to their large size and incompatibility with CMOS processes. Summary of the invention

[0007] The purpose of the present invention is to provide a deep cryogenic CMOS temperature sensor, which is based on the quasi-linear relationship between the threshold voltage and temperature of a thick oxygen PMOS device at deep cryogenic temperatures. By extracting the current of the thick oxygen PMOS device under three different specific biases and performing arithmetic operations on it, a linear function of the threshold voltage of the thick oxygen PMOS device is obtained, thereby realizing temperature perception at deep cryogenic temperatures, and meeting the real-time temperature monitoring on the chip in the liquid helium temperature range or even lower temperature ranges.

[0008] The purpose of the present invention can be achieved by the following technical solutions:

[0009] A deep low temperature CMOS temperature sensor, comprising:

[0010] A temperature sensing device bias control circuit is connected to the gate of the temperature sensing thick oxygen PMOS device to control the temperature sensing thick oxygen PMOS device to operate in different saturation region bias states;

[0011] A temperature-sensitive thick-oxygen PMOS device, whose gate is connected to the temperature-sensitive device bias control circuit and whose drain is connected to the input end of the capacitive transimpedance amplifier;

[0012] A capacitive transimpedance amplifier (CTIA), having an input end connected to the drain current of the temperature-sensitive thick oxygen PMOS device and an output end connected to the first comparator and the second comparator;

[0013] The comparator includes a first comparator and a second comparator, which respectively compare the output of the capacitive transimpedance amplifier with different thresholds;

[0014] an XOR gate, having input terminals connected to the outputs of the first comparator and the second comparator respectively, and an output terminal connected to the time-to-digital converter;

[0015] Time-to-Digital Converter (TDC), which quantifies the drain current of the temperature-sensitive thick oxygen PMOS device working in different saturation region bias states according to the output of the XOR gate, and outputs a digital code value;

[0016] The deep cryogenic CMOS temperature sensor calculates a temperature value according to the digital code value.

[0017] The temperature sensing device bias control circuit includes three bias setting switches, only one bias setting switch remains in a closed state at the same time, one end of the bias setting switch is respectively connected to different external bias voltages, and the other end is commonly connected to the gate of the temperature sensing thick oxygen PMOS device, so that three different gate voltages are set for the temperature sensing thick oxygen PMOS device, so that it works in three saturation region bias states.

[0018] The capacitive transimpedance amplifier includes an operational amplifier, a reset switch and an integrating capacitor, wherein the reset switch and the integrating capacitor are connected in parallel between the negative input terminal and the output terminal of the operational amplifier, and the positive input terminal of the operational amplifier is connected to a preset reference voltage input.

[0019] The negative input terminals of the first comparator and the second comparator are connected to the output of the capacitive transimpedance amplifier, and the positive input terminals are connected to the first comparison voltage and the second comparison voltage respectively, wherein the first comparison voltage is greater than the second comparison voltage.

[0020] The reference voltage is greater than the first comparison voltage.

[0021] The initialization process of the deep cryogenic CMOS temperature sensor is as follows: a certain bias setting switch is closed, the temperature-sensitive thick oxygen PMOS device is under the corresponding bias, and its drain voltage is set as the reference voltage by the operational amplifier; the reset switch of the capacitive transimpedance amplifier is closed, and its output is fixed to the reference voltage. According to the magnitude relationship between the reference voltage, the first comparison voltage and the second comparison voltage, the outputs of the first comparator and the second comparator are both low level, and the output of the XOR gate remains low level; the time-to-digital converter is in a non-working state.

[0022] The measurement process of the deep low temperature CMOS temperature sensor is as follows: after the initialization is completed, the reset switch is turned on, at which time the temperature-sensitive thick oxygen PMOS device is still under the corresponding bias, and at the same time, the drain current of the temperature-sensitive thick oxygen PMOS device flows into the integral capacitor of the capacitive transimpedance amplifier, and the output voltage of the capacitive transimpedance amplifier decreases linearly from the reference voltage, and its change rate is proportional to the magnitude of the drain current of the temperature-sensitive thick oxygen PMOS device;

[0023] When the output voltage of the capacitive transimpedance amplifier drops to the first comparison voltage, the output voltage of the first comparator flips from a low level to a high level, and the output voltage of the second comparator remains at a low level. At this time, the output voltage of the XOR gate flips from a low level to a high level, enabling the time-to-digital converter to start working;

[0024] When the output voltage of the capacitive transimpedance amplifier further drops to the second comparison voltage, the output voltage of the second comparator flips from a low level to a high level, and the output voltage of the first comparator remains at a high level. At this time, the output voltage of the XOR gate flips from a high level to a low level, and the time-to-digital converter stops working.

[0025] When the output voltage of the XOR gate is at a high level, the time-to-digital converter is enabled to convert the time when the output voltage of the XOR gate is at a high level into a digital code value, the size of which is inversely proportional to the drain current of the temperature-sensitive thick oxygen PMOS device.

[0026] The setting of the external bias voltage satisfies the following conditions: in the first saturation region bias state, the first bias setting switch is closed, and the gate voltage of the temperature-sensitive thick oxygen PMOS device is set to the first external bias voltage; in the second saturation region bias state, the second bias setting switch is closed, and the gate voltage of the temperature-sensitive thick oxygen PMOS device is set to the second external bias voltage; in the third saturation region bias state, the third bias setting switch is closed, and the gate voltage of the temperature-sensitive thick oxygen PMOS device is set to the third external bias voltage;

[0027] The first external bias voltage minus the source voltage of the temperature-sensitive thick oxygen PMOS device is recorded as the first gate-source voltage, the second external bias voltage minus the source voltage of the temperature-sensitive thick oxygen PMOS device is recorded as the second gate-source voltage, and the third external bias voltage minus the source voltage of the temperature-sensitive thick oxygen PMOS device is recorded as the third gate-source voltage, satisfying: the sum of the first gate-source voltage and the second gate-source voltage is equal to twice the third gate-source voltage.

[0028] The method for calculating the temperature value of the deep cryogenic CMOS temperature sensor according to the digital code value is as follows:

[0029]

[0030] Among them, D 1 , D 2 , D 3 They are the digital code values ​​corresponding to the first, second and third bias setting switches being closed; A and B are coefficients obtained by calibration through a known temperature and the corresponding digital code value.

[0031] Compared with the prior art, the present invention has the following beneficial effects:

[0032] The present invention is based on the quasi-linear relationship between the threshold voltage and temperature of the thick oxygen PMOS device at deep low temperatures. By extracting the current of the thick oxygen PMOS device under three different specific biases and performing arithmetic operations on it, a linear function of the threshold voltage of the thick oxygen PMOS device is obtained to achieve temperature perception at deep low temperatures, which has the advantages of simple perception method and accurate perception results. In addition, the deep low temperature sensor of the present invention is an integrated temperature sensor, which has the advantages of digital output, small size, and compatibility with CMOS technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 It is a structural schematic diagram of the deep low temperature CMOS temperature sensor of the present invention;

[0034] Figure 2 A circuit diagram of a deep cryogenic CMOS temperature sensor in one embodiment. DETAILED DESCRIPTION

[0035] The present invention is described in detail below in conjunction with the accompanying drawings and specific embodiments. This embodiment is implemented based on the technical solution of the present invention, and provides a detailed implementation method and specific operation process, but the protection scope of the present invention is not limited to the following embodiments.

[0036] The rapid development of new applications such as quantum computing, low-temperature superconductivity, and very long wave detection has put forward the demand for real-time on-chip temperature monitoring in the liquid helium temperature range or even lower temperature range.

[0037] Based on this, this embodiment provides a deep low temperature CMOS temperature sensor, such as Figure 1 As shown, including:

[0038] The temperature sensing device bias control circuit 1 is connected to the gate of the temperature sensing thick oxygen PMOS device 2 to control the temperature sensing thick oxygen PMOS device 2 to work in different saturation region bias states;

[0039] A temperature-sensitive thick-oxygen PMOS device 2, whose gate is connected to the temperature-sensitive device bias control circuit 1, and whose drain is connected to the input end of the capacitive transimpedance amplifier 3;

[0040] A capacitive transimpedance amplifier 3, whose input end is connected to the drain current of the temperature-sensitive thick oxygen PMOS device 2, and whose output end is connected to the first comparator 41 and the second comparator 42;

[0041] The comparator 4 includes a first comparator 41 and a second comparator 42, which compare the output of the capacitive transimpedance amplifier 3 with different thresholds respectively;

[0042] an XOR gate 5 , whose input terminals are respectively connected to the outputs of the first comparator 41 and the second comparator 42 , and whose output terminals are connected to the time-to-digital converter 6 ;

[0043] The time-to-digital converter 6 quantizes the drain current of the temperature-sensitive thick oxygen PMOS device 2 working in different saturation region bias states according to the output of the XOR gate 5 and outputs a digital code value;

[0044] The deep cryogenic CMOS temperature sensor calculates a temperature value according to the digital code value.

[0045] In one embodiment, if Figure 2 As shown, the temperature sensing device bias control circuit 1 includes three bias setting switches, namely a first bias setting switch 11, a second bias setting switch 12, and a third bias setting switch 13. Only one bias setting switch remains in a closed state at the same time. One end of the bias setting switch is connected to different external bias voltages, and the other end is commonly connected to the gate of the temperature sensing thick oxygen PMOS device 2. Three different gate voltages are set for the temperature sensing thick oxygen PMOS device 2, so that it works in three saturation region bias states.

[0046] Regardless of the saturation bias state, the source voltage of the temperature-sensitive thick oxygen PMOS device 2 is set to V b1 In the first saturation region bias state, the first bias setting switch 11 is closed, and the gate voltage of the temperature-sensitive thick oxygen PMOS device 2 is set to the first external bias voltage V b2 In the second saturation region bias state, the second bias setting switch 12 is closed, and the gate voltage of the temperature-sensitive thick oxygen PMOS device 2 is set to the second external bias voltage Vb3 In the third saturation region bias state, the third bias setting switch 13 is closed, and the gate voltage of the temperature-sensitive thick oxygen PMOS device 2 is set to the third external bias voltage V b4 .

[0047] The first external bias voltage V b2 Subtract the source voltage V of the temperature-sensitive thick oxygen PMOS device 2 b1 is the first gate-source voltage V GS1 , the second external bias voltage V b3 Subtract the source voltage V of the temperature-sensitive thick oxygen PMOS device 2 b1 is the second gate-source voltage V GS2 , the third external bias voltage V b4 Subtract the source voltage V of the temperature-sensitive thick oxygen PMOS device 2 b1 is the third gate-source voltage V GS3 .

[0048] Satisfies: The first gate-source voltage V GS1 and the second gate-source voltage V GS2 The sum is equal to twice the third gate-source voltage V GS3 , that is, V GS1 +V GS2 =2V GS3 .

[0049] like Figure 2 As shown, the capacitive transimpedance amplifier 3 includes an operational amplifier 31, a reset switch 32 and an integral capacitor 33, wherein the reset switch 32 and the integral capacitor 33 are connected in parallel between the negative input terminal and the output terminal of the operational amplifier 31, and the positive input terminal of the operational amplifier 31 is connected to a preset reference voltage input, and the reference voltage is recorded as V REF .

[0050] The negative input terminals of the first comparator 41 and the second comparator 42 are connected to the output of the capacitive transimpedance amplifier 3, and the positive input terminals are connected to the first comparison voltage V R1 and the second comparison voltage V R2 , where the first comparison voltage V R1 Greater than the second comparison voltage V R2 .

[0051] In this embodiment, the reference voltage V REF Greater than the first comparison voltage V R1 That is, V REF >V R1 >V R2 .

[0052] like Figure 2 As shown, the external bias V b1Set the source voltage of the temperature-sensitive thick oxygen PMOS device 2; one end of the bias setting switch 1-3 is connected to the external bias V b2 -V b4 , the other end is connected to the gate of the temperature-sensitive thick oxygen PMOS device 2, and three different gate voltages are set for the temperature-sensitive thick oxygen PMOS device 2 to make it work in Bias1-Bias3; the operational amplifier 31, the reset switch 32 and the integrating capacitor 33 together constitute a capacitive transimpedance amplifier 3 (CTIA), whose input is the drain current 22 of the temperature-sensitive thick oxygen PMOS device, and its output voltage 34 is provided to the first and second comparators 41, 42; the input of the XOR gate 5 is the output voltages 43, 44 of the first and second comparators, and its output 52 is provided to the time-to-digital converter 6 (TDC).

[0053] The initialization process of the deep cryogenic CMOS temperature sensor is as follows: one of the bias setting switches 11, 12 or 13 is closed, and the other two bias setting switches are kept open. The temperature-sensitive thick oxygen PMOS device 2 is placed under the corresponding bias Bias1, Bias2 or Bias3, and its drain voltage is set to the reference voltage V by the operational amplifier 31. REF The reset switch 32 of the capacitive transimpedance amplifier 3 is closed, and its output 34 is fixed to the reference voltage. According to the magnitude relationship among the reference voltage, the first comparison voltage and the second comparison voltage, the outputs 43 and 44 of the first comparator 41 and the second comparator 42 are both low level, and the output 52 of the XOR gate 5 remains low level; the time-to-digital converter 6 is in a non-working state.

[0054] The measurement process of the deep low temperature CMOS temperature sensor is as follows: after the initialization is completed, the reset switch 32 is turned on. At this time, the temperature-sensitive thick oxygen PMOS device 2 is still under the corresponding bias Bias1, Bias2 or Bias3. At the same time, the drain current 22 of the temperature-sensitive thick oxygen PMOS device 2 flows into the integral capacitor 33 of the capacitive transimpedance amplifier 3, and the output voltage 34 of the capacitive transimpedance amplifier 3 is increased from the reference voltage V REF It starts to decrease linearly, and its rate of change is proportional to the magnitude of the drain current 22 of the temperature-sensitive thick oxygen PMOS device 2;

[0055] When the output voltage 34 of the capacitive transimpedance amplifier 3 drops to the first comparison voltage V R1 When , the output voltage 43 of the first comparator 41 flips from a low level to a high level, and the output voltage 44 of the second comparator 42 is still at a low level. At this time, the output voltage 52 of the XOR gate 5 flips from a low level to a high level, enabling the time-to-digital converter 6 to start working;

[0056] When the output voltage 34 of the capacitive transimpedance amplifier 3 further drops to the second comparison voltage V R2When , the output voltage 44 of the second comparator 42 flips from a low level to a high level, and the output voltage 43 of the first comparator 41 remains at a high level. At this time, the output voltage 52 of the XOR gate 5 flips from a high level to a low level, and the time-to-digital converter 6 stops working.

[0057] During the period when the output voltage 52 of the XOR gate 5 is at a high level, the time-to-digital converter 6 is enabled, and converts the time when the output voltage 52 of the XOR gate 5 is at a high level into a digital code value D, the size of the digital code value is inversely proportional to the size of the drain current 22 of the temperature-sensitive thick oxygen PMOS device 2.

[0058] Close the bias setting switches 11, 12 and 13 respectively, perform the above initialization process and measurement process, and obtain the corresponding digital code value D 1 , D 2 , D 3 At this point, the circuit has completed the quantification of the drain current 22 of the temperature-sensitive thick oxygen PMOS device under different biases Bias1-3.

[0059] Next, the mathematical relationship between temperature and drain current 22 of the temperature-sensitive thick oxygen PMOS device is derived.

[0060] In the temperature sensor of this embodiment, the temperature sensing device is a thick oxygen PMOS, which will be placed in three different saturation region biases Bias1-Bias3 (under these three biases, the drain-source voltage of the PMOS is the same and the source is short-circuited with the substrate), and its current can be expressed as

[0061]

[0062] Among them, subscripts 1-3 correspond to three different biases Bias1-Bias3; D1 ,I D2 ,I D3 are the drain currents of the temperature-sensitive thick oxygen PMOS device when it is biased at Bias1, Bias2, and Bias3 respectively; μ P is the mobility of the thick oxide PMOS device; C ox is the gate oxide capacitance per unit area of ​​the thick oxide PMOS device; W is the gate width of the temperature-sensitive thick oxide PMOS device; L is the gate length of the temperature-sensitive thick oxide PMOS device; V GS1 、V GS2 、V GS3 are the gate-source voltages of the temperature-sensitive thick oxygen PMOS device when it is in bias Bias1, Bias2, and Bias3 respectively; V TH is the threshold voltage of the temperature-sensitive thick oxygen PMOS device; P is the channel length modulation coefficient of the temperature-sensitive thick oxygen PMOS device; V DSis the drain-source voltage of the temperature-sensitive thick oxygen PMOS device.

[0063] From (1.1) and (1.2) we can get

[0064]

[0065] According to V GS1 +V GS2 =2V GS3 , can be obtained

[0066]

[0067] From (1.3) and (1.5) we can get

[0068]

[0069] in,

[0070] The threshold voltage V of PMOS at deep low temperature TH Can be modeled as

[0071] V TH =V TH0 +C VTH ·(TT 0 )(1.7)

[0072] Among them, C VTH is the first-order temperature dependence of the threshold voltage, V TH0 is the threshold voltage of the temperature-sensitive thick oxygen PMOS device at room temperature, T 0 It is room temperature.

[0073] From (1.6) and (1.7) we can get

[0074]

[0075] in,

[0076] According to (1.8), I D3 / (I D2 -I D1 ) is linearly related to temperature. After A and B are determined by two-point calibration, I D3 / (I D2 -I D1 ) to obtain the temperature value.

[0077] According to the derivation in the previous text, the size of the digital code value is inversely proportional to the size of the drain current 22 of the temperature-sensitive thick oxygen PMOS device 2. Therefore, according to (1.8), the calculation method of the deep low temperature CMOS temperature sensor to calculate the temperature value according to the digital code value is:

[0078]

[0079] Among them, D 1 , D 2 , D 3 They are the digital code values ​​corresponding to the first, second and third bias setting switches being closed.

[0080] The preferred specific embodiments of the present invention are described in detail above. It should be understood that a person skilled in the art can make many modifications and changes based on the concept of the present invention without creative work. Therefore, any technical solution that can be obtained by a person skilled in the art through logical analysis, reasoning, or limited experiments based on the concept of the present invention on the basis of the prior art should be within the scope of protection determined by the claims.

Claims

1. A deep cryogenic CMOS temperature sensor, characterized in that: include: A temperature sensing device bias control circuit (1) is connected to the gate of the temperature sensing thick oxygen PMOS device (2) to control the temperature sensing thick oxygen PMOS device (2) to operate in different saturation region bias states; A temperature-sensitive thick-oxygen PMOS device (2), whose gate is connected to a temperature-sensitive device bias control circuit (1) and whose drain is connected to an input end of a capacitive transimpedance amplifier (3); A capacitive transimpedance amplifier (3), the input end of which is connected to the drain current of the temperature-sensitive thick oxygen PMOS device (2), and the output end of which is connected to the first comparator (41) and the second comparator (42); A comparator (4), comprising a first comparator (41) and a second comparator (42), for performing comparisons based on the output of the capacitive transimpedance amplifier (3) and different thresholds respectively; An XOR gate (5), the input end of which is respectively connected to the output of the first comparator (41) and the output end of which is connected to the time-to-digital converter (6); A time-to-digital converter (6) quantizes the drain current of the temperature-sensitive thick oxygen PMOS device (2) operating in different saturation region bias states according to the output of the XOR gate (5), and outputs a digital code value; The deep cryogenic CMOS temperature sensor calculates a temperature value according to the digital code value.

2. A deep cryogenic CMOS temperature sensor according to claim 1, characterized in that: The temperature sensing device bias control circuit (1) comprises three bias setting switches, only one bias setting switch remains in a closed state at the same time, one end of the bias setting switch is respectively connected to different external bias voltages, and the other end is commonly connected to the gate of the temperature sensing thick oxygen PMOS device (2), so that three different gate voltages are set for the temperature sensing thick oxygen PMOS device (2) so that it works in three saturation region bias states.

3. A deep cryogenic CMOS temperature sensor according to claim 1, characterized in that: The capacitive transimpedance amplifier (3) comprises an operational amplifier (31), a reset switch (32) and an integrating capacitor (33), wherein the reset switch (32) and the integrating capacitor (33) are connected in parallel between a negative input terminal and an output terminal of the operational amplifier (31), and the positive input terminal of the operational amplifier (31) is connected to a preset reference voltage input.

4. A deep cryogenic CMOS temperature sensor according to claim 3, characterized in that: The negative input terminals of the first comparator (41) and the second comparator (42) are connected to the output of the capacitive transimpedance amplifier (3), and the positive input terminals are connected to a first comparison voltage and a second comparison voltage respectively, wherein the first comparison voltage is greater than the second comparison voltage.

5. A deep cryogenic CMOS temperature sensor according to claim 4, characterized in that: The reference voltage is greater than the first comparison voltage.

6. A deep cryogenic CMOS temperature sensor according to claim 5, characterized in that: The initialization process of the deep cryogenic CMOS temperature sensor is as follows: a certain bias setting switch is closed, the temperature-sensitive thick oxygen PMOS device (2) is under a corresponding bias, and its drain voltage is set as a reference voltage by an operational amplifier (31); the reset switch (32) of the capacitive transimpedance amplifier (3) is closed, and its output is fixed to the reference voltage. According to the magnitude relationship between the reference voltage, the first comparison voltage and the second comparison voltage, the outputs of the first comparator (41) and the second comparator (42) are both low level, and the output of the XOR gate (5) remains low level; the time-to-digital converter (6) is in a non-working state.

7. A deep cryogenic CMOS temperature sensor according to claim 6, characterized in that: The measurement process of the deep low temperature CMOS temperature sensor is as follows: after initialization is completed, the reset switch (32) is turned on, at which time the temperature-sensitive thick oxygen PMOS device (2) is still under the corresponding bias, and at the same time, the drain current of the temperature-sensitive thick oxygen PMOS device (2) flows into the integral capacitor (33) of the capacitive transimpedance amplifier (3), and the output voltage of the capacitive transimpedance amplifier (3) decreases linearly from the reference voltage, and its change rate is proportional to the magnitude of the drain current of the temperature-sensitive thick oxygen PMOS device (2); When the output voltage of the capacitive transimpedance amplifier (3) drops to the first comparison voltage, the output voltage of the first comparator (41) flips from a low level to a high level, and the output voltage of the second comparator (42) remains at a low level. At this time, the output voltage of the XOR gate (5) flips from a low level to a high level, enabling the time-to-digital converter (6) to start working; When the output voltage of the capacitive transimpedance amplifier (3) further drops to the second comparison voltage, the output voltage of the second comparator (42) flips from a low level to a high level, and the output voltage of the first comparator (41) remains at a high level. At this time, the output voltage of the XOR gate (5) flips from a high level to a low level, and the time-to-digital converter (6) stops working.

8. The deep cryogenic CMOS temperature sensor according to claim 1, characterized in that: During the period when the output voltage of the XOR gate (5) is at a high level, the time-to-digital converter (6) is enabled to convert the time when the output voltage of the XOR gate (5) is at a high level into a digital code value, wherein the magnitude of the digital code value is inversely proportional to the magnitude of the drain current of the temperature-sensitive thick oxygen PMOS device (2).

9. The deep cryogenic CMOS temperature sensor according to claim 2, characterized in that: The setting of the external bias voltage satisfies the following conditions: in a first saturation region bias state, the first bias setting switch (11) is closed, and the gate voltage of the temperature-sensitive thick oxygen PMOS device (2) is set to the first external bias voltage; in a second saturation region bias state, the second bias setting switch (12) is closed, and the gate voltage of the temperature-sensitive thick oxygen PMOS device (2) is set to the second external bias voltage; in a third saturation region bias state, the third bias setting switch (13) is closed, and the gate voltage of the temperature-sensitive thick oxygen PMOS device (2) is set to the third external bias voltage; The first external bias voltage minus the source voltage of the temperature-sensitive thick oxygen PMOS device is recorded as the first gate-source voltage, the second external bias voltage minus the source voltage of the temperature-sensitive thick oxygen PMOS device is recorded as the second gate-source voltage, and the third external bias voltage minus the source voltage of the temperature-sensitive thick oxygen PMOS device is recorded as the third gate-source voltage, satisfying: the sum of the first gate-source voltage and the second gate-source voltage is equal to twice the third gate-source voltage.

10. The deep cryogenic CMOS temperature sensor according to claim 9, characterized in that: The method for calculating the temperature value of the deep cryogenic CMOS temperature sensor according to the digital code value is as follows: Wherein, D1, D2, and D3 are the digital code values ​​corresponding to the first, second, and third bias setting switches being closed, respectively; A and B are coefficients obtained by calibration through a known temperature and the corresponding digital code value.

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