Signal jump edge rise time detection device and method

Abstract

The invention relates to a signal jump edge rise time detection device and method, and the device comprises an XOR combinational logic module which is used for carrying out the XOR logic processing of a comparison signal outputted by a PE module, and obtaining a feed-in signal; the control module is connected with the XOR combinational logic module and is used for sampling and analyzing the feed-in signal and determining the time difference between the front edge and the rear edge of the feed-in signal; the rising time of the signal edge is calculated according to the time difference and the front and back edge delay parameters sent by the carry chain module; and the carry chain module is connected with the control module, and is used for obtaining delay parameters corresponding to the front and rear edges of the feed-in signal when the control module determines the front and rear edges of the feed-in signal, obtaining the delay parameters of the front and rear edges, and sending the delay parameters to the control module. The rising time of the signal edge is obtained by analyzing the time difference between the front edge and the rear edge of the feed-in signal and combining the delay parameters corresponding to the front edge and the rear edge of the feed-in signal, the rising time of the signal jump edge can be detected by adopting a universal chip, and the design complexity is reduced.

Description

Technical Field

[0001] The present application relates to the technical field of signal processing, and in particular to a device and method for detecting the rise time of a signal transition edge. Background Art

[0002] Timing Generator (TG, timing generation module) is an important component of the tester. It is responsible for synthesizing the output waveform according to the user's requirements and sampling the input signal according to the sampling time configured by the user. When detecting the signal transition edge, the clock or signal needs to be delayed. The traditional signal transition edge detection method is to use a dedicated time measurement circuit (TDC) chip to achieve this. The measurement of the rise time requires not only a TDC chip, but also additional auxiliary circuits. The implementation structure is complex and has the disadvantage of high design complexity. Summary of the invention

[0003] Based on this, it is necessary to provide a signal transition edge rise time detection device and method that can reduce the design complexity in order to address the above problems.

[0004] A signal transition edge rise time detection device, comprising:

[0005] XOR combination logic module, used for performing XOR logic processing on the comparison signal output by the PE module to obtain a feed-in signal;

[0006] A control module, connected to the XOR combinational logic module, for sampling and analyzing the feed signal, determining the time difference between the leading and trailing edges of the feed signal; and calculating the rising time of the signal edge according to the time difference and the leading and trailing edge delay parameters sent by the carry chain module;

[0007] The carry chain module is connected to the control module and is used to obtain the delay parameters corresponding to the leading and trailing edges of the feed signal when the control module determines the leading and trailing edges of the feed signal, and obtain the leading and trailing edge delay parameters and send them to the control module.

[0008] In one of the embodiments, the control module includes a pulse width measurement control unit and a counter unit, and the pulse width measurement control unit is connected to the counter unit, the XOR combination logic module and the carry chain module;

[0009] The pulse width measurement control unit is used to sample the feed signal, control the counter unit to count according to the detected leading and trailing edges of the feed signal, and determine the time difference between the leading and trailing edges of the feed signal;

[0010] The pulse width measurement control unit is further used to transmit the feed signal to the carry chain module, and control the carry chain module to capture the delay parameters corresponding to the leading and trailing edges of the feed signal.

[0011] In one of the embodiments, the pulse width measurement control unit samples the feed signal according to a clock signal, controls the counter unit to start timing according to the clock signal when a rising edge of the feed signal is identified, and controls the counter unit to stop timing when a falling edge of the feed signal is identified; the pulse width measurement control unit obtains the time difference between the leading and trailing edges of the feed signal according to the count value of the counter unit and the clock cycle.

[0012] In one embodiment, the carry chain module includes a CARRY unit, a trigger, an XOR gate logic unit and a tap acquisition unit, the number of the CARRY units is at least two, the number of the triggers is the same as the number of the CARRY units, the CARRY units are connected in sequence, and the CARRY unit located at the head end is connected to the pulse width measurement control unit; each trigger is respectively connected to the tap of a corresponding CARRY unit, the XOR gate logic unit connects the trigger and the tap acquisition unit, and the tap acquisition unit is connected to the pulse width measurement control unit; the trigger inputs the signal of each adjacent two taps of the corresponding CARRY unit into the same XOR gate logic unit.

[0013] In one embodiment, the delay parameter is a tap value; when the rising edge of the feed signal is identified, the pulse width measurement control unit captures and locks the tap value at the signal edge position in the carry chain module; when the falling edge of the feed signal is identified, it delays one beat to capture and lock the tap value at the signal edge position in the carry chain module.

[0014] In one of the embodiments, the pulse width measurement control unit determines the time of the corresponding signal edge relative to the clock signal based on the captured tap value and the resolution of a single tap of the CARRY unit; the pulse width measurement control unit calculates the rise time of the signal edge based on the time difference between the leading and trailing edges of the feed signal and the time of the corresponding signal edge relative to the clock signal.

[0015] In one embodiment, the signal transition edge rise time detection device further includes:

[0016] The PE module is connected to the device under test and the XOR combination logic module, and is used to compare and judge the input signal fed back by the device under test according to a preset level threshold value, and output a comparison signal.

[0017] In one embodiment, the comparison signal output by the PE module includes an output signal CA and an output signal CB, and the preset level threshold value includes a threshold value VOL and a threshold value VOH; when the input signal is less than the threshold value VOL, the output signal CA is at a low level, and the output signal CB is at a low level; when the input signal is greater than or equal to the threshold value VOL and less than or equal to the threshold value VOH, the output signal CA is at a low level, and the output signal CB is at a high level; when the input signal is greater than the threshold value VOH, the output signal CA is at a high level, and the output signal CB is at a high level.

[0018] A signal transition edge rise time detection method, comprising:

[0019] The XOR combination logic module performs XOR logic processing on the comparison signal output by the PE module to obtain a feed-in signal;

[0020] The control module samples and analyzes the input signal to determine the time difference between the leading and trailing edges of the input signal;

[0021] When the control module determines the leading and trailing edges of the feed-in signal, the carry chain module obtains the delay parameters corresponding to the leading and trailing edges of the feed-in signal to obtain the leading and trailing edge delay parameters;

[0022] The control module calculates the rising time of the signal edge according to the time difference and the leading and trailing edge delay parameters.

[0023] In one embodiment, the control module includes a pulse width measurement control unit and a counter unit, and the control module performs sampling analysis on the feed signal to determine the time difference between the leading and trailing edges of the feed signal, including:

[0024] The pulse width measurement control unit samples the feed signal according to the clock signal, controls the counter unit to start timing according to the clock signal when a rising edge of the feed signal is identified, and controls the counter unit to stop timing when a falling edge of the feed signal is identified;

[0025] The pulse width measurement control unit obtains the time difference between the leading and trailing edges of the input signal according to the count value of the counter unit and the clock cycle.

[0026] In one embodiment, the delay parameter is a tap value, and the control module calculates the rise time of the signal edge according to the time difference and the leading and trailing edge delay parameters, including:

[0027] The pulse width measurement control unit grabs the tap value at the position where the signal edge is located in the carry chain module when the rising edge of the feed signal is identified; and delays one beat to grab the tap value at the position where the signal edge is located in the carry chain module when the falling edge of the feed signal is identified;

[0028] The pulse width measurement control unit determines the time of the corresponding signal edge relative to the clock signal according to the captured tap value and the resolution of a single tap of the CARRY unit in the carry chain module;

[0029] The pulse width measurement control unit calculates the rising time of the signal edge according to the time difference between the leading and trailing edges of the input signal and the time of the corresponding signal edge relative to the clock signal.

[0030] In one embodiment, before the XOR combination logic module performs XOR logic processing on the comparison signal output by the PE module to obtain the feed-in signal, the method further includes:

[0031] The PE module compares and judges the input signal fed back by the device to be tested according to the preset level threshold value, and outputs a comparison signal.

[0032] The above-mentioned signal transition edge rise time detection device and method performs XOR logic processing on the comparison signal output by the PE module through the XOR combination logic module to obtain the feed signal. The control module samples and analyzes the feed signal to determine the time difference between the front and back edges of the feed signal. When the control module determines the front and back edges of the feed signal, the carry chain module obtains the delay parameters corresponding to the front and back edges of the feed signal, obtains the front and back edge delay parameters and sends them to the control module. The control module calculates the rise time of the signal edge based on the time difference and the front and back edge delay parameters sent by the carry chain module. The control module samples and analyzes the time difference between the front and back edges of the feed signal, and combines the delay parameters corresponding to the front and back edges of the feed signal captured by the carry chain module to obtain the rise time of the signal edge. A general chip can be used to implement the signal transition edge rise time detection, thereby reducing the design complexity. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 It is a structural principle diagram of a signal transition edge rise time detection device in one embodiment;

[0034] Figure 2 is a structural schematic diagram of a carry chain module in one embodiment;

[0035] Figure 3 1 is a flow chart of a method for detecting the rising time of a signal transition edge in one embodiment;

[0036] Figure 4 A schematic diagram of a flow chart of a signal transition edge rise time detection method in another embodiment;

[0037] Figure 5 A flow chart of a signal transition edge rise time detection function implementation in one embodiment;

[0038] Figure 6 A schematic diagram of signal conversion of a PE module in one embodiment;

[0039] Figure 7 FIG. 1 is a schematic diagram of the timing principle of rise time measurement in an embodiment. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0042] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if the connected circuits, modules, units, etc. have electrical signals or data transmission between each other.

[0043] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" etc. specify the presence of stated features, wholes, operations, components, parts or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, operations, components, parts or combinations thereof.

[0044] When detecting the signal transition edge, it is necessary to delay the clock or signal. At present, the equipment on the market is generally implemented with a dedicated delay measurement circuit chip, such as a TDC chip. The dedicated chip only realizes the TDC function, has a single function, and needs to cooperate with the peripheral circuit to realize the rise time measurement. Moreover, the dedicated chip occupies a large area of ​​the printed circuit board. Based on this, the present application provides a signal transition edge rise time detection device, which performs XOR logic processing on the comparison signal output by the PE module through the XOR combination logic module to obtain the feed signal. The control module samples and analyzes the feed signal to determine the time difference between the front and back edges of the feed signal. When the control module determines the front and back edges of the feed signal, the carry chain module obtains the delay parameters corresponding to the front and back edges of the feed signal, obtains the front and back edge delay parameters and sends them to the control module. The control module calculates the rise time of the signal edge according to the time difference and the front and back edge delay parameters sent by the carry chain module. The control module samples and analyzes the time difference between the leading and trailing edges of the input signal, and combines the delay parameters corresponding to the leading and trailing edges of the input signal captured by the carry chain module to obtain the rise time of the signal edge. A general FPGA (Field Programmable Gate Array) chip can be used to implement the signal transition edge rise time detection function, which is no longer limited by dedicated chips and reduces the design complexity.

[0045] In one embodiment, Figure 1 As shown, a signal transition edge rise time detection device is provided, including an XOR combination logic module XOR, a control module 120 and a carry chain module 130, wherein the control module 120 is connected to the XOR combination logic module XOR, and the carry chain module 130 is connected to the control module 120. The XOR combination logic module XOR is used to perform XOR logic processing on the comparison signal output by the PE (Pin Electronics Driver / Comparator) module 110 to obtain a feed-in signal; the control module 120 is used to sample and analyze the feed-in signal, determine the time difference between the leading and trailing edges of the feed-in signal, and calculate the rise time of the signal edge according to the time difference and the leading and trailing edge delay parameters sent by the carry chain module 130. The carry chain module 130 is used to obtain the delay parameters corresponding to the leading and trailing edges of the feed-in signal when the control module 120 determines the leading and trailing edges of the feed-in signal, and obtain the leading and trailing edge delay parameters and send them to the control module 120. Furthermore, the signal transition edge rise time detection device also includes a PE module 110, which is connected to the device under test DUT and the exclusive OR combination logic module XOR, and is used to compare and judge the input signal fed back by the device under test DUT according to a preset level threshold value, and output a comparison signal.

[0046] The device under test DUT may be a chip under test or other devices. After the XOR combination logic module XOR performs XOR logic processing on the comparison signal output by the PE module 110, the feed signal is transmitted to the control module 120. The way in which the PE module 210 compares and judges the input signal fed back by the device under test DUT according to the preset level threshold value is not unique. In one embodiment, the comparison signal output by the PE module 110 includes an output signal CA and an output signal CB. The preset level threshold value includes a threshold value VOL and a threshold value VOH. The values ​​of the threshold value VOH and the threshold value VOL are not unique and can be set according to actual needs. It only needs to satisfy that the threshold value VOH is greater than the threshold value VOL. The PE module 110 compares and judges the input signal in combination with the threshold value VOH\threshold value VOL, and outputs the corresponding output signal CA\output signal CB. Specifically, when the input signal is less than the threshold value VOL, the output signal CA is at a low level and the output signal CB is at a low level; when the input signal is greater than or equal to the threshold value VOL and less than or equal to the threshold value VOH, the output signal CA is at a low level and the output signal CB is at a high level; when the input signal is greater than the threshold value VOH, the output signal CA is at a high level and the output signal CB is at a high level.

[0047] In one embodiment, the control module 120 includes a pulse width measurement control unit 122 and a counter unit 124, and the pulse width measurement control unit 122 is connected to the counter unit 124, the XOR combination logic module XOR and the carry chain module 130. The pulse width measurement control unit 122 is used to sample the feed signal, control the counter unit 124 to count according to the detected leading and trailing edges of the feed signal, and determine the time difference between the leading and trailing edges of the feed signal. The pulse width measurement control unit 122 is also used to transmit the feed signal to the carry chain module 130, and control the carry chain module 130 to capture the delay parameters corresponding to the leading and trailing edges of the feed signal.

[0048] The structure of the carry chain module 130 is not unique. Specifically, the CARRY resources inside the FPGA can be used in series. The time span of CARRY needs to be greater than the working main frequency clock cycle of the counter unit 124. The function of CARRY is to latch and record the position (tap value) of the leading edge and trailing edge of the signal when entering CARRY, and then calculate the time covered by the high level of CARRY when the leading edge of the signal is in CARRY and the time covered by the high level of CARRY when the trailing edge of the signal is in CARRY.

[0049] Specifically, the pulse width measurement control unit 122 samples the feed signal according to the clock signal, controls the counter unit 124 to start timing according to the clock signal when the rising edge of the feed signal is identified, and controls the counter unit 124 to stop timing when the falling edge of the feed signal is identified; the pulse width measurement control unit 122 obtains the time difference between the leading and trailing edges of the feed signal according to the count value of the counter unit 124 and the clock cycle.

[0050] Furthermore, if Figure 2 As shown, in one embodiment, the carry chain module 130 includes a CARRY unit 132, a trigger DFF, an XOR gate logic unit and a tap acquisition unit 134. The number of the CARRY units 132 is at least two, and the time span of the CARRY unit 132 covers the clock cycle. The number of the trigger DFF is the same as the number of the CARRY units 132, and each CARRY unit 132 is connected in sequence, and the CARRY unit 132 located at the head end is connected to the pulse width measurement control unit 122; each trigger DFF is respectively connected to the tap of a corresponding CARRY unit 132, the XOR gate logic unit connects the trigger DFF and the tap acquisition unit 134, and the tap acquisition unit 134 is connected to the pulse width measurement control unit 122; the trigger DFF inputs the signal of each adjacent two taps of the corresponding CARRY unit 132 into the same XOR gate logic unit.

[0051] In one embodiment, the delay parameter is a tap value; the pulse width measurement control unit 122 captures and latches the tap value at the position of the signal edge in the carry chain module 130 when identifying the rising edge of the feed signal; and delays one beat to capture and latch the tap value at the position of the signal edge in the carry chain module when identifying the falling edge of the feed signal. It can be understood that the leading and trailing edge delay parameters obtained by the carry chain module 130 are the corresponding tap values ​​latched when the measured rising edge is in CARRY and the falling edge is in CARRY. Then, the pulse width measurement control unit 122 can calculate the corresponding time value through the measured tap value.

[0052] Specifically, the counter unit 124 performs counting processing according to the counting enable signal fed by the pulse width measurement control unit 122, and outputs the final count value after the counting enable signal fails. The counter unit 124 needs to be reset and cleared before the measurement starts. The pulse width measurement control unit 122 makes a judgment based on the input signal obtained after the XOR logic processing, controls the enable counter unit 124 to start and stop counting, and controls the carry chain module 130 to capture the signal edge and obtain the tap value corresponding to the signal edge. The pulse width measurement control unit 122 calculates the rise time of the signal edge based on the count value of the counter unit 124 and the tap values ​​of the leading and trailing edges collected by the carry chain module 130.

[0053] In one embodiment, the pulse width measurement control unit 122 determines the time of the corresponding signal edge relative to the clock signal based on the captured tap value and the resolution of a single tap of the CARRY unit 132; the pulse width measurement control unit 122 calculates the rise time of the signal edge based on the time difference between the leading and trailing edges of the feed signal and the time of the corresponding signal edge relative to the clock signal. The time difference between the leading and trailing edges of the feed signal refers to the time obtained by multiplying the count value of the counter unit 124 by the clock cycle (the total time of the counting clock cycle). The pulse width measurement control unit 122 determines the time of the corresponding signal edge relative to the clock signal, including the corresponding time of the leading edge latched tap value and the corresponding time of the trailing edge latched tap value. Finally, the calculated total rise time of the signal edge is: the count value of the counter unit 124 * the clock cycle + the corresponding time of the leading edge latched tap value + the corresponding time of the trailing edge latched tap value.

[0054] like Figure 2 As shown, in this embodiment, the CARRY unit 132 can be a CARRY8 unit, which leads to 8 taps connected to the trigger DFF. The CARRY8 unit is used in series in the carry chain module 130 to ensure that the carry chain series time span needs to be greater than the working main frequency clock cycle of the counter unit 124. All taps of the CARRY8 unit are collected by the trigger DFF according to the clock beat, and then the combined XOR gate logic unit is used to determine whether there is a jump edge between two adjacent taps. The signal after the XOR gate logic unit is fed into the tap acquisition unit 134. The tap acquisition unit 134 determines the position of the signal edge according to the XOR structure and then outputs the corresponding tap value. The tap value represents the position of the signal edge in the carry chain. The time of the signal edge relative to the clock signal can be determined according to the tap value and the resolution of the CARRY8 unit.

[0055] The above-mentioned signal transition edge rise time detection device samples and analyzes the time difference between the leading and trailing edges of the input signal through the control module 120, and obtains the rise time of the signal edge in combination with the delay parameters corresponding to the leading and trailing edges of the input signal captured by the carry chain module 130. A general chip can be used to implement the signal transition edge rise time detection, thereby reducing the design complexity.

[0056] In one embodiment, Figure 3 As shown, a signal transition edge rise time detection method is also provided, comprising:

[0057] Step S120: the XOR combination logic module performs XOR logic processing on the comparison signal output by the PE module to obtain a feed-in signal.

[0058] Step S130: the control module samples and analyzes the input signal to determine the time difference between the leading and trailing edges of the input signal.

[0059] Step S140: When the control module determines the leading and trailing edges of the input signal, the carry chain module obtains delay parameters corresponding to the leading and trailing edges of the input signal to obtain the leading and trailing edge delay parameters.

[0060] Step S150: The control module calculates the rising time of the signal edge according to the time difference and the delay parameters of the leading and trailing edges.

[0061] In one embodiment, the control module includes a pulse width measurement control unit and a counter unit, and step S130 includes: the pulse width measurement control unit samples the feed signal according to the clock signal, controls the counter unit to start timing according to the clock signal when the rising edge of the feed signal is identified, and controls the counter unit to stop timing when the falling edge of the feed signal is identified; the pulse width measurement control unit obtains the time difference between the leading and trailing edges of the feed signal according to the count value of the counter unit and the clock cycle.

[0062] In one embodiment, the delay parameter is a tap value, and step S150 includes: the pulse width measurement control unit captures the tap value of the signal edge position in the carry chain module when identifying the rising edge of the feed signal; delays one beat to capture the tap value of the signal edge position in the carry chain module when identifying the falling edge of the feed signal; the pulse width measurement control unit determines the time of the corresponding signal edge relative to the clock signal according to the captured tap value and the resolution of a single tap of the CARRY unit in the carry chain module; the pulse width measurement control unit calculates the rising time of the signal edge according to the time difference between the leading and trailing edges of the feed signal and the time of the corresponding signal edge relative to the clock signal.

[0063] In one embodiment, Figure 4 As shown, before step S120, the method further includes step S110: the PE module compares and judges the input signal fed back by the device to be tested according to a preset level threshold value, and outputs a comparison signal.

[0064] It can be understood that the specific implementation of the above-mentioned signal transition edge rise time detection method has been explained in detail in the above-mentioned signal transition edge rise time detection device, and will not be repeated here.

[0065] Specifically, Figure 5 As shown in the figure, the specific implementation process of signal transition edge rise time detection is as follows:

[0066] 1. Reset and clear the initial value of the registers of the pulse width measurement control unit, counter unit, and carry chain module.

[0067] 2. Configure the comparison threshold value (VOH\VOL) for measuring the rise time of the signal edge as required.

[0068] 3. The device under test (DUT) outputs signals to the PE module.

[0069] 4. The PE module compares the set comparison threshold VOH\VOL to obtain the output signal CA\output signal CB. Figure 6 As shown, the output signal CA\output signal CB of the PE module are standard high and low level digital signals. When the input signal is less than the threshold value VOL, the output signal CA is low level and the output signal CB is low level; when the input signal is between the threshold value VOL and the threshold value VOH, the output signal CA is low level and the output signal CB is high level; when the input signal is greater than the threshold value VOH, the output signal CA is high level and the output signal CB is high level.

[0070] 5. The output signal CA\output signal CB enters the XOR processing logic, and the XORed input signal is transmitted to the pulse width measurement control unit.

[0071] 6. The pulse width measurement control unit controls the counter unit logic and the carry chain module logic to perform time measurement according to the feed-in signal. Among them, the counter unit is responsible for measuring the time greater than the clock cycle, and the carry chain module is responsible for measuring the time less than the clock cycle. The carry chain module uses the CARRY resources inside the FPGA for series connection, and uses the characteristics of high resolution of CARRY propagation delay and single-stage CARRY tap that can reach 5ps for time measurement. The carry chain module records the position of the leading edge of the signal in the carry chain and the position of the trailing edge of the signal in the carry chain respectively. The final rising time of the signal edge is the time counted by the counter unit and the tap value of the leading and trailing edges in the carry chain. The timing is as follows Figure 7 As shown, CA\CB is the output signal of the PE module, and XOR is the input signal to the pulse width measurement control unit. The pulse width measurement control unit samples the input signal based on the clock signal Clock, and the input signal is fed into the carry chain module. The pulse width measurement control unit determines the rising edge of the signal according to the sampled value of the input signal, and outputs the counter enable signal Counter_En to take effect, and samples and latches the tap value of the signal edge in the carry chain at the same time; the pulse width measurement control unit performs sampling, and after identifying the falling edge of the input signal, the output counter enable signal Counter_En is invalid, and Counter is the counting signal of the counter unit. At the same time, the pulse width measurement control unit delays one beat to capture the tap value of the signal edge in the carry chain, and the measurement process ends at this time.

[0072] The pulse width measurement control unit calculates the pulse width of the input signal according to the counter value output by the counter unit and the twice extracted tap value latched by the carry chain module, that is, the rise time of the measured signal edge. The specific formula is as follows: Pulse width time = counter value * clock cycle + (tap_h_A + tap_h_B) * CARRY single tap resolution. The rise time represented by the pulse width time is the high level width of the output signal after XOR, corresponding to Figure 7 The high level width of the XOR signal in. Among them, Tap_h_A and tap_h_B are the tap numbers corresponding to the high level in the CARRY carry chain, which need to be numbered according to the captured tap value. Tap_h_a is the total tap value covering the clock cycle minus the captured tap value, and tap_h_b is the captured tap value.

[0073] The above-mentioned signal transition edge rise time detection device and method use more common and general FPGA chips to realize the signal transition edge rise time detection function, and are no longer limited by dedicated chips. The resolution of signal transition edge rise time detection is high, up to 5ps. The CARRY resources in the FPGA are used to realize the detection of the signal edge rise time and fall time. A single FPGA chip can realize both the signal delay function and the logic control, saving printed circuit board space.

[0074] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0075] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A signal transition edge rise time detection device, It is characterized in that include: XOR combination logic module, used for performing XOR logic processing on the comparison signal output by the PE module to obtain a feed-in signal; A control module, connected to the XOR combinational logic module, for sampling and analyzing the feed signal, determining the time difference between the leading and trailing edges of the feed signal; and calculating the rising time of the signal edge according to the time difference and the leading and trailing edge delay parameters sent by the carry chain module; The carry chain module is connected to the control module and is used to obtain the delay parameters corresponding to the leading and trailing edges of the feed signal when the control module determines the leading and trailing edges of the feed signal, and obtain the leading and trailing edge delay parameters and send them to the control module.

2. The signal transition edge rise time detection device according to claim 1, It is characterized in that The control module comprises a pulse width measurement control unit and a counter unit, wherein the pulse width measurement control unit is connected to the counter unit, the XOR combination logic module and the carry chain module; The pulse width measurement control unit is used to sample the feed signal, control the counter unit to count according to the detected leading and trailing edges of the feed signal, and determine the time difference between the leading and trailing edges of the feed signal; The pulse width measurement control unit is further used to transmit the feed signal to the carry chain module, and control the carry chain module to capture the delay parameters corresponding to the leading and trailing edges of the feed signal.

3. The signal transition edge rise time detection device according to claim 2, It is characterized in that The pulse width measurement control unit samples the feed signal according to the clock signal, controls the counter unit to start timing according to the clock signal when the rising edge of the feed signal is identified, and controls the counter unit to stop timing when the falling edge of the feed signal is identified; the pulse width measurement control unit obtains the time difference between the leading and trailing edges of the feed signal according to the count value of the counter unit and the clock cycle.

4. The signal transition edge rise time detection device according to claim 2, It is characterized in that The carry chain module includes a CARRY unit, a trigger, an XOR gate logic unit and a tap acquisition unit. The number of the CARRY units is at least two, the number of the triggers is the same as the number of the CARRY units, the CARRY units are connected in sequence, and the CARRY unit located at the head end is connected to the pulse width measurement control unit; each trigger is respectively connected to the tap of a corresponding CARRY unit, the XOR gate logic unit connects the trigger and the tap acquisition unit, and the tap acquisition unit is connected to the pulse width measurement control unit; the trigger inputs the signal of each adjacent two taps of the corresponding CARRY unit into the same XOR gate logic unit.

5. The signal transition edge rise time detection device according to claim 4, It is characterized in that The delay parameter is the tap value; when the rising edge of the feed signal is identified, the pulse width measurement control unit captures and locks the tap value at the position where the signal edge is located in the carry chain module; when the falling edge of the feed signal is identified, it delays one beat to capture and lock the tap value at the position where the signal edge is located in the carry chain module.

6. The signal transition edge rise time detection device according to claim 5, It is characterized in that The pulse width measurement control unit determines the time of the corresponding signal edge relative to the clock signal according to the captured tap value and the resolution of a single tap of the CARRY unit; the pulse width measurement control unit calculates the rise time of the signal edge according to the time difference between the leading and trailing edges of the feed signal and the time of the corresponding signal edge relative to the clock signal.

7. The signal transition edge rise time detection device according to any one of claims 1 to 6, It is characterized in that Also includes: The PE module is connected to the device under test and the XOR combination logic module, and is used to compare and judge the input signal fed back by the device under test according to a preset level threshold value, and output a comparison signal.

8. The signal transition edge rise time detection device according to claim 7, It is characterized in that The comparison signal output by the PE module includes an output signal CA and an output signal CB, and the preset level threshold values ​​include a threshold value VOL and a threshold value VOH; when the input signal is less than the threshold value VOL, the output signal CA is at a low level, and the output signal CB is at a low level; when the input signal is greater than or equal to the threshold value VOL and less than or equal to the threshold value VOH, the output signal CA is at a low level, and the output signal CB is at a high level; when the input signal is greater than the threshold value VOH, the output signal CA is at a high level, and the output signal CB is at a high level.

9. A method for detecting the rising time of a signal transition edge. It is characterized in that include: The XOR combination logic module performs XOR logic processing on the comparison signal output by the PE module to obtain a feed-in signal; The control module samples and analyzes the input signal to determine the time difference between the leading and trailing edges of the input signal; When the control module determines the leading and trailing edges of the feed-in signal, the carry chain module obtains the delay parameters corresponding to the leading and trailing edges of the feed-in signal to obtain the leading and trailing edge delay parameters; The control module calculates the rising time of the signal edge according to the time difference and the leading and trailing edge delay parameters.

10. The signal transition edge rise time detection method according to claim 9, It is characterized in that The control module includes a pulse width measurement control unit and a counter unit. The control module performs sampling analysis on the feed signal to determine the time difference between the leading and trailing edges of the feed signal, including: The pulse width measurement control unit samples the feed signal according to the clock signal, controls the counter unit to start timing according to the clock signal when a rising edge of the feed signal is identified, and controls the counter unit to stop timing when a falling edge of the feed signal is identified; The pulse width measurement control unit obtains the time difference between the leading and trailing edges of the input signal according to the count value of the counter unit and the clock cycle.

11. The signal transition edge rise time detection method according to claim 10, It is characterized in that The delay parameter is a tap value, and the control module calculates the rise time of the signal edge according to the time difference and the leading and trailing edge delay parameters, including: The pulse width measurement control unit grabs the tap value at the position where the signal edge is located in the carry chain module when the rising edge of the feed signal is identified; and delays one beat to grab the tap value at the position where the signal edge is located in the carry chain module when the falling edge of the feed signal is identified; The pulse width measurement control unit determines the time of the corresponding signal edge relative to the clock signal according to the captured tap value and the resolution of a single tap of the CARRY unit in the carry chain module; The pulse width measurement control unit calculates the rising time of the signal edge according to the time difference between the leading and trailing edges of the input signal and the time of the corresponding signal edge relative to the clock signal.

12. The signal transition edge rise time detection method according to any one of claims 9 to 11, It is characterized in that The XOR combination logic module performs XOR logic processing on the comparison signal output by the PE module to obtain the feed-in signal, and also includes: The PE module compares and judges the input signal fed back by the device to be tested according to the preset level threshold value, and outputs a comparison signal.

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