Low dropout linear regulator circuit, power supply and electronic equipment

Abstract

The invention discloses a low dropout regulator circuit, a power supply and electronic equipment, and belongs to the technical field of electronic equipment. The LDO circuit comprises a voltage sampling circuit, an output power tube, an error amplifier and a current sampling circuit. Under the condition that the LDO circuit jumps downwards, the current sampling circuit can collect increased sampling current, so that the error amplifier generates increased error amplification voltage, the output voltage of the output power tube is rapidly reduced, the overshoot voltage of the LDO circuit is reduced, and the state recovery duration of the output voltage of the LDO circuit is shortened. Under the condition that the LDO circuit jumps upwards, the current sampling circuit collects reduced sampling current, so that the error amplifier generates reduced error amplification voltage, the output voltage of the output power tube is rapidly increased, the undershoot voltage of the LDO circuit is reduced, the state recovery duration of the output voltage of the LDO circuit is shortened, and the load transient response capacity is improved.

Description

Technical Field

[0001] The present application belongs to the technical field of electronic equipment, and specifically relates to a low voltage drop linear regulator circuit, a power supply and an electronic device. Background Art

[0002] Low-dropout regulator (LDO) is a linear DC regulator that is used to provide a stable DC voltage supply. LDO circuits have excellent power supply ripple rejection ratio (PSRR) and simple structure, so they are widely used in various power supply systems.

[0003] In the actual use of the LDO circuit, if the load current jumps, the output voltage of the LDO circuit will also change accordingly. Under the action of the load transient jump, the process of the output voltage of the LDO circuit changing from the initial change state to the stable state is the load transient response process. Load transient response capability is an important performance of the LDO circuit, and the current power supply system also has high requirements for load transient response capability. For example, in the One Time Program (OTP) burning scenario, OTP burning has the characteristics of short burning cycle and large burning current jump. Therefore, the OTP burning system has high requirements for the load transient response capability of its power supply to meet the requirements of small power supply overshoot and fast state recovery.

[0004] However, the bandwidth of current LDO circuits is usually small. The quality of load transient response capability is limited by the bandwidth of the LDO circuit, which makes the load transient response capability of current LDO circuits poor, resulting in large overshoot voltage, large undershoot voltage, and long stable state recovery time under the action of load transient jump. Summary of the invention

[0005] The embodiments of the present application provide an LDO circuit, a power supply, and an electronic device, which can, to a certain extent, solve the problem of poor load transient response capability of the current LDO circuit.

[0006] In a first aspect, an LDO circuit is provided, the LDO circuit comprising: a voltage sampling circuit, an output power tube, an error amplifier and a current sampling circuit;

[0007] The voltage sampling circuit is connected to the voltage output terminal of the LDO circuit and the error amplifier, and is used to transmit a feedback voltage corresponding to the voltage output terminal to the error amplifier;

[0008] The current sampling circuit is connected to the error amplifier and the voltage output terminal, and is used for converting the output voltage of the voltage output terminal into a sampling current, and transmitting the sampling current to the error amplifier;

[0009] The error amplifier is connected to the output power tube, and is used for positively adjusting the error amplified voltage of the feedback voltage and the reference voltage according to the sampling current, and transmitting the error amplified voltage to the output power tube;

[0010] The output power tube is connected to the voltage output end, and is used for converting the input voltage into an output voltage under the control of the error amplification voltage, and transmitting the output voltage to the voltage output end.

[0011] In a second aspect, a power supply is provided, the power supply comprising: an LDO circuit as described in any one of the first aspects.

[0012] In a third aspect, an electronic device is provided, comprising: the LDO circuit described in any one of the first aspect, or the power supply described in the second aspect.

[0013] In the LDO circuit, power supply and electronic device provided in the embodiments of the present application, the LDO circuit includes: a voltage sampling circuit, an output power tube, an error amplifier and a current sampling circuit. The voltage sampling circuit is used to transmit the feedback voltage corresponding to the voltage output terminal of the LDO circuit to the error amplifier. The error amplifier is used to generate an error amplification voltage based on the reference voltage and the feedback voltage, and transmit the error amplification voltage to the output power tube. The output power tube is used to convert the input voltage of the LDO circuit into an output voltage under the control of the error amplification voltage, and transmit the output voltage to the voltage output terminal. The current sampling circuit is used to convert the output voltage into a sampling current and transmit the sampling current to the error amplifier. The error amplifier is also used to positively adjust the error amplification voltage according to the sampling current.

[0014] In this technical solution, the current sampling circuit can convert the magnitude change of the output voltage into the magnitude change of the sampling current, so that the error amplifier generates an error amplification voltage that changes with the positive current. In this way, when the load of the LDO circuit jumps downward and the output voltage overshoots, the current sampling circuit can collect the increased sampling current, so that the error amplifier generates an increased error amplification voltage, controls the increase of the on-resistance of the output power tube, and quickly reduces the output voltage transmitted by the output power tube to the voltage output end, reduces the overshoot voltage of the LDO circuit, reduces the state recovery time of the output voltage of the LDO circuit, and improves the load transient response capability. Similarly, when the load of the LDO circuit jumps upward and the output voltage undershoots, the current sampling circuit can collect the reduced sampling current, so that the error amplifier generates a reduced error amplification voltage, controls the reduction of the on-resistance of the output power tube, and quickly increases the output voltage transmitted by the output power tube to the voltage output end, reduces the undershoot voltage of the LDO circuit, reduces the state recovery time of the output voltage of the LDO circuit, and improves the load transient response capability. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a structural schematic diagram of an LDO circuit provided by the related technology;

[0016] Figure 2 It is a structural schematic diagram of another LDO circuit provided by the related technology;

[0017] Figure 3 It is a structural schematic diagram of an LDO circuit provided in an embodiment of the present application;

[0018] Figure 4 is a structural schematic diagram of another LDO circuit provided in an embodiment of the present application;

[0019] Figure 5 Schematic diagram of the structure of another LDO circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0020] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0021] LDO is a low-dropout linear regulator that is used to provide a stable DC voltage supply. LDO circuits have excellent PSRR and simple structure, so they are widely used in various power supply systems.

[0022] For an example, see Figure 1 , which shows a schematic diagram of the structure of an LDO circuit provided by the related art. Figure 1 As shown, the LDO circuit 10 includes: an error amplifier EA, an output power tube M10, a third resistor Rfb1, a fourth resistor Rfb2, an equivalent series resistance (ESR) ESR and a load capacitor Cload. Among them, the output power tube M10 can be a P-channel metal oxide semiconductor (positive channel Metal Oxide Semiconductor, PMOS) tube. The equivalent series resistance ESR is the equivalent series resistance of the load capacitor Cload.

[0023] Among them, the reverse input terminal of the error amplifier EA is connected to the reference voltage terminal VREF, and is used to receive the reference voltage Vref provided by the reference voltage terminal VREF. The positive input terminal of the error amplifier EA is connected to the third resistor Rfb1 and the fourth resistor Rfb2 respectively. The output terminal of the error amplifier EA is also connected to the gate of the output power tube M10. The source of the output power tube M10 is connected to the voltage input terminal VIN, and is used to receive the input voltage Vin provided by the voltage input terminal VIN. The drain of the output power tube M10 is grounded through the third resistor Rfb1 and the fourth resistor Rfb2 connected in series. The drain of the output power tube M10 is also connected to the voltage output terminal VOUT of the LDO circuit 10. One end of the equivalent series resistor ESR is connected to the voltage output terminal VOUT, and the other end of the equivalent series resistor ESR is grounded through the load capacitor Cload.

[0024] In the LDO circuit 10, the third resistor Rfb1 and the fourth resistor Rfb2 are used to collect the output voltage Vout of the voltage output terminal VOUT, and convert it into a feedback voltage Vfb in proportion to the resistance values ​​of the third resistor Rfb1 and the fourth resistor Rfb2, and transmit the feedback voltage Vfb to the error amplifier EA. The error amplifier EA is used to amplify the error between the feedback voltage Vfb and the reference voltage Vref, generate an error amplified voltage, and transmit the error amplified voltage to the output power tube M10 to adjust the on-resistance of the output power tube M10. The output power tube M10 is used to convert the input voltage Vin into the output voltage Vout according to the on-resistance, and transmit it to the voltage output terminal VOUT.

[0025] The LDO circuit 10 can amplify the error of the reference voltage Vref through negative feedback to output a stable output voltage Vout in proportion to the resistance of the feedback resistors (i.e., the third resistor Rfb1 and the fourth resistor Rfb2). The output voltage Vout satisfies the formula: Vout = (1 + R11 / R12) × Vref. In this formula, R11 represents the resistance of the third resistor Rfb1. R12 represents the resistance of the fourth resistor Rfb2. Vref represents the reference voltage. The LDO circuit 10 is generally suitable for low voltage power supplies, which have the advantages of low noise, small quiescent current, and low cost.

[0026] In another example, the device structure of the error amplifier included in the LDO circuit may be a folded cascode structure. The error amplifier of the folded cascode structure may be a folded amplifier. The LDO circuit including the error amplifier of the folded cascode structure is an LDO circuit of the folded cascode structure. Please refer to Figure 2 , which shows a structural schematic diagram of another LDO circuit provided by the related art. Figure 2 As shown, the LDO circuit 10 includes: a compensation capacitor Cc, an error amplifier 101, an output power tube M10, a third resistor Rfb1, a fourth resistor Rfb2, an equivalent series resistor ESR and a load capacitor Cload. Among them, the output power tube M10 is a PMOS tube M10.

[0027] The error amplifier 101 includes a first power tube M1, a second power tube M2, a third power tube M3, a fourth power tube M4, a fifth power tube M5, a sixth power tube M6, a seventh power tube M7, an eighth power tube M8 and a ninth power tube (ie, a tail current source tube) M9.

[0028] The gate of the first power tube M1 is connected to the feedback voltage node VFB. The drain of the first power tube M1 is connected to the source of the sixth power tube M6 and the drain of the fourth power tube M4. The source of the first power tube M1 is connected to the source of the second power tube M2 and the drain of the ninth power tube M9.

[0029] The gate of the second power tube M2 is connected to the reference voltage terminal VREF, and is used to receive the reference voltage Vref provided by the reference voltage terminal VREF. The drain of the second power tube M2 is connected to the source of the fifth power tube M5 and the drain of the third power tube M3. The source of the third power tube M3 and the source of the fourth power tube M4 are grounded. The gate of the third power tube M3 is connected to the gate of the fourth power tube M4 and the second bias voltage terminal.

[0030] The drain of the fifth power tube M5 is connected to the drain of the seventh power tube M7 and the gate of the output power tube M10. The gate of the fifth power tube M5 is connected to the gate of the sixth power tube M6 and the third bias voltage terminal.

[0031] The drain of the sixth power tube M6 is connected to the drain of the eighth power tube M8, the gate of the eighth power tube M8 and the gate of the seventh power tube M7 respectively. The source of the seventh power tube M7 and the source of the eighth power tube M8 are connected to the voltage input terminal VIN of the LDO circuit 10. The source of the ninth power tube M9 is connected to the voltage input terminal VIN. The gate of the ninth power tube M9 is connected to the fourth bias voltage terminal.

[0032] The fourth bias voltage terminal is used to provide a bias voltage Vb4 for the ninth power tube M9, and the bias voltage Vb4 is used to adjust the on-resistance of the ninth power tube M9, and control the ninth power tube M9 to be turned on or off. The second bias voltage terminal is used to provide a bias voltage Vb2 for the third power tube M3 and the fourth power tube M4, and the bias voltage Vb2 is used to adjust the on-resistance of the third power tube M3 and the fourth power tube M4, and control the third power tube M3 and the fourth power tube M4 to be turned on or off. The third bias voltage terminal is used to provide a bias voltage Vb3 for the fifth power tube M5 and the sixth power tube M6, and the bias voltage Vb3 is used to adjust the on-resistance of the fifth power tube M5 and the sixth power tube M6, and control the fifth power tube M5 and the sixth power tube M6 to be turned on or off. The voltage input terminal VIN is used to provide an input voltage Vin of the LDO circuit 10. Furthermore, the first power tube M1, the second power tube M2, the seventh power tube M7, the eighth power tube M8 and the ninth power tube M9 are PMOS tubes, and the third power tube M3, the fourth power tube M4, the fifth power tube M5 and the sixth power tube M6 are N-channel metal oxide semiconductor (NMOS) tubes.

[0033] The source of the output power tube M10 is connected to the voltage input terminal VIN. The drain of the output power tube M10 is connected to the voltage output terminal VOUT. One end of the third resistor Rfb1 is connected to the voltage output terminal VOUT, and the other end of the third resistor Rfb1 is grounded through the fourth resistor Rfb2. The feedback node VFB is located on the path between the third resistor Rfb1 and the fourth resistor Rfb2. One end of the equivalent series resistor ESR is connected to the voltage output terminal VOUT, and the other end of the equivalent series resistor ESR is grounded through the load capacitor Cload. One end of the compensation capacitor Cc is connected to the voltage output terminal VOUT, and the other end of the supplementary capacitor Cc is respectively connected to the source of the fifth power tube M5 and the drain of the third power tube M3. The supplementary capacitor Cc is used to compensate for circuit stability.

[0034] In the LDO circuit 10, the third resistor Rfb1 and the fourth resistor Rfb2 are used as feedback voltage-dividing resistors to collect the output voltage Vout of the voltage output terminal VOUT, and convert it into a feedback voltage Vfb in proportion to the resistance values ​​of the third resistor Rfb1 and the fourth resistor Rfb2, and transmit the feedback voltage Vfb to the first power tube M1 of the error amplifier 101. The error amplifier 101 is used to amplify the error between the feedback voltage Vfb and the reference voltage Vref to generate an error amplified voltage, and transmit the error amplified voltage to the gate of the output power tube M10 to adjust the on-resistance of the output power tube M10. The output power tube M10 is used to convert the input voltage Vin into an output voltage Vout according to the on-resistance, and transmit it to the voltage output terminal VOUT.

[0035] Compared to Figure 1 The LDO circuit shown, Figure 2 In the LDO circuit shown, by using PMOS tube as the input differential pair, the input noise can be effectively reduced. In addition, the error amplifier 101 adopts a folded amplifier with a folded common source and common gate structure, which can make the error amplifier 101 have a higher open-loop gain and improve the output voltage accuracy of the error amplifier 101. In addition, the output power tube M10 adopts a PMOS tube, which can have a lower dropout voltage (Dropout Voltage) compared to the NMOS tube. The use of capacitor Cc common source and common gate compensation (Cascode Compensation) can effectively isolate the feedforward path, eliminate the right half plane zero RHZ of the LDO circuit, and optimize the PSRR of the LDO circuit. In addition, compared with Miller compensation, capacitor common source and common gate compensation saves compensation series resistance and reduces circuit area.

[0036] However, the bandwidth of current LDO circuits is usually small. The quality of load transient response capability is limited by the bandwidth of the LDO circuit, which makes the current LDO circuit have poor load transient response capability. When the load current of the LDO circuit jumps, it cannot respond instantaneously, which leads to large overshoot voltage, large undershoot voltage, and long stable state recovery time under the action of load transient jump.

[0037] However, the current power supply system also has high requirements for load transient response capability. For example, in the OTP burning scenario, OTP burning has the characteristics of short burning cycle and large burning current jump. During the burning process, the OTP burning system will draw a current of more than ten to twenty milliamperes from its power supply, and the power supply is required to be able to reach a stable state and maintain the target output voltage within 10% of the burning time. Otherwise, it is easy to cause the fuse to burn out due to insufficient burning current, which will affect OTP burning. Therefore, the OTP burning system has high requirements for the load transient response capability of its power supply, and must meet requirements such as small power supply overshoot and fast state recovery.

[0038] Please refer to Figure 3 , which shows a schematic diagram of the structure of an LDO circuit provided by an embodiment of the present application. The LDO circuit can improve the load transient response capability to a certain extent. Figure 3 As shown, the LDO circuit 10 includes: an error amplifier 101 , an output power tube 102 , a current sampling circuit 103 and a voltage sampling circuit 104 .

[0039] The voltage sampling circuit 104 is connected to the voltage output terminal VOUT of the LDO circuit 10 and the error amplifier 101. The voltage sampling circuit 104 is used to transmit the feedback voltage Vfb corresponding to the voltage output terminal VOUT to the error amplifier 101. Specifically, the voltage sampling circuit 104 is used to convert the output voltage Vout of the voltage output terminal VOUT into the feedback voltage Vfb, and transmit the feedback voltage Vfb to the error amplifier 101.

[0040] The current sampling circuit 103 is connected to the error amplifier 101 and the voltage output terminal VOUT of the LDO circuit 10. The current sampling circuit 103 is used to convert the output voltage Vout of the voltage output terminal VOUT into a sampling current I, and transmit the sampling current I to the error amplifier 101.

[0041] The error amplifier 101 is connected to the output power tube 102. The error amplifier 101 is used to positively adjust the error amplified voltage Vc of the feedback voltage Vfb and the reference voltage Vref according to the sampling current I, and transmit the error amplified voltage Vc to the output power tube 102. Specifically, the error amplifier 101 is used to generate the error amplified voltage Vc according to the reference voltage Vref and the feedback voltage Vfb, and transmit the error amplified voltage Vc to the output power tube 102. And, the error amplifier 101 is also used to positively adjust the error amplified voltage Vc according to the sampling current I. That is, the error amplifier 101 increases the error amplified voltage Vc when the sampling current I increases; and decreases the error amplified voltage Vc when the sampling current I decreases. Optionally, the inverting input terminal of the error amplifier 101 is connected to the reference voltage terminal VREF, and is used to receive the reference voltage Vref provided by the reference voltage terminal VREF. The positive input terminal of the error amplifier 101 is connected to the voltage sampling circuit 104, and is used to receive the feedback voltage Vfb transmitted by the voltage sampling circuit 104. The output end of the error amplifier 101 is connected to the control end of the output power tube 102 for transmitting the error amplified voltage Vc to the output power tube 102 .

[0042] The output power tube 102 is connected to the voltage output terminal VOUT. The output power tube 102 is used to convert the input voltage into the output voltage Vout under the control of the error amplifier voltage Vc, and transmit the output voltage Vout to the voltage output terminal VOUT. Specifically, the error amplifier voltage Vc is used to adjust the on-resistance of the output power tube 102. The output power tube 102 is used to convert the input voltage into the output voltage Vout according to the on-resistance, and transmit it to the voltage output terminal VOUT. Optionally, the power supply end of the output power tube 102 is connected to the voltage input terminal VIN of the LDO circuit 10, and is used to receive the input voltage provided by the voltage input terminal VIN. The control end of the output power tube 102 is connected to the error amplifier 101. The output end of the output power tube 102 is connected to the voltage output terminal VOUT of the LDO circuit 10. By way of example, the output power tube 102 can be a PMOS tube. The gate of the output power tube 102 is connected to the error amplifier 101 , the source of the output power tube 102 is connected to the voltage input terminal VIN, and the drain of the output power tube 102 is connected to the voltage output terminal VOUT.

[0043] In the embodiment of the present application, when the load current of the LDO circuit 10 jumps downward, for example, from 15 milliamperes (mA) to 500 microamperes (uA), the output voltage Vout of the LDO circuit 10 will be instantly raised, an overshoot phenomenon will occur, and an overshoot voltage will be generated. The current sampling circuit 103 can convert the increased output voltage Vout into an increased sampling current I, and transmit it to the error amplifier 101. The error amplifier 101 positively adjusts the error amplification voltage Vc according to the sampling current I to increase the error amplification voltage Vc, and controls the output power tube 102 to turn off, so that the on-resistance of the output power tube 102 increases. The output power tube 102 stops providing the output voltage Vout to the voltage output terminal VOUT, so that the output voltage Vout of the LDO circuit 10 drops rapidly, the overshoot voltage decreases rapidly, and the influence of the output voltage overshoot is weakened.

[0044] As the output voltage Vout of the LDO circuit 10 gradually decreases, the sampling current I collected by the current sampling circuit 103 gradually decreases. The error amplified voltage Vc adjusted by the error amplifier 101 according to the sampling current I decreases, and the output power tube 102 is turned on. After the output voltage Vout of the LDO circuit 10 is in a stable state, the sampling current I collected by the current sampling circuit 103 is in a stable state. The error amplifier 101 weakens its ability to adjust the error amplified voltage Vc using the sampling current I, and the error amplified voltage Vc output by the error amplifier 101 is in a stable state.

[0045] Similarly, when the load current of the LDO circuit 10 jumps upward, for example, from 500uA to 15mA, the output voltage Vout of the LDO circuit 10 will be pulled down instantaneously, an undershoot phenomenon will occur, and an undershoot voltage will be generated. The current sampling circuit 103 can convert the reduced output voltage Vout into a reduced sampling current I, and transmit it to the error amplifier 101. The error amplifier 101 positively adjusts the error amplification voltage Vc according to the sampling current I to reduce the error amplification voltage Vc and control the on-resistance of the output power tube 102 to decrease. The output power tube 102 provides an increased output voltage Vout to the voltage output terminal VOUT, so that the output voltage Vout of the LDO circuit 10 increases rapidly, the undershoot voltage decreases rapidly, the influence of the output voltage undershoot is weakened, and the load transient response capability is improved.

[0046] In an embodiment of the present application, the LDO circuit includes: a voltage sampling circuit, an output power tube, an error amplifier and a current sampling circuit. The voltage sampling circuit is used to transmit a feedback voltage corresponding to the voltage output terminal of the LDO circuit to the error amplifier. The error amplifier is used to generate an error amplification voltage based on a reference voltage and a feedback voltage, and transmit the error amplification voltage to the output power tube. The output power tube is used to convert the input voltage of the LDO circuit into an output voltage under the control of the error amplification voltage, and transmit the output voltage to the voltage output terminal. The current sampling circuit is used to convert the output voltage into a sampling current and transmit the sampling current to the error amplifier. The error amplifier is also used to positively adjust the error amplification voltage according to the sampling current.

[0047] In this technical solution, the current sampling circuit can convert the magnitude change of the output voltage into the magnitude change of the sampling current, so that the error amplifier generates an error amplification voltage that changes with the positive current. In this way, when the load of the LDO circuit jumps downward and the output voltage overshoots, the current sampling circuit can collect the increased sampling current, so that the error amplifier generates an increased error amplification voltage, controls the increase of the on-resistance of the output power tube, and quickly reduces the output voltage transmitted by the output power tube to the voltage output end, reduces the overshoot voltage of the LDO circuit, reduces the state recovery time of the output voltage of the LDO circuit, and improves the load transient response capability. Similarly, when the load of the LDO circuit jumps upward and the output voltage undershoots, the current sampling circuit can collect the reduced sampling current, so that the error amplifier generates a reduced error amplification voltage, controls the reduction of the on-resistance of the output power tube, and quickly increases the output voltage transmitted by the output power tube to the voltage output end, reduces the undershoot voltage of the LDO circuit, reduces the state recovery time of the output voltage of the LDO circuit, and improves the load transient response capability.

[0048] Alternatively, if Figure 4 As shown, the current sampling circuit 103 includes: a current conversion module 1031 and a current amplification module 1032. The current conversion module 1031 is connected to the voltage output terminal VOUT of the LDO circuit 10 and the current amplification module 1032. The current conversion module 1031 is used to convert the output voltage Vout into a sampling current I and transmit the sampling current I to the current amplification module 1032.

[0049] The current amplification module 1032 is connected to the error amplifier 101. The current amplification module 1032 is used to amplify the sampling current I and transmit the amplified sampling current I to the error amplifier 101. In this way, the sampling current is amplified by the current amplification module 1032 so that the change of the sampling current can more accurately reflect the change of the output voltage of the LDO circuit. In addition, the error amplifier 101 can more accurately control the on-resistance of the output power tube 102 according to the error amplification voltage adjusted by the sampling current, effectively reduce the state recovery time of the output voltage of the LDO circuit, and improve the load transient response capability.

[0050] Further optionally, the device structure of the error amplifier 101 is a folded cascode structure. The error amplifier 101 includes a cascode module. Figure 5 As shown, the current amplification module 1032 includes a first current amplifier Q1 and a second current amplifier Q2.

[0051] The first current amplifier Q1 is connected to the current conversion module 1031 and the first input terminal IN1 of the cascode module of the error amplifier 101. The first current amplifier Q1 is used to amplify the sampling current I and transmit the amplified sampling current I to the first input terminal IN1.

[0052] The second current amplifier Q2 is connected to the second input terminal IN2 of the cascode module. The second current amplifier Q2 is used to provide a matching current between the second input terminal IN2 and the first input terminal IN1. Optionally, the matching current can be equal to the amplified sampling current I output by the first current amplifier Q1 when the voltage output terminal VOUT of the LDO circuit 10 is in a stable state. In this way, when the voltage output terminal VOUT of the LDO circuit 10 is in a stable state, the current transmitted by the current amplifier module 1032 to the first input terminal IN1 and the second input terminal IN2 of the cascode module are equal, avoiding the occurrence of an offset current that affects the circuit performance.

[0053] In an optional implementation, Figure 5 As shown, the first current amplifier Q1 is a first transistor Q1. The second current amplifier Q2 is a second transistor Q2. Optionally, both the first transistor Q1 and the second transistor Q2 are NPN transistors.

[0054] The base of the first transistor Q1 is connected to the current conversion module 1031. The base of the first transistor Q1 is also used to receive the bias voltage of the first transistor Q1. The emitter of the first transistor Q1 is grounded. The collector of the first transistor Q1 is connected to the first input terminal IN1. The base of the second transistor Q2 is used to receive the bias voltage of the second transistor Q2. The emitter of the second transistor Q2 is grounded. The collector of the second transistor Q2 is connected to the second input terminal IN2.

[0055] Among them, the first transistor Q1 is used to amplify the sampling current I transmitted by the current conversion module 1031 to obtain the amplified sampling current I. In addition, since the amplified sampling current I is output from the collector of the first transistor Q1. Therefore, Ic can also be used to represent the sampling current I amplified by the first transistor Q1. The amplified sampling current I satisfies the formula: I=β×Ib. In this formula, I represents the amplified sampling current I. β is the current amplification factor of the first transistor Q1. Ib represents the sampling current I output by the current conversion module 1031, that is, the sampling current before amplification. The second transistor Q2 is used to amplify the current corresponding to the bias voltage to obtain a matching current, and transmit the matching current to the second input terminal IN2 of the common source and common gate module.

[0056] Further optionally, the current amplification module 1032 also includes: a first resistor R1 and a second resistor R2. The base of the first transistor Q1 is connected to the current conversion module 1031. The base of the first transistor Q1 is also connected to the first bias voltage terminal VB1 through the first resistor R1. The emitter of the first transistor Q1 is grounded. The collector of the first transistor Q1 is connected to the first input terminal IN1 of the common source and common gate module. The base of the second transistor Q2 is connected to the first bias voltage terminal VB1 through the second resistor R2. The emitter of the second transistor Q2 is grounded. The collector of the second transistor Q2 is connected to the second input terminal IN2 of the common source and common gate module.

[0057] The first bias voltage terminal VB1 is used to provide a bias voltage Vb1 for the first transistor Q1 and the second transistor Q2. The first resistor R1 and the second resistor R2 are used as current limiting resistors to limit the current flowing into the second transistor Q2. In this way, the sampling current I transmitted by the current conversion module 1031 is blocked by the first resistor R1 and the second resistor R2, and mainly flows to the base of the first transistor Q1, so that the collector of the first transistor Q1 outputs the amplified sampling current I. Since the second transistor Q2 does not receive the additional sampling current I, the current of the base of the second transistor Q2 remains almost unchanged, and thus the output current of the collector of the second transistor Q2 remains almost unchanged.

[0058] In the embodiment of the present application, the voltage sampling circuit 104 is used to transmit the feedback voltage Vfb corresponding to the voltage output terminal VOUT to the error amplifier 101. Figure 5As shown, the voltage sampling circuit 104 includes a third resistor Rfb1 and a fourth resistor Rfb2. One end of the third resistor Rfb1 is connected to the voltage output terminal VOUT, and the other end of the third resistor Rfb1 is grounded through the fourth resistor Rfb2. The third resistor Rfb1 and the fourth resistor Rfb2 are used to collect the output voltage Vout of the voltage output terminal VOUT, and convert it into a feedback voltage Vfb in proportion according to the resistance values ​​of the third resistor Rfb1 and the fourth resistor Rfb2, and transmit the feedback voltage Vfb to the error amplifier 101.

[0059] In an optional case, the error amplifier 101 further includes: a differential input tube module, a tail current source tube, a power input tube module and a load tube module.

[0060] The differential input tube module is connected to the voltage sampling module 104, the tail current source tube, the power input tube module and the first input terminal IN1 and the second input terminal IN2 of the common source and common gate tube module. The tail current source tube is connected to the voltage input terminal VIN of the LDO circuit 10. The power input tube module is connected to the first input terminal IN1 and the second input terminal IN2 of the common source and common gate tube module, and the power input tube module is grounded. The common source and common gate tube module is also connected to the load tube module and the control terminal of the output power tube 102. The load tube module is also connected to the voltage input terminal VIN.

[0061] The voltage output node of the error amplifier 101 is located between the cascode module and the load module. The cascode module is used to extract the amplified sampling current I output by the current amplifier module 1032 and transmit the sampling current I to the load module so that the load module positively regulates the error amplification voltage Vc.

[0062] Further optionally, if Figure 5 As shown, the differential input tube module includes a first power tube M1 and a second power tube M2. The power input tube module includes a third power tube M3 and a fourth power tube M4. The common source and common gate tube module includes a fifth power tube M5 and a sixth power tube M6. The load tube module includes a seventh power tube M7 and an eighth power tube M8. That is, the error amplifier 101 includes: the first power tube M1 to the eighth power tube M8 and the tail current source tube (ninth power tube) M9.

[0063] The gate of the first power tube M1 is connected to the voltage sampling circuit 104. The drain of the first power tube M1 is connected to the source of the sixth power tube M6 and the drain of the fourth power tube M4. The source of the first power tube M1 is connected to the source of the second power tube M2 and the drain of the tail current source tube M9. The gate of the second power tube M2 is used to receive the reference voltage Vref of the error amplifier 101. The drain of the second power tube M2 is connected to the source of the fifth power tube M5 and the drain of the third power tube M3. The source of the third power tube M3 and the source of the fourth power tube M4 are grounded. The gate of the third power tube M3 is connected to the gate of the fourth power tube M4 and the second bias voltage terminal VB2. The drain of the fifth power tube M5 is connected to the drain of the seventh power tube M7 and the control terminal of the output power tube 102. The gate of the fifth power tube M5 is connected to the gate of the sixth power tube M6 and the third bias voltage terminal VB3. The drain of the sixth power tube M6 is connected to the drain of the eighth power tube M8, the gate of the eighth power tube M8 and the gate of the seventh power tube M7 respectively. The source of the seventh power tube M7 and the source of the eighth power tube M8 are connected to the voltage input terminal VIN of the LDO circuit 10. The source of the tail current source tube M9 is connected to the voltage input terminal VIN. The gate of the tail current source tube M9 is connected to the fourth bias voltage terminal VB4.

[0064] Among them, the first input terminal IN1 of the common source and common gate module is the source of the sixth transistor M6. The second input terminal IN2 of the common source and common gate module is the source of the fifth transistor M5. The second bias voltage terminal VB2 is used to provide a bias voltage Vb2 for the third power tube M3 and the fourth power tube M4. The third bias power supply terminal VB3 is used to provide a bias voltage Vb3 for the fifth power tube M5 and the sixth power tube M6. The fourth bias voltage terminal VB4 is used to provide a bias voltage Vb4 for the tail current source tube M9. And, optionally, the first power tube M1, the second power tube M2, the seventh power tube M7, the eighth power tube M8 and the ninth power tube M9 are PMOS tubes. The third power tube M3, the fourth power tube M4, the fifth power tube M5 and the sixth power tube M6 are NMOS tubes. For example, the gate of the first power tube M1 is connected to the feedback node VFB of the voltage sampling circuit 104. The feedback node VFB is located in a path between the third resistor Rfb1 and the fourth resistor Rfb2 of the voltage sampling circuit 104 .

[0065] Alternatively, if Figure 5 As shown, the current conversion module 1031 may include a sampling capacitor C. The sampling capacitor C is used to convert the output voltage Vout of the voltage output terminal VOUT into a sampling current I, and transmit the sampling current I to the error amplifier 101. The sampling current I satisfies the formula: I = C × dV / dt. In this formula, C represents the capacitance value of the sampling capacitor C. dV represents the change amount of the output voltage Vout. dt represents the change time of the output voltage Vout.

[0066] Alternatively, if Figure 5 As shown, the LDO circuit 10 further includes a compensation capacitor Cc. One end of the compensation capacitor Cc is connected to the second input terminal IN2 of the common source and common gate tube module, and the other end of the compensation capacitor Cc is connected to the voltage output terminal VOUT. The compensation capacitor Cc is used to perform advance compensation on the common source and common gate tube module to cut off the feedforward path of the error amplifier 101 and maintain circuit stability.

[0067] Optionally, please continue to refer to Figure 5 The LDO circuit 10 further includes a load capacitor Cload and an equivalent series resistor ESR. One end of the equivalent series resistor ESR is connected to the voltage output terminal VOUT. The other end of the equivalent series resistor ESR is grounded through the load capacitor Cload.

[0068] For example, Figure 5 Taking the LDO circuit shown as an example, the working principle of the LDO circuit provided in the embodiment of the present application to improve the transient response capability is explained again.

[0069] When the load current of the LDO circuit 10 changes downward, for example, from 15mA to 500uA, the output voltage of the LDO circuit 10 will rise instantaneously, resulting in an overshoot phenomenon and an overshoot voltage. The sampling capacitor C converts the overshoot voltage into an increased sampling current I, which is an AC current.

[0070] Due to the current limiting effect of the first resistor R1 and the second resistor R2, the sampling current I transmitted by the sampling capacitor C mainly flows to the base of the first transistor Q1, so that the collector of the first transistor Q1 outputs the amplified sampling current I and transmits it to the source of the sixth power tube M6. The current of the base of the second transistor Q2 is almost unchanged, and the output current of the collector of the second transistor Q2 is almost unchanged, so as to maintain the matching current of the second input terminal IN2 and the first input terminal IN1 of the output common source and common gate tube module.

[0071] The sampling current I flows into the source of the sixth power tube M6 (i.e., the folding point of the LDO circuit of the Fold-cascode structure), and is transmitted to the gate and drain of the eighth power tube M8 through the drain of the sixth power tube M6, so that the drain of the eighth transistor M8 increases the sampling current I based on the input voltage.

[0072] The drain of the eighth transistor M8 is connected to the gate of the eighth transistor M8 and the gate of the seventh transistor M7. At this time, the slew rate (SR) of the voltage of the gate of the eighth power tube M8 will instantly increase the target value. The target value is I / Cg. Wherein, Cg represents the parasitic capacitance of the gate of the eighth power tube M8. I represents the amplified sampling current transmitted by the first transistor Q1. That is, the gate-source voltage Vgs of the seventh power tube M7 and the eighth power tube M8 will instantly increase the target voltage dVgs. The target voltage dVg satisfies: dVgs≈[2I / (μ×Cox×W / L)]1 / 2+Vthp. Wherein, I represents the amplified sampling current transmitted by the first transistor Q1. μ represents the mobility of the seventh power tube M7 and the eighth power tube M8. Cox represents the unit capacitance of the gate oxide layer of the seventh power tube M7 and the eighth power tube M8. W / L represents the width-to-length ratio of the seventh power tube M7 and the eighth power tube M8. Vthp is the threshold voltage of the seventh power tube M7 and the eighth power tube M8.

[0073] The sampling current I increases the gate-source voltage of the seventh power tube M7, reduces the on-resistance of the seventh power tube M7, and instantly increases the voltage of the drain of the seventh power tube M7, that is, the error amplification voltage Vc transmitted to the output power tube M10 instantly increases, and the output power tube M10 is turned off. The output power tube 102 stops providing the output voltage to the voltage output terminal VOUT, so that the output voltage of the LDO circuit 10 drops rapidly, the overshoot is rapidly reduced, and the influence of the output voltage overshoot is weakened.

[0074] As the output voltage of the LDO circuit 10 gradually decreases, the sampling current I collected by the capacitor C gradually decreases. The sampling current I transmitted by the first transistor Q1 to the sixth power tube M6 decreases. The gate-source voltage of the seventh power tube M7 decreases, the on-resistance of the seventh power tube M7 increases, and the voltage of the drain of the seventh power tube M7 decreases. That is, the error amplified voltage Vc transmitted to the output power tube M10 decreases, the output power tube M10 is turned on, and the output power tube 102 provides an output voltage to the voltage output terminal Vout.

[0075] After the output voltage of the LDO circuit 10 is in a stable state, the sampling current I collected by the sampling capacitor C is in a stable state, and the sampling current I transmitted to the sixth power tube M6 by the first transistor Q1 is in a stable state. The gate-source voltage of the seventh power tube M7 is stable, the on-resistance of the seventh power tube M7 is stable, and the voltage of the drain of the seventh power tube M7 is stable. That is, the error amplified voltage Vc transmitted to the output power tube M10 is stable, and the output power tube 102 provides a stable output voltage to the voltage output terminal Vout.

[0076] Similarly, when the load current of the LDO circuit 10 jumps upward, for example, from 500uA to 15mA, the output voltage of the LDO circuit 10 will be instantly pulled down, and an undershoot phenomenon will occur, generating an undershoot voltage. The sampling capacitor C converts the undershoot voltage into a reduced sampling current I.

[0077] The first transistor Q1 amplifies the sampling current I received at its base, and outputs the amplified sampling current I to the source of the sixth power tube M6 through the collector. The sampling current I flows into the source of the sixth power tube M6, and is transmitted to the gate and drain of the eighth power tube M8 through the drain of the sixth power tube M6, so that the voltage of the drain of the eighth transistor M8 is reduced compared to when the LDO circuit 10 is in a stable state.

[0078] The drain of the eighth transistor M8 is connected to the gate of the eighth transistor M8 and the gate of the seventh transistor M7. The sampling current I reduces the gate-source voltage of the seventh power tube M7, increases the on-resistance of the seventh power tube M7, and reduces the voltage of the drain of the seventh power tube M7, that is, the error amplification voltage Vc transmitted to the output power tube M10 is reduced, and the on-resistance of the power adjustment tube M10 is reduced. The output power tube 102 provides an increased output voltage to the voltage output terminal Vout, so that the output voltage of the LDO circuit 10 increases rapidly, the undershoot is reduced rapidly, the influence of the output voltage undershoot is weakened, and the load transient response capability is improved.

[0079] As the output voltage of the LDO circuit 10 gradually increases, the sampling current I collected by the capacitor C gradually increases. The sampling current I transmitted by the first transistor Q1 to the sixth power tube M6 increases. The gate-source voltage of the seventh power tube M7 increases, the on-resistance of the seventh power tube M7 decreases, and the voltage of the drain of the seventh power tube M7 increases. That is, the error amplification voltage Vc transmitted to the output power tube M10 increases, the on-resistance of the power adjustment tube M10 increases, and the output power tube 102 provides a reduced output voltage to the voltage output terminal Vout until the output voltage of the LDO circuit 10 is stable.

[0080] In summary, the LDO circuit provided in the embodiment of the present application includes: a voltage sampling circuit, an output power tube, an error amplifier and a current sampling circuit. The voltage sampling circuit is used to transmit the feedback voltage corresponding to the voltage output terminal of the LDO circuit to the error amplifier. The error amplifier is used to generate an error amplification voltage according to the reference voltage and the feedback voltage, and transmit the error amplification voltage to the output power tube. The output power tube is used to convert the input voltage of the LDO circuit into an output voltage under the control of the error amplification voltage, and transmit the output voltage to the voltage output terminal. The current sampling circuit is used to convert the output voltage into a sampling current and transmit the sampling current to the error amplifier. The error amplifier is also used to positively adjust the error amplification voltage according to the sampling current.

[0081] In this technical solution, the current sampling circuit can convert the magnitude change of the output voltage into the magnitude change of the sampling current, so that the error amplifier generates an error amplified voltage that changes with the positive current. In this way, when the load of the LDO circuit jumps downward and the output voltage overshoots, the current sampling circuit can collect the increased sampling current, so that the error amplifier generates an increased error amplified voltage, controls the increase of the on-resistance of the output power tube, and quickly reduces the output voltage transmitted by the output power tube to the voltage output end, reduces the overshoot voltage of the LDO circuit, reduces the state recovery time of the output voltage of the LDO circuit, and improves the load transient response capability. Similarly, when the load of the LDO circuit jumps upward and the output voltage undershoots, the current sampling circuit can collect the reduced sampling current, so that the error amplifier generates a reduced error amplified voltage, controls the reduction of the on-resistance of the output power tube, quickly increases the output voltage transmitted by the output power tube to the voltage output end, reduces the undershoot voltage of the LDO circuit, reduces the state recovery time of the output voltage of the LDO circuit, and improves the load transient response capability. In addition, the LDO circuit provided in the embodiment of the present application also has the characteristics of easy implementation, good robustness, and small circuit area.

[0082] The present application also provides a power supply. The power supply may include the LDO circuit provided in the present application. Optionally, the power supply may include Figure 3 , Figure 4 or Figure 5 The power supply includes the aforementioned LDO circuit, and thus has the same technical effect as the aforementioned LDO circuit, and will not be described again here to avoid repetition.

[0083] The embodiment of the present application also provides an electronic device, which includes the LDO circuit provided in the embodiment of the present application, or includes the power supply provided in the embodiment of the present application. The electronic device includes the aforementioned LDO circuit, and thus has the same technical effect as the aforementioned LDO circuit, and will not be described here to avoid repetition.

[0084] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. A low dropout linear regulator LDO circuit, characterized in that: The LDO circuit includes: a voltage sampling circuit, an output power tube, an error amplifier and a current sampling circuit; The voltage sampling circuit is connected to the voltage output terminal of the LDO circuit and the error amplifier, and is used to transmit a feedback voltage corresponding to the voltage output terminal to the error amplifier; The current sampling circuit is connected to the error amplifier and the voltage output terminal, and is used for converting the output voltage of the voltage output terminal into a sampling current, and transmitting the sampling current to the error amplifier; The error amplifier is connected to the output power tube, and is used for positively adjusting the error amplified voltage of the feedback voltage and the reference voltage according to the sampling current, and transmitting the error amplified voltage to the output power tube; The output power tube is connected to the voltage output end, and is used for converting the input voltage into an output voltage under the control of the error amplification voltage, and transmitting the output voltage to the voltage output end.

2. The LDO circuit according to claim 1, characterized in that: The current sampling circuit comprises: a current conversion module and a current amplification module; The current conversion module is connected to the voltage output terminal and the current amplification module, and is used to convert the output voltage into a sampling current and transmit the sampling current to the current amplification module; The current amplification module is connected to the error amplifier, and is used to amplify the sampling current and transmit the amplified sampling current to the error amplifier.

3. The LDO circuit according to claim 2, characterized in that: The current conversion module includes: a sampling capacitor, and the sampling capacitor is used to convert the output voltage into the sampling current and transmit the sampling current to the error amplifier.

4. The LDO circuit according to claim 2 or 3, characterized in that: The device structure of the error amplifier is a folded common source and common gate structure; the current amplification module includes: a first current amplifier and a second current amplifier; The first current amplifier is connected to the first input end of the common-source and common-gate tube module of the current conversion module and the error amplifier, and is used to amplify the sampling current and transmit the amplified sampling current to the first input end; The second current amplifier is connected to the second input terminal of the common-source common-gate tube module, and is used to provide a matching current between the second input terminal and the first input terminal.

5. The LDO circuit according to claim 3, characterized in that: The first current amplifier is a first transistor, and the second current amplifier is a second transistor; The base of the first transistor is connected to the current conversion module, the base of the first transistor is also used to receive the bias voltage of the first transistor, the emitter of the first transistor is grounded, and the collector of the first transistor is connected to the first input terminal; The base of the second transistor is used to receive the bias voltage of the second transistor, the emitter of the second transistor is grounded, and the collector of the second transistor is connected to the second input terminal.

6. The LDO circuit according to claim 5, characterized in that: The current amplification module further includes: a first resistor and a second resistor; The base of the first transistor is also connected to a first bias voltage terminal through the first resistor, and the base of the second transistor is connected to the first bias voltage terminal through the second resistor. The first bias voltage terminal is used to provide bias voltages for the first transistor and the second transistor.

7. The LDO circuit according to claim 4, characterized in that: The error amplifier further includes: a differential input tube module, a tail current source tube, a power input tube module and a load tube module; The differential input tube module is connected to the voltage sampling module, the tail current source tube, the power input tube module and the first input end and the second input end of the common source and common gate tube module. The tail current source tube is connected to the voltage input end of the LDO circuit. The power input tube module is connected to the first input end and the second input end of the common source and common gate tube module, and the power input tube module is grounded. The common source and common gate tube module is also connected to the load tube module and the control end of the output power tube. The load tube module is also connected to the voltage input end, and the voltage input end is used to provide the input voltage.

8. The LDO circuit according to claim 7, characterized in that: The differential input tube module includes a first power tube and a second power tube, the power input tube module includes a third power tube and a fourth power tube, the common source and common gate tube module includes a fifth power tube and a sixth power tube, and the load tube module includes a seventh power tube and an eighth power tube. The gate of the first power tube is connected to the voltage sampling circuit, the drain of the first power tube is connected to the source of the sixth power tube and the drain of the fourth power tube, and the source of the first power tube is connected to the source of the second power tube and the drain of the tail current source tube; the gate of the second power tube is used to receive the reference voltage of the error amplifier, and the drain of the second power tube is connected to the source of the fifth power tube and the drain of the third power tube; The source of the third power tube and the source of the fourth power tube are grounded, the gate of the third power tube is connected to the gate of the fourth power tube and the second bias voltage terminal; the drain of the fifth power tube is connected to the drain of the seventh power tube and the control terminal of the output power tube, the gate of the fifth power tube is connected to the gate of the sixth power tube and the third bias voltage terminal; the drain of the sixth power tube is respectively connected to the drain, the gate and the gate of the seventh power tube of the eighth power tube; the source of the seventh power tube and the source of the eighth power tube are connected to the voltage input terminal; the source of the tail current source tube is connected to the voltage input terminal, and the gate of the tail current source tube is connected to the fourth bias voltage terminal; The first input end of the cascode module is the source of the sixth transistor, and the second input end is the source of the fifth transistor.

9. A power supply, characterized in that: The power supply comprises: a low dropout linear regulator LDO circuit as described in any one of claims 1 to 8.

10. An electronic device, characterized in that: The electronic device comprises: the low dropout linear regulator LDO circuit according to any one of claims 1 to 8, or the power supply according to claim 9.

Images