Separated planar gate low-resistance silicon carbide VDMOS

Abstract

The utility model provides a separated planar gate low-resistance silicon carbide VDMOS. The separated planar gate low-resistance silicon carbide VDMOS comprises a silicon carbide substrate; the lower side surface of the drift layer is connected to the upper side surface of the silicon carbide substrate; the well region is connected to the drift layer, and a source region is arranged in the well region; the low-resistance structure layer penetrates through the well region and is connected to the drift layer; the gate dielectric layer is connected to the well region and the low-resistance structure layer, and a groove is formed in the gate dielectric layer; the source electrode metal layer is connected to the well region and the source region; the gate metal layer is arranged in the groove, and the gate metal layer is positioned above the well region between the low-resistance structure layer and the source region; and the drain metal layer is connected to the lower side surface of the silicon carbide substrate, so that the area of a gate control inversion region is reduced, the gate charge is further reduced, and the driving loss of the device is reduced.

Description

Technical Field

[0001] The utility model relates to a separated plane gate low-resistance silicon carbide VDMOS. Background Art

[0002] As a representative device among SiC power devices, SiC VDMOS is widely used in electric vehicles, aerospace, power conversion and other fields. The gate charge of the device directly affects the switching speed and switching loss of the device. Reducing the gate charge is of great significance for increasing the operating frequency of the device and thus increasing the power density of the power system. It has a good effect on promoting the realization of the dual carbon goals. Utility Model Content

[0003] The technical problem to be solved by the utility model is to provide a separated planar gate low-resistance silicon carbide VDMOS, which reduces the area of ​​the gate control inversion region, thereby reducing the gate charge and reducing the driving loss of the device.

[0004] The utility model is implemented as follows: a separated planar gate low-resistance silicon carbide VDMOS, comprising:

[0005] Silicon carbide substrate;

[0006] A drift layer, wherein a lower side of the drift layer is connected to an upper side of the silicon carbide substrate;

[0007] A well region, the well region is connected to the drift layer, and a source region is arranged in the well region;

[0008] a low resistance structure layer, the low resistance structure layer passing through the well region and connected to the drift layer;

[0009] a gate dielectric layer, the gate dielectric layer being connected to the well region and the low-resistance structure layer, and the gate dielectric layer being provided with a groove;

[0010] A source metal layer connected to the well region and the source region;

[0011] A gate metal layer, wherein the gate metal layer is disposed in the groove and is located above the well region between the low resistance structure layer and the source region;

[0012] and a drain metal layer connected to the lower side of the silicon carbide substrate.

[0013] The advantages of the utility model are:

[0014] 1. The device adopts a planar gate structure and a split gate structure at the gate of the device, which reduces the area of ​​the gate-controlled inversion region, thereby reducing the gate charge and the driving loss of the device;

[0015] Second, the low-resistance structure layer of the device is arranged in the JFET region, and the JFET region forms a pn junction with the well region, which consumes the hole concentration in the gate control region, thereby reducing the full conduction voltage of the device and reducing the driving loss;

[0016] 3. The doping concentration of the low-resistance structure layer is 1e17 cm -3 , which reduces the on-resistance of the JFET region of the device and reduces device losses. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The present invention will be further described below in conjunction with the embodiments with reference to the accompanying drawings.

[0018] Figure 1 The utility model is a schematic diagram of a separated planar gate low-resistance silicon carbide VDMOS.

[0019] Figure 2 The utility model is a flow chart of a method for preparing a separated planar gate low-resistance silicon carbide VDMOS.

[0020] Figure 3 This is a process cross-section of a separated planar gate low-resistance silicon carbide VDMOS of the utility model. Figure 1 .

[0021] Figure 4 This is a process cross-section of a separated planar gate low-resistance silicon carbide VDMOS of the utility model. Figure 2 .

[0022] Figure 5 This is a process cross-section of a separated planar gate low-resistance silicon carbide VDMOS of the utility model. Figure 3 .

[0023] Figure 6 This is a process cross-section of a separated planar gate low-resistance silicon carbide VDMOS of the utility model. Figure 4 .

[0024] Figure 7 This is a process cross-section of a separated planar gate low-resistance silicon carbide VDMOS of the utility model. Figure 5 .

[0025] Figure 8 This is a process cross-section of a separated planar gate low-resistance silicon carbide VDMOS of the utility model. Figure 6 .

[0026] Fig. 9 This is a process cross-section of a separated planar gate low-resistance silicon carbide VDMOS of the utility model. Figure 7 .

[0027] Fig.10 This is a process cross-section of a separated planar gate low-resistance silicon carbide VDMOS of the utility model. Figure 8 . DETAILED DESCRIPTION

[0028] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0030] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "in contact with ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0031] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of one element or feature described in the figures to other elements or features. It should be understood that, in addition to the orientations described in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0032] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0033] like Figure 1 As shown, the embodiment of the present application provides a separated planar gate low-resistance silicon carbide VDMOS, including:

[0034] Silicon carbide substrate 1;

[0035] A drift layer 2, wherein the lower side of the drift layer 2 is connected to the upper side of the silicon carbide substrate 1;

[0036] A well region 3, wherein the well region 3 is connected to the drift layer 2, and a source region 31 is disposed in the well region 3;

[0037] A low-resistance structure layer 4, wherein the low-resistance structure layer 4 passes through the well region 3 and is connected to the drift layer 2;

[0038] A gate dielectric layer 5, the gate dielectric layer 5 is connected to the well region 3 and the low-resistance structure layer 4, and a groove 51 is provided on the gate dielectric layer 5;

[0039] A source metal layer 6, wherein the source metal layer 6 is connected to the well region 3 and the source region 31;

[0040] A gate metal layer 7, wherein the gate metal layer 7 is disposed in the groove 31 and is located above the well region 3 between the low resistance structure layer 4 and the source region 31;

[0041] and, a drain metal layer 8, wherein the drain metal layer 8 is connected to the lower side of the silicon carbide substrate 1;

[0042] The silicon carbide substrate 1 , the drift layer 2 , the low-resistance structure layer 4 and the source region 31 are all of N-type, and the well region 3 is of P-type.

[0043] The device adopts a planar gate structure, and the planar gate adopts a separated gate structure. The separated gate metal layer 7 is only distributed above the p-type well region 3 between the source region 31 and the low-resistance structure layer 4, and only the gate control is performed on this part of the p-type well region 3, which reduces the gate charge and thus reduces the driving loss of the device;

[0044] An n-type doped low-resistance structure layer 4 is provided in the JFET region of the device, and the low-resistance structure layer 4 forms a pn junction with the p-type well region 3, partially consuming the hole concentration in the gate control region, thereby reducing the gate drive voltage when the device is fully turned on, and reducing the drive loss;

[0045] An np structure (low-resistance structure layer 4 and p-type well region 3) is formed near the gate of the device, which has the ability to suppress drain voltage overshoot;

[0046] The doping concentration of the low-resistance structure layer 4 is 1e17 cm -3 ; This doping concentration is higher than that of the n-type drift layer 2, which can reduce the on-resistance of the JFET region and thus reduce the loss of the device.

[0047] like Figures 1 to 10 As shown, the method for preparing the silicon carbide VDMOS comprises the following steps:

[0048] Step 1: depositing metal on one side of the silicon carbide substrate 1 to form a drain metal layer 8, and depositing and growing a drift layer 2 on the other side of the silicon carbide substrate 1;

[0049] Step 2, depositing a barrier layer a on the drift layer 2, etching the barrier layer a to form a through hole, and performing ion implantation on the drift layer 2 to form a low-resistance structure layer 4, wherein the ion implantation energy of the low-resistance structure layer 4 is 100-1500kev;

[0050] Step 3, removing the original barrier layer a, re-forming the barrier layer a, etching the barrier layer a to form a through hole, and performing ion implantation on the drift layer 2 through the through hole to form a well region 3, wherein the ion implantation energy of the well region 3 is 100-500kev;

[0051] Step 4, remove the original barrier layer a, re-form the barrier layer a, etch to form a through hole, and perform ion implantation into the well region 3 through the through hole to form a source region 31, wherein the ion implantation energy of the source region 31 is 10-100 keV;

[0052] Step 5, removing the original barrier layer a, re-forming the barrier layer a, etching to form a through hole, and performing metal deposition on the through hole to form a source metal layer 6;

[0053] Step 6, removing the original barrier layer a, re-forming the barrier layer a, etching to form a through hole, depositing the through hole, and forming a gate dielectric layer 5;

[0054] Step 7, remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a and the gate dielectric layer 5 to form a through hole and a groove 51, perform metal deposition on the groove 51 through the through hole to form a gate metal layer 7, wherein the gate metal layer 7 is located above the well region 3 between the low resistance structure layer 4 and the source region 31; remove the barrier layer a, and complete the manufacturing;

[0055] The silicon carbide substrate 1, the drift layer 2, the low-resistance structure layer 4 and the source region 31 are all N-type, the well region 3 is P-type, and the doping concentration of the silicon carbide substrate 1 is 2e18cm -3 The doping concentration of the drift layer 2 is 3e16 cm -3 The doping concentration of the low-resistance structure layer 4 is 1e17cm -3 The doping concentration of the well region 3 is 6e16 cm -3 The doping concentration of the source region 31 is 5e19cm -3 .

[0056] Although the specific implementation methods of the present invention are described above, those skilled in the art should understand that the specific embodiments described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. A split planar gate low-resistance silicon carbide VDMOS, characterized in that: include: Silicon carbide substrate; A drift layer, wherein a lower side of the drift layer is connected to an upper side of the silicon carbide substrate; A well region, the well region is connected to the drift layer, and a source region is arranged in the well region; a low resistance structure layer, the low resistance structure layer passing through the well region and connected to the drift layer; a gate dielectric layer, the gate dielectric layer being connected to the well region and the low-resistance structure layer, and the gate dielectric layer being provided with a groove; A source metal layer connected to the well region and the source region; A gate metal layer, wherein the gate metal layer is disposed in the groove and is located above the well region between the low resistance structure layer and the source region; and a drain metal layer connected to the lower side of the silicon carbide substrate.

2. A split planar gate low-resistance silicon carbide VDMOS according to claim 1, characterized in that: The silicon carbide substrate, drift layer, low-resistance structure layer and source region are all N-type, and the well region is P-type.

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