Semiconductor device and display panel

Abstract

The invention discloses a semiconductor device and a display panel, the semiconductor device comprises an insulating substrate, at least one data input terminal and a plurality of clock lines, a plurality of shift registers are divided into a plurality of shift register groups, and each clock line in the plurality of clock lines controls the rate of one shift register group. Compared with controlling all shift registers through a single clock line, the rate of the shift register can be easily increased to a higher level as the frequency of the plurality of clock signals increases.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a semiconductor device and a display panel. Background Art

[0002] With the rise of 5G, Internet of Things (IoT), automobiles and other industries, the demand for silicon-based integrated circuits (ICs) is increasing. In addition, chips are expensive, and the shortage of chips may continue.

[0003] In a display panel, a source driver for providing a data signal usually exists in the form of a chip. However, the speed of the source driver is limited by a bottleneck and is difficult to increase. Summary of the invention

[0004] The present application provides a semiconductor device and a display panel to alleviate the technical problem that the speed of a source driver is limited by a bottleneck and is difficult to increase.

[0005] In a first aspect, the present application provides a semiconductor device, which includes an insulating substrate, at least one data input terminal and multiple clock lines, the insulating substrate includes a source driver, the source driver includes multiple shift register groups, each shift register group includes multiple shift registers, and the shift registers are electrically connected to corresponding pixel circuits through data lines; at least one data input terminal is electrically connected to the first-level shift register in each shift register group; each clock line is electrically connected to each shift register in the same shift register group.

[0006] In some of the implementations, the multiple clock lines are used to transmit multiple clock signals with the same frequency and different phases.

[0007] In some implementations, the shift registers in the plurality of shift register groups are arranged alternately in sequence.

[0008] In some of the embodiments, a clock line transmitting a clock signal with a later phase is electrically connected to a shift register group arranged later.

[0009] In some embodiments, the multiple shift register groups include a first shift register group and a second shift register group, and at least one data input terminal is electrically connected to the first shift register group and the second shift register group, respectively; the multiple clock lines include a first clock line and a second clock line, the first clock line is electrically connected to one of the first shift register group or the second shift register group, and the second clock line is electrically connected to the other of the first shift register group or the second shift register group.

[0010] In some embodiments, multiple shift register groups include a first shift register and a second shift register arranged alternately in sequence, the first shift register group includes a first shift register, and the second shift register group includes a second shift register; the first clock line is electrically connected to the first shift register group, and the second clock line is electrically connected to the second shift register group, the first clock line is used to transmit a first clock signal, and the second clock line is used to transmit a second clock signal, and the phase of the second clock signal lags behind the phase of the first clock signal.

[0011] In some embodiments, the frequency of the first clock signal is the same as the frequency of the second clock signal, and the phase difference between the first clock signal and the second clock signal is 180°.

[0012] In some of the embodiments, the source driver further includes a signal processing module, an input end of each signal processing module is electrically connected to an output end of a shift register, and each signal processing module outputs a corresponding data signal.

[0013] In some embodiments, the signal processing module includes a latch, a level converter, a digital-to-analog converter, and an amplifier electrically connected in sequence, the input end of the latch is electrically connected to the output end of the shift register, the trigger end of the latch is electrically connected to the data enable line, and the amplifier is used to output the corresponding data signal.

[0014] In some of the embodiments, at least one data input terminal and at least one of the plurality of clock lines are disposed in an insulating substrate.

[0015] In a second aspect, the present application provides a display panel, which includes the semiconductor device in at least one of the above-mentioned embodiments, wherein the data input terminal is used to transmit a digital signal.

[0016] The semiconductor device and display panel provided by the present application divide multiple shift registers into multiple shift register groups, and each clock line in the multiple clock lines controls the rate of a shift register group. Compared with controlling multiple shift registers through a single clock line, not only can the same rate as that of all shift registers controlled by a single clock line be achieved through multiple clock signals with lower frequencies in the multiple clock lines, but also there is a greater room for improvement due to the reduction in the frequency of multiple clock signals in the multiple clock lines. Therefore, as the frequency of the multiple clock signals increases, the rate of the shift register can be easily increased to a higher level, thereby increasing the rate of the source driver.

[0017] In addition, the source driver can be integrated into the insulating substrate in a non-chip form, which can not only alleviate the tight demand for silicon-based integrated circuits, but also reduce the cost of the source driver, thereby reducing the manufacturing cost of semiconductor devices or display panels. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0019] Figure 1 It is a schematic diagram of the first structure of a source driver in the related art.

[0020] Figure 2 for Figure 1 Schematic diagram of waveform simulation of relevant signals in .

[0021] Figure 3 It is a second structural diagram of a source driver in the related art.

[0022] Figure 4 A first structural schematic diagram of a semiconductor device provided in an embodiment of the present application.

[0023] Figure 5 for Figure 4 Schematic diagram of waveform simulation of relevant signals in .

[0024] Figure 6 A second structural schematic diagram of a semiconductor device provided in an embodiment of the present application.

[0025] Figure 7 A schematic diagram of the structure of a display panel provided in an embodiment of the present application. DETAILED DESCRIPTION

[0026] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0027] In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance or implicitly indicating the number of technical features indicated. Therefore, the features specified as "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present invention, "multiple" means two or more, unless otherwise clearly and specifically defined.

[0028] Figure 1 , Figure 3The source drivers are all integrated circuits formed on a silicon base. The source drivers finally generate data signals (D1, D2...Dn) required for the pixel array in the display area through shift registers (SH_unit_1, SH_unit_2...SH_unit_n), latches (LA_unit_1, LA_unit_2...LA_unit_n), level conversion circuits or level converters (LS_unit_1, LS_unit_2...LS_unit_n), analog-to-digital converters (DAC_1, DAC_2...DAC_n) and amplifiers (OP_1, OP_2...OP_n) that are electrically connected in sequence.

[0029] In fact, the source driver is a circuit for generating data signals of at least one gray scale. Figure 1 Taking the 2-bit digital signal (Vdata1, Vdata2) shown as an example, a 4-grayscale data signal can be generated. Its working principle is: a 2-bit digital signal, i.e., binary image information, is input in parallel. Through the shift of the clock signal CLK, Vdata1 and Vdata2 are shifted by the first-stage shift register SH_unit_1 to obtain output signals Out1_1 and Out2_1. The output signals Out1_1 and Out2_1 are both input into the latch LA_unit_1 and serve as the input signals of the second-stage shift register SH_unit_2. After being shifted by the second-stage shift register SH_unit_2, the output signals Out1_2 and Out2_2 are obtained. And so on, shifting step by step until the n-th-stage shift register SH_unit_n provides the output signals Out1_n and Out2_n.

[0030] by Figure 3Taking the 4-bit digital signal (Vdata1, Vdata2, Vdata3, Vdata4) shown as an example, a 16-grayscale data signal can be generated. The working principle is: a 4-bit digital signal, i.e., binary image information, is input in parallel. Through the shift of the clock signal CLK, Vdata1, Vdata2, Vdata3, and Vdata4 are shifted by the first-stage shift register SH_unit_1 to obtain output signals Out1_1, Out2_1, Out3_1, and Out4_1. The output signals Out1_1, Out2_1, Out3_1, and Out4_1 are both input into the latch LA_unit_1 and serve as the input signals of the second-stage shift register SH_unit_2. After being shifted by the second-stage shift register SH_unit_2, the output signals Out1_2, Out2_2, Out3_2, and Out4_2 are obtained. And so on, shifting step by step until the n-th-stage shift register SH_unit_n provides output signals Out1_n, Out2_n, Out3_n, and Out4_n.

[0031] Digital signals of other bits can be obtained in the same way.

[0032] Afterwards, the data enable signal DE is used to identify the states of the two output signals provided by each stage of the shift register, and the latches (LA_unit_1, LA_unit_2...LA_unit_n) are controlled to start working at the same time; then, the output signals of the latches are boosted through the level converters. The reason for the boost here is that the shift register and the latch are digital modules with a small voltage difference requirement, but they are later converted into analog signals with a large voltage difference requirement; then, they are simultaneously input to the subsequent analog-to-digital converters to convert the digital signals into analog signals required by the pixels; finally, the data signals (D1, D2...Dn) with enhanced capabilities are output through the amplifiers.

[0033] Above Figure 1 The working sequence of Zhongyuan driver is as follows Figure 2 As shown, taking the generation of 10 data signals as an example, assuming that the period of the clock signal CLK, i.e. CLK_T, is vs (vs is a time unit of the order of us / ns or less), the period of Vdata1, i.e. Vdata1_T, and the period of Vdata2, i.e. Vdata2_T, are 2vs and 4vs respectively, wherein Vdata1 and Vdata2 are parallel inputs.

[0034] in, Figure 2The process of Vdata1 being shifted by 10 levels is fully shown, namely Out1_1 to Out1_10. Out1_2 is delayed by vs compared to Out1_1, and so on. The completion time of Vdata1 being shifted by 10 levels is 10vs. In the timing diagram, the process of Vdata2 being shifted by 10 levels, namely Out2_1 to Out2_9, is omitted. The shifting principle of Vdata2 is the same as that of Vdata1, and it can be deduced by oneself according to the above process of Vdata1.

[0035] As mentioned above, the data enable signal DE takes effect only after the output signals are provided by each level of the shift register. Therefore, in the timing diagram, the period of the data enable signal DE is 10Vs, and the starting time of the data enable signal DE is the same as the starting times of Out1_10 and Out2_10. Since the subsequent latches, level converters, digital-to-analog converters, and amplifiers are all processed in parallel, the data signal D10 output by the 10th-level shift register is taken as an example in the timing diagram. Each latch is triggered in response to the rising edge of the data enable signal DE (the working principle of the D flip-flop). Out1_10 and Out2_10 output low-frequency 2-bit digital signals LA1_10 and LA2_10 after passing through the latch LA_unit_10. Among them, L1 is the low potential of LA1_10, H1 is the high potential of LA1_10, H2 > H1, and L2 < L1. After being boosted by the level converter LS_unit_10, LS1_10 and LS2_10 are obtained. Finally, after being processed by the digital-to-analog converter DAC_10 (not shown) and the amplifier OP_10 (not shown), a data signal D10 of analog type with 4 gray-scale voltages is obtained.

[0036] It should be noted that the amplifier OP_10 is used to enhance the output ability. The data signal D10 has been generated in the digital-to-analog converter DAC_10. The digital-to-analog converter belongs to a linear voltage-dividing type digital-to-analog converter, and its minimum voltage is the potential of the power negative signal Vss, and the maximum voltage is the potential of the power positive signal Vdd.

[0037] Figure 3 The working process of the shown source driver is similar to Figure 1 the working process of the shown source driver. The difference is that Figure 1 the shown source driver accesses two-bit digital signals, so all the signals processed during the modulation of each data signal and before the access of the analog-to-digital converter are also two-bit digital signals; while Figure 4 the shown source driver accesses four-bit digital signals, so all the signals processed during the modulation of each data signal and before the access of the analog-to-digital converter are also four-bit digital signals.

[0038] Based on the working principle of generating data signals, it can be known that the key to the speed or rate bottleneck of the source driver lies in the shift register. The input signal (Vdata) will be processed in the latch only after it shifts n stages, and the number of stages of the shift register is related to the number of columns of pixels in the display panel. Therefore, the higher the resolution or refresh rate of the display panel, the faster the speed of the single-stage shift register needs to be, that is, the frequency of the clock signal CLK needs to be higher and higher, until the clock signal CLK becomes a high-frequency signal that cannot be increased in frequency.

[0039] However, this will cause two problems. One problem is that the high-frequency clock signal CLK is easily affected by the load. As the resolution of the display panel increases, the number of shift registers increases. During the process of transmitting the clock signal CLK to the remote shift register, the loading is large and it is easy to be distorted, resulting in abnormal output of the tail-stage shift register. Another problem is that the speed of glass-based transistors is worse than that of silicon-based transistors. It is difficult to increase the operating speed of the shift register under the high-frequency clock signal CLK.

[0040] Therefore, in view of the technical problem that the speed of the source driver is limited by the bottleneck and is difficult to improve, this embodiment provides a semiconductor device 1000, see Figures 4 to 7 ,like Figure 4 , Figure 6 As shown, the semiconductor device 1000 includes an insulating substrate 500 , at least one data input terminal 300 , and at least one of a plurality of clock lines.

[0041] The insulating substrate 500 includes a source driver 100 , and the source driver 100 includes a plurality of shift register groups 109 , each of which includes one or more shift registers.

[0042] At least one data input terminal 300 is electrically connected to the shift register of the first stage in each shift register group 109 .

[0043] Each clock line is electrically connected to each shift register in the same shift register group 109 .

[0044] It can be understood that the semiconductor device 1000 provided in this embodiment divides multiple shift registers connected end to end (the output end of the last one is not connected to the output end of the first one) into multiple shift register groups 109, and each clock line in the multiple clock lines controls the rate of a shift register group 109. Compared with controlling multiple shift registers connected end to end by a single clock line, not only can the same rate as that of all shift registers controlled by a single clock line be achieved by using multiple clock signals with lower frequencies in the multiple clock lines, but also because the frequencies of the multiple clock signals in the multiple clock lines are reduced, there is greater room for improvement. Therefore, as the frequencies of the multiple clock signals increase, the rate of the shift register can be easily increased to a higher level, thereby increasing the rate of the source driver 100.

[0045] In addition, the source driver 100 can be integrated into the insulating substrate 500 in a non-chip form, which can not only alleviate the tight demand for silicon-based integrated circuits, but also reduce the cost of the source driver 100 and improve the utilization rate of the insulating substrate 500, thereby reducing the manufacturing cost of the semiconductor device 1000 or the display panel.

[0046] Among them, when there are multiple shift registers in the same shift register group 109, the multiple shift registers are connected end to end in sequence, that is, in a shift register group 109, the input end of the first shift register is connected to at least one data input terminal 300, the output end of the first shift register is connected to the input end of the second shift register, the output end of the second shift register is connected to the input end of the third shift register, and so on.

[0047] It should be noted that the data input terminal is used to transmit digital signals, for example, Figure 4 Vdata1, Vdata2 in; or Figure 6 The number of shift register groups 109 is the same as the number of clock lines. The plurality of shift register groups 109 may be 2, 3 or more integer shift register groups 109. The plurality of lines may also be two, 3 or more.

[0048] In one embodiment, the multiple clock lines are used to transmit multiple clock signals with the same frequency and different phases.

[0049] It should be noted that, in this embodiment, by means of different phases of the clock signals, the shift registers in different shift register groups 109 can be controlled to sequentially provide corresponding output signals as required.

[0050] In one embodiment, the shift registers in the plurality of shift register groups 109 are arranged alternately in sequence.

[0051] It should be noted that, in this embodiment, the shift registers in the plurality of shift register groups 109 are alternately arranged in sequence, which is beneficial for controlling the shift registers in different shift register groups 109 to provide corresponding output signals in sequence as needed.

[0052] In one embodiment, the clock line of the clock signal with a later transmission phase is electrically connected to the shift register group 109 arranged later. Alternatively, the clock lines of the clock signal with a later transmission phase are electrically connected to the shift register group 109 where the shift registers arranged later in sequence are located.

[0053] It should be noted that this embodiment can further control the shift registers in different shift register groups 109 to provide corresponding output signals in sequence as needed.

[0054] In one embodiment, if Figure 4 As shown, the multiple shift register groups 109 include a first shift register group 110 and a second shift register group 120, and at least one data input terminal 300 is electrically connected to the first shift register group 110 and the second shift register group 120 respectively; the multiple clock lines include a first clock line 202 and a second clock line 201, the first clock line 202 is electrically connected to one of the first shift register group 110 or the second shift register group 120, and the second clock line 201 is electrically connected to the other of the first shift register group 110 or the second shift register group 120.

[0055] It should be noted that at least one data input terminal 300 can synchronously provide corresponding digital signals, such as Vdata1 and Vdata2, to each shift register group 109 to generate data signals of corresponding grayscales.

[0056] In one embodiment, the plurality of shift register groups 109 include a first shift register 130 and a second shift register 140 arranged alternately in sequence, the first shift register group 110 includes the first shift register 130, and the second shift register group 120 includes the second shift register 140; the first clock line 202 is electrically connected to the first shift register group 110, and the second clock line 201 is electrically connected to the second shift register group 120, the first clock line 202 is used to transmit a first clock signal CLKn, and the second clock line 201 is used to transmit a second clock signal CLKp, and the phase of the second clock signal CLKp lags behind the phase of the first clock signal CLKn.

[0057] It should be noted that, in this embodiment, the frequency of the first clock signal CLKn and the frequency of the second clock signal CLKp may be lower than Figure 2Therefore, when the source driver 100 needs a higher speed, the frequency of the first clock signal CLKn and the frequency of the second clock signal CLKp have greater room for improvement, so the speed of the source driver 100 also has greater room for improvement.

[0058] The first shift register 130 may be at least one of the first shift register SH_unit_1, the third shift register SH_unit_3, ..., the 2n-1th shift register SH_unit_2n-1. The second shift register 140 may be at least one of the second shift register SH_unit_2, the fourth shift register SH_unit_4, ..., the 2nth shift register SH_unit_2n.

[0059] The first shift registers 130 and the second shift registers 140 may be arranged alternately from left to right, with each first shift register 130 being distributed in an odd column, and each second shift register 140 being distributed in an even column.

[0060] In one embodiment, the frequency of the first clock signal CLKn is the same as the frequency of the second clock signal CLKp, and the phase difference between the first clock signal CLKn and the second clock signal CLKp is 180°.

[0061] It should be noted that, in this embodiment, the frequency of the first clock signal CLKn and the frequency of the second clock signal CLKp can be reduced to Figure 2 Therefore, when the source driver 100 needs a higher rate, the frequency of the first clock signal CLKn and the frequency of the second clock signal CLKp have greater room for improvement, so that the rate of the source driver 100 also has greater room for improvement. The phase difference between the first clock signal CLKn and the second clock signal CLKp is 180°. Specifically, the phase of the second clock signal CLKp lags behind the phase of the first clock signal CLKn, so that the data signals D1, D2, D3, D4...Dn can output pulses for charging in the same frame.

[0062] In one embodiment, if Figure 4 As shown, the source driver 100 further includes signal processing modules, the input end of each signal processing module is electrically connected to the output end of a shift register, and each signal processing module outputs a corresponding data signal.

[0063] It should be noted that, in this embodiment, the signal processing module can be used to convert the output signal of each shift register into the data signal required by the pixel.

[0064] In one embodiment, if Figure 4 As shown, the signal processing module includes a latch, a level converter, a digital-to-analog converter and an amplifier which are electrically connected in sequence. The input end of the latch is electrically connected to the output end of the shift register, the trigger end of the latch is electrically connected to the data enable line, and the amplifier is used to output the corresponding data signal.

[0065] It should be noted that the specific working principle of this embodiment can refer to the above Figure 1 The data enable line is used to transmit the data enable signal DE.

[0066] It should be noted that compared with Figure 2 , Figure 5 Just Figure 2 The clock signal CLK in the embodiment is split into two parallel first clock signals CLKn and second clock signals CLKp. The frequencies of the first clock signal CLKn and the second clock signal CLKp are both half of the frequency of the clock signal CLK.

[0067] Assume that one cycle of the clock signal CLK is T, the total number of shift registers is n (the n data signals required by the pixel array in the display panel are D1 / 2…n), the first clock signal CLKn and the second clock signal CLKp have the same cycle and opposite phases, and the two sets of stage transmissions, such as one set of stage transmissions for the first register group and one set of stage transmissions for the second register group, still use one set of input signals Vdata1 and Vdata2. The first clock signal CLKn is responsible for the stage transmission of the odd-numbered shift registers, such as SH_unit_1 / 3 / 5…n-1, and the output Out1 / 2_1 of SH_unit_1 is the input of SH_unit_3; the second clock signal CLKp is responsible for the stage transmission of the even-numbered shift registers, such as SH_unit_2 / 4 / 6…n, and the time (t) to complete the n-stage shift remains unchanged. Figure 2 t = nT, now Figure 5 In this case, the frequency of the first clock signal CLKn and the frequency of the second clock signal CLKp are lower than the frequency of the clock signal CLK, and are less affected by loading. In addition, the number of shifts of the first clock signal CLKn and the second clock signal CLKp is small, which can better solve the problem of a clock signal CLK being Figure 1 There are two problems faced by multi-stage shifting. After the shift is completed, the subsequent operations of the signal processing module can be Figure 1 The relevant descriptions are consistent.

[0068] The working process of the source driver 100 in the above embodiments is as follows: Figure 5 As shown, still taking the generation of 10 data signals as an example, Figure 2The clock signal CLK with a period of vs is down-converted into a first clock signal CLKn and a second clock signal CLKp with opposite phases and a period of 2vs. The first clock signal CLKn is responsible for the stage transmission of the odd-numbered shift registers, and the second clock signal CLKp is responsible for the stage transmission of the even-numbered shift registers. The periods of Vdata1, i.e. Vdata1_T, and Vdata2, i.e. Vdata2_T, are 4vs and 8vs respectively. Vdata1 and Vdata2 are respectively input in parallel into the first-stage shift register in the first register group and the first-stage shift register in the second register group.

[0069] Figure 5 The process of Vdata1 shifting through 10 stages is fully shown in Figure 2 The difference is that Vdata1 is completed by shifting 5 levels in parallel through the first clock signal CLKn and the second clock signal CLKp respectively. Figure 1 The operation of the 10-stage shift register, i.e., the 5 shift registers SH_unit_1, SH_unit_3 ... SH_unit_9 in the first shift register group 110, which are connected head to tail in sequence, undergo 5-stage shifting, and the 5 shift registers SH_unit_2, SH_unit_4 ... SH_unit_10 in the second shift register group 120, which are connected head to tail in sequence, undergo 5-stage shifting in parallel. Out1_3 is delayed by 2vs compared to Out1_1, and Out1_4 is delayed by 2vs compared to Out1_2. Therefore, the time to complete the 10-stage shift is still 10vs = 5*2vs. Since the second clock signal CLKp is opposite to the first clock signal CLKn in phase, it can be considered that the phase of the second clock signal CLKp lags the phase of the first clock signal CLKn by vs, so Out1_2 is still delayed by vs compared to Out1_1, which is consistent with Figure 2 Be consistent.

[0070] in, Figure 5 The figure shows the intermediate timing of latch LA_9 / 10, level converter LS_9 / 10, and 4-grayscale data signals D9 and D10. It can be seen that the parallel operation of the first clock signal CLKn and the second clock signal CLKp does not change the frequency of the generated data signal, but the frequency of the high-speed shift register slows down and is not easily affected by loading; on the other hand, using two lower-frequency first clock signals CLKn and second clock signals CLKp to achieve the mission of a higher-frequency clock signal CLK can break through the rate bottleneck of glass-based devices.

[0071] It should be noted that Figure 6 The source driver operation process shown is similar to Figure 4 The source driver shown works similarly, except that Figure 4The source driver shown is connected to a two-bit digital signal, so in the process of modulating each data signal and before the analog-to-digital converter is connected, the two-bit digital signal is also processed; and Figure 6 The source driver shown is connected to a four-bit digital signal, so in the process of modulating each data signal and before the analog-to-digital converter is connected, four-bit digital signals are also processed.

[0072] In one embodiment, at least one data input terminal 300 and at least one of the plurality of clock lines are disposed in the insulating substrate 500 .

[0073] It should be noted that in this embodiment, at least one data input terminal 300 and at least one of the multiple clock lines are arranged in the insulating substrate 500 , which not only saves the original occupied space of these hardware in the semiconductor device 1000 , but also further improves the utilization rate of the insulating substrate 500 .

[0074] In one embodiment, this embodiment provides a display panel, which includes the semiconductor device 1000 in at least one of the above embodiments.

[0075] It can be understood that since the display panel provided in this embodiment includes the semiconductor device 1000 in at least one of the above-mentioned embodiments, it is also possible to divide a plurality of shift registers into a plurality of shift register groups 109, and each clock line in a plurality of clock lines controls the rate of a shift register group 109. Compared with controlling a plurality of shift registers through a single clock line, not only can the same rate as that of all shift registers controlled by a single clock line be achieved through a plurality of clock signals with lower frequencies in a plurality of clock lines, but also the frequency of a plurality of clock signals in a plurality of clock lines is reduced, resulting in a greater room for improvement. Therefore, as the frequency of a plurality of clock signals increases, the rate of the shift register can be easily increased to a higher level, thereby increasing the rate of the source driver 100.

[0076] In addition, the source driver 100 can be integrated into the insulating substrate 500 in a non-chip form, which can not only alleviate the tight demand for silicon-based integrated circuits, but also reduce the cost of the source driver 100, thereby reducing the manufacturing cost of the semiconductor device 1000 or the display panel.

[0077] It should be noted that the display panel further includes a plurality of data lines, each of which is electrically connected to an output end of a shift register to transmit a corresponding data signal to a pixel.

[0078] The display panel may be, but is not limited to, a liquid crystal display panel, and may also be a self-luminous display panel.

[0079] like Figure 7As shown, the display panel further includes a gate driving circuit (GOA, gate on array), a pixel array in the display area AA, and a field programmable gate array (FPGA, Field Programmable Gate Array) that provides an external power supply and required input signals.

[0080] The gate driving circuit is also integrated into the semiconductor device 1000 or the display panel in a non-chip form, which further reduces the demand for chips and reduces costs.

[0081] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0082] The semiconductor device 1000 and the display panel provided in the embodiments of the present application are introduced in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A semiconductor device, characterized in that: The semiconductor device comprises: An insulating substrate, the insulating substrate comprising a source driver, the source driver comprising a plurality of shift register groups, each shift register group comprising a plurality of shift registers, the shift registers being electrically connected to corresponding pixel circuits via data lines; at least one data input terminal, the at least one data input terminal being electrically connected to a first-stage shift register in each of the shift register groups; and A plurality of clock lines, each of the clock lines is electrically connected to each shift register in the same shift register group.

2. The semiconductor device according to claim 1, wherein: The multiple clock lines are used to transmit multiple clock signals with the same frequency and different phases.

3. The semiconductor device according to claim 1, wherein: The shift registers in the plurality of shift register groups are arranged alternately in sequence.

4. The semiconductor device according to claim 2, characterized in that The clock line transmitting the clock signal with a later phase is electrically connected to the shift register group arranged later.

5. The semiconductor device according to claim 1, wherein: The plurality of shift register groups include a first shift register group and a second shift register group, and the at least one data input terminal is electrically connected to the first shift register group and the second shift register group respectively; The plurality of clock lines include a first clock line and a second clock line, the first clock line is electrically connected to one of the first shift register group or the second shift register group, and the second clock line is electrically connected to the other of the first shift register group or the second shift register group.

6. The semiconductor device according to claim 5, characterized in that The plurality of shift register groups include first shift registers and second shift registers that are alternately arranged in sequence, the first shift register group includes the first shift register, and the second shift register group includes the second shift register; The first clock line is electrically connected to the first shift register group, the second clock line is electrically connected to the second shift register group, the first clock line is used to transmit a first clock signal, the second clock line is used to transmit a second clock signal, and the phase of the second clock signal lags behind the phase of the first clock signal.

7. The semiconductor device according to claim 6, characterized in that The frequency of the first clock signal is the same as the frequency of the second clock signal, and the phase difference between the first clock signal and the second clock signal is 180°.

8. The semiconductor device according to claim 1, wherein: The source driver further includes signal processing modules, the input end of each signal processing module is electrically connected to the output end of one of the shift registers, and each signal processing module outputs a corresponding data signal.

9. The semiconductor device according to claim 8, characterized in that The signal processing module includes a latch, a level converter, a digital-to-analog converter and an amplifier which are electrically connected in sequence, the input end of the latch is electrically connected to the output end of the shift register, the trigger end of the latch is electrically connected to the data enable line, and the amplifier is used to output the corresponding data signal.

10. The semiconductor device according to claim 1, wherein: The at least one data input terminal and at least one of the plurality of clock lines are disposed in the insulating substrate.

11. A display panel, characterized in that: The display panel comprises the semiconductor device according to any one of claims 1 to 10, wherein the data input terminal is used to transmit a digital signal.

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