Semiconductor structure and preparation method thereof
By using the second hard mask layer as a shading in the semiconductor structure, the problem of bit line manufacturing difficulty in memory manufacturing less than 20 nm is solved, and the high reliability and process simplification of the target film layer are achieved, thereby reducing process difficulty and manufacturing costs.
Patent Information
- Application Number
- CN202310629968.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-05-30
- Publication Date
- 2024-12-10
AI Technical Summary
In memory manufacturing process less than 20 nm, the aspect ratio in bit line manufacturing increases the difficulty of process manufacturing, and the prior art is difficult to effectively control the key size and morphology of the target film layer, resulting in reduced process difficulty and reliability.
By adopting a semiconductor structure preparation method, by forming a first hard mask material layer and a second hard mask material layer on the substrate surface, and using the second hard mask layer as a shield, the second hard mask layer is etched to the second hard mask layer. The etching rate is smaller than the etching rate of the first hard mask layer, thereby avoiding the first hard mask layer being thinned, reducing the overall thickness of the hard mask layer, and simplifying the process.
The total thickness of the hard mask layer above the target film layer is reduced, and the formation of a first hard mask layer with a high aspect ratio is avoided, the reliability of the target pattern and the controllability of the process are improved, and the process difficulty and manufacturing cost are reduced.
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Figure CN119108277A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of integrated circuits, and in particular to a semiconductor structure and a method for preparing the same. Background Art
[0002] The development of memory pursues high speed, high integration density, low power consumption, etc. With the miniaturization of semiconductor device size, especially in the manufacturing process of memory with key size less than 20nm, the increase of aspect ratio in the bit line manufacturing process has greatly increased the difficulty of process manufacturing. Summary of the invention
[0003] The technical problem to be solved by the present disclosure is to provide a semiconductor structure and a method for preparing the same, which can.
[0004] In order to solve the above problems, the present disclosure provides a method for preparing a semiconductor structure, comprising:
[0005] Providing a substrate, wherein a target film layer is disposed on a surface of the substrate, and a first hard mask material layer and a second hard mask material layer are disposed on a surface of the target film layer;
[0006] patterning the second hard mask material layer to form a second hard mask layer, wherein the second hard mask layer is a metal oxide layer;
[0007] Using the second hard mask layer as a mask, patterning the first hard mask material layer to form a first hard mask layer, wherein the first hard mask layer exposes a portion of the target film layer, wherein an etching rate of the etching substance on the second hard mask layer is lower than an etching rate on the first hard mask material layer;
[0008] The target film layer is patterned using the first hard mask layer and the second hard mask layer as shielding to form a target pattern.
[0009] In one embodiment, the method for forming the second hard mask material layer on the first hard mask material layer includes: forming the second hard mask material layer on the first hard mask material layer by using a spin-on dielectric layer process.
[0010] In one embodiment, the second hard mask layer is a tungsten-containing metal oxide layer.
[0011] In one embodiment, the first hard mask layer is a silicon nitride layer.
[0012] In one embodiment, in a direction perpendicular to the substrate surface, a thickness ratio of the second hard mask layer to the first hard mask layer is greater than 2:5 and less than or equal to 3:5.
[0013] In one embodiment, a ratio of an etching rate of the etching substance on the second hard mask layer to an etching rate of the etching substance on the first hard mask material layer is less than or equal to 2:5.
[0014] In one embodiment, after the step of patterning the target film layer using the first hard mask layer and the second hard mask layer as shielding to form a target pattern, the step includes: removing the second hard mask layer using an oxygen-containing ammonia solution.
[0015] In one embodiment, the concentration of ammonia in the oxygen-containing ammonia solution is 0.01M to 2M; the concentration of dissolved oxygen in the oxygen-containing ammonia solution is less than or equal to 50 ppb.
[0016] In one embodiment, the target film layer is a conductive film layer.
[0017] In one embodiment, the semiconductor structure includes an array region and a peripheral region, the first hard mask layer and the second hard mask layer are disposed in both the array region and the peripheral region, and the upper surface of the first hard mask layer located in the array region is flush with the upper surface of the first hard mask layer located in the peripheral region, the target film layer is located in the array region, and in the step of patterning the target film layer using the first hard mask layer and the second hard mask layer as shielding to form a target pattern, the peripheral region is shielded by the first hard mask layer and the second hard mask layer.
[0018] In one embodiment, in a direction perpendicular to the substrate surface, a thickness of the first hard mask layer located in the array region is greater than a thickness of the first hard mask layer located in the peripheral region.
[0019] In one embodiment, the step of patterning the second hard mask material layer includes:
[0020] forming a third hard mask material layer on the surface of the second hard mask material layer;
[0021] patterning the third hard mask material layer to form a third hard mask layer;
[0022] The second hard mask material layer is patterned using the third hard mask layer as a mask to form the second hard mask layer.
[0023] In one embodiment, the third hard mask layer is a carbon layer, or a stacked structure of a carbon layer and a silicon nitride layer.
[0024] In one embodiment, after the step of forming the second hard mask layer, the method further includes: removing the third hard mask layer.
[0025] The disclosed embodiment also provides a semiconductor structure manufactured by the above-mentioned manufacturing method.
[0026] The preparation method of the semiconductor structure provided by the embodiment of the present disclosure uses a metal oxide layer as the second hard mask layer, and the etching rate of the etching material on the second hard mask layer is lower than the etching rate on the first hard mask layer. The first hard mask layer is blocked by the second hard mask layer. Therefore, when patterning the target film layer, the first hard mask layer can be avoided from being thinned. The preparation method provided by the embodiment of the present disclosure reduces the total thickness of the hard mask layer above the target film layer as a whole, so there is no need to form a first hard mask layer with a higher aspect ratio to meet the design requirements. The key size and morphology of the target film layer are easier to control, and the process difficulty when etching the target film layer is reduced, thereby improving the reliability of the target film layer. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] Figure 1 is a schematic diagram of the steps of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure;
[0028] Figure 2A to Figure 2H It is a schematic diagram of a semiconductor structure formed by the main steps of the preparation method provided in one embodiment of the present disclosure. DETAILED DESCRIPTION
[0029] The specific implementation methods of the semiconductor structure and the preparation method thereof provided by the present disclosure are described in detail below with reference to the accompanying drawings.
[0030] Figure 1 Schematic diagram of the steps of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure. Figure 1 The preparation method includes: step S10, providing a substrate, the surface of the substrate has a target film layer, the surface of the target film layer has a first hard mask material layer and a second hard mask material layer; step S11, patterning the second hard mask material layer to form a second hard mask layer, the second hard mask layer is a metal oxide layer; step S12, using the second hard mask layer as a mask, patterning the first hard mask material layer to form a first hard mask layer, the first hard mask layer exposes part of the target film layer, wherein the etching rate of the etching material on the second hard mask layer is less than the etching rate of the first hard mask material layer; step S13, using the first hard mask layer and the second hard mask layer as masks, patterning the target film layer to form a target pattern.
[0031] In some embodiments, if the second hard mask layer is not provided and the first hard mask layer is directly used as the top mask layer, the first hard mask layer will be partially removed when patterning the target film layer, so the first hard mask layer must maintain a sufficiently large thickness to be able to meet the requirements of subsequent processes, which makes the first hard mask layer have a higher aspect ratio, resulting in a higher aspect ratio from the target film layer to the top surface of the semiconductor structure when patterning the target film layer. The key size and morphology of the target film layer are not easy to control, and the alignment in the process is greatly affected, which increases the process difficulty of preparing the target pattern and reduces the reliability of the formed target pattern.
[0032] In addition, in some embodiments, if the second hard mask layer does not exist, and the first hard mask layer is directly used as the top mask layer, due to the etching loading effect, different pattern densities lead to different etching rates, and the first hard mask layer located in the array area (in which the first hard mask layer has a pattern) is consumed to a greater height, and the first hard mask layer located in the peripheral area (in which the first hard mask layer does not have a pattern) is consumed to a lesser height, resulting in the height of the first hard mask layer in the array area being less than the height of the first hard mask layer in the peripheral area in the direction perpendicular to the surface of the substrate, and the height difference will affect the reliability of subsequent processes. If the height difference is to be eliminated, additional processes need to be introduced, increasing manufacturing costs.
[0033] The method for preparing the semiconductor structure provided by the embodiment of the present disclosure uses a metal oxide layer as the second hard mask layer, and the etching rate of the etching material on the second hard mask layer is lower than the etching rate on the first hard mask layer. The first hard mask layer is shielded by the second hard mask layer. Therefore, when patterning the target film layer, the first hard mask layer can be avoided from being thinned, and the thickness of the first hard mask layer that is too thick is not required, thereby reducing the total thickness of the hard mask layer above the target film layer as a whole. Therefore, there is no need to form the first hard mask layer with a higher aspect ratio to meet the design requirements. The critical size and morphology of the target pattern are easy to control, and the process difficulty when etching the target film layer is reduced, thereby improving the reliability of the target pattern.
[0034] In addition, in the present application, the first hard mask layer 280 is also covered with the second hard mask layer 250, so the first hard mask layer will not be etched when the target film layer is patterned. Therefore, the first hard mask layer will not form a height difference between the array area and the peripheral area, that is, in the direction perpendicular to the surface of the substrate, the upper surface of the first hard mask layer located in the array area is flush with the upper surface of the first hard mask layer located in the peripheral area, thereby improving the reliability of subsequent processes and eliminating the need for additional processes to eliminate the height difference between the array area and the peripheral area, thereby reducing manufacturing costs.
[0035] Figure 2A to Figure 2H It is a schematic diagram of a semiconductor structure formed by the main steps of the preparation method provided in one embodiment of the present disclosure.
[0036] See also Figure 1 and Figure 2A ,exist Figure 2A In the figure, (a) is a schematic diagram of the array area AA, (b) is a schematic diagram of the peripheral area PA, step S10, providing a substrate 200, the surface of the substrate 200 has a target film layer 210, the surface of the target film layer 210 has a first hard mask material layer 220 and a second hard mask material layer 230.
[0037] The substrate 200 may include a silicon substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, an SOI substrate or a GOI (Germanium-on-Insulator) substrate, etc.; the substrate 200 may also be a substrate including other element semiconductors or compound semiconductors, such as gallium arsenide, indium phosphide or silicon carbide, etc., and the substrate 200 may also be a stacked structure, such as a silicon / silicon germanium stack, etc.; in addition, the substrate 200 may be an ion-doped substrate, which may be P-type doped or N-type doped; a plurality of peripheral devices may also be formed in the substrate 200, such as field effect transistors, capacitors, inductors and / or diodes, etc. In this embodiment, the substrate 200 is a silicon substrate, and other device structures may also be included therein, such as a transistor structure, a metal wiring structure, etc., but they are not shown because they are irrelevant to the embodiments of the present disclosure.
[0038] In some embodiments, a shallow trench isolation structure 202 (STI) is provided in the substrate 200, and the shallow trench isolation structure 202 divides the substrate 200 into a plurality of active areas 201. The shallow trench isolation structure 202 includes but is not limited to an oxide isolation structure or a composite isolation structure of an oxide layer and a nitride. In this embodiment, the shallow trench isolation structure 202 is an oxide isolation structure.
[0039] In some embodiments, the surface of the substrate 200 is further covered with a protective layer 320, the protective layer 320 is used to protect the substrate 200, and the target film layer 210 covers the surface of the protective layer 320. In this embodiment, the protective layer 320 includes an oxide layer 321 covering the surface of the substrate 200 and a nitride layer 322 covering the oxide layer 321, the oxide layer 321 includes but is not limited to a silicon oxide layer, and the nitride layer 322 includes but is not limited to silicon nitride.
[0040] In some embodiments, the target film layer 210 is a conductive film layer, which may be a single-layer structure or a multi-layer composite structure. For example, in this embodiment, the target film layer 210 is a multi-layer composite structure, which includes a polysilicon material layer 211, a titanium nitride material layer 212, and a metal tungsten material layer 213. The polysilicon material layer 211 is located in the substrate 200 and is connected to the active area 201 in the substrate 200. The polysilicon material layer 211 also covers the surface of the substrate 200, the titanium nitride material layer 212 covers the surface of the polysilicon material layer 211, and the metal tungsten material layer 213 covers the surface of the titanium nitride material layer 212. In some embodiments, the target film layer 210 is a bit line structure layer. In this embodiment, the polysilicon material layer 211 also covers the surface of the protective layer 320 located on the surface of the substrate 200.
[0041] The first hard mask material layer 220 covers the target film layer 210, wherein the first hard mask material layer 220 is formed by a deposition process, and the deposition process may include but is not limited to a chemical vapor deposition process (Chemical Vapor Deposition, CVD), an atomic layer deposition process (Atomic Layer Deposition, ALD), a high density plasma deposition process (High Density Plasma, HDP), a plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapour Deposition, PECVD) and a spin-on dielectric layer (Spin-on Dielectric, SOD) process or a combination thereof. In this embodiment, the first hard mask material layer 220 is a silicon nitride layer, which is prepared by a chemical vapor deposition process.
[0042] The second hard mask material layer 230 covers the surface of the first hard mask material layer 220, and the second hard mask material layer 230 is a metal oxide material layer. For example, in this embodiment, the second hard mask material layer 230 is a tungsten-containing metal oxide layer.
[0043] In some embodiments, the second hard mask material layer 230 can be selected from a material having a higher etching selectivity ratio with the target film layer 210. In the subsequent step of patterning the target film layer 210, the second hard mask layer 250 can be prevented from being excessively removed, thereby reducing the height difference between the array area AA and the peripheral area PA, and further ensuring that the first hard mask layer 220 is not exposed during the etching process.
[0044] In some embodiments, a spin-on dielectric layer process can be used to form the second hard mask material layer 230 on the first hard mask material layer 220. Compared with some semiconductor deposition processes, such as chemical vapor deposition process, atomic layer deposition process, plasma enhanced chemical vapor deposition, etc., the spin-on dielectric layer process can shorten the process time and reduce the process cost.
[0045] In some embodiments, the material cost of the second hard mask material layer 230 is higher than the material cost of the first hard mask material layer 220. Therefore, in the direction perpendicular to the surface of the substrate 200 (such as the Z direction in the figure), the thickness H4 of the second hard mask material layer 230 is less than the thickness H3 of the first hard mask material layer 220, so as to take into account both the material cost and the reduction of the total thickness of the hard mask layer.
[0046] In some embodiments, the semiconductor structure includes an array area AA and a peripheral area PA, and the first hard mask material layer 220 and the second hard mask material layer 230 are disposed in the array area AA and the peripheral area PA, and the upper surface of the first hard mask material layer 220 located in the array area AA is flush with the upper surface of the first hard mask material layer 220 located in the peripheral area PA, and the target film layer 210 is located in the array area AA.
[0047] In the peripheral area PA, the target film layer 210 is not provided, but a gate structure 240 and an isolation layer 241 are provided on the surface of the substrate 200. The gate structure 240 and the active area 201 in the substrate 200 constitute a peripheral transistor structure, and the isolation layer 241 covers the gate structure 240 and the surface of the substrate 200. In the peripheral area PA, the first hard mask material layer 220 covers the surface of the isolation layer 241.
[0048] In some embodiments, in a direction perpendicular to the surface of the substrate 200 (such as the Z direction in the figure), a thickness H3 of the first hard mask material layer 220 located in the array area AA is greater than a thickness H5 of the first hard mask material layer 220 located in the peripheral area PA, and an upper surface of the first hard mask material layer 220 located in the array area AA is flush with an upper surface of the first hard mask material layer 220 located in the peripheral area PA.
[0049] In some embodiments, in a direction perpendicular to the surface of the substrate 200 (such as the Z direction in the figure), a thickness H4 of the second hard mask material layer 230 located in the array area AA is equal to a thickness H6 of the second hard mask material layer 230 located in the peripheral area PA, and an upper surface of the second hard mask material layer 230 located in the array area AA is flush with an upper surface of the second hard mask material layer 230 located in the peripheral area PA.
[0050] See also Figure 1 and Figure 2D ,exist Figure 2D In the figure, (a) is a schematic diagram of the array area AA, (b) is a schematic diagram of the peripheral area PA, and step S11, patterning the second hard mask material layer 230 to form a second hard mask layer 250, wherein the second hard mask layer 250 is a metal oxide layer. In the array area AA, the second hard mask layer 250 exposes a portion of the first hard mask material layer 220, and in the peripheral area PA, the second hard mask layer 250 completely covers the first hard mask material layer 220, and does not expose the first hard mask material layer 220.
[0051] In this step, the second hard mask material layer 230 is partially removed to form a second hard mask layer 250 having a pattern, wherein the second hard mask layer 250 exposes a portion of the first hard mask material layer 220 .
[0052] As an example, an embodiment of the present disclosure provides a method for patterning the second hard mask material layer 230. The method includes:
[0053] See also Figure 2B ,exist Figure 2B In the figure, (a) is a schematic diagram of the array area AA, (b) is a schematic diagram of the peripheral area PA, and a third hard mask material layer 260 is formed on the surface of the second hard mask material layer 230. The third hard mask material layer 260 is formed in both the array area AA and the peripheral area PA.
[0054] In some embodiments, the third hard mask material layer 260 is a stacked structure or a single layer structure. For example, in this embodiment, the third hard mask material layer 260 is a stacked structure composed of a carbon layer and a silicon nitride layer, the carbon layer covers the surface of the second hard mask material layer 230, and the silicon nitride layer covers the surface of the carbon layer. In another embodiment, the third hard mask material layer 260 is a single layer structure composed of a carbon layer. In some embodiments, the third hard mask material layer 260 is formed by a deposition process, and the deposition process may include but is not limited to a chemical vapor deposition process (Chemical Vapor Deposition, CVD), an atomic layer deposition process (Atomic Layer Deposition, ALD), a high density plasma deposition process (High Density Plasma, HDP), a plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapour Deposition, PECVD) and a spin-on dielectric layer (Spin-on Dielectric, SOD) process or a combination thereof.
[0055] See also Figure 2C ,exist Figure 2C In the figure, (a) is a schematic diagram of the array area AA, (b) is a schematic diagram of the peripheral area PA, and the third hard mask material layer 260 is patterned to form a third hard mask layer 270, and the third hard mask layer 270 exposes a portion of the second hard mask material layer 230. In this step, in the array area AA, the third hard mask layer 270 exposes a portion of the second hard mask material layer 230, and in the peripheral area PA, the third hard mask layer 270 completely covers the second hard mask material layer 230, and does not expose the second hard mask material layer 230.
[0056] The material of the third hard mask layer 270 is the same as that of the third hard mask material layer 260. For example, in this embodiment, the third hard mask layer 270 is a stacked structure consisting of a carbon layer and a silicon nitride layer. In another embodiment, the third hard mask layer 270 is a carbon layer.
[0057] In this step, the third hard mask material layer 260 is patterned by photolithography and etching processes to form the third hard mask material layer 270. For example, a photoresist layer is formed on the surface of the third hard mask material layer 260; the photoresist layer is patterned by photolithography, and in the array area AA, the photoresist layer exposes a portion of the third hard mask material layer 260, and in the peripheral area PA, the photoresist layer does not expose the third hard mask material layer 260, so as to form a patterned photoresist layer; the patterned photoresist layer is used as a shield to etch the third hard mask material layer 260 to form the third hard mask layer 270; the photoresist layer is removed by ashing or other processes to expose the surface of the third hard mask layer 270. See Figure 2D ,exist Figure 2D In the figure, (a) is a schematic diagram of the array area AA, and (b) is a schematic diagram of the peripheral area PA. The second hard mask material layer 230 is patterned with the third hard mask layer 270 as a shield to form the second hard mask layer 250. In this step, the second hard mask material layer 230 is partially removed in the array area AA, and the second hard mask material layer 230 is completely retained in the peripheral area PA to form the second hard mask layer 250 having a pattern in the array area AA.
[0058] In some embodiments, the third hard mask layer 270 is used as a shield, and the second hard mask material layer 230 is etched by a wet etching process to remove a portion of the second hard mask material layer 230 to form the second hard mask layer 250. In some embodiments, a material having a higher etching selectivity ratio with the second hard mask material layer 230 is selected as the material of the third hard mask layer 270 to improve the shielding effect of the third hard mask layer 270. For example, in this embodiment, the second hard mask material layer 230 is a metal oxide containing tungsten, and the third hard mask layer 270 is a carbon layer. When performing wet etching, an etching process can be performed using an etching material with a high etching rate for the second hard mask material layer 230 and a low etching rate for the third hard mask layer 270, so as to avoid the third hard mask layer 270 being completely removed and unable to play a masking role.
[0059] After the above steps, the second hard mask layer 250 having a pattern is formed on the surface of the first hard mask material layer 220 .
[0060] In some embodiments, after forming the second hard mask layer 250, the third hard mask layer 270 is retained. Since the third hard mask layer 270 has a small thickness, for example, its thickness is less than the thickness of the first hard mask material layer 220, the third hard mask layer 270 can be removed simultaneously when the first hard mask material layer 220 is subsequently patterned. Therefore, the preparation method disclosed in the present invention does not need to set an additional step of removing the third hard mask layer 270, further simplifying the process steps and reducing the manufacturing cost.
[0061] In some embodiments, the third hard mask layer 270 is also thinned while patterning the second hard mask material layer 230. In some embodiments, the remaining thickness of the third hard mask layer 270 is 1 / 8-5 / 8 of the thickness of the second hard mask layer 250, and the third hard mask layer 270 can be completely removed during the step of patterning the first hard mask material layer 220.
[0062] See also Figure 1 and Figure 2E ,exist Figure 2E In the figure, (a) is a schematic diagram of the array area AA, and (b) is a schematic diagram of the peripheral area PA. In step S12, the first hard mask material layer 220 is patterned with the second hard mask layer 250 as a shield to form a first hard mask layer 280, wherein the first hard mask layer 280 exposes a portion of the target film layer 210, wherein the etching rate of the etching material on the second hard mask layer 250 is lower than the etching rate on the first hard mask material layer 220. In the array area AA, the first hard mask layer 280 exposes a portion of the target film layer 210, and in the peripheral area PA, the first hard mask layer 280 completely covers the surface of the isolation layer 241, and does not expose the isolation layer 241. In this embodiment, the third hard mask layer 270 is completely consumed.
[0063] In this step, in some embodiments, the first hard mask material layer 220 is etched by a wet etching process with the second hard mask layer 250 as a shield. In order to improve the shielding effect of the second hard mask layer 250 and prevent it from being removed during the etching process, during the wet etching, an etching material having an etching rate for the second hard mask layer 250 lower than the etching rate for the first hard mask material layer 220 is selected for etching. For example, in one embodiment, the principle of selecting the etching material is that the ratio of the etching rate of the etching material for the second hard mask layer 250 to the etching rate of the first hard mask material layer 220 is less than or equal to 2:5, so as to further prevent the second hard mask layer 250 from being removed during the etching process.
[0064] In some embodiments, since the material cost of the second hard mask layer 250 is higher than the material cost of the first hard mask layer 280, in the direction perpendicular to the surface of the substrate 200 (such as the Z direction in the figure), the thickness H2 of the second hard mask layer 250 is less than the thickness H1 of the first hard mask layer 280, so as to take into account the material cost and reduce the total thickness of the hard mask layer above the target film layer 10.
[0065] In some embodiments, in a direction perpendicular to the surface of the substrate 200 (such as the Z direction in the figure), the ratio of the thickness H2 of the second hard mask layer 250 to the thickness H1 of the first hard mask layer 280 is greater than 2:5 and less than or equal to 3:5. When the thickness of the first hard mask layer 280 is a constant, if the ratio of the thickness H2 of the second hard mask layer 250 to the thickness H1 of the first hard mask layer 280 is too large, the total thickness of the hard mask layer formed by the first hard mask layer 280 and the second hard mask layer 250 will increase, thereby increasing the aspect ratio of the hard mask layer above the target film layer 210. If the ratio of the thickness H2 of the second hard mask layer 250 to the thickness H1 of the first hard mask layer 280 is too small, then in the step of patterning the target film layer 210, the second hard mask layer 250 may be completely removed, thereby exposing the first hard mask layer 280 and failing to protect the first hard mask layer 280.
[0066] In some semiconductor structures, if the second hard mask layer does not exist, and the third hard mask layer is directly used as a mask to pattern the first hard mask material layer, a thicker third hard mask layer needs to be set. For example, in one embodiment, the thickness of the first hard mask material layer is 140nm, and the thickness of the third hard mask layer is 170nm. The overall thickness of the third hard mask layer and the first hard mask material layer is relatively large, for example, 310nm. In some embodiments of the present application, the first hard mask material layer is patterned using the second hard mask layer as a mask, and the ratio of the thickness H2 of the second hard mask layer to the thickness of the first hard mask material layer 220 (that is, the thickness H1 of the first hard mask layer 280) is greater than 2:5 and less than or equal to 3:5. For example, the thickness of the second hard mask layer is 56-84nm, and the total thickness of the second hard mask layer and the first hard mask material layer is 196-224nm, which greatly reduces the overall aspect ratio of the hard mask layer.
[0067] See also Figure 1 and Figure 2F ,exist Figure 2FIn the figure, (a) is a schematic diagram of the array area AA, (b) is a schematic diagram of the peripheral area PA, and in step S13, the target film layer 210 is patterned using the first hard mask layer 280 and the second hard mask layer 250 as a shield to form a target pattern 290. In this embodiment, the target pattern 290 includes a polysilicon layer 291, a titanium nitride layer 292, and a metal tungsten layer 293.
[0068] In the array area AA, the target film layer 210 is partially removed to form the target pattern 290, and in the peripheral area PA, the first hard mask layer 280 and the second hard mask layer 250 are still retained. In some embodiments, while patterning the target film layer 210, the second hard mask layer 250 is only thinned but not removed, and the surface of the first hard mask layer 280 is still covered with the second hard mask layer 250.
[0069] In this embodiment, the method for patterning the target film layer 210 includes: using the first hard mask layer 280 and the second hard mask layer 250 as a shield, patterning the metal tungsten material layer 213, and the metal tungsten material layer 213 covered by the first hard mask layer 280 and the second hard mask layer 250 is retained; using the first hard mask layer 280, the second hard mask layer 250 and the remaining metal tungsten material layer 213 as a shield, patterning the titanium nitride material layer 212, and the titanium nitride material layer 212 covered by the metal tungsten material layer 213 is retained; using the first hard mask layer 280, the second hard mask layer 250, the remaining metal tungsten material layer 213 and the remaining titanium nitride material layer 212 as a shield, patterning the polysilicon material layer 211, and the polysilicon material layer 211 covered by the titanium nitride material layer 212 is retained to form a target pattern 290. The target pattern 290 includes but is not limited to a bit line pattern.
[0070] In some embodiments, a wet etching process is used to pattern the target film layer 210. When the wet etching process is performed, an etching material having an etching rate for the second hard mask layer 250 lower than that for the target film layer 210 is selected for etching, thereby preventing the second hard mask layer 250 from being removed during the etching process, thereby protecting the first hard mask layer 280.
[0071] The preparation method provided by the embodiment of the present disclosure reduces the total thickness of the hard mask layer above the target film layer 210 as a whole, thereby eliminating the need to form a first hard mask layer 280 with a higher aspect ratio to meet design requirements, thereby making the key dimensions and morphology of the target graphic 290 easier to control, reducing the process difficulty when etching the target film layer 210, and improving the reliability of the target graphic 290.
[0072] See also Figure 1 and Figure 2G ,exist Figure 2G In the figure, (a) is a schematic diagram of the array area AA, (b) is a schematic diagram of the peripheral area PA, and after patterning the target film layer 210, the method further includes: removing the second hard mask layer 250 using an oxygen-containing ammonia solution to expose the first hard mask layer 280. Since the second hard mask layer 250 may be incompatible with subsequent processes, the second hard mask layer 250 is removed after forming the target pattern 290.
[0073] The second hard mask layer 250 is a tungsten-containing metal oxide layer, and thus can be removed by using an oxygen-containing ammonia solution, which will not affect the first hard mask layer 280 and the target pattern 290. In addition, the oxygen-containing ammonia solution is a cleaning solution frequently used in the semiconductor manufacturing process. In the preparation method provided by an embodiment of the present disclosure, the second hard mask layer 250 can be removed by using the cleaning solution frequently used in the semiconductor manufacturing process, which will not increase the manufacturing cost of the semiconductor structure, and ingeniously solves the problem of a high aspect ratio in the process of forming the target pattern 290.
[0074] When the target pattern 290 is a conductive pattern, the oxygen-containing ammonia solution will not affect the conductive pattern, and the morphology of the target pattern 290 can be maintained. Specifically, in this embodiment, when the second hard mask layer 250 is a tungsten-containing metal oxide layer, and the target pattern 290 is a composite pattern of a metal tungsten layer 293, a titanium nitride layer 292, and a polysilicon layer 291, when the second hard mask layer 250 is removed by using the oxygen-containing ammonia solution, the composite pattern of the metal tungsten layer 293, the titanium nitride layer 292, and the polysilicon layer 291 will not be affected, and the morphology of the target pattern 290 can be maintained.
[0075] In some embodiments, the ammonia concentration in the oxygen-containing ammonia solution is 0.01M-2M; the concentration of dissolved oxygen in the oxygen-containing ammonia solution is less than or equal to 50 ppb, so as to avoid the residue of the oxygen-containing ammonia solution while completely removing the second hard mask layer 250 .
[0076] In some embodiments, after removing the second hard mask layer 250, a filling layer 300 may be formed. Figure 2H, (a) is a schematic diagram of the array area AA, (b) is a schematic diagram of the peripheral area PA, in the array area AA, the filling layer 300 is filled between adjacent target patterns 290 and in the gaps of the first hard mask layer 280, and covers the surface of the first hard mask layer 280, and is used to support the target pattern 290 and the first hard mask layer 280, and in the peripheral area PA, the filling layer 300 covers the surface of the first hard mask layer 280. The filling layer 300 can be made of the same material as the first hard mask layer 280 to improve the compatibility of the first hard mask layer 280 and the filling layer 300, and further improve the reliability of the semiconductor structure. For example, in this embodiment, the first hard mask layer 280 and the filling layer 300 are both silicon nitride layers.
[0077] The present disclosure also provides a semiconductor structure prepared by the above-mentioned preparation method. Figure 2A to Figure 2H The critical size and morphology of the target pattern 290 in the semiconductor structure meet the design requirements, and the reliability of the target pattern 290 is high, which greatly improves the reliability of the semiconductor structure.
[0078] The above is only a preferred embodiment of the present disclosure. It should be pointed out that a person skilled in the art can make several improvements and modifications without departing from the principle of the present disclosure. These improvements and modifications should also be regarded as within the scope of protection of the present disclosure.
Claims
1. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate, wherein a target film layer is disposed on a surface of the substrate, and a first hard mask material layer and a second hard mask material layer are disposed on a surface of the target film layer; patterning the second hard mask material layer to form a second hard mask layer, wherein the second hard mask layer is a metal oxide layer; Using the second hard mask layer as a mask, patterning the first hard mask material layer to form a first hard mask layer, wherein the first hard mask layer exposes a portion of the target film layer, wherein an etching rate of the etching substance on the second hard mask layer is lower than an etching rate on the first hard mask material layer; The target film layer is patterned using the first hard mask layer and the second hard mask layer as shielding to form a target pattern.
2. The method for preparing a semiconductor structure according to claim 1, characterized in that: The method for forming the second hard mask material layer on the first hard mask material layer includes: forming the second hard mask material layer on the first hard mask material layer by using a spin-on dielectric layer process.
3. The method for preparing a semiconductor structure according to claim 1, characterized in that: The second hard mask layer is a tungsten-containing metal oxide layer.
4. The method for preparing a semiconductor structure according to claim 3, characterized in that: The first hard mask layer is a silicon nitride layer.
5. The method for preparing a semiconductor structure according to claim 4, characterized in that: In a direction perpendicular to the substrate surface, a thickness ratio of the second hard mask layer to the first hard mask layer is greater than 2:5 and less than or equal to 3:
5.
6. The method for preparing a semiconductor structure according to claim 5, characterized in that: The ratio of the etching rate of the etching substance on the second hard mask layer to the etching rate of the etching substance on the first hard mask material layer is less than or equal to 2:
5.
7. The method for preparing a semiconductor structure according to claim 3, characterized in that: After the step of patterning the target film layer using the first hard mask layer and the second hard mask layer as shields to form a target pattern, the method includes: removing the second hard mask layer using an oxygen-containing ammonia solution.
8. The method for preparing a semiconductor structure according to claim 7, characterized in that: The concentration of ammonia in the oxygen-containing ammonia solution is 0.01M to 2M; the concentration of dissolved oxygen in the oxygen-containing ammonia solution is less than or equal to 50ppb.
9. The method for preparing a semiconductor structure according to claim 1, characterized in that: The target film layer is a conductive film layer.
10. The method for preparing a semiconductor structure according to claim 1, characterized in that: The semiconductor structure includes an array region and a peripheral region, wherein the first hard mask layer and the second hard mask layer are disposed in both the array region and the peripheral region, and the upper surface of the first hard mask layer located in the array region is flush with the upper surface of the first hard mask layer located in the peripheral region, and the target film layer is located in the array region. In the step of patterning the target film layer using the first hard mask layer and the second hard mask layer as shielding to form a target pattern, the peripheral region is shielded by the first hard mask layer and the second hard mask layer.
11. The method for preparing a semiconductor structure according to claim 10, characterized in that: In a direction perpendicular to the substrate surface, a thickness of the first hard mask layer located in the array region is greater than a thickness of the first hard mask layer located in the peripheral region.
12. The method for preparing a semiconductor structure according to claim 1, characterized in that: The step of patterning the second hard mask material layer comprises: forming a third hard mask material layer on the surface of the second hard mask material layer; patterning the third hard mask material layer to form a third hard mask layer; The second hard mask material layer is patterned using the third hard mask layer as a mask to form the second hard mask layer.
13. The method for preparing a semiconductor structure according to claim 12, characterized in that: The third hard mask layer is a carbon layer, or a stacked structure of a carbon layer and a silicon nitride layer.
14. The method for preparing a semiconductor structure according to claim 12, characterized in that: After the step of forming the second hard mask layer, the method further includes: removing the third hard mask layer.
15. A semiconductor structure prepared by the preparation method according to any one of claims 1 to 14.