Semiconductor element and manufacturing method thereof
By forming a cushion-shaped oxide layer covering island structure in semiconductor component manufacturing, the problem of electrical performance deterioration caused by active region rounding in traditional methods is solved, more efficient utilization of oxide materials is achieved, and the overall electrical power of semiconductor components is improved performance.
Patent Information
- Application Number
- CN202311389827.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-06-09
- Filing Date
- 2023-10-25
- Publication Date
- 2024-12-10
AI Technical Summary
Traditional semiconductor component manufacturing methods lead to active region rounding, resulting in reduced contact area, deterioration of electrical performance, and loss problems of shallow trench isolation have not been effectively solved.
By forming a pad-shaped oxide layer on a silicon substrate, covering the island-like structure, and forming in situ on the top of the oxide material, the loss of the oxide material is reduced and the rounding of the island-like structure is prevented. The ion implantation process and carbon ions are adopted. The implantation technology forms a cushion-like oxide layer, and combines a wet etching process to remove the cushion-like oxide layer to ensure that the top surface of the oxide material is parallel to the top surface of the island-like structure.
It effectively prevents the rounding of the island-like structure, reduces the loss of oxide materials, improves the electrical performance of semiconductor components, enhances the contact area, and improves the electrical performance.
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Figure CN119108336A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to a semiconductor device and a manufacturing method thereof. Background Art
[0002] As semiconductor processes continue to evolve, semiconductor structures in memory devices will face challenges. For semiconductor devices, the process related to the active region in dynamic random access memory (DRAM) is critical because it determines the performance and yield improvement of semiconductor devices.
[0003] However, the traditional method leads to a rounding scheme of the active area. This may result in a reduction in the contact area between the active area and the contact, which in turn leads to degradation of the electrical performance of the semiconductor element. According to previous experiments, although reducing the time of wet cleaning the active area can alleviate the rounding problem of the active area, the loss problem of shallow trench isolation (STI) has not yet been solved. Summary of the invention
[0004] In view of this, an object of the present disclosure is to provide a semiconductor device and a manufacturing method thereof that can solve the above-mentioned problems.
[0005] To achieve the above-mentioned purpose, according to one embodiment of the present disclosure, a method for manufacturing a semiconductor element includes: providing a semiconductor structure, wherein the semiconductor structure further includes a silicon substrate having a plurality of grooves and an oxide material filling the grooves and covering the silicon substrate, and the grooves define a plurality of island structures; forming a pad oxide layer on top of the oxide material, wherein the pad oxide layer is located above the silicon substrate; and removing the pad oxide layer so that the top surface of the oxide material is coplanar with the top surface of the island structure.
[0006] In one or more embodiments of the present disclosure, each of the island structures has a width in the range of 20 nm to 30 nm.
[0007] In one or more embodiments of the present disclosure, the step of forming the pad oxide is performed by an ion implantation process.
[0008] In one or more embodiments of the present disclosure, the step of forming the pad oxide is performed by implanting carbon ions into the top of the oxide material.
[0009] In one or more embodiments of the present disclosure, a pad oxide is formed in situ on top of the oxide material.
[0010] In one or more embodiments of the present disclosure, the step of forming the pad oxide is performed such that a top surface of the oxide material has a width in a range between 20 nanometers and 30 nanometers.
[0011] In one or more embodiments of the present disclosure, the method for manufacturing a semiconductor device further includes a step of planarizing the semiconductor structure after the step of providing the semiconductor structure.
[0012] In one or more embodiments of the present disclosure, the step of planarizing the semiconductor structure is performed so that the top surface of the oxide material is parallel to the top surface of the island structure.
[0013] In one or more embodiments of the present disclosure, providing a structure for a semiconductor structure further includes forming a filling material on the oxide material.
[0014] In one or more embodiments of the present disclosure, the step of forming a filling material on the oxide material is performed so that the trench is completely filled with the oxide material and the filling material.
[0015] In one or more embodiments of the present disclosure, the filling material is composed of nitride.
[0016] In one or more embodiments of the present disclosure, the method for manufacturing a semiconductor device further includes a step of planarizing the semiconductor structure after the step of forming the filling material.
[0017] In one or more embodiments of the present disclosure, the step of planarizing the semiconductor structure is performed such that a top surface of the oxide material is coplanar with a top surface of the filling material.
[0018] In one or more embodiments of the present disclosure, the step of removing the pad oxide layer is performed by a wet etching process.
[0019] In one or more embodiments of the present disclosure, the step of removing the pad oxide layer is performed by using hydrofluoric acid.
[0020] To achieve the above object, according to one embodiment of the present disclosure, a semiconductor device includes a silicon substrate and an oxide material. The silicon substrate has a plurality of grooves, and the grooves define a plurality of island structures. The oxide material fills the grooves so that the top surface of the oxide material is coplanar with the top surface of the island structure. Each of the island structures has a side surface and a rounded edge connected between the top surface and the side surface, and the radius of curvature of the rounded edge is less than or equal to 2.3 nanometers.
[0021] In one or more embodiments of the present disclosure, a top surface of the oxide material is coplanar with a top surface of the island structure.
[0022] In one or more embodiments of the present disclosure, each of the island structures has a width ranging between 20 nanometers and 30 nanometers.
[0023] In one or more embodiments of the present disclosure, the semiconductor device further includes a filling material on the oxide material.
[0024] In one or more embodiments of the present disclosure, the filling material and the oxide material completely fill the trench.
[0025] In summary, the semiconductor element and the manufacturing method thereof disclosed in the present invention provide an island structure without rounding problems. In the semiconductor element and the manufacturing method thereof disclosed in the present invention, since the pad-shaped oxide layer is formed on the top of the semiconductor structure and covers the island structure, the loss of oxide material can be reduced, thereby preventing the rounding of the island structure. In the semiconductor element and the manufacturing method thereof disclosed in the present invention, since the pad-shaped oxide layer is formed in situ on the top of the oxide material, no additional material is required, thereby improving the electrical performance of the entire semiconductor element. In summary, the manufacturing method of the semiconductor element disclosed in the present invention improves the overall electrical performance of the entire semiconductor element.
[0026] The above description is only used to illustrate the problem to be solved by the present disclosure, the technical means to solve the problem, and the effects produced, etc. The specific details of the present disclosure will be described in detail in the following implementation methods and related drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] In order to make the above and other purposes, features, advantages and implementation methods of the present disclosure more obvious and understandable, the attached drawings are described as follows:
[0028] Figure 1 The flowchart is a method for manufacturing a semiconductor device according to one embodiment of the present disclosure.
[0029] Figure 2 The cross-sectional view shows an intermediate stage of manufacturing a semiconductor device according to one embodiment of the present disclosure.
[0030] Figure 3 The figure is a cross-sectional view showing an intermediate stage of manufacturing a semiconductor device according to another embodiment of the present disclosure.
[0031] Figure 4 The cross-sectional view shows an intermediate stage of manufacturing a semiconductor device according to one embodiment of the present disclosure.
[0032] Figure 5 The cross-sectional view shows an intermediate stage of manufacturing a semiconductor device according to one embodiment of the present disclosure.
[0033] Figure 6 The cross-sectional view shows an intermediate stage of manufacturing a semiconductor device according to one embodiment of the present disclosure.
[0034] Figure 7The figure is a cross-sectional view showing an intermediate stage of manufacturing a semiconductor device according to another embodiment of the present disclosure.
[0035] Figure 8 To illustrate an embodiment of the present disclosure Figure 6 or Figure 7 An enlarged cross-sectional view of an intermediate stage in the manufacture of a semiconductor component. DETAILED DESCRIPTION
[0036] The following disclosure provides many different embodiments or examples for realizing the different features of the provided patent subject matter. Specific embodiments of components and configurations are described below to simplify the disclosure. Of course, these are only embodiments and are not intended to be limiting. For example, in the following specification, a first feature formed above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. In addition, the disclosure may repeat reference numerals and / or letters in a variety of embodiments. Such repetition is for the purpose of simplicity and clarity, and does not itself dictate the relationship between the various embodiments and / or configurations discussed.
[0037] Additionally, for ease of description, spatially relative terms such as "below," "below," "lower," "above," "upper," etc. may be used herein to describe the relationship between one element or feature and another element or feature shown in the drawings. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or in other orientations) and the spatially relative terms used herein may likewise be interpreted accordingly.
[0038] As used herein, "approximately," "about," "roughly," or "substantially" generally means within 20%, or within 10%, or within 5% of a given value or range. The numerical values given herein are approximate, meaning that if not explicitly stated, the term "approximately," "about," "roughly," or "substantially" can be inferred.
[0039] Please refer to Figure 1 . Figure 1 According to one embodiment of the present disclosure, Figure 6 The semiconductor device 100 shown in FIG. Figure 7 Flow chart of method M of semiconductor device 100A is shown. Figure 1 The method M shown includes step S101, step S102 and step S103. For a better understanding of step S101, please refer to Figure 1 , Figure 2 as well as Figure 3 To better understand step S102, please refer to Figure 1 as well as Figure 4 To better understand step S103, please refer to Figure 1 , Figure 5 , Figure 6 , Figure 7 as well as Figure 8 .
[0040] Step S101 , step S102 , and step S103 are described in detail below.
[0041] In step S101, a semiconductor structure SMS1 is provided, such as Figure 2 shown.
[0042] Please refer to Figure 2 . Figure 2 FIG. 1 is a cross-sectional view of an intermediate stage of manufacturing a semiconductor device 100 according to an embodiment of the present disclosure. Figure 2 As shown, a semiconductor structure SMS1 is provided. In this embodiment, the semiconductor structure SMS1 includes a silicon substrate 110 and an oxide material 120 on the silicon substrate 110. In some embodiments, the silicon substrate 110 can be an active region (e.g., a source / drain region). In some embodiments, the oxide material 120 is configured as a shallow trench isolation (STI). More specifically, the silicon substrate 110 has a plurality of trenches T, and the trenches T define a plurality of island structures 110A, such as Figure 2 For simplicity, Figure 2 Only the island structure 110A of the silicon substrate 110 is shown instead of the entire silicon substrate 110. Figure 2 As shown, the oxide material 120 fills the trench T of the silicon substrate 110 .
[0043] like Figure 2 As shown, in some embodiments, the oxide material 120 fills the trench T and covers the silicon substrate 110. More specifically, each island structure 110A has a top surface 110t, and the oxide material 120 has a top surface 120t. The oxide material 120 covers the island structure 110A of the silicon substrate 110, so that the top surface 120t of the oxide material 120 is higher than the top surface 110t of the island structure 110A.
[0044] like Figure 2 As shown, in some embodiments, each island structure 110A further has a width W 110A In some embodiments, the width W 110A is substantially equal to the shortest distance between two adjacent trenches T. In some embodiments, the width W of each island structure 110A is 110AIn the range between 20 nanometers and 30 nanometers.
[0045] In some embodiments, the method M further includes planarizing the semiconductor structure SMS1. The step of planarizing the semiconductor structure SMS1 is performed after the step of providing the semiconductor structure SMS1. More specifically, during the step S101, the oxide material 120 fills the trench T of the silicon substrate 110, and then planarization is performed, thereby correspondingly forming a top surface 120t, such as Figure 2 In some embodiments, planarizing the semiconductor structure SMS1 is performed so that the top surface 120t of the oxide material 120 is parallel to the top surface 110t of the island structure 110A.
[0046] Please refer to Figure 3 . Figure 3 According to another embodiment of the present disclosure, Figure 7 The structure of the semiconductor device 100A is substantially the same as that of the semiconductor device 100. The difference between the semiconductor device 100A and the semiconductor device 100 is that the semiconductor device 100A further includes a filling material 130, such as Figure 6 as well as Figure 7 As shown. Figure 3 As shown, in another embodiment, a semiconductor structure SMS2 is provided during the execution of step S101. In this embodiment, the semiconductor structure SMS2 further includes a silicon substrate 110, an oxide material 120, and a filling material 130. The filling material 130 is formed on the oxide material 120. More specifically, the filling material 130 is filled in the seams or gaps of the oxide material 120 to improve the quality of shallow trench isolation (STI). Figure 3 As shown, in some embodiments, the filling material 130 is formed on the oxide material 120 , so that the trench T is completely filled with the oxide material 120 and the filling material 130 .
[0047] In some embodiments, the method M further includes planarizing the semiconductor structure SMS2. The step of planarizing the semiconductor structure SMS2 is performed after the step of providing the semiconductor structure SMS2. More specifically, during the step S101, the oxide material 120 and the filling material 130 overfill the trench T of the silicon substrate 110, and then planarization is performed, so that the top surface 120t of the oxide material 120 and the top surface 130t of the filling material 130 are formed accordingly, as shown in FIG. Figure 3 In some embodiments, the semiconductor structure SMS2 is planarized so that the top surface 120t of the oxide material 120 is coplanar with the top surface 130t of the filling material 130, as shown in FIG. Figure 3 shown.
[0048] In some embodiments, the trench T may be formed by any suitable method, such as wet etching, dry etching, or the like. The present disclosure is not intended to be limited to the method for forming the trench T.
[0049] In some embodiments, the silicon substrate 110 may be composed of a silicon-based material. In some embodiments, the silicon substrate 110 may include, for example, polycrystalline silicon, single crystal silicon, amorphous silicon, or the like. However, any suitable material may be used.
[0050] In some embodiments, the silicon substrate 110 may be formed by any suitable method, such as CVD (chemical vapor deposition), PECVD (plasma enhanced chemical vapor deposition), PVD (physical vapor deposition), ALD (atomic layer deposition), PEALD (plasma enhanced atomic layer deposition), ECP (electrochemical plating), chemical plating, or the like. The present disclosure is not intended to be limited to the method of forming the silicon substrate 110.
[0051] In some embodiments, the oxide material 120 may be composed of an oxide. In some embodiments, the oxide material 120 may include, for example, silicon oxide (SiO2) or a similar material. However, any suitable material may be used.
[0052] In some embodiments, the oxide material 120 may be formed by any suitable method, such as CVD (chemical vapor deposition), PECVD (plasma enhanced chemical vapor deposition), PVD (physical vapor deposition), ALD (atomic layer deposition), PEALD (plasma enhanced atomic layer deposition), ECP (electrochemical plating), chemical plating, or the like. The present disclosure is not intended to be limited to the method of forming the oxide material 120.
[0053] In some embodiments, the filler material 130 may be composed of a nitride. In some embodiments, the filler material 130 may include, for example, titanium nitride (TiN), silicon nitride (Si x N y ) etc. However, any suitable material may be used.
[0054] In some embodiments, the filling material 130 may be formed by any suitable method, such as CVD (chemical vapor deposition), PECVD (plasma enhanced chemical vapor deposition), PVD (physical vapor deposition), ALD (atomic layer deposition), PEALD (plasma enhanced atomic layer deposition), ECP (electrochemical plating), chemical plating, or the like. The present disclosure is not intended to be limited to the method of forming the filling material 130.
[0055] In step S102, a pad oxide layer 140 is formed on top of the oxide material 120, such as Figure 4 shown.
[0056] Please refer to Figure 4 . Figure 4 FIG. 1 is a cross-sectional view of an intermediate stage of manufacturing a semiconductor device 100 according to an embodiment of the present disclosure. Figure 4 As shown, the pad oxide layer 140 is located above the silicon substrate 110. More specifically, the pad oxide layer 140 is formed to cover the island structure 110A. In this embodiment, the pad oxide layer 140 is formed in situ on top of the oxide material 120. In other words, the oxide material 120 will not be consumed during the execution of step S102. Figure 4 As shown, the pad oxide layer 140 is formed by the modification process IP. In some embodiments, the top of the oxide material 120 located on the side close to the top surface 120t of the oxide material 120 is exposed when the modification process IP is performed. In some embodiments, performing the modification process IP causes the etching resistance of the pad oxide layer 140 to be greater than the etching resistance of the oxide material 120. In some embodiments, the pad oxide layer 140 is configured as a protective layer of the semiconductor structure SMS1 to prevent the semiconductor structure SMS1 from being consumed.
[0057] In another embodiment, the filler material 130 may be included in Figure 4 The oxide material 120 shown in FIG. Figure 3 Inference.
[0058] In some embodiments, after performing the modification process IP, the pad oxide layer 140 has a thickness T 140 In some embodiments, the thickness T of the pad oxide layer 140 is 140 In some embodiments, the thickness T is from the top surface 120t of the oxide material 120 to the top surface 110t of the island structure 110A. 140 In some embodiments, the thickness T 140 It can be regarded as the range in which the modification process IP is performed. In other words, the modification process IP is preferably performed at a depth starting from the top surface 120t of the oxide material 120, wherein the depth is preferably in the range between 20 nanometers and 30 nanometers. In some embodiments in which the depth is less than 20 nanometers or greater than 30 nanometers, the pad oxide layer 140 may provide less effective protection for the semiconductor structure SMS1 or the semiconductor structure SMS2.
[0059] In some embodiments, the modification process IP may be any suitable method, such as an ion implantation process or the like. The present disclosure is not intended to be limited to the method of forming the pad oxide layer 140 .
[0060] In some embodiments, the pad oxide layer 140 may be composed of a doped oxide. In some embodiments, the pad oxide layer 140 may include, for example, doped silicon oxide (SiO2) or a similar material. In some embodiments, the pad oxide layer 140 is implanted using carbon ions as a dopant. More specifically, the pad oxide layer 140 is formed by implanting carbon ions on top of the oxide material 120. However, any suitable dopant may be utilized.
[0061] In step S103 , the pad oxide layer 140 is removed.
[0062] Please refer to Figure 5 as well as Figure 6 . Figure 5 as well as Figure 6 FIG. 1 is a cross-sectional view of an intermediate stage of manufacturing a semiconductor device 100 according to an embodiment of the present disclosure. In this embodiment, the pad oxide layer 140 is removed from the top of the oxide material 120. In some embodiments, the pad oxide layer 140 is removed by a cleaning process. After performing step S103, the semiconductor device 100 is formed.
[0063] In some embodiments, the pad oxide layer 140 is removed by two removal steps. More specifically, as Figure 5 As shown, the pad oxide layer 140 is removed by a cleaning process WC1, and then an intermediate pad oxide layer 150 is formed in situ. The cleaning process WC1 is performed so that the intermediate pad oxide layer 150 has a thickness T 150 In some embodiments, the thickness T of the intermediate pad oxide layer 150 is 150 The top surface 120t1 of the intermediate pad oxide layer 150 is from the top surface 120t1 of the intermediate pad oxide layer 150 to the top surface 110t of the island structure 110A. In some embodiments, the top surface 120t1 is lower than Figure 2 , Figure 3 and Figure 4 In some embodiments, the thickness T of the middle pad oxide layer 150 is 150 Less than thickness T 140 . Then, if Figure 6 As shown, the intermediate pad oxide layer 150 is removed by a cleaning process WC2. Performing the cleaning process WC2 causes the remaining oxide material 120 to have a top surface 120t2. In some embodiments, the top surface 120t2 is lower than Figure 5In some embodiments, the pad oxide layer 140 (or the intermediate pad oxide layer 150 ) is removed, so that the top surface 120t2 of the oxide material 120 is coplanar with the top surface 110t of the island structure 110A.
[0064] Removing the pad oxide layer 140 by the cleaning process WC1 and the cleaning process WC2 has some advantages. One of the advantages is that the two-step removal prevents the risk of removing the oxide material 120 due to over-etching the pad oxide layer 140 .
[0065] In some embodiments, the cleaning process WC1 and the cleaning process WC2 are performed by using a wet cleaning process (eg, a wet etching process). The present disclosure is not intended to be limited to the method of removing the pad oxide layer 140 .
[0066] In some embodiments, the cleaning process WC1 and the cleaning process WC2 are performed by using, for example, hydrofluoric acid (HF) or the like. However, any material suitable for removing the pad oxide layer 140 may be used.
[0067] Please refer to Figure 7 . Figure 7 FIG. 1 is a cross-sectional view of an intermediate stage of manufacturing a semiconductor device 100A according to another embodiment of the present disclosure. Figure 7 As shown, in another embodiment, after performing step S103, the semiconductor element 100A is formed. Figure 6 The semiconductor device 100 shown in FIG. 10A further includes a filling material 130, which can be obtained from Figures 3 to 6 Inference. Figure 7 As shown, in some embodiments, a top surface 130 t 2 of the filling material 130 is coplanar with a top surface 120 t of the oxide material 120 .
[0068] Please refer to Figure 8 . Figure 8 According to one embodiment of the present disclosure Figure 6 or Figure 7 FIG. 1 is an enlarged cross-sectional view of an intermediate stage of manufacturing a semiconductor device 100 and a semiconductor device 100A. Figure 8 As shown, each island structure 110A further has a side surface 110s and a rounded edge 110re. The top surface 110t of the island structure 110A refers to a surface coplanar with the top surface 120t2 of the oxide material 120. The side surface 110s of the island structure 110A refers to Figure 8 The vertical lines shown are located on opposite sides of each island structure 110A. The rounded edge 110re is connected between the top surface 110t and the side surface 110s. Figure 8As shown, the top surface 110t, the rounded edge 110re and the side surface 110s are Figure 8 The dashed lines shown are divided.
[0069] In some embodiments, the rounded edge 110re has a radius of curvature. In some embodiments, the radius of curvature of the rounded edge 110re is less than or equal to 2.3 nanometers. In some embodiments, the island structure 110A may not have a rounded edge 110re, because the radius of curvature of the rounded edge 110re theoretically approaches zero. In some embodiments where the radius of curvature of the rounded edge 110re is less than or equal to 2.3 nanometers, the contact area between each island structure 110A and a contact formed on the island structure 110A in a subsequent process can be increased, thereby reducing the resistance of the semiconductor element 100 and the semiconductor element 100A and improving the electrical performance of the semiconductor element 100 and the semiconductor element 100A.
[0070] By executing this disclosure Figure 1 The method M shown can form the semiconductor device 100 and the semiconductor device 100A with better electrical performance.
[0071] From the above detailed description of the specific embodiments of the present disclosure, it can be clearly seen that the semiconductor element and the manufacturing method thereof disclosed in the present disclosure provide an island structure without rounding problems. In the semiconductor element and the manufacturing method thereof disclosed in the present disclosure, since the pad-shaped oxide layer is formed on the top of the semiconductor structure and covers the island structure, the loss of oxide material can be reduced, thereby preventing the rounding of the island structure. In the semiconductor element and the manufacturing method thereof disclosed in the present disclosure, since the pad-shaped oxide layer is formed in situ on the top of the oxide material, no additional material is required, thereby improving the electrical performance of the entire semiconductor element. In summary, the manufacturing method of the semiconductor element disclosed in the present disclosure improves the overall electrical performance of the entire semiconductor element.
[0072] Although the present disclosure has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.
[0073] The above content summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present invention. Those skilled in the art should understand that the above content can be easily used as a basis for designing or modifying other variations without departing from the spirit and scope of the present invention to implement the same purpose and / or achieve the same advantages of the embodiments described herein. The above content should be understood as an example of the present disclosure, and its scope of protection should be based on the claims.
[0074]
Explanation of symbols
[0075] 100,100A:Semiconductor components
[0076] 110: Silicon substrate
[0077] 110A: Island structure
[0078] 110re: rounded edges
[0079] 110s: Side
[0080] 110t,120t,120t1,120t2,130t,130t2: Top
[0081] 120: Oxide material
[0082] 130: Filling material
[0083] 140: Pad oxide layer
[0084] 150: Intermediate pad oxide layer
[0085] IP: Modification process
[0086] M: Method
[0087] S101, S102, S103: Steps
[0088] SMS1, SMS2: semiconductor structure
[0089] T: Groove
[0090] T 140 ,T 150 :thickness
[0091] W 110A :width
[0092] WC1, WC2: Cleaning process.
Claims
1. A method for manufacturing a semiconductor element, characterized in that: Include: A semiconductor structure is provided, wherein the semiconductor structure comprises a silicon substrate having a plurality of trenches and an oxide material filled in the plurality of trenches and covering the silicon substrate, and the plurality of trenches define a plurality of island structures; forming a pad oxide layer on top of the oxide material, wherein the pad oxide layer is located above the silicon substrate; as well as The pad oxide layer is removed so that a top surface of the oxide material is coplanar with top surfaces of the plurality of island structures.
2. The method according to claim 1, characterized in that Each of the plurality of island structures has a width in the range of 20 nanometers and 30 nanometers.
3. The method according to claim 1, characterized in that: The step of forming the pad oxide is performed by an ion implantation process.
4. The method according to claim 1, characterized in that: The step of forming the pad oxide is performed by implanting carbon ions into the top portion of the oxide material.
5. The method according to claim 1, characterized in that The pad oxide is formed in-situ on the top of the oxide material.
6. The method according to claim 1, characterized in that The step of forming the pad oxide is performed such that a top surface of the oxide material has a width in a range between 20 nanometers and 30 nanometers.
7. The method according to claim 1, characterized in that The method further includes planarizing the semiconductor structure after providing the semiconductor structure.
8. The method according to claim 7, characterized in that The step of planarizing the semiconductor structure is performed such that the top surface of the oxide material is parallel to the top surfaces of the plurality of island structures.
9. The method according to claim 1, characterized in that: The providing the semiconductor structure further includes forming a filling material on the oxide material.
10. The method according to claim 9, characterized in that Performing the step of forming the filling material on the oxide material causes the plurality of trenches to be completely filled with the oxide material and the filling material.
11. The method according to claim 9, characterized in that The filling material consists of nitride.
12. The method according to claim 9, characterized in that The method further includes planarizing the semiconductor structure after forming the filling material.
13. The method according to claim 12, characterized in that The step of planarizing the semiconductor structure is performed such that the top surface of the oxide material is coplanar with a top surface of the fill material.
14. The method according to claim 1, characterized in that The step of removing the pad oxide layer is performed by a wet etching process.
15. The method according to claim 14, characterized in that The step of removing the pad oxide layer is performed by using hydrofluoric acid.
16. A semiconductor device, characterized in that: Include: A silicon substrate having a plurality of grooves, wherein the plurality of grooves define a plurality of island structures; and an oxide material filling the plurality of trenches so that a top surface of the oxide material is coplanar with a top surface of the plurality of island structures, Each of the plurality of island structures has a side surface and a rounded edge connected between the top surface and the side surface, and a radius of curvature of the rounded edge is less than or equal to 2.3 nanometers.
17. The semiconductor device according to claim 16, characterized in that The top surface of the oxide material is coplanar with the top surfaces of the plurality of island structures.
18. The semiconductor device according to claim 16, wherein: Each of the plurality of island structures has a width ranging between 20 nanometers and 30 nanometers.
19. The semiconductor device according to claim 16, wherein: The method further comprises a filling material on the oxide material.
20. The semiconductor device according to claim 19, characterized in that The filling material and the oxide material completely fill the plurality of trenches.