Avalanche photodiode based on two-time epitaxy and preparation method thereof

Abstract

According to the avalanche photodiode based on two-time epitaxy and the preparation method of the avalanche photodiode, injection of all P-type ions and N-type ions is achieved in a surface ion injection mode through the two-time epitaxy process, the requirement for deep ion injection is not needed, use of a high-energy ion implanter is avoided, the preparation difficulty is lowered, and the manufacturing cost is reduced; besides, according to the avalanche photodiode prepared by adopting the preparation method, the P + doping layer is formed on the surface of the first P-type epitaxial layer, and the doping concentration of the P + doping layer is higher than that of the first P-type epitaxial layer, so that the electric field distribution in the avalanche photodiode can be adjusted; the first anode ohmic contact electrode and the second anode ohmic contact electrode are used for assisting the second anode ohmic contact electrode to realize full depletion of the first P-type epitaxial layer and the second P-type epitaxial layer, namely, the full depletion state of the first P-type epitaxial layer and the second P-type epitaxial layer can be adjusted through the P + doping layer, so that the first P-type epitaxial layer and the second P-type epitaxial layer can be depleted at lower voltage, namely, depletion voltage is reduced, diffusion current is reduced, and the cut-off frequency of the device is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor integrated circuit design and manufacturing, and in particular to an avalanche photodiode based on double epitaxy and silicon-on-insulator (SOI) wafer and a preparation method thereof. Background Art

[0002] Avalanche photodiode (APD for short) is a photosensitive element used in laser communication. After reverse bias is applied to the PN junction of the photodiode, the incident light is absorbed by the PN junction to form a photocurrent. Increasing the reverse bias will produce "avalanche", that is, the phenomenon of photocurrent surging exponentially, so it is called "avalanche photodiode". It is mainly used in high-sensitivity detection occasions, including fiber-optic communication, laser ranging, 3D imaging, thermal imaging, volume scanning, and single-photon level detection and imaging. In the field of human body sensing such as laser radar and face recognition, near-infrared bands such as 840nm, 905nm, and 940nm are widely used.

[0003] Current industry pain points: Due to the randomness of the amplification process of avalanche photodiodes, redundant noise will be generated, which eventually leads to the traditional APD amplifying the noise while amplifying the signal (incident light), which is limited in high-sensitivity applications, especially in the near-infrared band. Due to the limitations of the properties of silicon materials themselves, the light detection quantum efficiency is lower than that of visible light, resulting in relatively weak signals in the near-infrared band and low signal-to-noise ratio. Usually, the absorption can be increased by increasing the thickness of the absorption layer, but it will generally increase the migration path of photogenerated carriers and reduce the APD bandwidth. Usually, the amplification region can be formed by deeper ion implantation to improve the light detection quantum efficiency, but a high-energy ion implanter is required, which often adds new difficulties in the requirements of wafer manufacturing equipment; secondly, in order to achieve high device bandwidth of APD, it is usually necessary to fully deplete the absorption layer, otherwise the diffusion current will cause tailing and reduce the device bandwidth, and full depletion requires high voltage, especially for APDs with large effective detection areas, and its high reverse bias voltage often causes premature breakdown of the device; in addition, non-depletion regions are easily formed in the device boundary area, and the body and surface dark currents are in the form of diffusion currents, thereby reducing the bandwidth of the APD. Summary of the invention

[0004] In view of the shortcomings of the prior art mentioned above, the purpose of the present invention is to provide an avalanche photodiode based on double epitaxy and a preparation method thereof, so as to solve at least one of the technical problems in the prior art, namely, the difficulty and high cost of preparing the avalanche photodiode, the need for high voltage for full depletion of the avalanche photodiode, the difficulty in achieving full depletion in the boundary region of the APD device leading to the formation of diffusion current, and the strong electric field in the boundary region of the APD device leading to premature breakdown of the device.

[0005] To achieve the above-mentioned object and other related objects, the present invention provides a method for preparing an avalanche photodiode based on double epitaxy, the preparation method comprising:

[0006] Providing an epitaxial wafer, wherein the epitaxial wafer includes a first P-type epitaxial layer;

[0007] Performing P-well ion implantation from the surface of the first P-type epitaxial layer inwards;

[0008] epitaxially depositing a second P-type epitaxial layer on the surface of the first P-type epitaxial layer; wherein the doping concentration of the second P-type epitaxial layer is the same as the doping concentration of the first P-type epitaxial layer;

[0009] Performing ion implantation of an N-well, an N-type guard ring, and a P-well type ohmic contact ring from the surface of the second P-type epitaxial layer inward;

[0010] The ion implantation is thermally annealed to form a P-well, an N-well, an N-type guard ring and a P-well type ohmic contact ring; wherein the P-well is located below the N-well, and the surface of the N-well completely covers the surface of the P-well; the P-well and the N-well form an avalanche region; the first P-type epitaxial layer and the second P-type epitaxial layer form an electron absorption region; the N-type guard ring is located at the periphery of the avalanche region; and the P-well type ohmic contact ring is located at the periphery of the N-type guard ring;

[0011] A P+ doped layer and a first anode ohmic contact electrode are sequentially formed on the lower side of the first P-type epitaxial layer, and a second anode ohmic contact electrode and a cathode ohmic contact electrode are formed on the upper surface of the second P-type epitaxial layer; wherein the doping concentration of the P+ doped layer is greater than the doping concentration of the first P-type epitaxial layer, the second anode ohmic contact electrode is contact-connected to the P-well type ohmic contact ring, and the cathode ohmic contact electrode is contact-connected to the N-well.

[0012] Optionally, the ion implantation of the N-well, the ion implantation of the N-type guard ring and the ion implantation of the P-well type ohmic contact ring also includes the step of implanting a first-level N-type guard ring from the surface of the second P-type epitaxial layer inward; after thermal annealing, a first-level N-type guard ring is formed, and the first-level N-type guard ring is formed on the periphery of the P-well type ohmic contact ring.

[0013] Optionally, the ion implantation of the N-well, the ion implantation of the N-type guard ring and the ion implantation of the P-well type ohmic contact ring also includes the steps of implanting a second-level N-type guard ring and a third-pole N-type guard ring from the surface of the second P-type epitaxial layer inward; after thermal annealing, a second-level N-type guard ring and a third-pole N-type guard ring are formed, and the second-level N-type guard ring and the third-pole N-type guard ring are nested in sequence and formed on the periphery of the P-well type ohmic contact ring.

[0014] Optionally, the ion implantation of the N-well, the ion implantation of the N-type guard ring and the ion implantation of the P-well type ohmic contact ring also includes the step of implanting a fourth-level N-type guard ring from the surface of the second P-type epitaxial layer inward; after thermal annealing, a fourth-level N-type guard ring is formed, and the fourth-level N-type guard ring is formed between the N-type guard ring and the P-well type ohmic contact ring.

[0015] Optionally, before performing the ion implantation of the P-well, the method further includes forming a first dielectric layer on the surface of the first P-type epitaxial layer, and removing the first dielectric layer before depositing the second P-type epitaxial layer.

[0016] Optionally, before performing the ion implantation of the N-well, the ion implantation of the N-type guard ring and the ion implantation of the P-well type ohmic contact ring, the method further includes forming a second dielectric layer on the surface of the second P-type epitaxial layer.

[0017] Furthermore, the epitaxial wafer further includes a P-type substrate, and the P-type substrate is in contact with and connected to the first P-type epitaxial layer. The method for sequentially forming the P+ doped layer and the first anode ohmic contact electrode on the lower side of the first P-type epitaxial layer includes:

[0018] bonding a first supporting wafer to the surface of the second dielectric layer;

[0019] Thinning the P-type substrate to a preset thickness;

[0020] Performing ion implantation of a P+ doping layer from the surface of the thinned P-type substrate inward, and thermally annealing the P+ doping layer to form the P+ doping layer, wherein the doping concentration of the P+ doping layer is greater than the doping concentration of the P-type substrate;

[0021] The first anode ohmic contact electrode is deposited on the surface of the P+ doped layer.

[0022] Furthermore, the method of forming the second anode ohmic contact electrode and the cathode ohmic contact electrode on the upper surface of the second P-type epitaxial layer includes:

[0023] Bonding a second supporting wafer to the surface of the first anode ohmic contact electrode;

[0024] debonding to remove the first support wafer;

[0025] removing the second dielectric layer, and forming a third dielectric layer on the surface of the second P-type epitaxial layer;

[0026] Performing pattern etching on the third dielectric layer to form a through electrode filling hole in the third dielectric layer;

[0027] Depositing a metal layer on the third dielectric layer, and the metal layer fully fills the electrode filling hole to obtain the second anode ohmic contact electrode and the cathode ohmic contact electrode;

[0028] Depositing electrode protection layer;

[0029] Debonding is performed to remove the second support wafer.

[0030] Optionally, the epitaxial wafer further includes a supporting substrate, an insulating dielectric layer and the P+ doped layer in sequence along the thickness direction, and the P+ doped layer is in contact with and connected to the first P-type epitaxial layer, and the method for forming the second anode ohmic contact electrode and the cathode ohmic contact electrode on the upper surface of the second P-type epitaxial layer includes:

[0031] removing the second dielectric layer, and forming a third dielectric layer on the surface of the second P-type epitaxial layer;

[0032] Performing pattern etching on the third dielectric layer to form a through electrode filling hole in the third dielectric layer;

[0033] Depositing a metal layer on the third dielectric layer, and the metal layer fully fills the electrode filling hole to obtain the second anode ohmic contact electrode and the cathode ohmic contact electrode;

[0034] Deposition of electrode protection layer.

[0035] Furthermore, the method of sequentially forming the P+ doped layer and the first anode ohmic contact electrode on the lower side of the first P-type epitaxial layer includes:

[0036] Etching the support substrate and the insulating dielectric layer to form a through groove;

[0037] The first anode ohmic contact electrode is deposited on the surface of the supporting substrate and the sidewalls and bottom walls of the through groove.

[0038] The present invention also provides an avalanche photodiode based on double epitaxy, which is prepared by the preparation method of the avalanche photodiode based on double epitaxy as described above, wherein the avalanche photodiode comprises in sequence along the thickness direction: a first anode ohmic contact electrode, a P+ doped layer, a first P-type epitaxial layer, a second P-type epitaxial layer, a P-well, an N-well, an N-type guard ring, a P-well type ohmic contact ring, a second anode ohmic contact electrode, and a cathode ohmic contact electrode; wherein,

[0039] The N-well, the N-type guard ring and the P-well type ohmic contact ring extend downward from the surface of the second P-type epitaxial layer; the P-well is located below the N-well, and the surface of the N-well completely covers the surface of the P-well; the P-well and the N-well form an avalanche region; the first P-type epitaxial layer and the second P-type epitaxial layer form an electron absorption region;

[0040] The N-type guard ring is located at the periphery of the avalanche zone;

[0041] The P-well type ohmic contact ring is located at the periphery of the N-type guard ring;

[0042] The second anode ohmic contact electrode is in contact with the P-well type ohmic contact ring;

[0043] The cathode ohmic contact electrode is contact-connected to the N-well.

[0044] Optionally, the avalanche photodiode further comprises: a P-type substrate; the upper and lower surfaces of the P-type substrate are respectively in contact with the P+ doped layer and the first P-type epitaxial layer, and the doping concentration of the P+ doped layer is greater than the doping concentration of the P-type substrate; the semiconductor material used in the avalanche photodiode is silicon; the doping concentration of the P+ doped layer is 1e18cm -3 -1e20cm -3 , with a thickness of 0.1 μm to 1.0 μm and a width of 200 μm to 2000 μm; the doping concentration of the P-type substrate is 1e14 cm -3 -1e18cm -3 , a thickness of 100 μm to 500 μm, a width of 200 μm to 2000 μm; a doping concentration of the first P-type epitaxial layer and the second P-type epitaxial layer is 1e11 cm -3 -1e14cm -3 The sum of the thickness of the first P-type epitaxial layer and the second P-type epitaxial layer is 0.5 μm to 100 μm, the width of the first P-type epitaxial layer and the second P-type epitaxial layer is 200 μm to 2000 μm; the doping concentration of the N-type guard ring is 1e14 cm -3 -1e18cm -3, the depth is 1.0μm to 3.0μm, the ring width is 10μm to 60μm; the doping concentration of the P well is 1e16cm -3 -1e19cm -3 , with a thickness of 0.8 μm to 2.0 μm and a width of 80 μm to 700 μm; the doping concentration of the N well is 1e16 cm -3 -1e19cm -3 , with a thickness of 0.7 μm to 1.5 μm and a width of 100 μm to 800 μm; the doping concentration of the P-well type ohmic contact ring is 1e18 cm -3 -1e20cm -3 , depth is 0.3μm~1.0μm, and ring width is 1.0μm~10μm.

[0045] As described above, the avalanche photodiode based on double epitaxy of the present invention and the preparation method thereof realize that the injection of all P-type ions and N-type ions is achieved through surface ion injection through double epitaxy processes, and does not require deeper ion injection, avoids the use of high-energy ion implanters, reduces the difficulty of preparation, and reduces manufacturing costs; in addition, the avalanche photodiode prepared by the preparation method of the present invention forms a P+ doping layer on the surface of the first P-type epitaxial layer, and its doping concentration is relatively large compared to the doping concentration of the first P-type epitaxial layer, which can adjust the electric field distribution inside the avalanche photodiode, and assist the second anode ohmic contact electrode to achieve full depletion of the first P-type epitaxial layer and the second P-type epitaxial layer, that is, the full depletion state of the first P-type epitaxial layer and the second P-type epitaxial layer can be adjusted through the P+ doping layer, so that they can be depleted at a lower voltage, that is, the depletion voltage is reduced, thereby reducing the diffusion current and improving the cut-off frequency of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figures 1 to 14 and Figures 18 to 20 It shows a schematic diagram of the cross-sectional structure presented in each step of the method for preparing an avalanche photodiode based on double epitaxy of the present invention.

[0047] Fig.15 FIG. 1 is a schematic cross-sectional structure diagram of a first example of an avalanche photodiode based on double epitaxy according to the present invention.

[0048] Fig.16 FIG. 4 is a schematic cross-sectional structure diagram of a second example of an avalanche photodiode based on double epitaxy according to the present invention.

[0049] Fig.17 FIG. 4 is a schematic cross-sectional structure diagram of a third example of a double-epitaxial avalanche photodiode according to the present invention.

[0050] Fig.21FIG. 4 is a schematic cross-sectional structure diagram of a fourth example of a double-epitaxial avalanche photodiode according to the present invention.

[0051] Component number description

[0052] 100 epitaxial wafer

[0053] 101 P-type substrate

[0054] 102 First P-type epitaxial layer

[0055] 103 First dielectric layer

[0056] 104 Second P-type epitaxial layer

[0057] 105 Second dielectric layer

[0058] 106 P-well

[0059] 107 N-well

[0060] 108 N type protection ring

[0061] 109 P-well ohmic contact ring

[0062] 110 First-level N-type protection ring

[0063] 111 Second level N type protection ring

[0064] 112 Third-level N-type protection ring

[0065] 113 Fourth level N type protection ring

[0066] 114 First support wafer

[0067] 115 P+ doped layer

[0068] 116 first anode ohmic contact electrode

[0069] 117 second supporting wafer

[0070] 118 Third dielectric layer

[0071] 119 Electrode filling hole

[0072] 120 second anode ohmic contact electrode

[0073] 121 cathode ohmic contact electrode

[0074] 122 Ohm contact electrode

[0075] 123 Electrode protection layer

[0076] 124 Support substrate

[0077] 125 Insulation dielectric layer

[0078] 126 Doped substrate layer

[0079] 127 Through slot DETAILED DESCRIPTION

[0080] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0081] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic view is only an example, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional space dimensions of length, width and depth should be included.

[0082] For ease of description, spatial relational terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatial relational terms are intended to include other directions of the device in use or operation in addition to the directions depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there can be one or more intervening layers. As used herein, "between..." means including the end point values.

[0083] See also Figures 1 to 21 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0084] This embodiment provides a method for preparing an avalanche photodiode based on double epitaxy, the method comprising:

[0085] Providing an epitaxial wafer, wherein the epitaxial wafer includes a first P-type epitaxial layer;

[0086] Performing P-well ion implantation from the surface of the first P-type epitaxial layer inwards;

[0087] epitaxially depositing a second P-type epitaxial layer on the surface of the first P-type epitaxial layer; wherein the doping concentration of the second P-type epitaxial layer is the same as the doping concentration of the first P-type epitaxial layer;

[0088] Performing ion implantation of an N-well, an N-type guard ring, and a P-well type ohmic contact ring from the surface of the second P-type epitaxial layer inward;

[0089] The ion implantation is thermally annealed to form a P-well, an N-well, an N-type guard ring and a P-well type ohmic contact ring; wherein the P-well is located below the N-well, and the surface of the N-well completely covers the surface of the P-well; the P-well and the N-well form an avalanche region; the P-type epitaxial layer forms an electron absorption region; the N-type guard ring is located at the periphery of the avalanche region; and the P-well type ohmic contact ring is located at the periphery of the N-type guard ring;

[0090] A P+ doped layer and a first anode ohmic contact electrode are sequentially formed on the lower side of the first P-type epitaxial layer, and a second anode ohmic contact electrode and a cathode ohmic contact electrode are formed on the upper surface of the second P-type epitaxial layer; wherein the doping concentration of the P+ doped layer is greater than the doping concentration of the first P-type epitaxial layer, the second anode ohmic contact electrode is contact-connected to the P-well type ohmic contact ring, and the cathode ohmic contact electrode is contact-connected to the N-well.

[0091] The preparation method of the avalanche photodiode based on double epitaxy of the present embodiment realizes that the injection of all P-type ions and N-type ions is achieved through surface ion injection through double epitaxy processes, and does not require deeper ion injection, avoids the use of high-energy ion implanters, reduces the difficulty of preparation, and reduces manufacturing costs; in addition, the avalanche photodiode prepared by the preparation method of the present embodiment forms a P+ doping layer on the surface of the first P-type epitaxial layer, and its doping concentration is relatively large compared to the doping concentration of the first P-type epitaxial layer, which can adjust the electric field distribution inside the avalanche photodiode and assist the second anode ohmic contact electrode to achieve full depletion of the first P-type epitaxial layer and the second P-type epitaxial layer, that is, the full depletion state of the first P-type epitaxial layer and the second P-type epitaxial layer can be adjusted through the P+ doping layer, so that they can be depleted at a lower voltage, that is, the depletion voltage is reduced, thereby reducing the diffusion current and improving the cut-off frequency of the device.

[0092] The method for preparing the avalanche photodiode based on double epitaxy of this embodiment is described in detail below with reference to the specific drawings.

[0093] like Figure 1 As shown, step S1 is first performed to provide an epitaxial wafer 100 , wherein the epitaxial wafer 100 includes a first P-type epitaxial layer 102 .

[0094] It should be noted here that the epitaxial wafer 100 can be directly purchased from outside; or the epitaxial wafer 100 can be obtained by purchasing a substrate wafer from outside and forming the first P-type epitaxial layer 102 thereon through a deposition process.

[0095] In this embodiment, the thickness of the epitaxial wafer 100 is selected to be 750 μm, and the diameter of the epitaxial wafer 100 can be 4 inches, 6 inches, 8 inches or 12 inches.

[0096] like Figure 1 As shown, as an example, the substrate of the epitaxial wafer 100 may be a single-layer semiconductor substrate, such as Figure 1 In the embodiment, the epitaxial wafer 100 is composed of a P-type substrate 101 and a first P-type epitaxial layer 102 thereon.

[0097] like Figure 3 As shown, as an example, the substrate of the epitaxial wafer 100 can be a semiconductor layer on insulator structure, that is, including a supporting substrate 124, an insulating dielectric layer 125 and a doped substrate layer 126, such as a SOI structure, including a silicon substrate, a silicon dioxide insulating dielectric layer and an upper doped substrate layer, such as Figure 2 As shown, a P+ doped layer 115 is formed by ion implantation into the doped substrate layer 126 .

[0098] For ease of description, in the subsequent related steps, the structure of the epitaxial wafer 100 is explained by taking a single-layer semiconductor substrate as an example, but those skilled in the art can understand that the substrate of the epitaxial wafer 100 can also be a semiconductor layer structure on an insulator, which does not require creative labor.

[0099] like Figure 5 As shown, step S2 is then performed to perform P-well ion implantation from the surface of the first P-type epitaxial layer 102 inward.

[0100] As a specific example, the method of performing ion implantation of the P well includes: Figure 4 As shown, firstly, a first dielectric layer 103 is formed on the surface of the first P-type epitaxial layer 102; Figure 5 As shown, the ion implantation of the P well is then performed based on the first dielectric layer 103 serving as a protective layer for ion implantation.

[0101] In this embodiment, the material of the first dielectric layer 103 is silicon dioxide, and is formed by thermal oxidation process with a thickness of The parameters of the thermal oxidation process are: oxygen atmosphere, temperature of 900°C to 1100°C, and time of 60min to 300min.

[0102] It should be noted here that the implantation width of the P-well ion implantation is set according to actual needs, and during ion implantation, the implantation position is determined by coating photoresist and performing patterning to achieve ion implantation at the desired position.

[0103] In this embodiment, the implantation conditions for the ion implantation of the P well are: boron ion implantation, and the ion implantation dose is 3e10cm -2 ~3e13cm -2 , the injection energy is 180keV~220keV.

[0104] like Figure 6 As shown, step S3 is then performed to epitaxially deposit a second P-type epitaxial layer 104 on the surface of the first P-type epitaxial layer 102 ; wherein the doping concentration of the second P-type epitaxial layer 104 is the same as the doping concentration of the first P-type epitaxial layer 102 .

[0105] It should be noted that the first dielectric layer 103 needs to be removed before depositing the second P-type epitaxial layer 104. Generally, the first dielectric layer 103 is removed by wet etching, and thermal annealing is performed after the first dielectric layer 103 is removed to repair the surface of the first P-type epitaxial layer 102.

[0106] In this embodiment, the thickness of the second P-type epitaxial layer 104 is selected to be 1 μm to 3 μm.

[0107] like Figures 7 to 9 As shown, step S4 is then performed to perform N-well ion implantation from the surface of the second P-type epitaxial layer 104 inward (as shown in FIG. Figure 7 As shown), ion implantation of N-type guard ring (as shown Figure 8 As shown) and ion implantation of P-well type ohmic contact ring (as shown Fig. 9 shown).

[0108] As a specific example, the method of performing the ion implantation of the N-well, the ion implantation of the N-type guard ring and the ion implantation of the P-well type ohmic contact ring includes: Figure 7 As shown, firstly, a second dielectric layer 105 is formed on the surface of the second P-type epitaxial layer 104, and the second dielectric layer 105 serves as a protective layer for ion implantation; then, ion implantation of the N-well is performed based on the second dielectric layer 105 serving as a protective layer for ion implantation; as shown Figure 8 As shown, the ion implantation of the N-type guard ring is then performed based on the second dielectric layer 105 as a protective layer for ion implantation; Fig. 9 As shown, the ion implantation of the P-well type ohmic contact ring is then performed based on the second dielectric layer 105 serving as a protective layer for ion implantation.

[0109] In this embodiment, the material of the second dielectric layer 105 is silicon dioxide, and is formed by thermal oxidation process with a thickness of The parameters of the thermal oxidation process are: oxygen atmosphere, temperature of 900°C to 1100°C, and time of 60min to 300min.

[0110] like Figures 15 to 17 As shown, when the subsequently prepared avalanche photodiode includes a first-stage N-type guard ring 110, a second-stage N-type guard ring 111, a third-stage N-type guard ring 112, and a fourth-stage N-type guard ring 113, the ion implantation of the corresponding guard rings can also be completed in this step. Fig.15 As shown, when the avalanche photodiode includes a first-level N-type guard ring 110, ion implantation of the first-level N-type guard ring can be performed from the surface of the second P-type epitaxial layer 104 inward in this step; Fig.16 As shown, when the avalanche photodiode includes a second-level N-type guard ring 111 and a third-level N-type guard ring 112, ion implantation of the second-level N-type guard ring and ion implantation of the third-level N-type guard ring can be performed from the surface of the second P-type epitaxial layer 104 inward in this step; Fig.17 As shown, when the avalanche photodiode includes a fourth-level N-type guard ring 113 , ion implantation of the fourth-level N-type guard ring can be performed from the surface of the second P-type epitaxial layer 104 inward in this step.

[0111] It should be noted here that the order of the ion implantation of the N-well, the ion implantation of the N-type guard ring, the ion implantation of the P-well type ohmic contact ring, the ion implantation of the first-level N-type guard ring 110, the ion implantation of the second-level N-type guard ring 111, the ion implantation of the third-level N-type guard ring 112, and the ion implantation of the fourth-level N-type guard ring 113 is not limited to each other, and can be performed one after another or simultaneously. The parameters such as the implantation depth and implantation width of the ion implantation of the N-well, the ion implantation of the N-type guard ring, the ion implantation of the P-well type ohmic contact ring, the ion implantation of the first-level N-type guard ring 110, the ion implantation of the second-level N-type guard ring 111, the ion implantation of the third-level N-type guard ring 112, and the ion implantation of the fourth-level N-type guard ring 113 are set according to actual needs, and no excessive restrictions are made here.

[0112] In this embodiment, the ion implantation of the N-well, the ion implantation of the N-type guard ring and the ion implantation of the P-well type ohmic contact ring are performed in sequence. The ion implantation of the N-well is performed under the following conditions: phosphorus ion implantation with an ion implantation dose of 3e10 cm -2 ~3e17cm -2 , the implantation energy is 180keV~220keV, single or multiple ion implantation; the ion implantation of N-type guard ring, the implantation conditions are: phosphorus ion implantation, the ion implantation dose is 1e11cm-2 ~1e13cm -2 The implantation depth is 0 μm to 2.5 μm, and the implantation energy is 300 keV, 200 keV, and 100 keV in steps. The ion implantation conditions of the P-well type ohmic contact ring are: boron ion implantation, and the ion implantation dose is 1e12 cm -2 ~1e14cm -2 The implantation depth is 0 μm to 1.5 μm, and the implantation energy is 180 keV to 220 keV.

[0113] like Fig. 9 As shown, step S5 is then performed to perform thermal annealing on the above-mentioned ion implantation to activate the implanted ions to form a P-well 106, an N-well 107, an N-type guard ring 108 and a P-well type ohmic contact ring 109; wherein the P-well 106 is located below the N-well 107, and the surface of the N-well 107 completely covers the surface of the P-well 106; the P-well 106 and the N-well 107 form an avalanche zone; the first P-type epitaxial layer 102 and the second P-type epitaxial layer 104 form an electron absorption zone; the N-type guard ring 108 is located at the periphery of the avalanche zone; and the P-well type ohmic contact ring 109 is located at the periphery of the N-type guard ring 108.

[0114] It should be noted that the surface of the N-well 107 completely covers the surface of the P-well 106, that is, the surface size of the N-well 107 can be the same as the surface size of the P-well 106, or can be larger than the surface size of the P-well 106. The P-well 106 is located below the N-well 107 and can be in contact with the N-well 107. Figures 14 to 17 and Fig. 20 In the figure, the P-well 106 and the N-well 107 are in contact with each other, or they may be in a non-contact state, such as Fig.21 As shown, there is a spacing distance between the P-well 106 and the N-well 107. Preferably, the P-well 106 and the N-well 107 are spaced apart, which can effectively increase the electron mean free migration path to improve the device gain under the same external bias voltage, while preventing the breakdown effect between the N-well 107 and the P+ doped layer 115. Setting the spacing between the two too large will increase the difficulty of the ion implantation process, and will also increase the bias voltage and affect the electric field distribution of the device. Therefore, it is preferably set to a spacing distance of no more than 4μm, for example, 1μm, 2μm, 3μm, etc.

[0115] In this embodiment, the annealing conditions for the thermal annealing treatment are as follows: the annealing temperature is 800° C. to 1100° C., and the annealing time is 20 min to 90 min.

[0116] like Figures 15 to 17As shown, when the prepared avalanche photodiode includes a first-level N-type guard ring 110, a second-level N-type guard ring 111, a third-level N-type guard ring 112, and a fourth-level N-type guard ring 113, the first-level N-type guard ring 110, the second-level N-type guard ring 111, the third-level N-type guard ring 112, and the fourth-level N-type guard ring 113 are formed after the thermal annealing treatment in this step. For example, Fig.15 As shown, after the thermal annealing treatment in this step, the avalanche photodiode includes a first-level N-type guard ring 110, and the first-level N-type guard ring 110 is formed on the periphery of the P-well type ohmic contact ring 109; Fig.16 As shown, after the thermal annealing treatment in this step, the avalanche photodiode includes a second-stage N-type guard ring 111 and a third-stage N-type guard ring 112, and the second-stage N-type guard ring 111 and the third-stage N-type guard ring 112 are nested in sequence and formed on the periphery of the P-well type ohmic contact ring 109; Fig.17 As shown, after the thermal annealing treatment in this step, the avalanche photodiode includes a fourth-level N-type guard ring 113 , and the fourth-level N-type guard ring 113 is formed between the N-type guard ring 108 and the P-well type ohmic contact ring 109 .

[0117] Finally, step S6 is performed to sequentially form a P+ doped layer 115 and a first anode ohmic contact electrode 116 on the lower side of the first P-type epitaxial layer 102, and form a second anode ohmic contact electrode 120 and a cathode ohmic contact electrode 121 on the upper surface of the second P-type epitaxial layer 104; wherein the doping concentration of the P+ doped layer 115 is greater than the doping concentration of the first P-type epitaxial layer 102, the second anode ohmic contact electrode 120 is in contact with and connected to the P-well type ohmic contact ring 109, and the cathode ohmic contact electrode 121 is in contact with and connected to the N-well 107.

[0118] As a specific example, Figures 10 to 14 As shown, the epitaxial wafer 100 further includes a P-type substrate 101, and the P-type substrate 101 is in contact with the first P-type epitaxial layer 102. The method of sequentially forming the P+ doped layer 115 and the first anode ohmic contact electrode 116 on the lower side of the first P-type epitaxial layer 102 includes: Fig.10 As shown, first, a first supporting wafer 114 is bonded to the surface of the second dielectric layer 105; then the P-type substrate 101 is thinned to a preset thickness; Fig.11 As shown, ion implantation of a P+ doped layer is performed from the surface of the thinned P-type substrate 101 inward, and thermal annealing is performed to form the P+ doped layer 115, wherein the implantation conditions of the ion implantation of the P+ doped layer are: boron ion implantation, and the ion implantation dose is 1e12 cm -2～ 1e14cm-2 , the implantation depth is 0μm~1.5μm, the implantation energy is 180keV~220keV, the annealing conditions of the thermal annealing treatment are: the annealing temperature is 800℃~1100℃, and the annealing time is 20min~90min; Fig.12 As shown, finally, the first anode ohmic contact electrode 116 is deposited on the surface of the P+ doped layer 115. The method for forming the second anode ohmic contact electrode 120 and the cathode ohmic contact electrode 121 on the upper surface of the second P-type epitaxial layer 104 includes: Fig.12 As shown, firstly, a second supporting wafer 117 is bonded to the surface of the first anode ohmic contact electrode 116; then, the first supporting wafer 114 is removed by debonding; then, the second dielectric layer 105 is removed, and a third dielectric layer 118 is formed on the surface of the second P-type epitaxial layer 104. The material of the third dielectric layer 118 is selected to be silicon dioxide, and is formed by a thermal oxidation process. The parameters of the thermal oxidation process are: oxygen atmosphere, temperature of 900°C to 1100°C, and time of 60min to 300min; as shown Fig.13 As shown, the third dielectric layer 118 is then pattern-etched to form a through electrode filling hole 119 in the third dielectric layer 118; a metal layer is then deposited on the third dielectric layer 118, and the metal layer fills the electrode filling hole 119 to obtain the second anode ohmic contact electrode 120 and the cathode ohmic contact electrode 121; an electrode protection layer 123 is then deposited; as shown Fig.14 As shown, the second supporting wafer 117 is finally removed by debonding.

[0119] As another specific example, Figures 18 to 20 As shown, the epitaxial wafer 100 also includes a supporting substrate 124, an insulating dielectric layer 125 and the P+ doping layer 115 in sequence along the thickness direction, and the P+ doping layer 115 is in contact with the first P-type epitaxial layer 102. The method of forming the second anode ohmic contact electrode 120 and the cathode ohmic contact electrode 121 on the upper surface of the second P-type epitaxial layer 104 includes: Fig.18 As shown, first, the second dielectric layer 105 is removed, and a third dielectric layer 118 is formed on the surface of the second P-type epitaxial layer 104; then, the third dielectric layer 118 is pattern-etched to form a through electrode filling hole 119 in the third dielectric layer 118; then, a metal layer is deposited on the third dielectric layer 118, and the metal layer fills the electrode filling hole to obtain the second anode ohmic contact electrode 120 and the cathode ohmic contact electrode 121; finally, an electrode protection layer 123 is deposited. The method of sequentially forming the P+ doped layer 115 and the first anode ohmic contact electrode 116 on the lower side of the first P-type epitaxial layer 102 includes: Fig.19 As shown, first, the support substrate 124 and the insulating dielectric layer 125 are etched to form a through groove 127; Fig. 20 As shown, the first anode ohmic contact electrode 116 is then deposited on the surface of the support substrate 124 and the sidewalls and bottom walls of the through groove 127. The epitaxial wafer 100 with a semiconductor-on-insulator structure is used to prepare an avalanche photodiode. The semiconductor-on-insulator structure can be used to reduce the use of a support wafer during the preparation process, thereby reducing the bonding and debonding processes, and effectively reducing the preparation complexity and manufacturing cost.

[0120] like Figures 15 to 17 As shown, when the prepared avalanche photodiode includes a first-level N-type guard ring 110, a second-level N-type guard ring 111, a third-level N-type guard ring 112, and a fourth-level N-type guard ring 113, the corresponding ohmic contact electrode 122 is simultaneously formed during the process of forming the electrode in this step. Fig.15 As shown, an ohmic contact electrode 122 is formed to contact the first-level N-type guard ring 110; Fig.16 As shown, an ohmic contact electrode 122 is formed to contact the second-level N-type guard ring 111 and the third-level N-type guard ring 112; Fig.17 As shown, an ohmic contact electrode 122 is formed to contact the fourth-level N-type guard ring 113 .

[0121] like Figures 12 to 15 As shown, based on the above-mentioned method for preparing an avalanche photodiode, this embodiment further provides an avalanche photodiode, which is prepared by the above-mentioned preparation method. The avalanche photodiode includes, in sequence along the thickness direction: a first anode ohmic contact electrode 116, a P+ doped layer 115, a first P-type epitaxial layer 102, a second P-type epitaxial layer 104, a P-well 106, an N-well 107, an N-type guard ring 108, a P-well type ohmic contact ring 109, a second anode ohmic contact electrode 120, and a cathode ohmic contact electrode 121; wherein,

[0122] The N-well 107, the N-type guard ring 108 and the P-well type ohmic contact ring 109 extend downward from the surface of the second P-type epitaxial layer 104; the P-well 106 is located below the N-well 107, and the surface of the N-well 107 completely covers the surface of the P-well 106; the P-well 106 and the N-well 107 form an avalanche region; the first P-type epitaxial layer 102 and the second P-type epitaxial layer 104 form an electron absorption region;

[0123] The N-type guard ring 108 is located at the periphery of the avalanche region;

[0124] The P-well type ohmic contact ring 109 is located at the periphery of the N-type guard ring 108;

[0125] The second anode ohmic contact electrode 120 is in contact with and connected to the P-well type ohmic contact ring 109;

[0126] The cathode ohmic contact electrode 121 is in contact with and connected to the N-well 107 .

[0127] As a preferred example, the avalanche photodiode further includes: a P-type substrate 101; the upper and lower surfaces of the P-type substrate 101 are respectively in contact with the P+ doping layer 115 and the first P-type epitaxial layer 102, and the doping concentration of the P+ doping layer 115 is greater than the doping concentration of the P-type substrate 101; the semiconductor material used in the avalanche photodiode is silicon; the doping concentration of the P+ doping layer 115 is 1e18cm -3 -1e20cm -3 , with a thickness of 0.1 μm to 1.0 μm and a width of 200 μm to 2000 μm; the doping concentration of the P-type substrate 101 is 1e14 cm -3 -1e18cm -3 , a thickness of 100 μm to 500 μm, a width of 200 μm to 2000 μm; a doping concentration of the first P-type epitaxial layer 102 and the second P-type epitaxial layer 104 is 1e11 cm -3 -1e14cm -3 The sum of the thickness of the first P-type epitaxial layer 102 and the second P-type epitaxial layer 104 is 0.5 μm to 100 μm, the width of the first P-type epitaxial layer 102 and the second P-type epitaxial layer 104 is 200 μm to 2000 μm; the doping concentration of the N-type guard ring 108 is 1e14 cm -3 -1e18cm -3 , the depth is 1.0μm to 3.0μm, the ring width is 10μm to 60μm; the doping concentration of the P well 106 is 1e16cm -3 -1e19cm -3 , with a thickness of 0.8 μm to 2.0 μm and a width of 80 μm to 700 μm; the doping concentration of the N well 107 is 1e16 cm -3 -1e19cm -3 , with a thickness of 0.7 μm to 1.5 μm and a width of 100 μm to 800 μm; the doping concentration of the P-well type ohmic contact ring 109 is 1e18 cm -3 -1e20cm -3, depth is 0.3μm~1.0μm, and ring width is 1.0μm~10μm. By setting these parameters, the avalanche photodiode can work in the near-infrared band of 800nm~950nm, and the avalanche photodiode can fully meet the required device cutoff frequency, absorption peak and dark current requirements.

[0128] In summary, the present invention provides an avalanche photodiode based on double epitaxy and a preparation method thereof. Through the double epitaxy process, the implantation of all P-type ions and N-type ions is realized in the form of surface ion implantation, and there is no need for deeper ion implantation, avoiding the use of high-energy ion implantation machines, reducing the difficulty of preparation and reducing the manufacturing cost. In addition, the avalanche photodiode prepared by the preparation method of this embodiment forms a P+ doping layer on the surface of the first P-type epitaxial layer, and its doping concentration is relatively large compared to the doping concentration of the first P-type epitaxial layer, which can adjust the electric field distribution inside the avalanche photodiode, and assist the second anode ohmic contact electrode to achieve full depletion of the first P-type epitaxial layer and the second P-type epitaxial layer, that is, the full depletion state of the first P-type epitaxial layer and the second P-type epitaxial layer can be adjusted through the P+ doping layer, so that it can be depleted at a lower voltage, that is, the depletion voltage is reduced, thereby reducing the diffusion current and improving the cut-off frequency of the device. Therefore, the present invention effectively overcomes the various shortcomings in the prior art and has a high industrial utilization value.

[0129] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for preparing an avalanche photodiode based on double epitaxy, characterized in that: The preparation method comprises: Providing an epitaxial wafer, wherein the epitaxial wafer includes a first P-type epitaxial layer; Performing P-well ion implantation from the surface of the first P-type epitaxial layer inward; epitaxially depositing a second P-type epitaxial layer on the surface of the first P-type epitaxial layer; wherein the doping concentration of the second P-type epitaxial layer is the same as the doping concentration of the first P-type epitaxial layer; Performing ion implantation of an N-well, an N-type guard ring, and a P-well ohmic contact ring from the surface of the second P-type epitaxial layer inward; The ion implantation is thermally annealed to form a P-well, an N-well, an N-type guard ring, and a P-well ohmic contact ring; wherein the P-well is located below the N-well, and the surface of the N-well completely covers the surface of the P-well; the P-well and the N-well form an avalanche region; the first P-type epitaxial layer and the second P-type epitaxial layer form an electron absorption region; the N-type guard ring is located outside the avalanche region; and the P-well ohmic contact ring is located outside the N-type guard ring. A P+ doped layer and a first anode ohmic contact electrode are sequentially formed on the lower side of the first P-type epitaxial layer, and a second anode ohmic contact electrode and a cathode ohmic contact electrode are formed on the upper surface of the second P-type epitaxial layer; wherein, the doping concentration of the P+ doped layer is greater than the doping concentration of the first P-type epitaxial layer, the second anode ohmic contact electrode is contact-connected to the P-well ohmic contact ring, and the cathode ohmic contact electrode is contact-connected to the N-well.

2. The method for fabricating a double-epitaxial avalanche photodiode according to claim 1, wherein: The ion implantation of the N-well, the ion implantation of the N-type guard ring and the ion implantation of the P-well ohmic contact ring also includes the step of implanting a first-level N-type guard ring from the surface of the second P-type epitaxial layer inward; after thermal annealing, a first-level N-type guard ring is formed, and the first-level N-type guard ring is formed on the periphery of the P-well ohmic contact ring.

3. The method for fabricating avalanche photodiode based on double epitaxy according to claim 1, characterized in that: The ion implantation of the N-well, the ion implantation of the N-type guard ring and the ion implantation of the P-well ohmic contact ring also includes the steps of implanting the second-level N-type guard ring and the third-level N-type guard ring from the surface of the second P-type epitaxial layer inward; after thermal annealing, the second-level N-type guard ring and the third-level N-type guard ring are formed, and the second-level N-type guard ring and the third-level N-type guard ring are nested in sequence and formed on the periphery of the P-well ohmic contact ring.

4. The method for fabricating avalanche photodiode based on double epitaxy according to claim 1, characterized in that: The ion implantation of the N-well, the ion implantation of the N-type guard ring, and the ion implantation of the P-well ohmic contact ring also includes the step of implanting a fourth-level N-type guard ring from the surface of the second P-type epitaxial layer inward; after thermal annealing, a fourth-level N-type guard ring is formed, and the fourth-level N-type guard ring is formed between the N-type guard ring and the P-well ohmic contact ring.

5. The method for fabricating avalanche photodiode based on double epitaxy according to claim 1, characterized in that: Before performing the ion implantation of the P-well, the method further includes forming a first dielectric layer on the surface of the first P-type epitaxial layer, and removing the first dielectric layer before depositing the second P-type epitaxial layer.

6. The method for fabricating avalanche photodiode based on double epitaxy according to claim 1, characterized in that: Before performing the ion implantation of the N-well, the ion implantation of the N-type guard ring and the ion implantation of the P-well type ohmic contact ring, a step of forming a second dielectric layer on the surface of the second P-type epitaxial layer is also included.

7. The method for preparing avalanche photodiode based on double epitaxy according to claim 6, characterized in that: The epitaxial wafer further includes a P-type substrate, and the P-type substrate is in contact with the first P-type epitaxial layer. The method of sequentially forming the P+ doped layer and the first anode ohmic contact electrode on the lower side of the first P-type epitaxial layer includes: bonding a first supporting wafer to the surface of the second dielectric layer; Thinning the P-type substrate to a preset thickness; Performing ion implantation of a P+ doping layer inward from the thinned surface of the P-type substrate, and thermally annealing the P+ doping layer to form the P+ doping layer, wherein the doping concentration of the P+ doping layer is greater than the doping concentration of the P-type substrate; The first anode ohmic contact electrode is deposited on the surface of the P+ doped layer.

8. The method for preparing avalanche photodiode based on double epitaxy according to claim 7, characterized in that: The method of forming the second anode ohmic contact electrode and the cathode ohmic contact electrode on the upper surface of the second P-type epitaxial layer includes: bonding a second supporting wafer to the surface of the first anode ohmic contact electrode; debonding to remove the first support wafer; removing the second dielectric layer and forming a third dielectric layer on the surface of the second P-type epitaxial layer; Performing pattern etching on the third dielectric layer to form a through electrode filling hole in the third dielectric layer; Depositing a metal layer on the third dielectric layer, and the metal layer completely fills the electrode filling hole to obtain the second anode ohmic contact electrode and the cathode ohmic contact electrode; Deposition of electrode protection layer; Debonding is performed to remove the second support wafer.

9. The method for preparing avalanche photodiode based on double epitaxy according to claim 6, characterized in that: The epitaxial wafer further includes a supporting substrate, an insulating dielectric layer, and the P+ doped layer in sequence along the thickness direction, and the P+ doped layer is in contact with the first P-type epitaxial layer. The method for forming the second anode ohmic contact electrode and the cathode ohmic contact electrode on the upper surface of the second P-type epitaxial layer includes: removing the second dielectric layer and forming a third dielectric layer on the surface of the second P-type epitaxial layer; Performing pattern etching on the third dielectric layer to form a through electrode filling hole in the third dielectric layer; Depositing a metal layer on the third dielectric layer, and the metal layer completely fills the electrode filling hole to obtain the second anode ohmic contact electrode and the cathode ohmic contact electrode; Depositing the electrode protection layer.

10. The method for preparing avalanche photodiode based on double epitaxy according to claim 9, characterized in that: The method of sequentially forming the P+ doped layer and the first anode ohmic contact electrode on the lower side of the first P-type epitaxial layer includes: Etching the support substrate and the insulating dielectric layer to form a through groove; The first anode ohmic contact electrode is deposited on the surface of the supporting substrate and the sidewalls and bottom walls of the through groove.

11. A double-epitaxial avalanche photodiode, prepared by the method for preparing a double-epitaxial avalanche photodiode according to any one of claims 1 to 10, characterized in that: The avalanche photodiode includes, in order along the thickness direction: a first anode ohmic contact electrode, a P+ doped layer, a first P-type epitaxial layer, a second P-type epitaxial layer, a P-well, an N-well, an N-type guard ring, a P-well type ohmic contact ring, a second anode ohmic contact electrode, and a cathode ohmic contact electrode; wherein, The N-well, the N-type guard ring, and the P-well ohmic contact ring extend downward from the surface of the second P-type epitaxial layer; the P-well is located below the N-well, and the surface of the N-well completely covers the surface of the P-well; the P-well and the N-well form an avalanche region; the first P-type epitaxial layer and the second P-type epitaxial layer form an electron absorption region; The N-type guard ring is located at the periphery of the avalanche zone; The P-well type ohmic contact ring is located on the periphery of the N-type guard ring; The second anode ohmic contact electrode is in contact with the P-well type ohmic contact ring; The cathode ohmic contact electrode is contact-connected to the N-well.

12. The double-epitaxial avalanche photodiode according to claim 11, characterized in that: The avalanche photodiode further comprises: a P-type substrate; the upper and lower surfaces of the P-type substrate are in contact with the P+ doped layer and the first P-type epitaxial layer, respectively, and the doping concentration of the P+ doped layer is greater than the doping concentration of the P-type substrate; the semiconductor material used in the avalanche photodiode is silicon; the doping concentration of the P+ doped layer is 1e18cm -3 -1e20cm -3 , with a thickness of 0.1 μm to 1.0 μm and a width of 200 μm to 2000 μm; the doping concentration of the P-type substrate is 1e14 cm -3 -1e18cm -3 , a thickness of 100 μm to 500 μm, a width of 200 μm to 2000 μm; a doping concentration of the first P-type epitaxial layer and the second P-type epitaxial layer is 1e11 cm -3 -1e14cm -3 The sum of the thickness of the first P-type epitaxial layer and the second P-type epitaxial layer is 0.5 μm to 100 μm, and the width of the first P-type epitaxial layer and the second P-type epitaxial layer is 200 μm to 2000 μm; the doping concentration of the N-type guard ring is 1e14 cm -3 -1e18cm -3 , the depth is 1.0μm~3.0μm, the ring width is 10μm~60μm; the doping concentration of the P well is 1e16cm -3 -1e19cm -3 , with a thickness of 0.8μm to 2.0μm and a width of 80μm to 700μm; the doping concentration of the N well is 1e16cm -3 -1e19cm -3 , with a thickness of 0.7μm to 1.5μm and a width of 100μm to 800μm; the doping concentration of the P-well type ohmic contact ring is 1e18cm -3 -1e20cm -3 , the depth is 0.3μm~1.0μm, and the ring width is 1.0μm~10μm.

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