A method and system for automatically obtaining MCU clock frequency by a host computer

Abstract

The present invention relates to the field of MCU technology, and in particular to a method and system for a host computer to automatically obtain an MCU clock frequency, the steps of which include: connecting a target chip, downloading a frequency multiplication coefficient evaluation program, and configuring a minimum frequency multiplication coefficient; running the evaluation program, obtaining results, and adjusting the frequency multiplication coefficient; downloading a capture and analysis program, configuring the frequency multiplication coefficient and the JTAG_TDI pin to generate a fixed PWM frequency; initializing the capture and analysis program, and reading the PWM pin level state; analyzing the clock frequency and saving it; the host computer connects to the target chip to obtain and save the clock frequency. The present invention has strong versatility, does not require additional hardware, and is simple to implement. The clock frequency is automatically obtained, the abnormalities of artificial settings are reduced, the communication waiting time is more accurate, and the system clock diagnosis can be performed.

Description

Technical Field

[0001] The present invention relates to the technical field of MCU, and in particular to a method and system for a host computer to automatically obtain a clock frequency of an MCU. Background Art

[0002] MCU chips, as a general-purpose programmable device, often require multiple program burning and debugging verification during the program development process. When burning Flash programs, the timing setting is based on the MCU's input clock or system clock frequency as the time base. Therefore, during the program burning process, users need to carefully search the hardware circuit to determine the input clock frequency of the target chip and configure its burning main frequency accordingly. This process needs to be implemented manually by the user.

[0003] For the first type of MCU, there is no on-chip clock source module integrated in the chip. In this case, the host computer debugging software will provide a default clock frequency. The user needs to configure according to the input clock of the hardware board level and manually set the clock frequency. Although this processing method can meet the needs in some cases, the user needs to have certain hardware knowledge and debugging experience.

[0004] For the second type of MCU, the clock source module is already integrated in the chip. In this case, the host computer will select the known clock frequency in the chip by default, and the user cannot configure it. Although this processing method simplifies the operation, it is not very flexible and may not meet the needs of all users. Therefore, when choosing an MCU, users need to decide which type of MCU to choose based on their specific needs and application scenarios. Summary of the invention

[0005] In view of the deficiencies in the prior art, the present invention discloses a method and system suitable for a host computer to automatically obtain the MCU clock frequency, which is used to solve the above problems.

[0006] The present invention is achieved through the following technical solutions:

[0007] In a first aspect, the present invention provides a method for a host computer to automatically obtain an MCU clock frequency, comprising the following steps:

[0008] The host computer is connected to the target chip, the frequency multiplication coefficient evaluation program is downloaded to the target chip, and the minimum frequency multiplication coefficient is configured;

[0009] Run the frequency multiplication coefficient evaluation program and perform the evaluation. The host computer obtains the evaluation results and determines whether the program passes. If it passes, it proceeds to the next step. If it fails, it adjusts the frequency multiplication coefficient.

[0010] Download the capture and analysis program to the target chip and configure the frequency multiplication factor. At the same time, configure the simulator JTAG_TDI pin to generate a fixed known PWM frequency.

[0011] Initialize the capture parsing program, identify the capture mode variables, configure the CAP and GPIO registers, and continuously read the PWM pin level status to the data RAM;

[0012] Analyze the clock frequency, generate the program end flag and save it to the data RAM, connect the host computer to the target chip, obtain the clock frequency and save it.

[0013] Furthermore, in the method, in the process of connecting the host computer with the target chip, a synchronization protocol based on the MCU-JTAG simulation debugging interface is adopted. The host computer is connected to the emulator through a USB interface, and then establishes a communication link with the target chip to realize the read and write operations of the microcontroller (MCU) register and random access memory (RAM).

[0014] Furthermore, in the method, the frequency multiplication factor evaluation program is intended to perform data transmission and logic operations on the target chip and generate a flag bit indicating the termination of the operation. The operation result and the termination flag bit will be stored in a predetermined data RAM area.

[0015] Furthermore, in the method, after the host computer receives the evaluation result, if the passing standard is not met, the multiplication factor should be reduced by 2 units as a new multiplication factor for the capture analysis program.

[0016] Furthermore, in the method, first, the lowest multiplication factor is set for performance evaluation. Then, the multiplication factor is gradually increased after each test, and the cycle continues. If an abnormal calculation result occurs during the test, or the end flag is not generated, this indicates that the current multiplication factor has exceeded the maximum main frequency of the microcontroller unit (MCU). At this time, the host computer should read the configuration value of the phase locked loop (PLL) multiplication register.

[0017] Furthermore, in the method, the host computer is responsible for downloading and parsing the program, setting the entry address of the target chip program, and issuing a run instruction. In the JTAG interface, the TMS and TCK pins should be configured to a low level state, while other pins should remain in a high impedance state to maintain an idle state.

[0018] Furthermore, in the method, the capture and analysis program starts the initialization phase, and the host computer sends instructions to the emulator to configure the TMS and TCK pins of the JTAG interface to a low level state. At the same time, the TDI pin outputs a stable pulse width modulation (PWM) frequency signal, which is used as the reference time for the microcontroller (MCU) clock frequency calculation. The relationship between the clock frequency and the reference time base will be set according to the clock frequency analysis algorithm.

[0019] Furthermore, in the method, the host computer is responsible for reading the program termination flag and clock frequency value of the microcontroller unit (MCU). If the termination flag is invalid, it means that the clock frequency analysis process has not been successfully executed; on the contrary, if the termination flag is valid, the clock frequency should be read and stored.

[0020] Furthermore, in the method, the number of pulse width modulation (PWM) level cycles read should be no less than three.

[0021] In a second aspect, the present invention provides a system for a host computer to automatically obtain an MCU clock frequency, the system being used to implement the method for a host computer to automatically obtain an MCU clock frequency as described in the first aspect, comprising:

[0022] The host computer is used to run on the PC, simulate debugging and send command programs;

[0023] Emulator, used to implement USB to JTAG protocol and generate PWM frequency;

[0024] JTAG port, a communication protocol interface used to implement simulation debugging;

[0025] Core CPU, used to implement system control and algorithm functions;

[0026] Program RAM, used to provide running space for frequency multiplication coefficient evaluation program and capture analysis program;

[0027] Data RAM, used to provide IO capture level data cache space;

[0028] GPIO, used to implement IO multiplexing, input and output, and IO status cache functions;

[0029] CAP, used to realize edge-triggered automatic capture of PWM cycle and pulse width function;

[0030] PLL is used to multiply the input clock frequency and provide system and peripheral clocks.

[0031] The beneficial effects of the present invention are:

[0032] The present invention has strong versatility, does not require additional hardware support, and is simple to implement. The Flash program burning software automatically obtains the clock frequency, reducing the abnormal frequency setting caused by human factors. By automatically obtaining the clock, the communication waiting time of the host computer is more accurate and the status flag polling is reduced. System clock diagnosis can be realized. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0034] Figure 1 This is a method for the host computer to automatically obtain the MCU clock frequency principle and steps diagram;

[0035] Figure 2 It is a flow chart of a method for a host computer to automatically obtain the MCU clock frequency;

[0036] Figure 3 This is a functional block diagram of the MCU-CAP capture mode according to an embodiment of the present invention;

[0037] Figure 4 MCU-CPU reading mode clock diagram of the embodiment of the present invention

[0038] Figure 5 It is a CPU data migration program diagram of an embodiment of the present invention;

[0039] Figure 6 It is a program diagram of a clock frequency software algorithm of an embodiment of the present invention;

[0040] Figure 7 The system principle block diagram is suitable for the host computer to automatically obtain the MCU clock frequency. DETAILED DESCRIPTION

[0041] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0042] In one embodiment, referring to Figure 1 As shown, a method for a host computer to automatically obtain the MCU clock frequency is provided, including the following steps:

[0043] The host computer is connected to the target chip, the frequency multiplication coefficient evaluation program is downloaded to the target chip, and the minimum frequency multiplication coefficient is configured;

[0044] Run the frequency multiplication coefficient evaluation program and perform the evaluation. The host computer obtains the evaluation results and determines whether the program passes. If it passes, it proceeds to the next step. If it fails, it adjusts the frequency multiplication coefficient.

[0045] Download the capture and analysis program to the target chip and configure the frequency multiplication factor. At the same time, configure the simulator JTAG_TDI pin to generate a fixed known PWM frequency.

[0046] Initialize the capture parsing program, identify the capture mode variables, configure the CAP and GPIO registers, and continuously read the PWM pin level status to the data RAM;

[0047] Analyze the clock frequency, generate the program end flag and save it to the data RAM, connect the host computer to the target chip, obtain the clock frequency and save it.

[0048] In this embodiment, the host computer is connected to the target chip: first, the APP1 program is downloaded to the target chip, and the minimum multiplication factor is set.

[0049] In this embodiment, the APP1 program is run and evaluated: the host computer starts the APP1 program and waits for a period of time after running. After that, the host computer obtains the evaluation result to determine whether the program passes. If it fails, the multiplication factor is adjusted.

[0050] In this embodiment, the multiplication factor is optimized: if the APP1 evaluation fails, the multiplication factor is reduced by 2 and used as the multiplication factor of the APP2 program. Then, the host computer increases the multiplication factor and resets the APP1 program.

[0051] In this embodiment, APP2 program configuration and operation: download APP2 program to the target chip, and configure the optimal multiplication factor. After running APP2, disconnect the JTAG connection.

[0052] In this embodiment, PWM frequency capture configuration: configure the simulator JTAG_TDI pin to generate a fixed known PWM frequency, and wait for the APP2 system initialization to be completed.

[0053] In this embodiment, CAP capture mode and register configuration: After APP2 identifies the capture mode variable, it configures the CAP and GPIO registers to enable CAP capture, and waits for the capture to be completed.

[0054] In this embodiment, GPIO register reading and data storage: configure the GPIO register to continuously read the PWM pin level status to the data RAM.

[0055] In this embodiment, clock frequency analysis and data storage: the clock frequency is analyzed using a clock analysis algorithm, and a program end mark is generated and stored in a specific data RAM.

[0056] In this embodiment, the host computer clock frequency is obtained: the host computer enables the JTAG mode to connect to the target chip after waiting for a specified time, obtains the clock frequency and saves it.

[0057] In one embodiment, the MCU-JTAG simulation debugging interface (which is a synchronous protocol) is used, and the host computer is connected to the emulator via USB, and then establishes communication with the target MCU-JTAG to realize read and write operations on the MCU registers and RAM; the host computer reads and identifies specific registers of the target MCU or reads and writes RAM to ensure the normality of the hardware physical connection and the online status of the target MCU.

[0058] In one embodiment, the functions of APP1 include: the microcontroller unit (MCU) and the central processing unit (CPU) work together to realize on-chip data transmission, logical operations, and generate a flag bit for the end of operation. The operation results and the end flag bit will be stored in the specified data random access memory (RAM) area. After completing the development, debugging and verification of APP1, the program execution file needs to be converted into machine code and stored in the host computer.

[0059] Since the input clock frequency is unknown (the maximum main frequency of the MCU is known), the initial evaluation should be configured with the lowest multiplier. Subsequently, the test is performed by gradually increasing the multiplier to form a loop. If an abnormal calculation result appears in a test or the end flag is not generated, it indicates that the current multiplier has exceeded the maximum main frequency of the MCU. At this time, the host computer will read the configuration value of the phase-locked loop (PLL) multiplier register.

[0060] In this embodiment, the main frequency of the microcontroller unit (MCU) in actual operation should not exceed its nominal maximum main frequency. When determining the reserved frequency margin, factors such as the application environment of the MCU, the power consumption of the chip itself, and the heat dissipation performance must be considered comprehensively. By subtracting an appropriate value from the evaluation coefficient of APP1, the frequency multiplication coefficient of APP2 can be obtained. Generally speaking, the higher the main frequency, the higher the corresponding detection accuracy.

[0061] In this embodiment, after the host computer completes the download of the APP2 program, it configures the entry address of the MCU-PC program and issues a full-speed run instruction. Subsequently, the TMS and TCK pins of the JTAG interface are set to a low level state, and other pins are adjusted to a high impedance mode to ensure that the JTAG interface is in an idle state.

[0062] In this embodiment, the application APP2 starts to execute the initialization program. The host computer sends instructions to the emulator, causing the TMS and TCK pins of the emulator's JTAG interface to be set to a low level state. At the same time, the TDI pin generates a fixed, known pulse width modulation (PWM) frequency, which will be used as the reference time for the microcontroller (MCU) clock frequency calculation.

[0063] In this embodiment, the initialization time of the MCU-APP2 system must exceed the time required for the JTAG interface TDI to output PWM configuration, so as to ensure that the PWM signal is stably established before the MCU-APP2 program enters the capture mode.

[0064] In this embodiment, the user can set a variable tag in APP2, which is stored in the data RAM. The central processing unit (CPU) of the microcontroller (MCU) will read this tag to identify and decide which capture mode to use.

[0065] In one embodiment, if Figure 3 As shown in the figure, in MCU-CAP capture mode, the JTAG_TDI pin of the microcontroller unit (MCU) is required to be configured as a capture (CAP) input signal. This mode should support a 32-bit counter and allow the edge configuration of the CAP1, CAP2, CAP3 and CAP4 capture submodules. When the edge of the input signal is triggered, the capture unit will save the current counter value. For example, if CAP1 and CAP2 are configured as rising edge triggers, once the capture is completed, the difference between CAP2 and CAP1 will represent the number of system clock cycles within the input signal period.

[0066] In one embodiment, the MCU-CPU read mode: fast assembly instructions must be used for data stacking to achieve a uniform cycle and maximize the speed of each reading of the pulse width modulation (PWM) level. When determining the duration of the read level, the capacity of the data random access memory (RAM), the multiple relationship between the signal frequency and the system clock frequency, and ensuring that the number of cycles for reading the PWM level is not less than 3 cycles should be considered. Its clock circuit is as follows Figure 4 shown.

[0067] In one embodiment, referring to Figure 2 As shown, a method for the host computer to automatically obtain the MCU clock frequency is as follows:

[0068] 1. Initial connection and program download:

[0069] - The host computer establishes a connection with the target chip.

[0070] - Download the APP1 program to the target chip and set the initial multiplication factor (assuming it is the lowest value).

[0071] 2. APP1 program evaluation and adjustment:

[0072] - The host computer starts the APP1 program and waits for a while after running to collect evaluation data.

[0073] - If the test results show that APP1 is invalid, the multiplier factor will be automatically adjusted (minus 2) and the program will be prepared to be downloaded again.

[0074] - If the multiplier adjustment is effective, proceed to the next step; otherwise, continue adjusting the multiplier until the preset maximum value is reached or an effective setting is found.

[0075] 3. APP2 program preparation and operation:

[0076] - Download the APP2 program to the target chip using the optimized multiplier factor.

[0077] - Configure the optimal multiplier factor used by the APP2 program.

[0078] - Run the APP2 program and disconnect the JTAG connection after the program runs stably.

[0079] 4. PWM frequency capture preparation:

[0080] - After disconnecting the JTAG connection, configure the JTAG_TDI pin to generate a fixed known PWM frequency through other means (such as emulator settings).

[0081] - Ensure that the APP2 system has been initialized and is ready to capture the PWM frequency.

[0082] 5. CAP capture mode configuration and waiting:

[0083] - After the APP2 program recognizes the capture mode variable, it configures the CAP and GPIO registers to enable the CAP capture function.

[0084] - Wait for CAP capture to complete to ensure that the frequency information of the PWM signal has been correctly captured.

[0085] 6. GPIO register reading and data processing:

[0086] - Configure the GPIO registers to continuously read the level status of the PWM pin and save the data into the data RAM.

[0087] - Prepare software algorithms to process the data to resolve the clock frequency.

[0088] 7. Clock frequency analysis and storage:

[0089] - Use software Algorithm 1 and Algorithm 2 to analyze the clock frequency and verify the accuracy and consistency of the results.

[0090] - Save the parsed clock frequency data to a specific data RAM location and set the program end flag.

[0091] 8. Host computer data acquisition:

[0092] - The host computer re-establishes the JTAG connection after the specified time and accesses the target chip.

[0093] - Read and save clock frequency data obtained from data RAM for subsequent analysis or processing.

[0094] In this embodiment, the parameters used in the algorithm are described as follows:

[0095] N cap : CAP captures the difference between the CAP module counter and one PWM cycle, CAP capture value.

[0096] F pwm : The simulator provides a known fixed frequency.

[0097] F clkin : MCU input clock frequency, unknown value.

[0098] A pll_mult : PLL multiplication factor, known value.

[0099] T mov : The number of cycles required to assemble the move instruction, a known value.

[0100] The clock frequency algorithm 1 formula of the MCU-CAP mode in this embodiment is:

[0101] Requirements: The MCU has an integrated CAP, and the JTAG-related pins can be configured as input pins of the CAP module.

[0102] F sysclk = F clkin * A pll_mult / / Formula 1 CAP counter input frequency is configured as system frequency

[0103] The PWM cycle value captured by CAP is equal to the known PWM cycle value to obtain the following formula

[0104] (1 / F sysclk ) * N cap =1 / F pwm / / Formula 2

[0105] Substituting formula 1 into formula 2 yields

[0106] Ncap / (F clkin * A pll_mult ) = 1 / F pwm Get F clkin = N cap * F pwm / A pll_mult .

[0107] MCU-CPU mode clock frequency algorithm 2 formula:

[0108] Requirements: The number of PWM level cycles to be read must be >= 3. It is recommended to use assembly move instructions. The original address remains unchanged and the destination address is incremented. This is done by stacking several repeated instructions.

[0109] Sequentially read the PWM pin level to the data RAM, compare the data in the RAM, find the RAM location where 1 changes to 0 or 0 changes to 1 and save its address A n

[0110] Continue to read the data RAM space value to compare and find the 0 to 1 or 1 to 0 data RAM location and save its address A n+1

[0111] Continue to read the data RAM space value to compare and find the 1 to 0 or 0 to 1 data RAM location and save its address A n+2

[0112] The PWM cycle is the difference between two consecutive changes N read_sysclk = A n+2 -A n .

[0113] F sysclk = F clkin * A pll_mult / / Formula 3

[0114] The PWM cycle value captured by the CPU is equal to the known PWM cycle value and the following formula is obtained

[0115] (1 / F sysclk ) * N read_sysclk * T mov =1 / F pwm / / Formula 4

[0116] Substituting formula 3 into formula 4 yields

[0117] N read_sysclk * T mov / (F clkin * A pll_mult ) = 1 / F pwm Get F clkin = Fpwm * N read_sysclk * T mov / A pll_mult .

[0118] In one embodiment, the CPU mode is selected to automatically identify the external input clock frequency by testing the AVP32F069 and ADP32F035B finished product Flash.

[0119] F pwm : The emulator JTAG_TDI provides PWM frequency 100KHz.

[0120] A pll_mult : The PLL multiplication factor is 10 through the APP1 program, the specification CLKINMAX <= 30MHz, and the maximum main frequency < 120MHz. The APP1 program is a general algorithm for CRC32 verification of BOOTROM, which will not be shown here.

[0121] F clkin : The actual input frequency is 10MHz. The frequency identified by this method is in the range of 9.9~10.1MHz.

[0122] CPU data migration program such as Figure 5 As shown: The clock frequency software algorithm program is as follows Figure 6 shown.

[0123] In this embodiment, the host computer downloads the first program APP1 to the MCU on-chip RAM through the emulator JTAG interface, runs this program to evaluate an optimal frequency multiplication factor, and then downloads the second program APP2 to the MCU on-chip RAM. The host computer issues an instruction to make the emulator exit the JTAG debugging mode and the TDI pin of the JTAG interface provides a known fixed PWM frequency. The APP2 program reads the PWM level state through the MCU-CPU and saves it to the data RAM or enables the MCU on-chip CAP module to capture PWM. The clock frequency is analyzed through the MCU's software algorithm, and the host computer then enables the JTAG mode to read the MCU-specified data RAM clock frequency result.

[0124] In one embodiment, referring to Figure 7 As shown, a system suitable for a host computer to automatically obtain the MCU clock frequency is provided, including

[0125] The host computer is used to run on the PC, simulate debugging and send command programs;

[0126] Emulator, used to implement USB to JTAG protocol and generate PWM frequency;

[0127] JTAG port, a communication protocol interface used to implement simulation debugging;

[0128] Core CPU, used to implement system control and algorithm functions;

[0129] Program RAM, used to provide running space for frequency multiplication coefficient evaluation program and capture analysis program;

[0130] Data RAM, used to provide IO capture level data cache space;

[0131] GPIO, used to implement IO multiplexing, input and output, and IO status cache functions;

[0132] CAP, used to realize edge-triggered automatic capture of PWM cycle and pulse width function;

[0133] PLL is used to multiply the input clock frequency and provide system and peripheral clocks.

[0134] In summary, the present invention has strong versatility, does not require additional hardware support, and is simple to implement. The Flash program burning software automatically obtains the clock frequency, reducing the abnormal frequency setting caused by human factors. By automatically obtaining the clock, the host computer communication waiting time is more accurate and the status flag polling is reduced. System clock diagnosis can be achieved.

[0135] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for automatically obtaining the MCU clock frequency by a host computer, characterized in that: The following steps are involved: The host computer is connected to the target chip, downloads the frequency multiplication coefficient evaluation program to the target chip, and configures the minimum frequency multiplication coefficient; the frequency multiplication coefficient evaluation program is used for data migration and logic operation in the target chip and generates a running end flag, and the operation result and the end flag are saved to the specified data RAM space; Run the frequency multiplication coefficient evaluation program and perform the evaluation. The host computer obtains the evaluation results and determines whether the program passes. If it passes, it proceeds to the next step. If it fails, it adjusts the frequency multiplication coefficient. After the host computer obtains the evaluation results, if it fails, it subtracts 2 from the frequency multiplication coefficient and uses it as the frequency multiplication coefficient of the capture and analysis program. Download the capture and analysis program to the target chip and configure the frequency multiplication factor. At the same time, configure the simulator JTAG_TDI pin to generate a fixed known PWM frequency. Initialize the capture parsing program, identify the capture mode variables, configure the CAP and GPIO registers, and continuously read the PWM pin level status to the data RAM; Analyze the clock frequency, generate the program end flag and save it to the data RAM, connect the host computer to the target chip, obtain the clock frequency and save it.

2. A method for automatically obtaining the MCU clock frequency by a host computer according to claim 1, characterized in that: In the method, when the host computer is connected to the target chip, based on the MCU-JTAG simulation debugging interface and using a synchronization protocol, the host computer establishes communication with the target chip through a USB connection emulator to achieve reading and writing of MCU registers and RAM.

3. A method for automatically obtaining the MCU clock frequency by a host computer according to claim 1, characterized in that: In the method, the lowest multiplication coefficient is first configured for evaluation, and the multiplication coefficient is increased in each test, and the cycle is repeated in sequence. When the calculation result is abnormal or the end flag is not generated, indicating that the multiplication coefficient has exceeded the highest main frequency of the MCU, the host computer reads the configuration value of the PLL multiplication register.

4. A method for automatically obtaining the MCU clock frequency by a host computer according to claim 1, characterized in that: In the method, the host computer downloads the parsing program, sets the target chip program entry address, issues a running instruction, configures the TMS and TCK pins of the JTAG port to a low level, and the rest to a high impedance state, maintaining an idle state.

5. A method for automatically obtaining the MCU clock frequency by a host computer according to claim 1, characterized in that: In the method, the capture and analysis program is initialized, the host computer commands the emulator to configure the JTAG port TMS, TCK to a low level, and TDI generates a fixed PWM frequency as a reference time base for MCU clock frequency calculation, and the frequency relationship is set by a clock frequency analysis algorithm.

6. A method for automatically obtaining the MCU clock frequency by a host computer according to claim 1, characterized in that: In the method, the host computer reads the MCU program end flag and the clock frequency value. If the end flag is invalid, it means that the clock frequency analysis is invalid. If the end flag is valid, the clock frequency is read and saved.

7. A method for automatically obtaining the MCU clock frequency by a host computer according to claim 1, characterized in that: In the method, the number of PWM level cycles read is ≥3.

8. A system for automatically acquiring the MCU clock frequency by a host computer, the system being used to implement the method for automatically acquiring the MCU clock frequency by a host computer as claimed in any one of claims 1 to 7, characterized in that: include The host computer is used to run on the PC, simulate debugging and send command programs; Emulator, used to implement USB to JTAG protocol and generate PWM frequency; JTAG port, a communication protocol interface used to implement simulation debugging; Core CPU, used to implement system control and algorithm functions; Program RAM, used to provide running space for frequency multiplication coefficient evaluation program and capture analysis program; Data RAM, used to provide IO capture level data cache space; GPIO, used to implement IO multiplexing, input and output, and IO status cache functions; CAP, used to realize edge-triggered automatic capture of PWM cycle and pulse width function; PLL is used to multiply the input clock frequency and provide system and peripheral clocks.

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