Data sorting module, processor, equipment and method

Abstract

The invention discloses a data sorting module, a processor, equipment and a method, and relates to the technical field of chips. The data sorting module comprises a vector execution unit; the first comparator is used for acquiring a first vector sorting result of the nth vector sorting stage under the condition that the first comparison signal is received; performing vector comparison in the (n + 1) th vector sorting stage based on the first vector sorting result, wherein n is a positive integer; the first comparator is also used for obtaining a second vector sorting result of the mth vector sorting stage under the condition that the second comparison signal is received; based on the second vector sorting result, vector comparison of the (m + 1) th vector sorting stage is executed, m is a positive integer, and n is different from m. According to the scheme, hardware resources are saved, and the usable area of a processor chip is reduced.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of chip technology, and in particular to a data sorting module, processor, device, and method. Background Art

[0002] Comparing vector values ​​of data is a basic data processing operation in the field of artificial intelligence. Therefore, in AI (Artificial Intelligence) processors, data sorting circuits are often integrated to perform the above sorting operations.

[0003] In the related art, since a single comparator is used to perform numerical comparison between two vector data, for the sorting process of multiple data, multiple vector comparators are often designed in the AI ​​processor to form a sorting network, wherein the multiple vector comparators are respectively used to perform vector comparisons at different sorting stages.

[0004] However, the above solution requires stacking corresponding hardware computing resources and designing corresponding hardware winding methods in the processor chip in the process of sorting multiple data, resulting in waste of hardware resources and expansion of chip volume. Summary of the invention

[0005] The embodiment of the present application provides a data sorting module, processor, device and method. The technical solution provided by the embodiment of the present application is as follows:

[0006] According to one aspect of an embodiment of the present application, a data sorting module applied to a processor is provided, wherein the data sorting module includes a vector execution unit, wherein the vector execution unit includes a plurality of vector comparators, wherein the plurality of vector comparators are distributed in a plurality of vector sorting stages to perform vector comparison, wherein the plurality of vector comparators include a first comparator;

[0007] The first comparator is configured to obtain a first vector sorting result of the nth vector sorting stage upon receiving the first comparison signal; and perform vector comparison of the n+1th vector sorting stage based on the first vector sorting result, where n is a positive integer;

[0008] The first comparator is further used to obtain a second vector sorting result of the mth vector sorting stage when a second comparison signal is received; and perform vector comparison of the m+1th vector sorting stage based on the second vector sorting result, where m is a positive integer and n is different from m.

[0009] According to one aspect of an embodiment of the present application, a processor is provided, wherein the processor includes the data sorting module as described above.

[0010] According to one aspect of an embodiment of the present application, a computer device is provided, wherein the computer device includes a processor, and the processor includes the data sorting module as described above.

[0011] According to one aspect of an embodiment of the present application, a data type conversion method based on a data sorting module is provided, wherein the data sorting module comprises: a vector execution unit, wherein the vector execution unit comprises a plurality of vector comparators, wherein the plurality of vector comparators are distributed in a plurality of vector sorting stages to perform vector comparison, wherein the plurality of vector comparators comprises a first comparator; the method comprises:

[0012] When the first comparison signal is received, obtaining a first vector sorting result of the nth vector sorting stage;

[0013] Performing vector comparison of the n+1th vector sorting stage based on the first vector sorting result, where n is a positive integer;

[0014] When the second comparison signal is received, obtaining a second vector sorting result of the mth vector sorting stage;

[0015] A vector comparison of the m+1th vector sorting stage is performed based on the second vector sorting result, where m is a positive integer, and n is different from m.

[0016] The technical solution provided by the embodiments of the present application includes at least the following beneficial effects:

[0017] Different comparison signals are received by the first comparator, and the vector sorting results of the corresponding vector sorting stage are obtained according to the comparison signals, so as to perform vector comparison of the next sorting stage of the vector sorting stage. That is, when the distribution of vector comparators used to perform vector comparison in at least two sorting stages is consistent, different comparison signals are used to reuse the same comparator in different sorting stages to perform the vector comparison process of the sorting stage corresponding to the comparison signal, thereby reducing the number of comparators used and simplifying the winding method for the comparators in the final sorting network, saving hardware resources and reducing the usage area of ​​the processor chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a schematic diagram of the hardware structure of a processor for data sorting provided by an embodiment of the present application;

[0019] Figure 2 is a schematic diagram of a data sorting module applied to a processor provided by an embodiment of the present application;

[0020] Figure 3 is a schematic diagram of a data sorting module provided by an embodiment of the present application;

[0021] Figure 4 is a schematic diagram of a sorting circuit provided by an embodiment of the present application;

[0022] Figure 5 is a flow chart of a data sorting method based on a data sorting module provided by an embodiment of the present application;

[0023] Figure 6 is a schematic diagram of a comparator input signal and an output signal provided by an embodiment of the present application;

[0024] Figure 7 This is a schematic diagram of comparator input signals and output signals provided in one embodiment of the present application. DETAILED DESCRIPTION

[0025] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0026] Artificial intelligence is the theory, method, technology and application system that uses digital computers or machines controlled by digital computers to simulate, extend and expand human intelligence, perceive the environment, acquire knowledge and use knowledge to obtain the best results. In other words, artificial intelligence is a comprehensive technology in computer science that attempts to understand the essence of intelligence and produce a new intelligent machine that can respond in a similar way to human intelligence. Artificial intelligence is to study the design principles and implementation methods of various intelligent machines so that machines have the functions of perception, reasoning and decision-making.

[0027] Artificial intelligence technology is a comprehensive discipline that covers a wide range of fields, including both hardware-level and software-level technologies. Basic artificial intelligence technologies generally include sensors, dedicated artificial intelligence chips, cloud computing, distributed storage, big data processing technology, pre-trained model technology, operation / interaction systems, mechatronics, etc. Among them, pre-trained models are also called large models and basic models. After fine-tuning, they can be widely used in downstream tasks in various major directions of artificial intelligence. Artificial intelligence software technology mainly includes computer vision technology, speech processing technology, natural language processing technology, and machine learning / deep learning.

[0028] With the research and advancement of artificial intelligence technology, artificial intelligence technology has been studied and applied in many fields, such as common smart homes, smart wearable devices, virtual assistants, smart speakers, smart marketing, driverless cars, autonomous driving, drones, digital twins, virtual humans, robots, artificial intelligence generated content (AI Generated Content, AIGC), conversational interaction, smart medical care, smart customer service, game AI, etc. It is believed that with the development of technology, artificial intelligence technology will be applied in more fields and play an increasingly important role.

[0029] The technical solution of this application mainly relates to the development and design of AI processors in artificial intelligence technology, and mainly to data sorting modules applied to processors.

[0030] The operation of vector comparison on vector data is a basic data processing operation in the field of artificial intelligence. Therefore, in AI processor chips with vector computing engines, multiple vector comparators are often integrated to build a sorting network. After obtaining multiple vector data, the vector data is input into the sorting network, and multiple comparators distributed in different vector sorting stages are used to perform vector comparisons on multiple vector data at multiple vector sorting stages. Finally, multiple vector data that meet the sorting requirements are input into the sorting network.

[0031] In the related art, the above-mentioned method of laying out multiple vector comparators in the AI ​​processor chip will result in occupying too many hardware resources on the chip, increasing the resource occupation pressure of the chip.

[0032] The present application optimizes the sharing of circuit resources by using different comparison signals and the same comparator to realize vector data comparison in different sorting stages, thereby optimizing the resources of the vector computing engine, reducing the number of vector comparators on the chip, alleviating the resource occupation pressure of the chip, and reducing the complexity of layout and wiring on the chip, thereby improving the competitiveness of chip products.

[0033] Please refer to Figure 1 , which shows a hardware structure diagram of a processor for data sorting provided by an embodiment of the present application. The processor includes an instruction decoder, a data sorting module, a data load storage execution unit (Load Store Unit) and a memory (Buffer).

[0034] The instruction parser is used to parse the execution instruction received by the processor. In the embodiment of the present application, the instruction parser is used to parse the comparison signal (i.e., the comparison instruction) used to indicate the sorting stage. The memory is used to store the vector data to be sorted, and the data load storage execution unit is used to obtain the vector data to be sorted from the memory, and return the vector data after the data sorting process is completed to the memory.

[0035] The data sorting module is used to obtain the vector sorting result obtained in the corresponding sorting stage according to the comparison instruction parsed by the instruction parser, and perform the vector comparison of the next sorting stage to obtain the vector sorting result of the next sorting stage. In some embodiments, the data sorting module can sort the multiple vector data in ascending order (that is, sort them in a surprising way according to the size of the vector from small to large), or the data sorting module can also sort the multiple vector data in descending order (that is, sort them in a way according to the size of the vector from large to small). Please refer to the following embodiments for the specific structure of the data sorting module, which will not be repeated here.

[0036] Based on the above hardware structure design, data sorting of multiple vector data can be achieved.

[0037] The processor may include one or more processing cores, such as a 4-core processor, an 8-core processor, and the like. The processor may be implemented in at least one of the following hardware forms: DSP (Digital Signal Processing), FPGA (Field Programmable Gate Array), and PLA (Programmable Logic Array). The processor may also include a main processor and a coprocessor. The main processor is a processor for processing data in an awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in a standby state. In some embodiments, the processor may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor may also include an AI processor for processing computing operations related to machine learning.

[0038] The memory may include one or more computer-readable storage media, which may be non-transitory. The memory may also include high-speed random access memory, and non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In some embodiments, the non-transitory computer-readable storage medium in the memory is used to store a computer program, which is configured to be executed by one or more processors to implement the data type conversion method based on the above-mentioned data sorting module.

[0039] Those skilled in the art will understand that Figure 1The structure shown in the figure does not constitute a limitation on the computer device, and may include more or less components than shown in the figure, or combine some components, or adopt a different component arrangement.

[0040] Please refer to Figure 2 , which shows a schematic diagram of a data sorting module applied to a processor provided by an exemplary embodiment of the present application. The data sorting module 20 can be a unit of a pure hardware structure, which can be set on the chip of the processor. The data sorting module 20 includes a vector execution unit 21, and the vector execution unit 21 includes a plurality of vector comparators, and the plurality of vector comparators are distributed in a plurality of vector sorting stages to perform vector comparison, wherein the plurality of vector comparators include a first comparator.

[0041] In some embodiments, the vector execution unit 21 is a unit module in the data sorting module 20 for processing multiple vector data, and a vector sorting circuit is integrated in the vector execution unit 21 to implement comparison between vector data. The vector sorting circuit includes multiple vector comparators, which are distributed in multiple vector sorting execution stages, so that in a specified vector sorting stage, the vector comparator corresponding to the sorting stage is used to perform vector comparison on the vector data.

[0042] In some embodiments, when the vector execution unit 21 inputs multiple vector data, it needs to perform vector comparison in sequence through multiple different vector sorting stages, and finally output the sorting result of the last vector sorting stage as the final sorting result of the multiple vector data.

[0043] In some embodiments, multiple vector data are input into a vector execution unit in a specified arrangement order for vector sorting, and finally, multiple vector data are output in sequence in an order corresponding to the sorting results. In the process of vector sorting, vector comparison is performed on vector data at two specified positions through a vector comparator, so as to move the arrangement position corresponding to the vector data according to the sorting requirements corresponding to the comparator and the comparison results of the two vector data.

[0044] Schematically, in a single vector sorting stage, a vector comparison is performed on at least two vector data at a specified position in a plurality of vector data through a vector comparator in the vector sorting stage. For example: input vector data a, vector data b and vector data c are respectively input into the vector execution unit 21 in the first, second and third positions, and the vector execution unit 21 includes two vector sorting stages, wherein comparator 1 is used to perform vector comparison in the first vector sorting stage, wherein comparator 1 compares the vector data at the first position with the vector data at the second position, and places the vector data with the larger comparison result in the second position, that is, in the current first vector sorting stage, comparator 1 is used to perform vector comparison on vector data a and vector data b, and if vector data a is larger than vector data b, vector data a is moved to the second position, and vector data b is moved to the first place; in the second vector sorting stage, comparator 2 is used to perform vector comparison, wherein comparator 2 performs vector comparison on the vector data at the second place and the vector data at the third place according to the sorting result in the first vector sorting stage, and moves the vector data with the larger comparison result to the third place, that is, currently according to the sorting result in the first vector sorting stage, vector comparison is performed on vector data a and vector data c through comparator 2, if vector data a is larger than vector data c, then vector data a is moved to the third place, and vector data c is moved to the second place, and finally, vector data b is output at the first place, vector data c is output at the second place, and vector data a is output at the third place.

[0045] Optionally, the vector data includes at least one of the data types of single-precision floating point (Full Precise Float Point, FP32), half-precision floating point (Half Precision Floating Point, FP16), and signed 32-bit integer (32bit integer, int32).

[0046] Optionally, the comparison modes corresponding to the multiple comparators in the vector execution unit 21 are the same or different, which is not limited.

[0047] Optionally, the number of comparators in each vector execution stage is the same or different, which is not limited.

[0048] Next, the first comparator is described in detail. .

[0049] First comparator

[0050] The first comparator is used to obtain the first vector sorting result of the nth vector sorting stage when receiving the first comparison signal; perform vector comparison of the n+1th vector sorting stage based on the first vector sorting result, where n is a positive integer; the first comparator is also used to obtain the second vector sorting result of the mth vector sorting stage when receiving the second comparison signal; perform vector comparison of the m+1th vector sorting stage based on the second vector sorting result, where m is a positive integer and n is different from m.

[0051] Schematically, a vector comparator is a component for comparing at least two vector data. It plays an important role in many applications, including artificial intelligence, graphics processing, numerical computing, etc.

[0052] In some embodiments, the function of the vector comparator is to compare the corresponding elements in the two vectors, and output a corresponding flag or signal according to the comparison result. The vector comparator can be used to perform various comparison operations, including at least one of the multiple operation types such as equal, greater than, less than, and not equal. For example: comparator 1 compares input data a and data b, and when the element in data a is greater than the element in data b, the output signal value is "1", when the element in data a is less than the element in data b, the output signal value is "0", and when the element in data a is equal to the element in data b, the output signal value is "2".

[0053] In some embodiments, when multiple vector comparators in the vector execution unit 21 are distributed in multiple different vector sorting stages, a sorting circuit is formed according to the arrangement of the multiple vector comparators, wherein in each vector sorting stage, a corresponding sorting subcircuit is formed according to the arrangement of the corresponding vector comparators. Therefore, among the multiple sorting subcircuits, there are at least two sorting subcircuits with the same arrangement of comparators. Therefore, for the sorting subcircuits with the same arrangement, the sharing of circuit resources can be achieved, that is, only one sorting subcircuit is arranged, and by receiving different comparison signals, the sorting subcircuit is driven to complete the vector comparison in the vector sorting stage corresponding to the comparison signal. For example: multiple vector sorting stages include stage a and stage b, wherein both stage a and stage b can use the first comparator for vector comparison, therefore, the first comparison signal is received by the first comparator, the vector sorting result obtained in the previous stage of stage a is obtained, and the vector comparison corresponding to stage a is performed according to the vector sorting result; the second comparison signal is received by the first comparator, the vector sorting result obtained in the previous stage of stage b is obtained, and the vector comparison corresponding to stage b is performed according to the vector sorting result.

[0054] Optionally, the first comparator performs ascending processing on the input vector data during the vector comparison, or performs descending processing on the input vector data.

[0055] For example: when the first comparison signal is stg2_en=1, the output signal (stg1_res) of stage 1 (i.e. stage_1) is selected as the vector sorting result corresponding to stage 1, and the vector comparison of stage 2 is performed through the first comparator; when the second comparison signal is stge2_en=0, the output signal (stg4_res) of stage 4 (i.e. stage_4) is selected as the vector sorting result corresponding to stage 4, and the vector comparison of stage 5 is performed through the first comparator. The logic of stage determination is as follows:

[0056] Share_sort_din[3:0]=stg2_en? stg1_res[3:0]:stg4_res

[0057] Among them, din[3:0] represents the input vector data, that is, the corresponding vector sorting result is selected according to the value of the comparison signal stg2_en. When stg2_en=1, stg1_res is selected, and if stg2_en=0, stg4_res is selected, where "?" is the selection symbol. When the value to the left of "?" is 1, the data before the ":" symbol is selected, and when the value to the left of "?" is 0, the data after the ":" symbol is selected.

[0058] In this embodiment, din[3:0] includes four vector data, namely din[0], din[1], din[2] and din[3], where these four data are all 32-bit unsigned integer data.

[0059] In some embodiments, when a first comparison signal and a first sorting signal are received, a first vector sorting result of the nth vector sorting stage is obtained, and the first sorting signal corresponds to a first sorting requirement; based on the first vector sorting result and the first sorting requirement, a vector comparison of the n+1th vector sorting stage is performed; when a second comparison signal and a second sorting signal are received, a second vector sorting result of the mth vector sorting stage is obtained, and the second sorting signal corresponds to the second sorting requirement; based on the second vector sorting result and the second sorting requirement, a vector comparison of the m+1th vector sorting stage is performed.

[0060] In schematic form, different sorting signals are provided for different sorting requirements. For example, for ascending processing, the sorting signal is set to "11", wherein ascending processing refers to arranging at least two vector data in the order of vector value from small to large through a comparator; for descending processing, the sorting signal is set to "10", wherein descending processing refers to sorting at least two vector data in the order of vector value from large to small through a comparator.

[0061] In this embodiment, after the first comparator receives the first sorting signal and the first comparison signal, the first vector sorting result of the nth vector sorting stage is obtained according to the first comparison signal, and the vector comparison of the n+1th vector sorting stage is performed on the first vector sorting result according to the first sorting requirement corresponding to the first sorting signal. In one example, when the comparison signal stg2_en=1 and the sorting signal valu_idx=0, the first vector sorting result of the nth vector sorting stage is obtained, and the vector data in the first vector sorting result is processed in ascending order in the n+1th vector sorting stage; when the comparison signal stg2_en=1 and the sorting signal valu_idx=1, the first vector sorting result of the nth vector sorting stage is obtained, and the vector data in the first vector sorting result is processed in descending order in the n+1th vector sorting stage.

[0062] In this embodiment, after the first comparator receives the second sorting signal and the second comparison signal, the second vector sorting result of the mth vector sorting stage is obtained according to the second comparison signal, and, according to the second sorting requirement corresponding to the second sorting signal, the vector comparison of the m+1th vector sorting stage is performed on the second vector sorting result. In one example, when the comparison signal stg2_en=0 and the sorting signal valu_idx=0, the second vector sorting result of the mth vector sorting stage is obtained, and the vector data in the second vector sorting result is processed in ascending order in the m+1th vector sorting stage; when the comparison signal stg2_en=0 and the sorting signal valu_idx=1, the second vector sorting result of the mth vector sorting stage is obtained, and the vector data in the second vector sorting result is processed in descending order in the m+1th vector sorting stage.

[0063] Optionally, the first sorting requirement and the second sorting requirement are the same or different. Therefore, when the first sorting requirement and the second sorting requirement are the same, the first sorting signal and the second sorting signal are the same; when the first sorting requirement and the second sorting requirement are different, the first sorting signal and the second sorting signal are different.

[0064] In some embodiments, in response to the first vector sorting result of the n+1th vector sorting stage meeting the stage completion condition, the first vector sorting result of the n+1th vector sorting stage is output as the output result of the vector execution unit; or, in response to the first vector sorting result of the n+1th vector sorting stage meeting the stage continuation condition, vector comparison of the n+2th vector sorting stage is performed based on the first vector sorting result of the n+1th vector sorting stage.

[0065] Illustratively, if the arrangement order of multiple vector data in the first vector sorting result of the n+1th vector sorting stage meets the preset arrangement requirement, it means that the vector sorting result corresponding to the current stage has met the stage completion condition, and the first vector sorting result of the n+1th vector sorting stage is used as the sorting result of the final vector execution unit 21. If the arrangement order of multiple vector data in the first vector sorting result of the n+1th vector sorting stage does not meet the arrangement requirement, it means that the vector data arrangement needs to be continued, so the vector comparison process of the n+2th vector sorting stage is executed through the first comparator.

[0066] In some embodiments, the vector execution unit 21 also includes a register, which is used to receive the first vector sorting result of the nth vector sorting stage; after a delay of a preset clock cycle, the first vector sorting result is sent to the first comparator; the first comparator is also used to receive the first vector sorting result of the nth vector sorting stage sent by the register.

[0067] Schematically, between two adjacent vector sorting stages, the sorting of the previous vector sorting stage needs to be beat processed through a register, and then transmitted to the next vector sorting stage for vector comparison, wherein the beat processing refers to saving the signal corresponding to the data sorting result obtained in the previous vector sorting stage into the register, and at the same time, there is a certain delay in the saving process.

[0068] Indicatively, the clock cycle is pre-set, and when the nth vector sorting stage is executed and the first vector sorting result is output, it is stored in a register, and after being delayed by at least one clock cycle, it is sent to the first comparator through the register to perform vector comparison of the n+1th vector sorting stage.

[0069] Among them, delaying one clock cycle is called "hitting one beat", and delaying two clock cycles is called "hitting two beats".

[0070] In summary, the data sorting module provided in the embodiment of the present application receives different comparison signals through a first comparator, obtains the vector sorting result of the corresponding vector sorting stage according to the comparison signal, and thus performs the vector comparison of the next sorting stage of the vector sorting stage. That is, when the distribution of vector comparators used to perform vector comparison in at least two sorting stages is consistent, different comparison signals are used to implement the vector comparison process of the sorting stage corresponding to the comparison signal by reusing the same comparator in different sorting stages, thereby reducing the number of comparators used and simplifying the winding method for the comparators in the final sorting network, saving hardware resources and reducing the usage area of ​​the processor chip.

[0071] In some embodiments, the vector execution unit is further divided into two vector execution sub-units, for example, see Figure 3 , which shows a schematic diagram of a data sorting module provided by an exemplary embodiment of the present application, such as Figure 3 As shown, a vector execution unit 300 is currently displayed, wherein the vector execution unit 300 includes a first vector execution subunit 310 and a second vector execution subunit 320, the first vector execution subunit includes a first comparator, and the second vector execution subunit includes a second comparator.

[0072] Schematically, the vector execution unit 300 is obtained by instantiating a specified module in the AI ​​processor chip, wherein instantiation refers to declaring a module instance to be used in a target module and connecting the port corresponding to the module instance with the port in the target module, thereby realizing the reuse and combination of the target module.

[0073] In some embodiments, during the design of the AI ​​processor chip, the modules in the chip are integrated into the full chip netlist in a separate hardening (Harden) manner, that is, each Harden is implemented as a regional layout and routing in the chip. Each Harden itself has a corresponding resource upper limit requirement, which is used to indicate the maximum amount of data that the Harden can transmit.

[0074] In this embodiment, the vector execution unit 300 is split into two vector execution sub-units according to the resource upper limit requirement of Harden, including a first vector execution sub-unit 310 and a second vector execution sub-unit 320. In the splitting process, the first vector execution sub-unit 310 and the second vector execution sub-unit 320 are obtained by instantiating the same designated module in different ways.

[0075] Illustratively, the first vector execution subunit 310 and the second vector execution subunit 320 respectively perform vector sorting of different vector data, and the numerical range of the vector data sorted by the first vector execution subunit 310 is different from the numerical range of the vector data sorted by the second vector execution subunit 320.

[0076] Optionally, the first vector data is greater than the second vector data, or the first vector data is less than the second vector data. When the first vector execution subunit 310 processes a plurality of first vector data and the second vector execution subunit 320 processes a plurality of second vector data, the plurality of first vector data are all greater than the plurality of second vector data, or the plurality of first vector data are all less than the plurality of second vector data, or at least one first vector data among the plurality of first vector data is less than the second vector data, or at least one first vector data among the plurality of first vector data is greater than the first vector data.

[0077] In some embodiments, a first vector execution subunit 310 is provided with a plurality of comparators corresponding to a plurality of different vector sorting stages, wherein the first comparator is used to perform vector comparison on the first vector data in a specified vector sorting stage, and a second vector execution subunit 320 is provided with a plurality of comparators corresponding to a plurality of different vector sorting stages, wherein the second comparator is used to perform vector comparison on the second vector data.

[0078] The first comparator and the second comparator are described in detail below.

[0079] First comparator

[0080] In some embodiments, when a first comparison signal is received, a first sorting sub-result of the first vector data in the nth vector sorting stage is obtained; based on the first sorting sub-result, a vector comparison of the first vector data in the n+1th vector sorting stage is performed, where n is a positive integer; when a second comparison signal is received, a second sorting sub-result of the first vector data in the mth vector sorting stage is obtained; based on the second sorting sub-result, a vector comparison of the first vector data in the m+1th vector sorting stage is performed, where the first vector data and the second vector data correspond to different numerical ranges, and m is a positive integer.

[0081] Optionally, the first comparator performs ascending processing on the input vector data during the vector comparison, or performs descending processing on the input vector data.

[0082] In some embodiments, when receiving the first comparison signal, the first comparator obtains a first sorting sub-result of the first vector data in the nth vector sorting stage, and performs vector sorting in the (n+1)th vector sorting stage based on the first sorting sub-result.

[0083] The first comparator performs the vector sorting process independently in the first vector execution sub-unit 310 .

[0084] In this embodiment, the first comparator receives different comparison signals and executes the vector sorting process in the vector sorting phase corresponding to the comparison signals.

[0085] Second comparator

[0086] In some embodiments, when a first comparison signal is received, a third sorting sub-result of the second vector data in the nth vector sorting stage is obtained; based on the third sorting sub-result, a vector comparison of the second vector data in the n+1th vector sorting stage is performed, where n is a positive integer; when a second comparison signal is received, a fourth sorting sub-result of the second vector data in the mth vector sorting stage is obtained; based on the fourth sorting sub-result, a vector comparison of the second vector data in the m+1th vector sorting stage is performed, where m is a positive integer.

[0087] Optionally, the first comparator performs ascending processing on the input vector data during the vector comparison, or performs descending processing on the input vector data.

[0088] In some embodiments, when receiving the first comparison signal, the second comparator obtains the third sorting sub-result of the second vector data in the nth vector sorting stage, and performs vector sorting in the (n+1)th vector sorting stage based on the third sorting sub-result.

[0089] The second comparator performs the vector sorting process independently in the second vector execution sub-unit 320 .

[0090] In this embodiment, the second comparator receives different comparison signals and executes the vector sorting process in the vector sorting phase corresponding to the comparison signals.

[0091] In some embodiments, the vector sorting stage is for both the first vector execution subunit 310 and the second vector execution subunit 320 , that is, in the same vector sorting stage, the first vector execution subunit 310 and the second vector execution subunit 320 perform vector sorting on the first vector data and the second vector data respectively.

[0092] In addition, there is also a data exchange process between the first vector execution subunit 310 and the second vector execution subunit 320 in the specified vector sorting phase, that is, the first vector execution subunit 310 sends the first vector data to the second vector execution subunit 320, and at the same time, the second vector execution subunit 320 sends the second vector data to the first vector execution subunit 310, so that the first vector execution subunit 310 and the second vector execution subunit 320 both perform vector sorting on the first vector data and the second vector data.

[0093] The first vector execution subunit 310 performs vector sorting on the first vector data and the second vector data through a third comparator, and the second vector execution subunit 320 performs vector sorting on the first vector data and the second vector data through a fourth comparator.

[0094] In some embodiments, the first vector execution subunit also includes a third comparator, and the second vector execution subunit also includes a fourth comparator; the third comparator is used to obtain the fifth sorting sub-result of the first vector data in the i-th vector sorting stage when a data exchange signal is received; and send the fifth sorting sub-result to the fourth comparator to perform a vector comparison between the first vector data and the second vector data in the i+1-th vector sorting stage; the fourth comparator is used to obtain the sixth sorting sub-result of the second vector data in the i-th vector sorting stage when a data exchange signal is received; and send the sixth sorting sub-result to the third comparator to perform a vector comparison between the first vector data and the second vector data in the i+1-th vector sorting stage, wherein i is a positive integer, and i is different from m and n.

[0095] Illustratively, the data exchange signal is used to instruct to exchange data between the fifth sorting sub-result of the first vector execution sub-unit 310 in the i-th vector sorting stage and the sixth sorting sub-result of the second vector execution sub-unit 320 in the i-th vector sorting stage.

[0096] In some embodiments, when the first vector execution unit 310 receives a data exchange signal, the fifth sorting sub-result corresponding to the first vector data in the i-th vector sorting stage is sent to the second vector execution unit 320, and the fourth comparator in the second vector execution sub-unit 320 performs a vector comparison between the first vector data and the second vector data in the i+1-th vector sorting stage according to the fifth sorting sub-result. When the second vector execution unit 320 receives a data exchange signal, the sixth sorting sub-result corresponding to the second vector data in the i-th vector sorting stage is sent to the first vector execution sub-unit 310, and the third comparator in the first vector execution sub-unit 310 performs a vector comparison between the first vector data and the second vector data in the i+1-th vector sorting stage according to the sixth sorting sub-result.

[0097] In this embodiment, the first vector execution subunit 310 and the second vector execution subunit 320 receive the data exchange signal at the same time. Therefore, when the third comparator receives the sixth sorting sub-result, the fourth comparator also receives the fifth sorting sub-result. Therefore, the third comparator and the fourth comparator synchronously perform vector comparison of the i+1th vector sorting stage based on the fifth sorting sub-result and the sixth sorting sub-result.

[0098] In some embodiments, the first vector data corresponds to a first numerical range, and the second vector data corresponds to a second numerical range; the third comparator is also used to perform a vector comparison on the first vector data and the second vector data in the i+1th vector sorting stage to obtain a vector comparison result; based on the first numerical range, the first target vector data is obtained from the vector comparison result, and the first target vector data is used to perform vector comparison in the i+2th vector sorting stage; the fourth comparator is also used to perform a vector comparison on the first vector data and the second vector data in the i+1th vector sorting stage to obtain a vector comparison result; based on the second numerical range, the second target vector data is obtained from the vector comparison result, and the second target vector data is used to perform vector comparison in the i+2th vector sorting stage.

[0099] Schematically, when the third comparator and the fourth comparator respectively perform the vector comparison of the i+1th vector sorting stage, the third comparator and the fourth comparator can both obtain the vector comparison result of the i+1th vector sorting stage, that is, at this time, the vector comparison results of the third comparator and the fourth comparator in the i+1th vector sorting stage are the same. At this time, since the first vector execution unit 310 is used to process the first vector data, and the first vector data corresponds to the first numerical range, therefore, after the third comparator obtains the vector comparison result, it obtains the first target vector data from the vector comparison result according to the first numerical range, and its numerical range corresponds to the first data range, so as to perform the vector comparison in the i+2th vector sorting stage according to the first target vector data; similarly, the second vector execution unit 320 is used to process the second vector data, and the second vector data corresponds to the second numerical range, therefore, after the fourth comparator obtains the vector comparison result, it obtains the second target vector data from the vector comparison result according to the second numerical range, and its numerical range corresponds to the second numerical range, so as to perform the vector comparison in the i+2th vector sorting stage according to the second target vector data.

[0100] In this embodiment, the first vector data is vector data with a lower value, and the second vector data is vector data with a higher value. Therefore, the third comparator re-obtains the vector data with a lower value from the vector comparison result as the first target vector data, wherein the first target vector data is exactly the same as the first vector data, or there is at least one vector data that is different; the fourth comparator re-obtains the vector data with a higher value from the vector comparison result as the second target vector data, wherein the second target vector data is exactly the same as the second vector data, or there is at least one vector data that is different.

[0101] For illustration, please refer to Figure 4, which shows a schematic diagram of a sorting circuit provided by an exemplary embodiment of the present application, currently showing a sorting network 400, which includes multiple vector sorting stages (for example: stage_1 represents the first vector sorting stage), from Figure 4 It can be seen that din0 to din3 input four second vector data for vector comparison in the second vector execution subunit, and din4 to din7 input four first vector data for vector comparison in the first vector execution subunit, wherein the data exchange between the first vector data and the second vector data occurs only in stage_4 (the fourth vector sorting stage), the delay of stage_4 is 2 beats (delay of 2 preset clock cycles), the delay of stage_1, stage_2, stage_5, and stage_6 is one beat each, so the total delay is 7 (delay of 7 preset clock cycles), so the use of a dual-tone sorting circuit can improve the performance of the processor.

[0102] At the same time, Figure 4 It can be found that the comparator (the arrowhead indicates a comparator, the circuit 410 includes four comparators, and the arrow is used to indicate the sorting direction) in the circuit 410 selected by stage_2 and stage_3 is the same as the comparator in the circuit 420 of stage_5 and stage_6, so the two circuits can share the same set of resources, that is, through the same set of comparators, different comparison signals are received to perform vector comparisons in different vector sorting stages. The sorting directions of the comparators in the circuit 430 of stage_2 and stage_3 and the circuit 440 of stage_5 and stage_6 are opposite (stage_2 and stage_3 are ascending, stage_5 and stage_6 are descending), but the sorting order is the same, so the two circuits can actually share the same set of resources and select ascending or descending order through external indication signals.

[0103] In some embodiments, the first vector execution subunit also includes a fifth comparator, and the second vector execution subunit also includes a sixth comparator; the fifth comparator is also used to obtain first vector data when the first data signal is received, and the first vector data corresponds to the numerical range corresponding to the first data signal; the sixth comparator is also used to obtain second vector data when the second data signal is received, and the second vector data corresponds to the numerical range corresponding to the second data signal.

[0104] Schematically, the first vector execution subunit 310 also includes a fifth comparator for performing vector comparison in the first vector sorting stage, and the second vector execution subunit 320 also includes a sixth comparator for performing vector comparison in the first vector sorting stage. Taking the fifth comparator as an example, when the first data signal is received, the fifth comparator in the first vector execution subunit 310 obtains the first vector data according to the numerical range corresponding to the first data signal. Similarly, when the second data signal is received, the sixth comparator in the second vector execution subunit 320 obtains the second vector data according to the numerical range corresponding to the second data signal.

[0105] Indicative, such as Figure 3 As shown, when the first vector execution subunit 310 receives the data signal valu_idx=1, it indicates that vector data with a lower value is obtained, so the first vector data is obtained through the fifth comparator to perform vector comparison in the first vector sorting stage; when the second vector execution subunit 320 receives the data signal valu_idx=0, it indicates that vector data with a higher value is obtained, so the second vector data is obtained through the sixth comparator to perform vector comparison in the first vector sorting stage.

[0106] In addition, if Figure 3 As shown, there is also a data exchange process between the first vector execution subunit 310 and the second vector execution subunit 320, that is, the cross-Harden process, wherein, taking the first vector execution subunit 310 sending the vector sorting result of the first vector data in the i-th vector sorting stage to the second vector execution subunit 320 as an example, when the first vector execution subunit 310 receives the data exchange signal, the vector sorting result is transmitted out of the first vector execution subunit 310, and is transmitted to the second vector execution subunit 320 after performing two beat processing (i.e., delaying two clock cycles) through the register. Similarly, the second vector execution subunit 320 transmits the vector sorting result of the second vector data in the i-th vector sorting stage out of the second vector execution subunit 310, and is transmitted to the first vector execution subunit 310 after performing two beat processing through the register. The beat processing method can alleviate the timing winding pressure between Hardens. The first vector execution subunit 310 and the second vector execution subunit 320 exchange data via a set of signals of a general vector bit width length, namely, two data exchange signals data_0to1 and data_1to0.

[0107] Among them, left_din and right_din represent the data received by the vector execution subunit, and right_dout and left_dout represent the data sent by the vector execution subunit.

[0108] In summary, the data sorting module provided in the embodiment of the present application receives different comparison signals through a first comparator, obtains the vector sorting result of the corresponding vector sorting stage according to the comparison signal, and thus performs the vector comparison of the next sorting stage of the vector sorting stage. That is, when the distribution of vector comparators used to perform vector comparison in at least two sorting stages is consistent, different comparison signals are used to implement the vector comparison process of the sorting stage corresponding to the comparison signal by reusing the same comparator in different sorting stages, thereby reducing the number of comparators used and simplifying the winding method for the comparators in the final sorting network, saving hardware resources and reducing the usage area of ​​the processor chip.

[0109] In some embodiments, for example, please refer to Figure 5 , which shows a flow chart of a data sorting method based on a data sorting module provided by an exemplary embodiment of the present application, such as Figure 5 As shown, the method includes the following steps.

[0110] Step 510: upon receiving the first comparison signal, obtaining a first vector sorting result of the nth vector sorting stage.

[0111] In some embodiments, the data sorting module includes: a vector execution unit, the vector execution unit includes a plurality of vector comparators, the plurality of vector comparators are distributed in a plurality of vector sorting stages to perform vector comparison, and the plurality of vector comparators include a first comparator.

[0112] In some embodiments, the vector execution unit is a unit module in the data sorting module for processing multiple vector data, and a vector sorting circuit is integrated in the vector execution unit to realize comparison between vector data. The vector sorting circuit includes multiple vector comparators, and the multiple vector comparators are distributed in multiple vector sorting execution stages, so that in a specified vector sorting stage, the vector comparator corresponding to the sorting stage is used to perform vector comparison on the vector data.

[0113] In some embodiments, when a vector execution unit inputs multiple vector data, it is necessary to perform vector comparison in sequence through multiple different vector sorting stages, and finally output the sorting result of the last vector sorting stage as the final sorting result of the multiple vector data.

[0114] In some embodiments, multiple vector data are input into a vector execution unit in a specified arrangement order for vector sorting, and finally, multiple vector data are output in sequence in an order corresponding to the sorting results. In the process of vector sorting, vector comparison is performed on vector data at two specified positions through a vector comparator, so as to move the arrangement position corresponding to the vector data according to the sorting requirements corresponding to the comparator and the comparison results of the two vector data.

[0115] Schematically, in a single vector sorting stage, a vector comparison is performed on at least two vector data at a specified position in a plurality of vector data through a vector comparator in the vector sorting stage. For example: input vector data a, vector data b and vector data c are respectively input into a vector execution unit according to the first, second and third positions, and the vector execution unit includes two vector sorting stages, wherein comparator 1 is used to perform vector comparison in the first vector sorting stage, wherein comparator 1 compares the vector data at the first position with the vector data at the second position, and places the vector data with a larger comparison result in the second position, that is, in the current first vector sorting stage, comparator 1 is used to perform vector comparison on vector data a and vector data b, and if vector data a is larger than vector data b, vector data a is moved to the second position, and vector data b is moved to the first position. One bit; in the second vector sorting stage, comparator 2 is used to perform vector comparison, wherein comparator 2 performs vector comparison on the vector data at the second bit and the vector data at the third bit according to the sorting result in the first vector sorting stage, and moves the vector data with the larger comparison result to the third bit, that is, currently according to the sorting result in the first vector sorting stage, vector comparison is performed on vector data a and vector data c through comparator 2, if vector data a is larger than vector data c, then vector data a is moved to the third bit, and vector data c is moved to the second bit, and finally, vector data b is output at the first bit, vector data c is output at the second bit, and vector data a is output at the third bit.

[0116] Optionally, the vector data includes at least one of the data types of single-precision floating point (Full Precise Float Point, FP32), half-precision floating point (Half Precision Floating Point, FP16), and signed 32-bit integer (32bit integer, int32).

[0117] Optionally, the comparison modes corresponding to the multiple comparators in the vector execution unit 21 are the same or different, which is not limited.

[0118] Optionally, the number of comparators in each vector execution stage is the same or different, which is not limited.

[0119] Step 520 : Perform vector comparison of the (n+1)th vector sorting stage based on the first vector sorting result.

[0120] Wherein, n is a positive integer.

[0121] The first comparator is used to obtain the first vector sorting result of the nth vector sorting stage when receiving the first comparison signal; perform vector comparison of the n+1th vector sorting stage based on the first vector sorting result, where n is a positive integer; the first comparator is also used to obtain the second vector sorting result of the mth vector sorting stage when receiving the second comparison signal; perform vector comparison of the m+1th vector sorting stage based on the second vector sorting result, where m is a positive integer and n is different from m.

[0122] Schematically, a vector comparator is a component for comparing at least two vector data. It plays an important role in many applications, including artificial intelligence, graphics processing, numerical computing, etc.

[0123] In some embodiments, the function of the vector comparator is to compare the corresponding elements in the two vectors, and output a corresponding flag or signal according to the comparison result. The vector comparator can be used to perform various comparison operations, including at least one of the multiple operation types such as equal, greater than, less than, and not equal. For example: comparator 1 compares input data a and data b, and when the element in data a is greater than the element in data b, the output signal value is "1", when the element in data a is less than the element in data b, the output signal value is "0", and when the element in data a is equal to the element in data b, the output signal value is "2".

[0124] In some embodiments, when multiple vector comparators in the vector execution unit 21 are distributed in multiple different vector sorting stages, a sorting circuit is formed according to the arrangement of the multiple vector comparators, wherein in each vector sorting stage, a corresponding sorting subcircuit is formed according to the arrangement of the corresponding vector comparators. Therefore, among the multiple sorting subcircuits, there are at least two sorting subcircuits with the same arrangement of comparators. Therefore, for the sorting subcircuits with the same arrangement, the sharing of circuit resources can be achieved, that is, only one sorting subcircuit is arranged, and by receiving different comparison signals, the sorting subcircuit is driven to complete the vector comparison in the vector sorting stage corresponding to the comparison signal. For example: multiple vector sorting stages include stage a and stage b, wherein both stage a and stage b can use the first comparator for vector comparison, therefore, the first comparison signal is received by the first comparator, the vector sorting result obtained in the previous stage of stage a is obtained, and the vector comparison corresponding to stage a is performed according to the vector sorting result; the second comparison signal is received by the first comparator, the vector sorting result obtained in the previous stage of stage b is obtained, and the vector comparison corresponding to stage b is performed according to the vector sorting result.

[0125] Optionally, the first comparator performs ascending processing on the input vector data during the vector comparison, or performs descending processing on the input vector data.

[0126] Step 530: upon receiving the second comparison signal, obtaining a second vector sorting result of the mth vector sorting stage.

[0127] Illustratively, when a second comparison signal different from the first comparison signal is received, a second vector sorting result corresponding to the second comparison signal is acquired through the first comparator.

[0128] Step 540 : Perform vector comparison of the (m+1)th vector sorting stage based on the second vector sorting result.

[0129] Here, m is a positive integer, and n is different from m.

[0130] Illustratively, after the second vector sorting result is obtained through the second comparison signal, the vector comparison of the m+1th vector sorting stage is performed according to the second vector sorting result to obtain the vector sorting result of the m+1th vector sorting stage.

[0131] In summary, the data sorting module provided in the embodiment of the present application receives different comparison signals through a first comparator, obtains the vector sorting result of the corresponding vector sorting stage according to the comparison signal, and thus performs the vector comparison of the next sorting stage of the vector sorting stage. That is, when the distribution of vector comparators used to perform vector comparison in at least two sorting stages is consistent, different comparison signals are used to implement the vector comparison process of the sorting stage corresponding to the comparison signal by reusing the same comparator in different sorting stages, thereby reducing the number of comparators used and simplifying the winding method for the comparators in the final sorting network, saving hardware resources and reducing the usage area of ​​the processor chip.

[0132] For illustration, please refer to Figure 6 , which shows a schematic diagram of a comparator input signal and an output signal provided by an exemplary embodiment of the present application, such as Figure 6 As shown, the vector comparator 600 is currently displayed, wherein the vector comparator 600 includes the following input signals and output signals:

[0133] valu_idx: This module processes vector data of different numerical ranges. valu_idx = 0, processes vector data of smaller numerical range; valu_idx = 1, processes vector data of larger numerical range.

[0134] din_valid: A signal indicating that the input vector data is valid.

[0135] din[3:0]: input vector data, din[0], din[1], din[2], din[3] are all 32-bit unsigned integer data.

[0136] dout_valid: A signal indicating that the output vector data is valid.

[0137] dout[3:0]: output vector data (also called vector sorting result).

[0138] stg3_res_i: The sorting result of stage_3 passed in from the vector sorting module of another vector execution subunit.

[0139] stg3_res_o: The sorting result of stage_3 of the vector sorting module passed to another vector execution subunit.

[0140] For illustration, please refer to Figure 7 , which shows a schematic diagram of the internal modules of a vector comparator provided by an exemplary embodiment of the present application, such as Figure 7 As shown, the following modules are currently included.

[0141] Figure 7 The middle dotted line is for beat processing, that is, the signal is output to the next level through the register.

[0142] (1) stg1_sort module: performs the first-level sorting comparison logic on the four input data, processing the lower two numbers in ascending order and the higher two numbers in descending order. The formula is as follows:

[0143] stg1_sort_res[1:0]=(din[1]>din[0])? {din[0],din[1]}:{din[1],din[0]}

[0144] stg1_sort_res[3:2]=(din[3]>din[2])? {din[2],din[3]}:{din[3],din[2]}

[0145] (2) mux module: selects input data based on whether it is currently in stage_2, stg2_en is the result of a beat of din_valid. When stg2_en = 1, the output signal stg1_res of stage_1 is selected;

[0146] When stge2_en=0, the output signal stg4_res of stage_4 is selected.

[0147] The logic for selecting data is as follows:

[0148] Share_sort_din[3:0]=stg2_en? stg1_res[3:0]:stg4_res

[0149] (3) share_sort module: completes the sorting logic of stage_2+stage_3 and stage_5+stage_6.

[0150] When stg2_en=1 and valu_idx=0, ascending processing is performed, and the other three cases (stg2_en=0 and valu_idx=0, stg2_en=1 and valu_idx=1, and stg2_en=0 and valu_idx=0) are processed in descending order.

[0151] For the output share_sort_res of the share_sort module, when dout_valid = 1 ， at this time,

[0152] share_sort_res is the final output result dout of the vector comparator;

[0153] When dout_valid=0, share_sort_res is the output result of stage_3, which will be passed to the exchange_sort module for internal sorting. ， It will also be passed to the comparator of another vector execution subunit, namely the signal stg3_res_o.

[0154] (4) exchange_sort module: Sort and select data for the stage_3 sort result share_sort_res generated by this module and the stage_3 sort result stg3_res_i passed in by the sorting module of another vector execution subunit. Since the input of stg3_res_i involves Harden, register tapping is required during input. In order to align the input time of share_sort_res with stg3_res_i, register tapping is also required.

[0155] Inside this module, share_sort_res will make a corresponding comparison with stg3_res_i, and directly select the larger or smaller number through the valu_idx signal. The logical formula is as follows:

[0156] stg4_res[0]=(share_sort_res[0]>stg3_res_i[0])^valu_idx? stg3_res_i[0]:

[0157] share_sort_res[0]

[0158] stg4_res[1]=(share_sort_res[1]>stg3_res_i[1])^valu_idx? stg3_res_i[1]:

[0159] share_sort_res[1]

[0160] stg4_res[2]=(share_sort_res[2]>stg3_res_i[2])^valu_idx? stg3_res_i[2]:

[0161] share_sort_res[2]

[0162] stg4_res[3]=(share_sort_res[3]>stg3_res_i[3])^valu_idx? stg3_res_i[3]:

[0163] share_sort_res[3]

[0164] (5) dout_valid logic: Since a delay of 7 beats is required to complete the sorting function logic, dout_valid is generated by the in_valid signal beating directly through the 7 serial registers.

[0165] In summary, the data sorting module provided in the embodiment of the present application receives different comparison signals through a first comparator, obtains the vector sorting result of the corresponding vector sorting stage according to the comparison signal, and thus performs the vector comparison of the next sorting stage of the vector sorting stage. That is, when the distribution of vector comparators used to perform vector comparison in at least two sorting stages is consistent, different comparison signals are used to implement the vector comparison process of the sorting stage corresponding to the comparison signal by reusing the same comparator in different sorting stages, thereby reducing the number of comparators used and simplifying the winding method for the comparators in the final sorting network, saving hardware resources and reducing the usage area of ​​the processor chip.

[0166] Compared with the existing technical solutions, this application has the following benefits:

[0167] (1) Reduced chip area: Through synthesis tools, the area of ​​the circuit of the present application is 23% of the area of ​​the existing technical solution. The reason is that the dual-tuning sorting circuit can optimize the resource sharing of the previous and next levels, which can greatly reduce the hardware overhead;

[0168] (2) Reduced layout and routing complexity: The dual-tuning sorting circuit reuses the logic resources of the previous and next levels while also reusing the routing resources and module ports, thus reducing the pressure on the layout and routing process.

[0169] It should be noted that before collecting the user's relevant data and during the process of collecting the user's relevant data, this application can display a prompt interface, pop-up window or output voice prompt information. The prompt interface, pop-up window or voice prompt information is used to prompt the user that its relevant data is currently being collected, so that this application only starts to execute the relevant steps of obtaining the user's relevant data after obtaining the user's confirmation operation on the prompt interface or pop-up window. Otherwise (that is, when the user's confirmation operation on the prompt interface or pop-up window is not obtained), the relevant steps of obtaining the user's relevant data are terminated, that is, the user's relevant data is not obtained. In other words, all user data collected by this application (including data to be converted into data types) are processed strictly in accordance with the requirements of relevant national laws and regulations. The informed consent or separate consent of the subject of personal information is obtained only with the user's consent and authorization. The subsequent data use and processing behavior is carried out within the scope of authorization of laws and regulations and the subject of personal information, and the collection, use and processing of relevant user data must comply with the relevant laws, regulations and standards of relevant countries and regions.

[0170] It should be understood that the "multiple" mentioned in this article refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. In addition, the step numbers described in this article only illustrate a possible execution sequence between the steps. In some other embodiments, the above steps may not be executed in the order of the numbers, such as two steps with different numbers are executed at the same time, or two steps with different numbers are executed in the opposite order to the diagram. The embodiments of the present application are not limited to this.

[0171] The above are merely exemplary embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A data sorting module applied to a processor, characterized in that: The data sorting module includes a vector execution unit, the vector execution unit includes a plurality of vector comparators, the plurality of vector comparators are distributed in a plurality of vector sorting stages to perform vector comparison, and the plurality of vector comparators include a first comparator; The first comparator is used to obtain a first vector sorting result in the nth vector sorting stage when receiving the first comparison signal; Performing vector comparison of the n+1th vector sorting stage based on the first vector sorting result, where n is a positive integer; The first comparator is further configured to obtain a second vector sorting result of the mth vector sorting stage when receiving a second comparison signal; A vector comparison of the m+1th vector sorting stage is performed based on the second vector sorting result, where m is a positive integer, and n is different from m.

2. The data sorting module according to claim 1, characterized in that: The first comparator is further configured to obtain a first vector sorting result of the nth vector sorting stage when the first comparison signal and the first sorting signal are received, the first sorting signal corresponding to the first sorting requirement; and perform vector comparison of the n+1th vector sorting stage based on the first vector sorting result and the first sorting requirement; The first comparator is further used to obtain a second vector sorting result of the mth vector sorting stage when receiving the second comparison signal and the second sorting signal, and the second sorting signal corresponds to a second sorting requirement; and perform vector comparison of the m+1th vector sorting stage based on the second vector sorting result and the second sorting requirement.

3. The data sorting module according to claim 2, characterized in that: The first comparator is further configured to output the first vector sorting result of the n+1th vector sorting stage as the sorting result of the vector execution unit in response to the first vector sorting result of the n+1th vector sorting stage meeting the stage completion condition; or The first comparator is further configured to, in response to the first vector sorting result of the n+1th vector sorting stage meeting the stage continuation condition, perform vector comparison of the n+2th vector sorting stage based on the first vector sorting result of the n+1th vector sorting stage.

4. The data sorting module according to claim 1, characterized in that: The vector execution unit also includes a register; The register is used to receive the first vector sorting result of the nth vector sorting stage; after delaying a preset clock cycle, the first vector sorting result is sent to the first comparator; The first comparator is further configured to receive the first vector sorting result of the nth vector sorting stage sent by the register.

5. The data sorting module according to any one of claims 1 to 4, characterized in that: The vector execution unit includes a first vector execution subunit and a second vector execution subunit, the first vector execution subunit includes the first comparator, and the second vector execution subunit includes a second comparator; The first comparator is configured to, upon receiving the first comparison signal, obtain a first sorting sub-result of the first vector data in the nth vector sorting stage; and perform vector comparison of the first vector data in the n+1th vector sorting stage based on the first sorting sub-result, where n is a positive integer; The first comparator is further configured to, upon receiving the second comparison signal, obtain a second sorting sub-result of the first vector data at the m-th vector sorting stage; and perform vector comparison of the first vector data at the m+1-th vector sorting stage based on the second sorting sub-result, where m is a positive integer; The second comparator is used to obtain a third sorting sub-result of the second vector data in the nth vector sorting stage when receiving the first comparison signal; based on the third sorting sub-result, the second vector data performs vector comparison in the n+1th vector sorting stage, the first vector data and the second vector data correspond to different numerical ranges, and n is a positive integer; The second comparator is also used to obtain the fourth sorting sub-result of the second vector data in the mth vector sorting stage when the second comparison signal is received; and perform vector comparison of the second vector data in the m+1th vector sorting stage based on the fourth sorting sub-result, where m is a positive integer.

6. The data sorting module according to claim 5, characterized in that: The first vector execution subunit further includes a third comparator, and the second vector execution subunit further includes a fourth comparator; The third comparator is used to obtain a fifth sorting sub-result of the first vector data in the i-th vector sorting stage when receiving the data exchange signal; and send the fifth sorting sub-result to the fourth comparator to perform vector comparison between the first vector data and the second vector data in the i+1-th vector sorting stage; The fourth comparator is used to obtain the sixth sorting sub-result of the second vector data in the i-th vector sorting stage when receiving the data exchange signal; and send the sixth sorting sub-result to the third comparator to perform vector comparison of the first vector data and the second vector data in the i+1-th vector sorting stage, where i is a positive integer and i is different from m and n.

7. The data sorting module according to claim 6, characterized in that: The first vector data corresponds to a first numerical range, and the second vector data corresponds to a second numerical range; The third comparator is further used to perform vector comparison on the first vector data and the second vector data in the (i+1)th vector sorting stage to obtain a vector comparison result; obtain first target vector data from the vector comparison result based on the first numerical range, and the first target vector data is used to perform vector comparison in the (i+2)th vector sorting stage; The fourth comparator is further used to perform vector comparison on the first vector data and the second vector data in the (i+1)th vector sorting stage to obtain a vector comparison result; A second target vector data is obtained from the vector comparison result based on the second numerical range, and the second target vector data is used to perform vector comparison in the (i+2) th vector sorting stage.

8. The data sorting module according to claim 5, characterized in that: The first vector execution subunit further includes a fifth comparator, and the second vector execution subunit further includes a sixth comparator; The fifth comparator is further configured to obtain the first vector data when the first data signal is received, wherein the first vector data corresponds to a numerical range corresponding to the first data signal; The sixth comparator is further used to obtain the second vector data when a second data signal is received, and the second vector data corresponds to a numerical range corresponding to the second data signal.

9. A data sorting method based on a data sorting module, characterized in that: The data sorting module comprises: a vector execution unit, the vector execution unit comprises a plurality of vector comparators, the plurality of vector comparators are distributed in a plurality of vector sorting stages to perform vector comparison, the plurality of vector comparators comprises a first comparator; the method comprises: When the first comparison signal is received, obtaining a first vector sorting result of the nth vector sorting stage; Performing vector comparison of the n+1th vector sorting stage based on the first vector sorting result, where n is a positive integer; When the second comparison signal is received, obtaining a second vector sorting result of the mth vector sorting stage; A vector comparison of the m+1th vector sorting stage is performed based on the second vector sorting result, where m is a positive integer, and n is different from m.

10. A processor, characterized in that: The processor comprises a data sorting module as described in any one of claims 1 to 8.

11. A computer device, characterized in that: The computer device comprises a processor, and the processor comprises the data sorting module as described in any one of claims 1 to 8.

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