Instruction processing system and instruction processing method

Abstract

The present invention discloses an instruction processing system and an instruction processing method, the system comprises: a storage unit for storing a target instruction; a decoding unit connected to the storage unit; a processing unit connected to the decoding unit; an illegal instruction monitoring unit connected between the storage unit and the decoding unit, the illegal instruction monitoring unit is used to determine the legality of the target instruction according to a preset encoding format and the encoding format of the target instruction, and in response to the legality indicating that the target instruction is an illegal instruction, the target instruction is normalized into a normalized illegal instruction and then output to the decoding unit for decoding to obtain a decoding result, so that the processing unit performs corresponding processing according to the decoding result. The embodiments of the present invention can reduce the design complexity and difficulty of the decoder and improve the program execution efficiency.

Description

Technical Field

[0001] The present invention relates to the technical field related to instruction processing, and in particular to an instruction processing system and an instruction processing method. Background Art

[0002] With the development of new energy vehicles and industrial intelligence, the performance requirements for processors are getting higher and higher, which will inevitably lead to a larger and larger processor instruction set. However, problems such as complex application environment and electromagnetic interference will cause interference to the processor during operation, causing legal instructions to suddenly become illegal instructions. For existing processor cores, the instructions are first input into the decoder for decoding, and then the legality of the decoded instructions is judged for subsequent processing. Therefore, the design requirements of the decoder are higher, and the decoder needs to have more complex decoding logic. This method leads to a large circuit scale of the processor core, high complexity of the decoder design, high decoding difficulty, and low program execution efficiency. Summary of the invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, the present invention proposes an instruction processing system that can reduce the design complexity and difficulty of a decoder and improve program execution efficiency.

[0004] The present invention also provides an instruction processing method, a control device for executing the instruction processing method, and a computer-readable storage medium.

[0005] According to the instruction processing system of the first aspect of the present invention, the system comprises:

[0006] A storage unit, used for storing target instructions;

[0007] A decoding unit connected to the storage unit;

[0008] A processing unit connected to the decoding unit;

[0009] An illegal instruction monitoring unit is connected between the storage unit and the decoding unit. The illegal instruction monitoring unit is used to determine the legality of the target instruction according to a preset encoding format and the encoding format of the target instruction. In response to the legality indicating that the target instruction is an illegal instruction, the target instruction is normalized into a normalized illegal instruction and then output to the decoding unit for decoding to obtain a decoding result, so that the processing unit performs corresponding processing according to the decoding result.

[0010] The instruction processing system according to the embodiment of the present invention has at least the following beneficial effects:

[0011] By setting an illegal instruction monitoring unit before the decoding unit, the legality of the target instruction is determined according to the preset encoding format and the encoding format of the target instruction before decoding. When the legality indicates that the target instruction is an illegal instruction, the target instruction is normalized into a normalized illegal instruction and then output to the decoding unit for decoding. Compared with first decoding the target instruction and then judging the legality of the target instruction, the embodiment of the present invention judges the legality of the target instruction before decoding, and unifies all illegal instructions into the same format and then inputs them into the decoding unit for decoding, so that the decoding unit only needs to have one decoding logic for illegal instructions, which can reduce the design complexity and difficulty of the decoder and improve the efficiency of program execution.

[0012] According to some embodiments of the present invention, an ECC error correction module is further provided between the storage unit and the illegal instruction monitoring unit, and the ECC error correction module is used to obtain the target instruction, perform verification and error correction processing on the target instruction, and then input it into the illegal instruction monitoring unit.

[0013] The instruction processing method according to the second aspect of the present invention is applied to the instruction processing system as described in the first aspect of the present invention, and the instruction processing method includes:

[0014] Obtaining the target instruction;

[0015] Determining the legitimacy of the target instruction according to the preset encoding format and the encoding format of the target instruction;

[0016] In response to the legality indicating that the target instruction is an illegal instruction, the target instruction is normalized into a normalized illegal instruction and then output to the decoding unit for decoding to obtain a decoding result, so that the processing unit performs corresponding processing according to the decoding result.

[0017] The instruction processing method according to the embodiment of the present invention has at least the following beneficial effects:

[0018] By setting an illegal instruction monitoring unit before the decoding unit, the legality of the target instruction is determined according to the preset encoding format and the encoding format of the target instruction before decoding. When the legality indicates that the target instruction is an illegal instruction, the target instruction is normalized into a normalized illegal instruction and then output to the decoding unit for decoding. Compared with first decoding the target instruction and then judging the legality of the target instruction, the embodiment of the present invention judges the legality of the target instruction before decoding, and unifies all illegal instructions into the same format and then inputs them into the decoding unit for decoding, so that the decoding unit only needs to have one decoding logic for illegal instructions, which can reduce the design complexity and difficulty of the decoder and improve the efficiency of program execution.

[0019] According to some embodiments of the present invention, the decoding unit comprises a sampling unit and an instruction decoding module connected in sequence, the input end of the sampling unit is connected to the output end of the illegal instruction monitoring unit, and the output end of the instruction decoding module is connected to the processing unit;

[0020] The step of normalizing the target instruction into a normalized illegal instruction and then outputting the normalized illegal instruction to the decoding unit for decoding to obtain a decoding result includes:

[0021] generating a shielding signal to shut down the output end of the illegal instruction monitoring unit;

[0022] The input end of the sampling unit is reset to zero, so that the sampling unit outputs the normalization illegal instruction of all zeros to the instruction decoding module for decoding to obtain the decoding result.

[0023] According to some embodiments of the present invention, the preset encoding format includes an opcode encoding format, and the target instruction includes an opcode; and determining the legitimacy of the target instruction according to the preset encoding format and the encoding format of the target instruction includes:

[0024] Determine an opcode matching result according to the opcode encoding format and the opcode of the target instruction;

[0025] In response to the opcode matching result indicating that the encoding format of the opcode of the target instruction does not match the opcode encoding format, determining the legality indicates that the target instruction is an illegal instruction.

[0026] According to some embodiments of the present invention, the target instruction further includes an operand; after determining the opcode matching result according to the opcode encoding format and the opcode of the target instruction, the instruction processing method further includes:

[0027] In response to the opcode matching result indicating that the encoding format of the opcode of the target instruction matches the opcode encoding format, determining a matching format of the opcode of the target instruction;

[0028] Determining the operand form of the operand of the target instruction according to the matching format;

[0029] In response to the operand form being a register form, determining a target register corresponding to the register form;

[0030] Determining a register matching result between the target register and an existing register;

[0031] In response to the register match result indicating that the target register does not match an existing register, determining the legality indicates that the target instruction is an illegal instruction.

[0032] According to some embodiments of the present invention, an ECC error correction module is further provided between the storage unit and the illegal instruction monitoring unit, and the instruction processing method further includes the following steps performed by the ECC error correction module:

[0033] Obtaining the target instruction;

[0034] Verifying the target instruction to obtain a first verification result;

[0035] In response to the first verification result indicating that the target instruction has a one-bit error, the target instruction is error-corrected and then input into the illegal instruction monitoring unit.

[0036] According to some embodiments of the present invention, after verifying the target instruction to obtain a first verification result, the instruction processing method further includes:

[0037] In response to the first verification result indicating that the target instruction has more than one bit error, re-reading the target instruction for verification to obtain a second verification result;

[0038] In response to the second verification result indicating that the target instruction has more than one bit error, error information is generated, and the target instruction is input to the illegal instruction monitoring unit.

[0039] According to some embodiments of the present invention, the ECC error correction module includes an error status register and an error address register, the error status register includes an instruction error flag bit and an error bit number bit; generating error information includes:

[0040] Setting the instruction error flag in the error status register to an instruction error status;

[0041] Determine the number of error bits and the error address according to the second check result;

[0042] Writing the error bit number into the error bit number bit of the error status register;

[0043] The error address is written into the error address register.

[0044] According to some embodiments of the present invention, the instruction processing method further includes:

[0045] Polling the instruction error flag bit in the error status register;

[0046] In response to the instruction error flag being in the instruction error state, the control system is reset.

[0047] According to the third aspect of the present invention, the control device comprises a memory, a processor and a computer program stored in the memory and executable on the processor, and the processor implements the instruction processing method as described in the second aspect of the embodiment when executing the computer program. Since the control device adopts all the technical solutions of the instruction processing method of the above embodiment, it has at least all the beneficial effects brought by the technical solutions of the above embodiment.

[0048] According to the computer-readable storage medium of the fourth aspect embodiment of the present invention, computer-executable instructions are stored, and the computer-executable instructions are used to execute the instruction processing method as described in the second aspect embodiment. Since the computer-readable storage medium adopts all the technical solutions of the instruction processing method of the above embodiment, it at least has all the beneficial effects brought by the technical solutions of the above embodiment.

[0049] Other features and advantages of the present invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0051] Figure 1 is a system block diagram of an instruction processing system according to an embodiment of the present invention;

[0052] Figure 2 is a flow chart of an instruction processing method according to an embodiment of the present invention.

[0053] Reference numerals:

[0054] Storage unit 100;

[0055] Sampling unit 210, instruction register 221, decoder 222;

[0056] Processing unit 300;

[0057] Illegal instruction monitoring unit 400;

[0058] ECC error correction module 500. DETAILED DESCRIPTION

[0059] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0060] In the description of the present invention, if there is a description of first, second, etc., it is only for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0061] In the description of the present invention, it should be understood that descriptions involving orientation, such as orientation or positional relationship indicated as up, down, etc., are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0062] In the description of the present invention, it should be noted that, unless otherwise clearly defined, terms such as setting, installing, connecting, etc. should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in the present invention in combination with the specific content of the technical solution.

[0063] With the development of new energy vehicles and industrial intelligence, the performance requirements for processors are getting higher and higher, which will inevitably lead to a larger and larger processor instruction set. However, problems such as complex application environment and electromagnetic interference will cause the processor to be interfered with during operation, causing legal instructions to suddenly become illegal instructions. For existing processor cores, the instructions are first input into the decoder 222 for decoding, and then the legality of the decoded instructions is judged for subsequent processing. Therefore, the design requirements for the decoder 222 are higher, and the decoder 222 needs to have a more complex decoding logic. This method results in a large circuit scale of the processor core, high design complexity of the decoder 222, high decoding difficulty, and low program execution efficiency.

[0064] Based on this, the embodiments of the present invention provide an instruction processing system and an instruction processing method, which can reduce the design complexity and difficulty of the decoder 222 and improve the program execution efficiency.

[0065] The following will be combined Figure 1 and Figure 2 The instruction processing system of the embodiment of the present invention is described clearly and completely. Obviously, the embodiment described below is only a part of the embodiment of the present invention, not all the embodiments.

[0066] According to the instruction processing system of the first aspect of the present invention, the system includes a storage unit 100, a decoding unit, a processing unit 300 and an illegal instruction monitoring unit 400.

[0067] The storage unit 100 is used to store target instructions;

[0068] A decoding unit connected to the storage unit 100;

[0069] The processing unit 300 is connected to the decoding unit;

[0070] The illegal instruction monitoring unit 400 is connected between the storage unit 100 and the decoding unit. The illegal instruction monitoring unit 400 is used to determine the legality of the target instruction according to the preset encoding format and the encoding format of the target instruction. In response to the legality indication that the target instruction is an illegal instruction, the target instruction is normalized into a normalized illegal instruction and then output to the decoding unit for decoding to obtain a decoding result, so that the processing unit 300 performs corresponding processing according to the decoding result.

[0071] It is understandable that instructions are generally divided into legal instructions, illegal instructions and reserved instructions. Reserved instructions are generally treated as empty instructions, that is, reserved instructions can be executed but do not produce any practical effect. The processor executes the program as follows: the processing unit 300 reads instructions from the storage unit 100, and the fetched instructions wait in the instruction queue to be sent to the decoding unit for decoding. After decoding, micro-operation signals are generated to control the internal execution unit of the processing unit 300 to perform corresponding operations. In the process of instruction transmission, electromagnetic interference or signal crosstalk may cause instruction mutations, thereby causing system operation errors or legal instructions to become illegal instructions.

[0072] An illegal instruction is an instruction that has no corresponding assembly instruction after disassembly. The most critical part of the processor core design is the pipeline design. The decoding unit between the pipelines carries the most critical work such as decoding all instructions and generating micro-operation signals. It is also the most complex module. For a 32-bit instruction system, the encoding space of the instruction ranges from 0x00000000 to 0xFFFFFFFF. According to this calculation, it can support up to Instructions. If the decoding logic determines the legality of all illegal instructions, the decoding logic circuit structure of the decoding unit will be very complicated, and the decoding unit needs to add a lot of decoding logic, and the decoding logic of some formats of illegal instructions may be missed, which will increase the design complexity of the decoding unit, increase the difficulty of decoding, and reduce the efficiency of program execution. The embodiment of the present invention determines the legality of the target instruction before decoding, and unifies all illegal instructions into the same format and then inputs them into the decoding unit for decoding, so that the decoding unit only needs to have one type of decoding logic for illegal instructions, which can reduce the design complexity and difficulty of the decoder 222 and improve the efficiency of program execution.

[0073] The decoding unit includes a sampling unit 210 and an instruction decoding module connected in sequence. The input end of the sampling unit 210 is connected to the output end of the illegal instruction monitoring unit 400. The output end of the instruction decoding module is connected to the processing unit 300. The instruction decoding module includes an instruction register 221 and a decoder 222 connected in sequence.

[0074] In some embodiments of the present invention, the preset encoding format includes an opcode encoding format, and the target instruction includes an opcode and an operand; determining the legality of the target instruction according to the preset encoding format and the encoding format of the target instruction includes:

[0075] Determine an opcode matching result according to an opcode encoding format and an opcode of a target instruction;

[0076] In response to the opcode matching result indicating that the encoding format of the opcode of the target instruction does not match the opcode encoding format, determining the legality indicates that the target instruction is an illegal instruction;

[0077] In response to the opcode matching result indicating that the encoding format of the opcode of the target instruction matches the opcode encoding format, determining a matching format of the opcode of the target instruction;

[0078] Determine the operand form of the operand of the target instruction according to the matching format;

[0079] In response to the operand form being a register form, determining a target register corresponding to the register form;

[0080] Determine a register match result between a target register and an existing register;

[0081] In response to the register match result indicating that the target register matches the existing register, determining the legality indicates that the target instruction is a legal instruction;

[0082] In response to the register match result indicating that the target register does not match the existing register, determining the legality indicates that the target instruction is an illegal instruction.

[0083] An instruction consists of an opcode and an operand. The legality of an instruction is determined by first determining the legality of its opcode and then determining the legality of its operand. The instruction set has its specific encoding format, and the opcode also has a specific bit field and encoding format. Operands are in the form of immediate numbers and registers. The opcode of the target instruction input into the illegal instruction monitoring unit 400 is compared with the preset opcode encoding format. If there is no match, it is determined to be an illegal instruction. If there is a match, the operand matching continues. According to the matching form of the opcode, it can be determined whether the operand it carries is an immediate number or a register form. If it is a register form, it is matched to see if there is a corresponding register. If there is no corresponding register, it is determined to be an illegal instruction; if there is a corresponding register, it is determined to be a legal instruction. If the operand is an immediate number, there is no need to match it, and it is directly considered to be a legal instruction.

[0084] Compared with designing different decoding logics for illegal instructions, the embodiments of the present invention compare whether the opcode encoding format matches the opcode of the target instruction, determine the operand form, and when the operand form is in register form, determine whether the target register corresponding to the register form matches the existing register. The legitimacy judgment logic is simpler and the judgment speed is faster, which can reduce the design complexity and difficulty of the decoder 222 and improve the program execution efficiency.

[0085] After the illegal instruction monitoring unit 400 detects that the target instruction is an illegal instruction, it normalizes the target instruction into a normalized illegal instruction, including: generating a mask signal to turn off the output end of the illegal instruction monitoring unit 400; setting the input end of the sampling unit 210 to zero, so that the sampling unit 210 outputs an all-zero normalized illegal instruction to the instruction decoding module for decoding to obtain a decoding result. When the decoding unit decodes the normalized illegal instruction, the control triggers the instruction illegal trap interrupt. The decoding speed of the all-zero normalized illegal instruction is faster than that of other complex instruction formats, which can further improve the efficiency of program execution.

[0086] It should be noted that the normalization illegal instruction may also be in other instruction formats, which cannot be regarded as a limitation to the present invention.

[0087] According to the instruction processing system of the embodiment of the present invention, by setting the illegal instruction monitoring unit 400 before the decoding unit, the legality of the target instruction is first determined according to the preset encoding format and the encoding format of the target instruction before decoding. When the legality indicates that the target instruction is an illegal instruction, the target instruction is normalized into a normalized illegal instruction and then output to the decoding unit for decoding. Compared with first decoding the target instruction and then judging the legality of the target instruction, the embodiment of the present invention judges the legality of the target instruction before decoding, and unifies all illegal instructions into the same format and then inputs them into the decoding unit for decoding, so that the decoding unit only needs to have one decoding logic for illegal instructions, which can reduce the design complexity and difficulty of the decoder 222 and improve the efficiency of program execution.

[0088] In some embodiments of the present invention, reference Figure 1 An ECC error correction module 500 is also provided between the storage unit 100 and the illegal instruction monitoring unit 400. The ECC error correction module 500 is used to obtain the target instruction, perform verification and error correction processing on the target instruction, and then input it into the illegal instruction monitoring unit 400.

[0089] The ECC error correction module 500 is used to perform the following steps:

[0090] Get target instructions;

[0091] Verifying the target instruction to obtain a first verification result;

[0092] In response to the first verification result indicating that the target instruction has a bit error, the target instruction is corrected and then input to the illegal instruction monitoring unit 400;

[0093] In response to the first verification result indicating that the target instruction has more than one bit error, re-reading the target instruction for verification to obtain a second verification result;

[0094] In response to the second verification result indicating that the target instruction has more than one bit error, error information is generated and the target instruction is input to the illegal instruction monitoring unit 400 .

[0095] The storage unit 100 of the embodiment of the present invention adopts a program memory supporting the ECC function, and the read target instruction is first input into the ECC error correction module 500 for ECC verification and error correction. The ECC error correction module 500 includes an instruction re-fetch counter, an error status register, an error address register and a decoding checker. The decoding checker can receive the target instruction and the program memory check code that already supports the ECC function, recalculate the check code according to the read target instruction and the same ECC check rule as the program memory supporting the ECC function, and compare and analyze the consistency of the new check code with the original check code. If they are consistent, there is no error; if they are inconsistent, it can be determined whether there is a single error or more than one error. The ECC error correction module 500 can directly correct the data with a single error. When the error data bit is greater than one bit, the instruction re-fetch counter is controlled to read the target instruction again from the same address. If it is still greater than one bit error, the error information is output, and the target instruction is input into the illegal instruction monitoring unit 400 for instruction legitimacy judgment and subsequent decoding.

[0096] In some embodiments of the present invention, generating an error message includes:

[0097] Set the instruction error flag bit in the error status register to the instruction error status;

[0098] Determine the number of error bits and the error address according to the second check result;

[0099] Write the error bit number into the error bit number bit of the error status register;

[0100] Write the error address to the error address register.

[0101] After the error information is generated, the processing unit 300 can poll the instruction error flag in the error status register, and in response to the instruction error flag being in the instruction error state, the control system is reset to restart the system to improve the correctness of system operation and functional safety. The error address in the error address register can also be obtained to determine the mutation location.

[0102] It should be noted that after the error information is generated, the error information can be processed according to actual needs, which cannot be regarded as a limitation of the present invention.

[0103] By setting the ECC error correction module 500 before the illegal instruction monitoring unit 400, the instruction accuracy can be effectively improved and the program running error rate can be reduced. It can also effectively reduce the probability of program running errors caused by interference with the operand field data, thereby improving the system functional safety.

[0104] The following will be combined Figure 1 and Figure 2 The instruction processing method of the embodiment of the present invention is described clearly and completely. Obviously, the embodiment described below is only a part of the embodiments of the present invention, not all the embodiments.

[0105] According to the instruction processing method of the second aspect of the present invention, applied to the instruction processing system of the first aspect of the present invention, the instruction processing method includes:

[0106] Get target instructions;

[0107] Determining the legality of the target instruction according to the preset coding format and the coding format of the target instruction;

[0108] In response to the legality indicating that the target instruction is an illegal instruction, the target instruction is normalized into a normalized illegal instruction and then output to the decoding unit for decoding to obtain a decoding result, so that the processing unit 300 performs corresponding processing according to the decoding result.

[0109] It is understandable that instructions are generally divided into legal instructions, illegal instructions and reserved instructions. Reserved instructions are generally treated as empty instructions, that is, reserved instructions can be executed but do not produce any practical effect. The processor executes the program as follows: the processing unit 300 reads instructions from the storage unit 100, and the fetched instructions wait in the instruction queue to be sent to the decoding unit for decoding. After decoding, micro-operation signals are generated to control the internal execution unit of the processing unit 300 to perform corresponding operations. In the process of instruction transmission, electromagnetic interference or signal crosstalk may cause instruction mutations, thereby causing system operation errors or legal instructions to become illegal instructions.

[0110] An illegal instruction is an instruction that has no corresponding assembly instruction after disassembly. The most critical part of the processor core design is the pipeline design. The decoding unit between the pipelines carries the most critical work such as decoding all instructions and generating micro-operation signals. It is also the most complex module. For a 32-bit instruction system, the encoding space of the instruction ranges from 0x00000000 to 0xFFFFFFFF. According to this calculation, it can support up to Instructions. If the decoding logic determines the legality of all illegal instructions, the decoding logic circuit structure of the decoding unit will be very complicated, and the decoding unit needs to add a lot of decoding logic, and the decoding logic of some formats of illegal instructions may be missed, which will increase the design complexity of the decoding unit, increase the difficulty of decoding, and reduce the efficiency of program execution. The embodiment of the present invention determines the legality of the target instruction before decoding, and unifies all illegal instructions into the same format and then inputs them into the decoding unit for decoding, so that the decoding unit only needs to have one type of decoding logic for illegal instructions, which can reduce the design complexity and difficulty of the decoder 222 and improve the efficiency of program execution.

[0111] Compared with designing different decoding logics for illegal instructions, the embodiments of the present invention compare the encoding format of the opcode with the encoding format of the opcode of the target instruction, determine the operand form, and when the operand form is in register form, determine whether the target register corresponding to the register form matches the existing register. The legality judgment logic is simpler and the judgment speed is faster, which can reduce the design complexity and difficulty of the decoder 222 and improve the program execution efficiency.

[0112] According to the instruction processing method of the embodiment of the present invention, by setting the illegal instruction monitoring unit 400 before the decoding unit, the legality of the target instruction is first determined according to the preset encoding format and the encoding format of the target instruction before decoding, and when the legality indicates that the target instruction is an illegal instruction, the target instruction is normalized into a normalized illegal instruction and then output to the decoding unit for decoding. Compared with first decoding the target instruction and then judging the legality of the target instruction, the embodiment of the present invention judges the legality of the target instruction before decoding, and unifies all illegal instructions into the same format and then inputs them into the decoding unit for decoding, so that the decoding unit only needs to have one decoding logic for illegal instructions, which can reduce the design complexity and difficulty of the decoder 222 and improve the program execution efficiency.

[0113] In some embodiments of the present invention, reference Figure 1 The decoding unit includes a sampling unit 210 and an instruction decoding module connected in sequence, the input end of the sampling unit 210 is connected to the output end of the illegal instruction monitoring unit 400, and the output end of the instruction decoding module is connected to the processing unit 300;

[0114] The target instruction is normalized into a normalized illegal instruction and then output to the decoding unit for decoding to obtain a decoding result, including:

[0115] Generate a shielding signal to shut down the output of the illegal instruction monitoring unit 400;

[0116] The input end of the sampling unit 210 is reset to zero, so that the sampling unit 210 outputs an all-zero normalized illegal instruction to the instruction decoding module for decoding to obtain a decoding result.

[0117] The instruction decoding module includes an instruction register 221 and a decoder 222 which are connected in sequence.

[0118] The decoding speed of the all-zero normalization illegal instruction is faster than other complex instruction formats, which can further improve the program execution efficiency.

[0119] It should be noted that the normalization illegal instruction may also be in other instruction formats, which cannot be regarded as a limitation to the present invention.

[0120] In some embodiments of the present invention, the preset encoding format includes an opcode encoding format, and the target instruction includes an opcode; determining the legality of the target instruction according to the preset encoding format and the encoding format of the target instruction includes:

[0121] Determine an opcode matching result according to an opcode encoding format and an opcode of a target instruction;

[0122] In response to the opcode matching result indicating that the encoding format of the opcode of the target instruction does not match the opcode encoding format, determining the legality indicates that the target instruction is an illegal instruction.

[0123] In some embodiments of the present invention, the target instruction further includes an operand; after determining the opcode matching result according to the opcode encoding format and the opcode of the target instruction, the instruction processing method further includes:

[0124] In response to the opcode matching result indicating that the encoding format of the opcode of the target instruction matches the opcode encoding format, determining a matching format of the opcode of the target instruction;

[0125] Determine the operand form of the operand of the target instruction according to the matching format;

[0126] In response to the operand form being a register form, determining a target register corresponding to the register form;

[0127] Determine a register match result between a target register and an existing register;

[0128] In response to the register match result indicating that the target register does not match the existing register, determining the legality indicates that the target instruction is an illegal instruction.

[0129] An instruction consists of an opcode and an operand. The legality of an instruction is determined by first determining the legality of its opcode and then determining the legality of its operand. The instruction set has its specific encoding format, and the opcode also has a specific bit field and encoding format. Operands are in the form of immediate numbers and registers. The opcode of the target instruction input into the illegal instruction monitoring unit 400 is compared with the preset opcode encoding format. If there is no match, it is determined to be an illegal instruction. If there is a match, the operand matching continues. According to the matching form of the opcode, it can be determined whether the operand it carries is an immediate number or a register form. If it is a register form, it is matched to see if there is a corresponding register. If there is no corresponding register, it is determined to be an illegal instruction; if there is a corresponding register, it is determined to be a legal instruction. If the operand is an immediate number, there is no need to match it, and it is directly considered to be a legal instruction.

[0130] Compared with designing different decoding logics for illegal instructions, the embodiments of the present invention compare the encoding format of the opcode with the encoding format of the opcode of the target instruction, determine the operand form, and when the operand form is in register form, determine whether the target register corresponding to the register form matches the existing register. The legality judgment logic is simpler and the judgment speed is faster, which can reduce the design complexity and difficulty of the decoder 222 and improve the program execution efficiency.

[0131] In some embodiments of the present invention, reference Figure 1 An ECC error correction module 500 is further provided between the storage unit 100 and the illegal instruction monitoring unit 400, and the instruction processing method further includes the following steps executed by the ECC error correction module 500:

[0132] Get target instructions;

[0133] Verifying the target instruction to obtain a first verification result;

[0134] In response to the first verification result indicating that the target instruction has a one-bit error, the target instruction is corrected and then input into the illegal instruction monitoring unit 400 .

[0135] The storage unit 100 of the embodiment of the present invention adopts a program memory supporting the ECC function, and the read target instruction is first input into the ECC error correction module 500 for ECC verification and error correction. The ECC error correction module 500 includes an instruction re-fetch counter, an error status register, an error address register and a decoding checker. The decoding checker can receive the target instruction and the program memory check code that already supports the ECC function, recalculate the check code according to the read target instruction and the same ECC check rule as the program memory supporting the ECC function, and compare and analyze the consistency of the new check code with the original check code. If consistent, there is no error; if inconsistent, it can be determined whether there is a single error or more than one error. The ECC error correction module 500 can directly correct the data with a single error. By setting the ECC error correction module 500 before the illegal instruction monitoring unit 400, it can effectively avoid the situation where the instruction is illegal due to a single data mutation, reduce the probability of a certain bit of the operation code being disturbed and becoming an illegal instruction, causing system failure, and improve the overall program execution efficiency.

[0136] In some embodiments of the present invention, reference Figure 1 After verifying the target instruction to obtain a first verification result, the instruction processing method further includes:

[0137] In response to the first verification result indicating that the target instruction has more than one bit error, re-reading the target instruction for verification to obtain a second verification result;

[0138] In response to the second verification result indicating that the target instruction has more than one bit error, error information is generated and the target instruction is input to the illegal instruction monitoring unit 400 .

[0139] The ECC error correction module 500 can directly correct data with one bit error. When the error data bit is greater than one bit, the instruction re-fetch counter is controlled to read the target instruction again from the same address. If the second check result indicates that the target instruction has one bit error, the target instruction is corrected and input into the illegal instruction monitoring unit 400. If the error is still greater than one bit, error information is output, and the target instruction is input into the illegal instruction monitoring unit 400 for instruction legitimacy judgment and subsequent decoding.

[0140] The processing method of determining that more than one bit of data is continuously reported as an error by the ECC error correction module 500 can effectively provide effective information to the user and avoid major problems caused by program execution errors.

[0141] In some embodiments of the present invention, the ECC error correction module 500 includes an error status register and an error address register, the error status register includes an instruction error flag bit and an error bit number bit; error information is generated, including:

[0142] Set the instruction error flag bit in the error status register to the instruction error status;

[0143] Determine the number of error bits and the error address according to the second check result;

[0144] Write the error bit number into the error bit number bit of the error status register;

[0145] Write the error address to the error address register.

[0146] Setting the instruction error flag in the error status register to the instruction error status may be to set the instruction error flag to "1", and if there is no error, to "0", and the corresponding instruction error flag is the instruction correct status. The instruction error flag can enable the processing unit 300 to quickly identify the error status of the target instruction so as to perform corresponding processing.

[0147] It should be noted that the specific values ​​of the instruction error state and the instruction correct state can be set according to actual conditions and cannot be regarded as a limitation of the present invention.

[0148] In some embodiments of the present invention, the instruction processing method further includes:

[0149] Poll the instruction error flag bit in the error status register;

[0150] In response to the instruction error flag being in the instruction error state, the control system is reset.

[0151] After the error information is generated, the processing unit 300 can poll the instruction error flag in the error status register, and in response to the instruction error flag being in the instruction error state, the control system is reset to restart the system to improve the correctness of system operation and functional safety. The error address in the error address register can also be obtained to determine the mutation location.

[0152] It should be noted that after the error information is generated, the error information can be processed according to actual needs, which cannot be regarded as a limitation of the present invention.

[0153] In order to better demonstrate the advantages of the instruction processing system and instruction processing method according to the embodiments of the present invention, three specific embodiments are described below.

[0154] Embodiment 1:

[0155] The target instruction read from the storage unit 100 is 0x71A5 and its corresponding check bit. When the target instruction passes through the instruction transmission path, it may become 0x70A5 when it reaches the ECC error correction module 500 due to interference, but the instruction is still a legal instruction. After the instruction is rechecked by the ECC error correction module 500, an error is found, and the error position is determined and corrected to 0x71A5. The corrected instruction enters the subsequent instruction decoding process normally, thereby improving the functional safety performance.

[0156] Embodiment 2:

[0157] The instruction read from the storage unit 100 is 0x71A5 and its corresponding check bit. When the target instruction passes through the instruction transmission path, it may become 0x77A5 when it reaches the ECC error correction module 500 due to interference. After the target instruction is rechecked by the ECC error correction module 500, it is found that there are two errors. Then the current instruction re-fetch count value is recorded, and the target instruction and its corresponding check bit are re-read from the current instruction re-fetch count value. If the target instruction is still 0x77A5 or suddenly changes to other data with any two errors when it passes through the instruction transmission path again due to interference, and the target instruction at the same address has more than one error twice in a row, an error message is given, and the target instruction continues to be transmitted to the illegal instruction monitoring unit 400, and is continued to be processed by the subsequent process. At the same time, the user can decide the program execution process according to the error information.

[0158] Embodiment three:

[0159] When storing the program into the storage unit 100, the target instruction expected to be stored is 0x71A5, but due to strong electromagnetic interference or signal crosstalk during the writing process, the written target instruction suddenly changes to 0x73A5. Since the written data itself is wrong, the check code saved in the storage unit 100 that supports ECC check is also calculated based on 0x73A5. When reading the target instruction, if there is no error in the transmission process, the ECC error correction module 500 naturally believes that 0x73A5 is correct and no error correction is required. In fact, there is no disassembly instruction corresponding to 0x73A5 in the instruction set architecture. When the target instruction flows into the illegal instruction monitoring unit 400, it is determined that 0x73A5 is an illegal instruction. Then the illegal instruction monitoring unit 400 generates a shielding signal to turn off the output of the illegal instruction monitoring unit 400, and the input of the sampling unit 210 is reset to zero, so that the sampling unit 210 outputs an all-zero normalized illegal instruction to the instruction decoding module for decoding. Therefore, the instruction decoding module only needs to process one type of illegal instruction with all zeros, which greatly simplifies the design complexity and difficulty of the instruction decoding module. At the same time, the instruction illegal trap interrupt is immediately triggered, and the illegal instruction interrupt service subroutine is entered.

[0160] The instruction processing system and instruction processing method of the embodiment of the present invention can effectively avoid the situation where an instruction is illegal due to a sudden change of a bit of data by adding an ECC error correction module 500, reduce the probability of a certain bit of the operation code being disturbed and becoming an illegal instruction, resulting in system failure, and improve the overall program execution efficiency. The processing method of judging that more than one bit of data is continuously reported as an error by the ECC error correction module 500 can effectively provide effective information to the user, avoiding major problems caused by program execution errors. The illegal instruction monitoring unit 400 can effectively and quickly judge whether the instruction is legal, effectively reducing the complexity and difficulty of the decoder 222 design.

[0161] In addition, an embodiment of the present invention further provides a control device, which includes: a memory, a processor, and a computer program stored in the memory and executable on the processor. The processor and the memory may be connected via a bus or other means.

[0162] The memory, as a non-transient computer-readable storage medium, can be used to store non-transient software programs and non-transient computer executable programs. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some embodiments, the memory may optionally include a memory remotely disposed relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0163] The non-transitory software program and instructions required to implement the instruction processing method of the above embodiment are stored in the memory, and when executed by the processor, the instruction processing method of the above embodiment is executed.

[0164] The device embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separated, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0165] In addition, an embodiment of the present invention also provides a computer-readable storage medium, which stores computer-executable instructions, and the computer-executable instructions are executed by a processor or controller, for example, by the processor of the above embodiment, so that the above processor can execute the instruction processing method in the above embodiment.

[0166] It will be appreciated by those skilled in the art that all or some of the steps and systems in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or transient medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically embodies computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0167] The embodiments of the present invention are described in detail above in conjunction with the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge scope of ordinary technicians in the relevant technical field without departing from the purpose of the present invention.

Claims

1. An instruction processing system, characterized in that: The system comprises: A storage unit, used for storing target instructions; A decoding unit, comprising a sampling unit and an instruction decoding module connected in sequence; A processing unit connected to the output end of the instruction decoding module; an illegal instruction monitoring unit, wherein the input end is connected to the storage unit, and the output end is connected to the input end of the sampling unit, wherein the illegal instruction monitoring unit is used to obtain the target instruction, wherein the target instruction includes an operation code and an operand; determine an operation code matching result according to a preset operation code encoding format and the operation code of the target instruction; determine that the target instruction is an illegal instruction in response to the operation code matching result indicating that the encoding format of the operation code of the target instruction does not match the operation code encoding format; determine a matching format of the operation code of the target instruction according to the matching format; The operand form of the operand of the instruction; in response to the operand form being a register form, determining the target register corresponding to the register form; determining the register matching result between the target register and the existing register; in response to the register matching result indicating that the target register does not match the existing register, determining that the target instruction is an illegal instruction; in response to the target instruction being an illegal instruction, generating a shielding signal to turn off the output end of the illegal instruction monitoring unit, and setting the input end of the sampling unit to zero, so that the sampling unit outputs an all-zero normalized illegal instruction to the instruction decoding module for decoding to obtain a decoding result, so that the processing unit performs corresponding processing according to the decoding result.

2. The instruction processing system according to claim 1, characterized in that: An ECC error correction module is also provided between the storage unit and the illegal instruction monitoring unit. The ECC error correction module is used to obtain the target instruction, perform verification and error correction processing on the target instruction, and then input the target instruction into the illegal instruction monitoring unit.

3. A command processing method, characterized in that: Applied to the instruction processing system according to claim 1 or 2, the instruction processing method comprises: Acquire the target instruction, wherein the target instruction includes an operation code and an operand; Determine an opcode matching result according to a preset opcode encoding format and the opcode of the target instruction; In response to the opcode matching result indicating that the encoding format of the opcode of the target instruction does not match the opcode encoding format, determining that the target instruction is an illegal instruction; In response to the opcode matching result indicating that the encoding format of the opcode of the target instruction matches the opcode encoding format, determining the matching format of the opcode of the target instruction; determining the operand form of the operand of the target instruction according to the matching format; in response to the operand form being a register form, determining the target register corresponding to the register form; determining a register matching result between the target register and an existing register; in response to the register matching result indicating that the target register does not match the existing register, determining that the target instruction is an illegal instruction; In response to the target instruction being an illegal instruction, a masking signal is generated to turn off the output of the illegal instruction monitoring unit, and the input of the sampling unit is reset to zero so that the sampling unit outputs an all-zero normalized illegal instruction to the instruction decoding module for decoding to obtain a decoding result, so that the processing unit performs corresponding processing according to the decoding result.

4. The instruction processing method according to claim 3, characterized in that: An ECC error correction module is also provided between the storage unit and the illegal instruction monitoring unit, and the instruction processing method further includes the following steps performed by the ECC error correction module: Obtaining the target instruction; Verifying the target instruction to obtain a first verification result; In response to the first verification result indicating that the target instruction has a one-bit error, the target instruction is error-corrected and then input into the illegal instruction monitoring unit.

5. The instruction processing method according to claim 4, characterized in that: After verifying the target instruction to obtain a first verification result, the instruction processing method further includes: In response to the first verification result indicating that the target instruction has more than one bit error, re-reading the target instruction for verification to obtain a second verification result; In response to the second verification result indicating that the target instruction has more than one bit error, error information is generated, and the target instruction is input to the illegal instruction monitoring unit.

6. The instruction processing method according to claim 5, characterized in that: The ECC error correction module includes an error status register and an error address register, and the error status register includes an instruction error flag bit and an error number bit; The generated error information includes: Setting the instruction error flag in the error status register to an instruction error status; Determine the number of error bits and the error address according to the second check result; Writing the error bit number into the error bit number bit of the error status register; The error address is written into the error address register.

7. The instruction processing method according to claim 6, characterized in that: The instruction processing method further includes: Polling the instruction error flag bit in the error status register; In response to the instruction error flag being in the instruction error state, the control system is reset.

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