Method and device for loading multiple different configuration files, equipment and medium

Abstract

The invention discloses a method, a device, equipment and a medium for loading multiple different configuration files. The method comprises the following steps of: loading a configuration file of which a starting address is a zero address; maintaining the configuration function of the current configuration file, and detecting whether a configuration instruction is received; analyzing the configuration instruction, determining a starting address of a next configuration file, loading a corresponding configuration file, and keeping a corresponding configuration function; and detecting the remaining configuration instructions, and keeping the configuration function of the corresponding configuration file. According to the invention, a plurality of different configuration files are stored in the single FLASH chip, and the FPGA chip can respectively load the plurality of different configuration files and carry out flexible switching according to the configuration instruction, so that the FPGA chip realizes different configuration functions. A plurality of different configuration functions can be realized without a plurality of FLASH chips, so that the number of hardware interfaces is reduced, and the cost is reduced; the use process is simple, and the method is suitable for long-distance program configuration; the system has the advantages of miniaturization, low power consumption, high reliability, high speed and flexibility.

Description

Technical Field

[0001] The present invention relates to the field of FPGA technology, and in particular to a method, device, equipment and medium for loading multiple different configuration files. Background Art

[0002] FPGA (Field-Programmable Gate Array) is a field programmable gate array. Due to its rich wiring resources, repeatable programming, high integration and low power consumption, FPGA has been widely used in the field of digital circuit design.

[0003] At present, the general application method is to use an FPGA chip with a FLASH (flash memory) chip. However, as the functional requirements increase, if more functions are to be implemented in a single FPGA chip, the following three methods are usually used.

[0004] The first is to use a higher-level FPGA chip with more available logic resources. This method requires combining programs with different functions, which will increase the resource occupancy and power consumption of the FPGA chip, increase the difficulty of software design, and increase the design cost, which is not conducive to product miniaturization.

[0005] The second method is to use multiple FLASH chips to store different configuration files. If different configuration files are loaded from the FPGA off-chip configuration chip, the traditional method requires the preparation of multiple FLASH chips, which will increase the hardware connection interface and occupy more printed circuit board size. If a FLASH chip is used to solidify multiple configuration files, although it can meet the above design requirements and reduce design costs, how to achieve flexible switching between different configuration files will be a major difficulty.

[0006] The third method is to burn different configuration files according to different requirements each time. If the configuration file is burned directly through the JTAG interface, the FPGA board needs to reserve a downloader emulator interface, and the wiring process is cumbersome. Each configuration requires repeated disassembly and assembly of the interface, which is not easy to maintain the subsequent program updates. At the same time, it is not suitable for long-distance program configuration due to the limited length. Summary of the invention

[0007] The present invention provides a method, device, equipment and medium for loading multiple different configuration files, so as to solve the problems that when a single FPGA chip needs to realize more configuration functions, the existing method has high software design cost, high power consumption, high hardware cost, complex use process, is not easy to maintain the update of subsequent programs, is not suitable for remote program configuration, has complex product structure, and cannot realize flexible switching between different configuration files.

[0008] In order to solve the above technical problems, the technical solution adopted by the present invention is to provide a method for loading multiple different configuration files, including the following steps: the first step is to power on the FPGA chip and load the configuration file whose startup address in the FLASH chip is the zero address; the second step is to keep the configuration function corresponding to the current configuration file if the loading is successful, and detect whether the configuration instruction is received; the third step is to parse the configuration instruction if the configuration instruction is received, and if the parsing is successful, determine the startup address corresponding to the next configuration file according to the parsed configuration instruction; the fourth step is to jump to the corresponding startup address and load the corresponding configuration file, and keep the configuration function of the corresponding configuration file; the fifth step is to continue to detect the remaining configuration instructions, and repeat the third and fourth steps.

[0009] In some embodiments, it includes the preliminary steps of: designing an ICAPE2 primitive logic circuit, and compiling the ICAPE2 primitive logic circuit into multiple configuration files with different configuration functions; merging multiple configuration files to obtain an MCS file, and burning the MCS file into the FLASH chip; wherein the startup address of each configuration file is different.

[0010] In some embodiments, after the step of parsing the configuration instruction if the configuration instruction is received, the step of: if the parsing fails, waiting to receive the next configuration instruction is also included.

[0011] In some embodiments, before the step of jumping to the corresponding startup address and loading the corresponding configuration file, the step also includes: receiving an IPROG instruction, resetting and clearing the configuration function corresponding to the currently maintained configuration file, and initializing it.

[0012] In some embodiments, determining the startup address corresponding to the next configuration file based on the parsed configuration instruction specifically includes: synchronizing the configuration instruction according to a synchronization word frame, wherein the configuration instruction includes a reload address instruction; and determining the startup address corresponding to the next configuration file using the reload address instruction.

[0013] In some embodiments, the ICAPE2 primitive logic circuit includes at least the following operation tasks: sending a synchronization word frame, determining the startup address, and sending an IPROG instruction.

[0014] In some embodiments, the size of the MCS file is no greater than three times the capacity of the FLASH chip, and the startup address of each of the configuration files is an integer multiple of 64KB.

[0015] The present invention also provides a device for loading multiple different configuration files, including: a storage unit, used to store multiple different configuration files; a detection unit, used to detect whether a configuration instruction is received; a parsing unit, used to parse the configuration instruction; a determination unit, used to determine the startup address corresponding to the next configuration file according to the parsed configuration instruction; a loading unit, used to load multiple different configuration files respectively, and maintain the configuration function corresponding to the current configuration file.

[0016] The present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the above method when executing the computer program.

[0017] The present invention also provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the above method are implemented.

[0018] The beneficial effects of the present invention are as follows: the present invention discloses a method, device, equipment and medium for loading multiple different configuration files, the method comprising the following steps: the first step is to power on the FPGA chip and load the configuration file whose startup address is zero in the FLASH chip; the second step is to keep the configuration function corresponding to the current configuration file if the loading is successful, and detect whether the configuration instruction is received; the third step is to parse the configuration instruction if the configuration instruction is received, and if the parsing is successful, determine the startup address corresponding to the next configuration file according to the parsed configuration instruction; the fourth step is to jump to the corresponding startup address and load the corresponding configuration file to keep the configuration function of the corresponding configuration file; the fifth step is to continue to detect the remaining configuration instructions and repeat the third and fourth steps. The device comprises: a storage unit for storing multiple different configuration files; a detection unit for detecting whether the configuration instruction is received; a parsing unit for parsing the configuration instruction; a determination unit for determining the startup address corresponding to the next configuration file according to the parsed configuration instruction; a loading unit for loading multiple different configuration files respectively and keeping the configuration function corresponding to the current configuration file. The present invention stores multiple different configuration files in a single FLASH chip, and according to the configuration instructions, allows the FPGA chip to load multiple different configuration files and switch them flexibly, so that the FPGA chip can realize different configuration functions as needed. The present invention can realize multiple different configuration functions without multiple FLASH chips, reduces hardware interfaces, and reduces the cost of hardware; the use process is simple and suitable for remote program configuration; the present invention also has the advantages of miniaturization, low power consumption, high reliability, high speed and flexibility. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a flow chart of an embodiment of a method for loading multiple different configuration files of the present application;

[0020] Figure 2 It is a schematic diagram of configuration instructions in an embodiment of a method for loading multiple different configuration files of the present application;

[0021] Figure 3 This is a schematic diagram of address mapping of a FLASH chip in an embodiment of a method for loading multiple different configuration files of the present application;

[0022] Figure 4 It is a structural block diagram of an embodiment of a device for loading multiple different configuration files of the present application;

[0023] Figure 5 It is a schematic diagram of the structure of an electronic device according to an embodiment of the present application;

[0024] Figure 6 It is a schematic block diagram of an embodiment of a computer-readable storage medium of the present application. DETAILED DESCRIPTION

[0025] In order to facilitate the understanding of the present invention, the present invention is described in more detail below in conjunction with the accompanying drawings and specific embodiments. Preferred embodiments of the present invention are provided in the accompanying drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described in this specification. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present invention more thorough and comprehensive.

[0026] It should be noted that, unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used in this specification includes any and all combinations of one or more related listed items.

[0027] In order to facilitate the understanding of the present application, some terms that may be involved in the embodiments of the present application are first explained as follows:

[0028] ICAPE2 (Internal Configuration Access Port Enhanced version 2): It is a primitive in FPGA (Field Programmable Gate Array) that allows users to dynamically reconfigure the FPGA. This primitive provides the ability to reconfigure the internal resources of the FPGA, allowing the FPGA to flexibly adjust its functions as needed.

[0029] FLASH (Flash Memory): Also known as flash memory, it is a long-life non-volatile memory that can retain stored data even when the power is off. Its data is deleted not in units of single bytes, but in fixed blocks, and the block size is generally 256KB-20MB.

[0030] FPGA (Field Programmable Gate Array): is a product further developed on the basis of programmable devices such as PAL (Programmable Array Logic) and GAL (General Array Logic). It appears as a semi-custom circuit in the field of Application Specific Integrated Circuit (ASIC), which not only solves the shortcomings of custom circuits, but also overcomes the shortcomings of the limited number of gate circuits of the original programmable devices.

[0031] Figure 1 The flowchart of the method for loading multiple different configuration files provided by the present application is shown, including the steps of:

[0032] S1: Design the ICAPE2 primitive logic circuit and compile the ICAPE2 primitive logic circuit into multiple configuration files with different configuration functions.

[0033] S2: Merge multiple configuration files to obtain an MCS file, and burn the MCS file into the FLASH chip.

[0034] S3: Power on the FPGA chip and load the configuration file whose startup address in the FLASH chip is address zero.

[0035] S4: If the loading is successful, the configuration function corresponding to the current configuration file is maintained, and it is detected whether the configuration instruction is received.

[0036] S5: If a configuration instruction is received, the configuration instruction is parsed. If the parsing is successful, the startup address corresponding to the next configuration file is determined according to the parsed configuration instruction.

[0037] S6: Jump to the corresponding startup address, load its corresponding configuration file, and maintain the configuration function of the corresponding configuration file.

[0038] S7: Continue to detect the remaining configuration instructions, and repeat S5 and S6.

[0039] The present invention stores multiple different configuration files in a single FLASH chip, and according to the configuration instructions, allows the FPGA chip to load multiple different configuration files and switch them flexibly, so that the FPGA chip can realize different configuration functions as needed. The present invention can realize multiple different configuration functions without multiple FLASH chips, reduces hardware interfaces, and reduces the cost of hardware; the use process is simple and suitable for remote program configuration; the present invention also has the advantages of miniaturization, low power consumption, high reliability, high speed and flexibility.

[0040] Combine the following Figures 1 to 6 , this application is described in detail with specific embodiments.

[0041] S1: Design the ICAPE2 primitive logic circuit and compile the ICAPE2 primitive logic circuit into multiple configuration files with different configuration functions.

[0042] The ICAPE2 primitive logic circuit includes at least the following operation tasks: sending synchronization word frames, determining the startup address, and sending IPROG instructions. Users can write and design the corresponding ICAPE2 primitive logic circuit according to their needs, so that the FPGA chip can realize different functions.

[0043] In this embodiment, combined with Figure 2 As shown, AA99_5566 represents a synchronization word frame, which is used to synchronize subsequent configuration instructions, such as synchronizing the empty instruction (2000_0000) and the reload address instruction (3002_0001) below AA99_5566; determining the startup address refers to determining the startup address where the corresponding configuration file is located; the function of the IPROG instruction is to reset the FPGA chip.

[0044] Furthermore, a configuration file is a computer file used to define and configure the logic circuits and functions inside the FPGA chip.

[0045] S2: Merge multiple configuration files to obtain an MCS file, and burn the MCS file into the FLASH chip.

[0046] Specifically, use the MCS file generation tool to merge multiple configuration files to obtain an MCS file that can be solidified (i.e. burned) in the FLASH chip; wherein the MCS file (Microcontroller Hexadecimal File) is a file format for storing FPGA chip configuration bit streams, usually encoded in hexadecimal format, and used to configure FPGA chips.

[0047] Among them, combined Figure 3As shown, after burning, the startup address of each configuration file in the FLASH chip is different. For example, among n configuration files, the startup address of configuration file 1 is address 0, and the startup address of configuration file 2 is address 1.

[0048] In this embodiment, according to different erasing or reading formats of the FLASH chip, the startup address of each configuration file is an integer multiple of 64KB. Therefore, the size of the entire MCS file after merging is no more than three times the capacity of the FLASH chip (ie, the virtual address).

[0049] S3: Power on the FPGA chip and load the configuration file whose startup address in the FLASH chip is address zero.

[0050] Specifically, first power on the FPGA chip to provide it with a suitable power supply voltage for normal operation. After powering on, the FPGA chip automatically loads the configuration file with the startup address of the FLASH chip as zero address (i.e. address 0) by default. Figure 3 Configuration file 1 in.

[0051] If the loading fails, continue to reload the configuration file until it succeeds.

[0052] S4: If the loading is successful, the configuration function corresponding to the current configuration file is maintained, and it is detected whether the configuration instruction is received.

[0053] Specific, combined Figure 3 If the configuration file 1 at address 0 is loaded successfully, the FPGA chip currently maintains the configuration function corresponding to the configuration file 1.

[0054] Furthermore, the FPGA chip starts to detect whether the ICAPE2 interface has received the configuration instruction.

[0055] Among them, the ICAPE2 interface is an internal configuration access port in the FPGA chip, which allows the FPGA chip to introspect and access the internal configuration state.

[0056] like Figure 2 As shown, the configuration instructions include a reload address instruction (3002_0001), which is used to determine the startup address corresponding to the next configuration file; in this embodiment, the configuration instructions may also include an idle data instruction (FFFF_FFFF), a synchronization word frame instruction (AA99_5566), a null instruction (2000_0000), an enable instruction (3000_8001), etc., which can be designed and added as needed.

[0057] S5: If a configuration instruction is received, the configuration instruction is parsed. If the parsing is successful, the startup address corresponding to the next configuration file is determined according to the parsed configuration instruction.

[0058] Specific, combined Figure 2 If the ICAPE2 interface receives a configuration instruction, the FPGA chip will parse the configuration instruction. After the parsing is successful, the remaining multiple different instructions in the configuration instruction are synchronized according to the synchronization word frame instruction (i.e., AA99_5566). The reload address instruction (3002_0001) in the configuration instruction is used to determine the startup address corresponding to the next configuration file. For example, combined with Figure 3 As shown, if the next required configuration file is configuration file 3, then its corresponding startup address is address 2.

[0059] If the FPGA chip fails to parse the configuration instruction, such as an abnormality in the external environment during parsing, causing the FPGA chip to be powered off, further causing data in the configuration instruction to be lost, then it continues to wait for the ICAPE2 interface to receive the next configuration instruction.

[0060] S6: Jump to the corresponding startup address, load its corresponding configuration file, and maintain the configuration function of the corresponding configuration file.

[0061] In S5, after determining the startup address corresponding to the next configuration file, the FPGA chip will receive the IPROG instruction, and use the IPROG instruction to reset and clear the configuration function corresponding to the configuration file currently held by the FPGA chip, and initialize it.

[0062] For example, combined with Figure 3 , if the current configuration file is configuration file 1, the configuration function corresponding to configuration file 1 maintained by the FPGA chip will be reset and cleared to allow the FPGA chip to further load the next configuration file and maintain its corresponding configuration function to avoid conflicts. It should be noted that if the configuration function corresponding to configuration file 1 contains a specific configuration logic function, the specific configuration logic function will be retained and the rest will be reset and cleared.

[0063] Furthermore, after the FPGA chip is initialized, it can jump to the startup address where the next configuration file in the FLASH chip is located, and load the configuration file while maintaining its corresponding configuration function.

[0064] S7: Continue to detect the remaining configuration instructions, and repeat S5 and S6.

[0065] Furthermore, the next configuration instruction is continuously detected and received in real time through the ICAPE2 interface, so as to realize the real-time switching of different configuration functions in the FPGA chip.

[0066] Specifically, different configuration instructions are received in real time and continuously through the ICAPE2 interface, different configuration files are loaded, and different configuration functions are maintained until all required configuration files are loaded and can be used.

[0067] Based on the same inventive concept, Figure 4 As shown, the present application also provides a device for loading multiple different configuration files, the device comprising:

[0068] The storage unit 101 is used to store a plurality of different configuration files.

[0069] The detection unit 102 is used to detect whether a configuration instruction is received.

[0070] The parsing unit 103 is used to parse the configuration instruction.

[0071] The determination unit 104 is used to determine the startup address corresponding to the next configuration file according to the parsed configuration instruction.

[0072] The loading unit 105 is used to load a plurality of different configuration files respectively and maintain the configuration functions corresponding to the current configuration files.

[0073] Correspondingly, each functional unit is used to implement its respective corresponding function, and reference may be made to the description in the aforementioned corresponding method embodiments, which will not be repeated here.

[0074] Based on the same inventive concept, the present application also provides an electronic device, which includes a processor, a memory and a communication circuit, wherein the processor is connected to the memory and the communication circuit respectively; wherein the communication circuit is used for communication connection, the memory is used to store a computer program, and the processor is used to execute the computer program to implement the above-mentioned method of loading multiple different configuration files.

[0075] See also Figure 5 The electronic device described in the embodiment of the present application may specifically include a processor 210 and a memory 220. The memory 220 is coupled to the processor 210.

[0076] The processor 210 is used to control the operation of the electronic device. The processor 210 may also be referred to as a CPU (Central Processing Unit). The processor 210 may be an integrated circuit chip having the ability to process signals. The processor 210 may also be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. A general-purpose processor may be a microprocessor or the processor 210 may also be any conventional processor, etc.

[0077] The memory 220 is used to store computer programs, and may be a RAM, a ROM, or other types of storage terminals. Specifically, the memory 220 may include one or more computer-readable storage media, which may be non-transitory or transient. The memory 220 may also include a high-speed random access memory, and a non-volatile memory, such as one or more disk storage terminals, flash memory storage terminals. In some embodiments, the non-transitory computer-readable storage medium in the memory 220 is used to store at least one program code.

[0078] The processor 210 is used to execute the computer program stored in the memory 220 to implement the methods described in the various method embodiments of the present application.

[0079] In some embodiments, the electronic device may further include: a peripheral terminal interface 230 and at least one peripheral terminal. The processor 210, the memory 220 and the peripheral terminal interface 230 may be connected via a bus or a signal line. Each peripheral terminal may be connected to the peripheral terminal interface 230 via a bus, a signal line or a circuit board. Specifically, the peripheral terminal includes: at least one of a radio frequency circuit 240, a display screen 250, an audio circuit 260 and a power supply 270.

[0080] The peripheral terminal interface 230 may be used to connect at least one peripheral terminal related to I / O (Input / output) to the processor 210 and the memory 220. In some embodiments, the processor 210, the memory 220, and the peripheral terminal interface 230 are integrated on the same chip or circuit board; in some other implementations, any one or two of the processor 210, the memory 220, and the peripheral terminal interface 230 may be implemented on a separate chip or circuit board, which is not limited in this embodiment.

[0081] The radio frequency circuit 240 is used to receive and transmit RF (Radio Frequency) signals, also known as electromagnetic signals. The radio frequency circuit 240 communicates with the communication network and other IoT devices through electromagnetic signals, and the radio frequency circuit 240 is the communication circuit of the electronic device. The radio frequency circuit 240 converts the electrical signal into an electromagnetic signal for transmission, or converts the received electromagnetic signal into an electrical signal. Optionally, the radio frequency circuit 240 includes: an antenna system, an RF transceiver, one or more amplifiers, a tuner, an oscillator, a digital signal processor, a codec chipset, an operator identity module card, and the like. The radio frequency circuit 240 can communicate with other terminals through at least one wireless communication protocol. The wireless communication protocol includes, but is not limited to: the World Wide Web, a metropolitan area network, an intranet, various generations of mobile communication networks (2G, 3G, 4G and 5G), a wireless local area network and / or a WiFi (Wireless Fidelity) network. In some embodiments, the radio frequency circuit 240 may also include circuits related to NFC (Near Field Communication), which is not limited in this application.

[0082] The display screen 250 is used to display the UI (User Interface). The UI may include graphics, text, icons, videos, and any combination thereof. When the display screen 250 is a touch display screen, the display screen 250 also has the ability to collect touch signals on the surface or above the surface of the display screen 250. The touch signal can be input to the processor 210 as a control signal for processing. At this time, the display screen 250 can also be used to provide virtual buttons and / or virtual keyboards, also known as soft buttons and / or soft keyboards. In some embodiments, the display screen 250 can be one, set on the front panel of the electronic device; in other embodiments, the display screen 250 can be at least two, respectively set on different surfaces of the electronic device or in a folding design; in other embodiments, the display screen 250 can be a flexible display screen, set on a curved surface or a folding surface of the electronic device. Even, the display screen 250 can also be set to a non-rectangular irregular shape, that is, a special-shaped screen. The display screen 250 can be made of materials such as LCD (Liquid Crystal Display), OLED (Organic Light-Emitting Diode, organic light-emitting diode).

[0083] The audio circuit 260 may include a microphone and a speaker. The microphone is used to collect sound waves from the operator and the environment, and convert the sound waves into electrical signals and input them into the processor 210 for processing, or input them into the radio frequency circuit 240 to achieve voice communication. For the purpose of stereo acquisition or noise reduction, there may be multiple microphones, which are respectively arranged in different parts of the electronic device. The microphone may also be an array microphone or an omnidirectional acquisition microphone. The speaker is used to convert the electrical signal from the processor 210 or the radio frequency circuit 240 into sound waves. The speaker may be a traditional film speaker or a piezoelectric ceramic speaker. When the speaker is a piezoelectric ceramic speaker, it can not only convert the electrical signal into sound waves audible to humans, but also convert the electrical signal into sound waves inaudible to humans for purposes such as ranging. In some embodiments, the audio circuit 260 may also include a headphone jack.

[0084] The power supply 270 is used to power various components in the electronic device. The power supply 270 can be an alternating current, a direct current, a disposable battery, or a rechargeable battery. When the power supply 270 includes a rechargeable battery, the rechargeable battery can be a wired rechargeable battery or a wireless rechargeable battery. A wired rechargeable battery is a battery that is charged through a wired line, and a wireless rechargeable battery is a battery that is charged through a wireless coil. The rechargeable battery can also be used to support fast charging technology.

[0085] For a detailed description of the functions and execution processes of each functional module or component in the electronic device embodiment of the present application, reference can be made to the description in the above-mentioned method embodiments of the present application, which will not be repeated here.

[0086] In the several embodiments provided in the present application, it should be understood that the disclosed electronic devices and methods can be implemented in other ways. For example, the various embodiments of the electronic devices described above are only schematic. For example, the division of modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0087] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0088] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0089] Based on the same inventive concept, the present application also provides a computer-readable storage medium storing a computer program, which can be executed by a processor to implement the above method of loading multiple different configuration files.

[0090] See also Figure 6 , if the above-mentioned integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium 300. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including several instructions / computer programs to enable an IoT device (which can be a personal computer, server, or network terminal, etc.) or a processor (processor) to perform all or part of the steps of each implementation method of the present application. The aforementioned storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), magnetic disks or optical disks, and electronic terminals such as computers, mobile phones, laptops, tablet computers, cameras, etc. having the above-mentioned storage media.

[0091] The description of the execution process of the program data in the computer-readable storage medium can refer to the description in the above-mentioned method embodiments of the present application, and will not be repeated here.

[0092] It can be seen that the present invention discloses a method, device, equipment and medium for loading multiple different configuration files, the method comprising the following steps: the first step is to power on the FPGA chip and load the configuration file whose startup address is zero in the FLASH chip; the second step is to keep the configuration function corresponding to the current configuration file if the loading is successful, and detect whether the configuration instruction is received; the third step is to parse the configuration instruction if the configuration instruction is received, and if the parsing is successful, determine the startup address corresponding to the next configuration file according to the parsed configuration instruction; the fourth step is to jump to the corresponding startup address and load the corresponding configuration file to keep the configuration function of the corresponding configuration file; the fifth step is to continue to detect the remaining configuration instructions and repeat the third and fourth steps. The device comprises: a storage unit for storing multiple different configuration files; a detection unit for detecting whether the configuration instruction is received; a parsing unit for parsing the configuration instruction; a determination unit for determining the startup address corresponding to the next configuration file according to the parsed configuration instruction; a loading unit for loading multiple different configuration files respectively and keeping the configuration function corresponding to the current configuration file. The present invention stores multiple different configuration files in a single FLASH chip, and according to the configuration instructions, allows the FPGA chip to load multiple different configuration files and switch them flexibly, so that the FPGA chip can realize different configuration functions as needed. The present invention can realize multiple different configuration functions without multiple FLASH chips, reduces hardware interfaces, and reduces the cost of hardware; the use process is simple and suitable for remote program configuration; the present invention also has the advantages of miniaturization, low power consumption, high reliability, high speed and flexibility.

[0093] The above are only embodiments of the present invention, and are not intended to limit the protection scope of the present invention. Any equivalent structural transformations made using the contents of the present invention description and drawings, or directly or indirectly applied in other related technical fields, are included in the protection scope of the present invention.

Claims

1. A method for loading multiple different configuration files, characterized in that: Includes steps: The first step is to power on the FPGA chip and load the configuration file whose startup address is zero in the FLASH chip; The second step is to keep the configuration function corresponding to the current configuration file if the loading is successful, and detect whether the configuration instruction is received; The third step is to parse the configuration instruction if it is received, and if the parsing is successful, determine the startup address corresponding to the next configuration file according to the parsed configuration instruction; The fourth step is to jump to the corresponding startup address and load the corresponding configuration file, and keep the configuration function of the corresponding configuration file; Step 5: Continue to detect the remaining configuration instructions and repeat steps 3 and 4.

2. The method according to claim 1, characterized in that: It includes the following pre-steps: Designing an ICAPE2 primitive logic circuit, and compiling the ICAPE2 primitive logic circuit into a plurality of configuration files with different configuration functions; Merge the multiple configuration files to obtain an MCS file, and burn the MCS file into the FLASH chip; The startup address of each configuration file is different.

3. The method according to claim 1, characterized in that After the step of parsing the configuration instruction if the configuration instruction is received, the method further includes the following steps: If the parsing fails, wait for receiving the next configuration instruction.

4. The method according to claim 1, characterized in that: Before the step of jumping to the corresponding startup address and loading the corresponding configuration file, the step further includes: Receive the IPROG instruction, reset and clear the configuration function corresponding to the currently maintained configuration file, and initialize it.

5. The method according to claim 1, characterized in that Determining the startup address corresponding to the next configuration file according to the parsed configuration instruction specifically includes: synchronizing the configuration instructions according to a synchronization word frame, wherein the configuration instructions include a reload address instruction; The reload address instruction is used to determine the startup address corresponding to the next configuration file.

6. The method according to claim 2, characterized in that The ICAPE2 primitive logic circuit includes at least the following operation tasks: sending a synchronization word frame, determining the startup address, and sending an IPROG instruction.

7. The method according to claim 2, characterized in that The size of the MCS file is no greater than three times the capacity of the FLASH chip, and the startup address of each of the configuration files is an integer multiple of 64KB.

8. A device for loading multiple different configuration files, characterized in that: include: A storage unit, used for storing a plurality of different configuration files; A detection unit, used to detect whether a configuration instruction is received; A parsing unit, used for parsing the configuration instruction; A determination unit, configured to determine a startup address corresponding to the next configuration file according to the parsed configuration instruction; The loading unit is used to load a plurality of different configuration files respectively and maintain the configuration function corresponding to the current configuration file.

9. An electronic device, characterized in that: The method comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the method according to any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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