Preparation method of semiconductor structure, semiconductor structure, device and equipment

Abstract

The invention provides a preparation method of a semiconductor structure, the semiconductor structure, a device and equipment. The method comprises the following steps: providing a substrate; the substrate comprises a transverse diffusion region and a core region; performing ion implantation in the transverse diffusion region to form a P-type well region and an N-type drift region; etching the transverse diffusion region and the core region to form a fin-shaped structure; the fin-shaped structure comprises a first fin-shaped structure and a second fin-shaped structure which are stacked in the first direction; performing first fin cutting processing on the first fin-shaped structure to form a first fin cutting groove; filling the first fin-cut trench with an oxide; forming a first transistor based on the first fin-shaped structure; reversing the wafer and removing the substrate; performing second fin cutting processing on the second fin-shaped structure to form a second fin cutting groove; filling the second fin-cut trench with an oxide; and forming a second transistor based on the second fin-shaped structure. According to the invention, the process compatibility between the transverse diffusion device and the stacked transistor can be realized.

Description

Technical Field

[0001] The present application relates to the semiconductor field, and in particular to a method for preparing a semiconductor structure, a semiconductor structure, a device and an apparatus. Background Art

[0002] As the performance of FinFET (fin field-effect transistor) approaches its limit, a laterally-diffused metal-oxide semiconductor (LDMOS) process based on a new structure is to be developed, which will help further miniaturize the size of transistors. Transistor stacking is considered to be a very promising miniaturization method. At present, as a part of the supporting circuit module, how to achieve process compatibility with stacked transistors for FinFET LDMOS is still a problem that needs to be solved urgently. Summary of the invention

[0003] The present application provides a method for preparing a semiconductor structure, a semiconductor structure, a device and an apparatus to achieve process compatibility between a lateral diffusion device and a stacked transistor.

[0004] In a first aspect, an embodiment of the present application provides a method for preparing a semiconductor structure, wherein the semiconductor structure includes a lateral diffusion device and a core device, wherein the core device includes a first transistor and a second transistor stacked along a first direction; the semiconductor structure also includes a lateral diffusion device, wherein the lateral diffusion device is arranged side by side with the first transistor or arranged side by side with the second transistor; the above method includes: providing a substrate; the substrate includes a lateral diffusion region and a core region; the lateral diffusion region and the core region are adjacently arranged in a second direction; the second direction is perpendicular to the first direction; ion implantation is performed in the lateral diffusion region to form a P-type well region and an N-type drift region; the lateral diffusion region and the core region are etched to form a fin-shaped structure; the fin structure includes a first fin structure and a second fin structure stacked along the first direction; a first fin cutting process is performed on the first fin structure to form a first fin cutting groove; the first fin cutting groove is perpendicular to the extension direction of the first fin structure ... The etching depth of the first fin cut process is half of the height of the fin structure; oxide is filled in the first fin cut groove; based on the first fin structure, a first transistor is formed; flipping and removing the substrate; performing a second fin cut process on the second fin structure to form a second fin cut groove; the second fin cut groove is perpendicular to the extension direction of the second fin structure; the etching depth of the second fin cut process is equal to the height of the fin structure or half of the height of the fin structure; oxide is filled in the second fin cut groove; based on the second fin structure, a second transistor is formed; wherein the method also includes: while performing the first fin cut process on the first fin structure, a first groove is formed in the N-type drift region corresponding to the first fin structure, and a lateral diffusion device is formed based on the first groove, or, while performing the second fin cut process on the second fin structure, a first groove is formed in the N-type drift region corresponding to the second fin structure, and a lateral diffusion device is formed based on the first groove; the first groove is used to fill the oxide.

[0005] In some possible embodiments, a first fin-cut process is performed on the first fin-like structure to form a first fin-cut groove, including: performing a first fin-cut process on the first fin-like structure to form a first fin-cut groove in a core area corresponding to the first fin-like structure, and forming a first groove in an N-type drift area corresponding to the first fin-like structure; filling the first fin-cut groove with oxide, including: depositing oxide on the fin-like structure and a substrate to form a shallow trench isolation structure; the shallow trench isolation structure wraps the fin-like structure and fills the first groove and the first fin-cut groove.

[0006] In some possible embodiments, a first transistor is formed based on a first fin structure, including: forming a first dummy gate structure in the first transistor and a second dummy gate structure in the lateral diffusion device based on the first fin structure; etching a portion of the first fin structure to form a first source-drain groove and a second source-drain groove; performing source-drain epitaxial growth in the first source-drain groove and the second source-drain groove to form a first source-drain structure in the first transistor and a second source-drain structure in the lateral diffusion device; removing the first dummy gate structure and the second dummy gate structure, and forming a first gate structure in the first transistor and a second gate structure in the lateral diffusion device; forming a first source-drain metal in the first transistor and a second source-drain metal in the lateral diffusion device on the first source-drain structure and the second source-drain structure; performing post-processing on the first gate structure, the second gate structure, the first source-drain metal, and the second source-drain metal to form a first metal interconnection layer in the first transistor and a second metal interconnection layer in the lateral diffusion device.

[0007] In some possible embodiments, a second transistor is formed based on a second fin structure, including: forming a third dummy gate structure in the second transistor based on the second fin structure; etching a portion of the second fin structure to form a third source-drain groove; performing source-drain epitaxial growth in the third source-drain groove to form a third source-drain structure in the second transistor; removing the third dummy gate structure and forming a third gate structure in the second transistor; forming a third source-drain metal in the second transistor on the third source-drain structure; performing a post-processing on the third gate structure and the third source-drain metal to form a third metal interconnect layer in the second transistor and a back dielectric layer in the isolation device; and the lateral diffusion device and the isolation device are stacked along a first direction.

[0008] In some possible embodiments, a second fin-cut process is performed on the second fin structure to form a second fin-cut groove, including: performing a second fin-cut process on the second fin structure to form a second fin-cut groove in a core area corresponding to the second fin structure, and forming a first groove in an N-type drift area corresponding to the second fin structure; filling oxide in the second fin-cut groove, including: filling oxide in the second fin-cut groove and the first groove.

[0009] In some possible embodiments, a first transistor is formed based on a first fin structure, including: forming a first dummy gate structure in the first transistor based on the first fin structure; etching a portion of the first fin structure to form a first source-drain groove; performing source-drain epitaxial growth in the first source-drain groove to form a first source-drain structure in the first transistor; removing the first dummy gate structure and forming a first gate structure in the first transistor; forming a first source-drain metal in the first transistor on the first source-drain structure; performing a post-processing on the first gate structure and the first source-drain metal to form a first metal interconnect layer in the first transistor and a front dielectric layer in the isolation device; the isolation device and the lateral diffusion device are stacked along a first direction.

[0010] In some possible embodiments, a second transistor is formed based on a second fin structure, including: forming a third dummy gate structure in the second transistor and a second dummy gate structure in the lateral diffusion device based on the second fin structure; etching a portion of the second fin structure to form a third source-drain groove and a second source-drain groove; performing source-drain epitaxial growth in the third source-drain groove and the second source-drain groove to form a third source-drain structure in the second transistor and a second source-drain structure in the lateral diffusion device; removing the third dummy gate structure and the second dummy gate structure, and forming a third gate structure in the second transistor and a second gate structure in the lateral diffusion device; forming a third source-drain metal in the second transistor and a second source-drain metal in the lateral diffusion device on the third source-drain structure and the second source-drain structure; performing post-processing on the third gate structure, the second gate structure, the third source-drain metal, and the second source-drain metal to form a third metal interconnection layer in the second transistor and a second metal interconnection layer in the lateral diffusion device.

[0011] In a second aspect, an embodiment of the present application provides a semiconductor structure, which is prepared by a method as in any of the above embodiments, and the semiconductor structure includes: a core device; the core device includes a first transistor and a second transistor stacked along a first direction; a lateral diffusion device; the lateral diffusion device is arranged side by side with the first transistor or side by side with the second transistor; an isolation device; the isolation device and the lateral diffusion device are stacked in the first direction; wherein the lateral diffusion device includes a P-type well region and an N-type drift region; a first groove is arranged in the N-type drift region in the lateral diffusion device, and the first groove is used to fill oxide.

[0012] In a third aspect, an embodiment of the present application provides a semiconductor device, which includes: a semiconductor structure as described in the above embodiment.

[0013] In a fourth aspect, an embodiment of the present application provides an electronic device, which includes: a circuit board and a semiconductor device as described in the above embodiment, wherein the semiconductor device is arranged on the circuit board.

[0014] In the present application, by forming a first groove in the N-type drift region and filling the first groove with oxide while performing a first fin cut process on the first fin structure or a second fin cut process on the second fin structure, the formed lateral diffusion device can withstand higher voltages while being compatible with the process of preparing stacked transistors, thereby optimizing the preparation process of the semiconductor structure.

[0015] Furthermore, when the second fin structure is subjected to the second fin cutting process, different etching depths can be selected according to actual needs, that is, the etching depth of the second fin cutting process is equal to the height of the fin structure or equal to half the height of the fin structure, making the layout of the internal devices of the semiconductor structure more flexible.

[0016] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0018] Figure 1 A schematic diagram of an implementation process of a method for preparing a semiconductor structure in an embodiment of the present application;

[0019] Figure 2 A design layout of a semiconductor structure in an embodiment of the present application;

[0020] Figure 3 This is a schematic diagram of the first structure of the semiconductor structure in the embodiment of the present application;

[0021] 4A to 4D A schematic diagram of a first preparation process of a semiconductor structure in an embodiment of the present application;

[0022] Figure 5 This is a schematic diagram of a second structure of a semiconductor structure in an embodiment of the present application;

[0023] Figure 6 A schematic diagram of a second preparation process of a semiconductor structure in an embodiment of the present application;

[0024] Figure 7 This is a schematic diagram of a third structure of a semiconductor structure in an embodiment of the present application;

[0025] The above pictures:

[0026] 10. semiconductor structure; 11. first transistor; 111. first spacer; 112. first source-drain structure; 113. first interlayer dielectric layer; 114. first gate dielectric layer; 115. first gate structure; 116. first source-drain metal; 12. lateral diffusion device; 121. second spacer; 122. second source-drain structure; 123. second interlayer dielectric layer; 124. second gate dielectric layer; 125. second gate structure; 126. second source-drain metal; 13. second transistor; 131. third spacer; 132. third source-drain structure; 133. third interlayer dielectric layer; 134. third gate dielectric layer; 13 5. third gate structure; 136. third source-drain metal; 14. isolation device; 143. fourth interlayer dielectric layer; 15. first insulating layer; 16. carrier wafer; 21. substrate; 22. fin structure; 221. first fin structure; 222. second fin structure; 231. first fin-cut groove; 232. second fin-cut groove; 24. first groove; 25. shallow trench isolation structure; 251. shallow trench isolation layer; 261. first gate oxide layer; 262. second gate oxide layer; 271. first contact layer; 272. second contact layer; 311. first dummy gate structure; 312. second dummy gate structure; 313. third dummy gate structure. DETAILED DESCRIPTION

[0027] Here, exemplary embodiments are described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application.

[0028] In some embodiments, the LDMOS structure seeks to obtain a higher breakdown voltage and a lower on-resistance. In order to increase the breakdown voltage, there is a drift region between the source region and the drain region. The impurity concentration of the drift region is low, presenting a high resistance state, and thus being able to withstand a higher voltage. The LDMOS drift region uses STI (shallow trench isolation) / field oxygen technology, which makes the current path blocked and longer, thereby further improving the voltage resistance. In order to further shrink the size, LDMOS based on FinFET (finfield-effect transistor) technology has received widespread attention. Taking nLDMOS as an example, a P-well and an N-type drift region are injected into a p-type substrate, where the source region is located in the P-well, the drain region and STI are located in the N-type drift region, and the gate covers the channel region, part of the N-type drift region and part of the STI region.

[0029] As FinFET performance approaches its limit, LDMOS processes based on new structures are to be developed, which will help further shrink the size of transistors. Transistor stacking is considered to be a very promising way to shrink transistors, for example, complementary field effect transistor (CFETs) technology. However, there are also some problems, such as: (1) thermal stability of the bottom layer device when making the upper layer device; (2) performance of the top layer device under low thermal budget; (3) metal interconnection between transistors between layers.

[0030] At present, as a part of the supporting circuit module, how to achieve process compatibility with stacked transistors for FinFET LDMOS is still a problem that needs to be solved urgently.

[0031] In order to solve the above technical problems, an embodiment of the present application provides a method for preparing a semiconductor structure to achieve process compatibility between a lateral diffusion device and a stacked transistor.

[0032] In the embodiments of the present application, the semiconductor structure described above can be applied to semiconductor devices such as memory and processor.

[0033] In some possible embodiments, the semiconductor structure includes: a core device; the core device includes a first transistor and a second transistor stacked along a first direction; a lateral diffusion device; the lateral diffusion device is arranged side by side with the first transistor or side by side with the second transistor; an isolation device; the isolation device and the lateral diffusion device are stacked in the first direction; wherein the lateral diffusion device includes a P-type well region and an N-type drift region; a first groove is arranged in the N-type drift region in the lateral diffusion device, and the first groove is used to fill oxide.

[0034] It is understandable that the semiconductor structure mentioned in the embodiment of the present application includes a lateral diffusion device (i.e., LDMOS) and a core device. The lateral diffusion device and the core device can be arranged adjacent to each other, or can be arranged at intervals, or can be arranged in other forms, and the embodiment of the present application does not specifically limit this. It should be noted that the semiconductor structure may include multiple lateral diffusion devices and multiple core devices. The lateral diffusion devices and core devices in the same semiconductor structure are prepared based on the same substrate (i.e., wafer). For ease of explanation, the embodiment of the present application takes the semiconductor structure including a lateral diffusion device and a core device as an example for explanation.

[0035] In some embodiments, the lateral diffusion device in the semiconductor structure is only arranged on the front side or the back side of the semiconductor structure, that is, the lateral diffusion device is arranged side by side with the first transistor or side by side with the second transistor. The isolation device and the lateral diffusion device are stacked in the first direction, when the lateral diffusion device is arranged side by side with the first transistor, the isolation device is arranged side by side with the second transistor; when the lateral diffusion device is arranged side by side with the second transistor, the isolation device is arranged side by side with the first transistor.

[0036] In the embodiment of the present application, the core device includes a first transistor and a second transistor which are stacked, and the first transistor and the second transistor are arranged back to back to form a stacked transistor. The first transistor and the second transistor can be transistors of the same type, such as fin field effect transistors.

[0037] Figure 2 It is a semiconductor structure composed of fin field effect transistors and lateral diffusion devices. Figure 2 As shown, the semiconductor structure includes a lateral diffusion device and a core device, the core device includes a first transistor and a second transistor stacked along a first direction; the semiconductor structure also includes a lateral diffusion device, the lateral diffusion device is arranged side by side with the first transistor or arranged side by side with the second transistor. Figure 2 The semiconductor structure shown illustrates the method for preparing the semiconductor structure provided in the embodiment of the present application.

[0038] Figure 1 FIG. 1 is a schematic diagram of an implementation process of a method for preparing a semiconductor structure in an embodiment of the present application, see Figure 1 As shown, the method for preparing the semiconductor structure may include:

[0039] S101, providing a substrate.

[0040] The substrate includes a lateral diffusion region and a core region; the lateral diffusion region and the core region are adjacently arranged in a second direction; and the second direction is perpendicular to the first direction.

[0041] It can be understood that the substrate includes a lateral diffusion region for forming lateral diffusion devices and isolation devices and a core region for forming core devices. The lateral diffusion region and the core region can be arranged adjacent to each other.

[0042] In some embodiments, the semiconductor structure is a stacked transistor, and accordingly, the lateral diffusion device and the isolation device are stacked; the first transistor and the second transistor in the core device are stacked.

[0043] In some embodiments, the substrate may be a Si substrate made of a silicon (Si) material, or other forms of substrates may be selected according to actual needs, such as a silicon-on-insulator (SOI) substrate.

[0044] S102, performing ion implantation in the lateral diffusion region to form a P-type well region and an N-type drift region.

[0045] It can be understood that, using the mask process flow, ion implantation can be performed twice in the lateral diffusion region to form a high-concentration P-type well region and a low-concentration N-type drift region, respectively. In the process of ion implantation, the P-type well region can be formed first, and then the N-type drift region; or the N-type drift region can be formed first, and then the P-type well region. It should be noted that the injection method of the N-type drift region can be selected according to actual needs, whether it is a whole-piece injection or a partial injection, and the embodiment of the present application does not specifically limit this; a PN junction in the horizontal direction (i.e., the second direction mentioned above) can be formed between the N-type drift region and the P-well.

[0046] S103, etching the lateral diffusion region and the core region to form a fin structure.

[0047] The fin structure includes a first fin structure and a second fin structure stacked along a first direction.

[0048] It can be understood that by etching the substrate, a fin structure (fin) can be formed. The fin structure in the lateral diffusion region is used to form a lateral diffusion device and an isolation device, and the fin structure in the core region is used to form a core device. The fin structure can be divided into two parts, the upper part is the first fin structure, and the lower part is the second fin structure. Among them, the first fin structure located in the lateral diffusion region is used to form a lateral diffusion device or an isolation device, and the second fin structure located in the lateral diffusion region is used to form an isolation device or a lateral diffusion device; the first fin structure located in the core region is used to form a first transistor, and the second fin structure located in the core region is used to form a second transistor.

[0049] S104, performing a first fin cutting process on the first fin-shaped structure to form a first fin cutting groove, wherein the first fin cutting groove is perpendicular to the extension direction of the first fin-shaped structure; and the etching depth of the first fin cutting process is half of the height of the fin-shaped structure.

[0050] It is understandable that after the fin-shaped structure is formed, the first fin-shaped structure may be fincut by photolithography to form a first fincut groove; the etching depth is half of the height of the fin-shaped structure, ie, half depth.

[0051] S105 , filling the first fin cut trench with oxide.

[0052] It can be understood that after forming the first fin-cut trench, a shallow trench isolation (STI) structure may be formed by depositing oxide on the substrate and the fin-shaped structure, and while forming the shallow trench isolation structure, the first fin-cut trench is filled with oxide.

[0053] S106 , forming a first transistor based on the first fin structure.

[0054] It can be understood that after the first fin-cut trench is filled with oxide, the first transistor can be formed according to a standard process for manufacturing a transistor.

[0055] S107, flip the wafer and remove the substrate.

[0056] It can be understood that after the first transistor is formed, in order to prepare the second transistor, the first transistor can be flipped and the substrate can be removed so that the second fin structure is placed upward.

[0057] In some possible implementations, before the above S107, the method for preparing the above semiconductor structure may further include: depositing an insulating material on the upper surface of the first transistor to form an insulating layer; and bonding the insulating layer to the carrier wafer.

[0058] In the embodiment of the present application, the bonded carrier wafer can provide physical support for the flipped first transistor after inversion, thereby effectively preventing the first transistor from being broken by external force during the preparation of the second transistor.

[0059] S108, performing a second fin cutting process on the second fin structure to form a second fin cutting groove, wherein the second fin cutting groove is perpendicular to the extension direction of the second fin structure; and the etching depth of the second fin cutting process is equal to the height of the fin structure or equal to half of the height of the fin structure.

[0060] It is understandable that after exposing the second fin structure, the second fin structure may be fin-cut by photolithography to form a second fin-cut groove. The etching depth may be half of the height of the fin structure or equal to the height of the fin structure, that is, half depth or full depth.

[0061] In the embodiment of the present application, when the second fin-shaped structure is subjected to fin cutting, the depth of the fin cutting can be set according to actual needs, such as half-width depth or full-width depth, and the embodiment of the present application does not make any specific limitation on this.

[0062] S109 , filling the second fin cut trench with oxide.

[0063] It is understandable that after forming the second fin-cut trench, oxide may be filled in the second fin-cut trench. It should be noted that the oxide filled in the first fin-cut trench and the second fin-cut trench is the same.

[0064] S110 , forming a second transistor based on the second fin structure.

[0065] It can be understood that after filling the second fin-cut trench with oxide, the second transistor can be formed according to a standard process for manufacturing a transistor.

[0066] In some possible embodiments, the above method may also include: while performing a first fin cutting process on the first fin structure, forming a first groove in the N-type drift region corresponding to the first fin structure, and forming a lateral diffusion device based on the first groove, or, while performing a second fin cutting process on the second fin structure, forming a first groove in the N-type drift region corresponding to the second fin structure, and forming a lateral diffusion device based on the first groove; the first groove is used to fill oxide.

[0067] It can be understood that the N-type drift region can be divided into a first N-type drift region and a second N-type drift region, the first N-type drift region corresponds to the first fin structure, and the second N-type drift region corresponds to the second fin structure. The first groove can be set in the first N-type drift region or the second N-type drift region according to actual needs. In the case where the first groove is located in the first N-type drift region, the lateral diffusion device is arranged side by side with the first transistor; and the first groove is formed while forming the first fin cut structure, and then the first groove is filled with oxide in the process of forming the shallow trench isolation structure. In the case where the first groove is located in the second N-type drift region, the lateral diffusion device is arranged side by side with the second transistor; and the first groove is formed while forming the second fin cut structure, and then the first groove is filled with oxide.

[0068] In some possible embodiments, when the first groove is located in the first N-type drift region, the above S104 may include: performing a first fin cutting process on the first fin structure to form a first fin cutting groove in a core area corresponding to the first fin structure, and forming a first groove in the N-type drift region corresponding to the first fin structure.

[0069] It can be understood that, in the case where the first recess is located in the first N-type drift region, the first fin-cut trench and the first recess can be formed in the same etching process.

[0070] In some possible implementations, when the first groove is located in the first N-type drift region, the above S105 may include: depositing oxide on the fin structure and the substrate to form a shallow trench isolation structure; the shallow trench isolation structure wraps the fin structure and fills the first groove and the first fin cut trench.

[0071] It can be understood that when the first groove is located in the first N-type drift region, oxide is deposited on the substrate and the fin structure to form a shallow trench isolation structure. While depositing oxide on the substrate and the fin structure, oxide is also deposited in the first fin cut groove and the first groove, so that the formed shallow trench isolation structure not only wraps the fin structure but also fills the first fin cut groove and the first groove.

[0072] In some possible embodiments, when the first groove is located in the first N-type drift region, the above S106 may include: based on the first fin structure, forming a first dummy gate structure in the first transistor and a second dummy gate structure in the lateral diffusion device; etching a portion of the first fin structure to form a first source-drain groove and a second source-drain groove; performing source-drain epitaxial growth in the first source-drain groove and the second source-drain groove to form a first source-drain structure in the first transistor and a second source-drain structure in the lateral diffusion device; removing the first dummy gate structure and the second dummy gate structure, and forming a first gate structure in the first transistor and a second gate structure in the lateral diffusion device; forming a first source-drain metal in the first transistor and a second source-drain metal in the lateral diffusion device on the first source-drain structure and the second source-drain structure; performing post-processing on the first gate structure, the second gate structure, the first source-drain metal, and the second source-drain metal to form a first metal interconnection layer in the first transistor and a second metal interconnection layer in the lateral diffusion device.

[0073] It is understandable that after filling the first groove, a lateral diffusion device can be formed based on the first fin structure in the lateral diffusion region; and a first transistor can be formed based on the first fin structure in the core region. The first transistor and the same device in the lateral diffusion device are formed in the same process, for example, the first dummy gate structure and the second dummy gate structure are formed in the same process, and the first source-drain structure and the second source-drain structure are formed in the same process.

[0074] In one example, after forming a shallow trench isolation structure, a shallow trench isolation structure of a preset height is etched so that the first fin structure is exposed. An oxide of a preset height is deposited on the surface of the first fin structure to form a first gate oxide layer, and the first gate oxide layer covers the surface of the first fin structure. Then, a gate groove is opened on the first gate oxide layer by photolithography, and polysilicon is deposited in the gate groove to form a first pseudo-gate structure in the first transistor and a second pseudo-gate structure in the lateral diffusion device; a dielectric material is deposited on the sidewall of the first pseudo-gate structure to form a first spacer (spcer) in the first transistor, and a dielectric material is deposited on the sidewall of the second pseudo-gate structure to form a second spacer in the lateral diffusion device. A portion of the first fin structure is etched to form a first source-drain groove and a second source-drain groove; source-drain epitaxial growth is performed in the first source-drain groove to form a first source-drain structure in the first transistor, and source-drain epitaxial growth is performed in the second source-drain groove to form a second source-drain structure in the lateral diffusion device. A dielectric material is deposited on the first source-drain structure, the second source-drain structure, and the etched shallow trench isolation structure to form a first interlayer dielectric layer in the first transistor and a second interlayer dielectric layer in the lateral diffusion device. It should be noted that the height of the first interlayer dielectric layer and the second interlayer dielectric layer is the same as the height of the first pseudo-gate structure and the second pseudo-gate structure. Next, the first pseudo-gate structure and the second pseudo-gate structure are removed to expose the gate groove, and a metal material is deposited in the gate groove to form a first gate structure in the first transistor and a second gate structure in the lateral diffusion device. An insulating material is deposited on the first interlayer dielectric layer and the second interlayer dielectric layer to form a first contact layer. By photolithography, the first contact layer, the first interlayer dielectric layer and the second interlayer dielectric layer are etched to form a first through hole located on the upper surface of the first source and drain structure and a second through hole located on the upper surface of the second source and drain structure. Metal material is deposited in the first through hole and the second through hole to form a first source and drain metal and a second source and drain metal. Finally, a back-end process is performed on the first contact layer to form a first metal interconnect layer in the first transistor and a second metal interconnect layer in the lateral diffusion device.

[0075] In some possible embodiments, when the first groove is located in the first N-type drift region, the above S110 may include: forming a third pseudo gate structure in the second transistor based on the second fin structure; etching a portion of the second fin structure to form a third source-drain groove; performing source-drain epitaxial growth in the third source-drain groove to form a third source-drain structure in the second transistor; removing the third pseudo gate structure and forming a third gate structure in the second transistor; forming a third source-drain metal in the second transistor on the third source-drain structure; performing a back-end process on the third gate structure and the third source-drain metal to form a third metal interconnect layer in the second transistor and a back dielectric layer in the isolation device; and stacking the lateral diffusion device and the isolation device along the first direction.

[0076] It can be understood that when the first groove is located in the first N-type drift region, no gate structure, source-drain structure and source-drain metal are formed in the isolation device.

[0077] In one example, a shallow trench isolation structure of a preset height is etched so that the second fin structure is exposed, and the retained shallow trench isolation structure is used as a shallow trench isolation layer. An oxide of a preset height is deposited on the surface of the second fin structure to form a second gate oxide layer, and the second gate oxide layer covers the surface of the second fin structure. Then, a gate groove is opened on the second gate oxide layer by photolithography, and polysilicon is deposited in the gate groove to form a third pseudo-gate structure in the second transistor; a dielectric material is deposited on the sidewall of the third pseudo-gate structure to form a third spacer in the second transistor. A portion of the second fin structure is etched to form a third source-drain groove; source-drain epitaxial growth is performed in the third source-drain groove to form a third source-drain structure in the second transistor. A dielectric material is deposited on the third source-drain structure and the shallow trench isolation layer to form a third interlayer dielectric layer in the second transistor and a fourth interlayer dielectric layer in the isolation device. It should be noted that the height of the third interlayer dielectric layer and the fourth interlayer dielectric layer is the same as the height of the third pseudo-gate structure. Then, the third pseudo-gate structure is removed to expose the gate groove, and a metal material is deposited in the gate groove to form a third gate structure in the second transistor. An insulating material is deposited on the third interlayer dielectric layer and the fourth interlayer dielectric layer to form a second contact layer. The second contact layer and the third interlayer dielectric layer are etched by photolithography to form a third through hole located on the upper surface of the third source-drain structure. A metal material is deposited in the third through hole to form a third source-drain metal. Finally, a back-end process is performed on the second contact layer to form a third metal interconnect layer in the second transistor and a back dielectric layer in the isolation device.

[0078] It should be noted that when the first groove is located in the first N-type drift region, since no gate structure and source-drain structure are formed in the isolation device, only a dielectric layer (i.e., a back dielectric layer) needs to be formed during the back-end process, and there is no need to perform metal interconnection in the back dielectric layer.

[0079] In some possible embodiments, when the first groove is located in the second N-type drift region, the above S108 may include: performing a second fin cut process on the second fin structure to form a second fin cut groove in the core area corresponding to the second fin structure, and forming a first groove in the N-type drift region corresponding to the second fin structure.

[0080] It can be understood that when the first groove is located in the second N-type drift region, the second fin-cut trench and the first groove can be formed in the same etching process.

[0081] In some possible implementations, when the first groove is located in the second N-type drift region, the above S109 may include: filling oxide in the second fin-cut trench and the first groove.

[0082] It can be understood that when the first groove is located in the second N-type drift region, after the second fin-cut groove and the first groove are formed, the second fin-cut groove and the first groove are filled with the same oxide as the shallow trench isolation structure.

[0083] In some possible embodiments, when the first groove is located in the second N-type drift region, the above S106 may include: forming a first pseudo gate structure in the first transistor based on the first fin structure; etching a portion of the first fin structure to form a first source-drain groove; performing source-drain epitaxial growth in the first source-drain groove to form a first source-drain structure in the first transistor; removing the first pseudo gate structure and forming a first gate structure in the first transistor; forming a first source-drain metal in the first transistor on the first source-drain structure; performing a back-end process on the first gate structure and the first source-drain metal to form a first metal interconnect layer in the first transistor and a front dielectric layer in the isolation device; the isolation device and the lateral diffusion device are stacked along a first direction.

[0084] It can be understood that when the first groove is located in the second N-type drift region, no gate structure, source-drain structure and source-drain metal are formed in the isolation device.

[0085] In one example, a shallow trench isolation structure of a preset height is etched so that the first fin structure is exposed. An oxide of a preset height is deposited on the surface of the first fin structure to form a first gate oxide layer, and the first gate oxide layer covers the surface of the first fin structure. Then, a gate groove is opened on the first gate oxide layer by photolithography, and polysilicon is deposited in the gate groove to form a first pseudo-gate structure in the first transistor; a dielectric material is deposited on the sidewall of the first pseudo-gate structure to form a first spacer in the first transistor. A portion of the first fin structure is etched to form a first source-drain groove; and source-drain epitaxial growth is performed in the first source-drain groove to form a first source-drain structure in the first transistor. A dielectric material is deposited on the first source-drain structure and the etched shallow trench isolation structure to form a first interlayer dielectric layer in the first transistor and a fourth interlayer dielectric layer in the isolation device. It should be noted that the height of the first interlayer dielectric layer and the fourth interlayer dielectric layer is the same as the height of the first pseudo-gate structure. Then, the first pseudo-gate structure is removed to expose the gate groove, and a metal material is deposited in the gate groove to form a first gate structure in the first transistor. An insulating material is deposited on the first interlayer dielectric layer and the fourth interlayer dielectric layer to form a first contact layer. The first contact layer and the first interlayer dielectric layer are etched by photolithography to form a first through hole located on the upper surface of the first source-drain structure. A metal material is deposited in the first through hole to form a first source-drain metal. Finally, a back-end process is performed on the first contact layer to form a first metal interconnect layer in the first transistor and a front dielectric layer in the isolation device.

[0086] It should be noted that when the first groove is located in the second N-type drift region, no gate structure and source-drain structure are formed in the isolation device. Therefore, in the process of the back-end process, only a dielectric layer (i.e., a front dielectric layer) needs to be formed, and no metal interconnection is required in the front dielectric layer.

[0087] In some possible embodiments, when the first groove is located in the second N-type drift region, the above S110 may include: based on the second fin structure, forming a third dummy gate structure in the second transistor and a second dummy gate structure in the lateral diffusion device; etching a portion of the second fin structure to form a third source-drain groove and a second source-drain groove; performing source-drain epitaxial growth in the third source-drain groove and the second source-drain groove to form a third source-drain structure in the second transistor and a second source-drain structure in the lateral diffusion device; removing the third dummy gate structure and the second dummy gate structure, and forming a third gate structure in the second transistor and a second gate structure in the lateral diffusion device; forming a third source-drain metal in the second transistor and a second source-drain metal in the lateral diffusion device on the third source-drain structure and the second source-drain structure; performing post-processing on the third gate structure, the second gate structure, the third source-drain metal and the second source-drain metal to form a third metal interconnection layer in the second transistor and a second metal interconnection layer in the lateral diffusion device.

[0088] It can be understood that after filling the first groove, a lateral diffusion device can be formed based on the second fin structure in the lateral diffusion region; and a second transistor can be formed based on the second fin structure in the core region; wherein the second transistor and the same device in the lateral diffusion device are formed in the same process, for example, the third pseudo-gate structure and the second pseudo-gate structure are formed in the same process, and the third source-drain structure and the second source-drain structure are formed in the same process.

[0089] In one example, a shallow trench isolation structure of a preset height is etched so that the second fin structure is exposed and a shallow trench isolation layer is formed. An oxide of a preset height is deposited on the surface of the second fin structure to form a second gate oxide layer, and the second gate oxide layer covers the surface of the second fin structure. Then, a gate groove is opened on the second gate oxide layer by photolithography, and polysilicon is deposited in the gate groove to form a third pseudo-gate structure in the second transistor and a second pseudo-gate structure in the lateral diffusion device; a dielectric material is deposited on the sidewall of the third pseudo-gate structure to form a third spacer in the second transistor, and a dielectric material is deposited on the sidewall of the second pseudo-gate structure to form a second spacer in the lateral diffusion device. A portion of the second fin structure is etched to form a third source-drain groove and a second source-drain groove; source-drain epitaxial growth is performed in the third source-drain groove to form a third source-drain structure in the second transistor, and source-drain epitaxial growth is performed in the second source-drain groove to form a second source-drain structure in the lateral diffusion device. A dielectric material is deposited on the third source-drain structure, the second source-drain structure and the shallow trench isolation layer to form a third interlayer dielectric layer in the second transistor and a second interlayer dielectric layer in the lateral diffusion device. It should be noted that the height of the third interlayer dielectric layer and the second interlayer dielectric layer is the same as the height of the third pseudo-gate structure and the second pseudo-gate structure. Next, the third pseudo-gate structure and the second pseudo-gate structure are removed to expose the gate groove, and metal material is deposited in the gate groove to form the third gate structure in the second transistor and the second gate structure in the lateral diffusion device. An insulating material is deposited on the third interlayer dielectric layer and the second interlayer dielectric layer to form a second contact layer. By photolithography, the second contact layer, the third interlayer dielectric layer and the second interlayer dielectric layer are etched to form a third through hole located on the upper surface of the third source and drain structure and a second through hole located on the upper surface of the second source and drain structure. Metal material is deposited in the third through hole and the second through hole to form a third source and drain metal and a second source and drain metal. Finally, a back-end process is performed on the second contact layer to form a third metal interconnect layer in the second transistor and a second metal interconnect layer in the lateral diffusion device.

[0090] In some embodiments, the metal materials forming the first gate structure, the second gate structure and the third gate structure may include but are not limited to: tantalum nitride (TaN), titanium nitride (TiN), aluminum nitride (AlN), titanium aluminum carbide (TiAlC), titanium aluminum nitride (TiAlN). The materials of the first gate structure, the second gate structure and the third gate structure can be selected according to actual conditions and are not limited to the metal materials listed above.

[0091] It should be noted that, for ease of explanation, the first source-drain structure mentioned in the embodiments of the present application is an abbreviation, specifically referring to the first source structure and / or the first drain structure. In addition, the second source-drain structure, the first source-drain metal, the second source-drain metal, etc. are similar to the first source-drain structure, where "source-drain" is an abbreviation for "source and / or drain".

[0092] In some embodiments, the oxide forming the shallow trench isolation structure may be any one of the following: silicon dioxide (SiO 2 ) or silicon oxycarbide (SiCO), etc.

[0093] Below, the semiconductor structure provided in the embodiment of the present application is described by taking the first transistor and the second transistor as fin-type field effect transistors as an example. Figure 2 This is a design layout of the semiconductor structure in the embodiment of this application. Figure 2 (a) is the design layout of the lateral diffusion device. It should be noted that for ease of understanding, only the fin structure, gate structure and source-drain structure are shown in the design layout; (b) is the design layout of the first transistor; (c) is the design layout of the isolation device; and (d) is the design layout of the second transistor. Figure 3 This is a schematic diagram of the first structure of the semiconductor structure in the embodiment of the present application. Figure 3 (a) is a cross-sectional view of the semiconductor structure made along the AA' direction of the lateral diffusion region; (b) is a cross-sectional view of the semiconductor structure made along the BB' direction of the lateral diffusion region; (c) is a cross-sectional view of the semiconductor structure made along the A1-A1' direction of the core region; (d) is a cross-sectional view of the semiconductor structure made along the B1-B1' direction of the core region.

[0094] Figure 3 In the semiconductor structure 10 shown, the first groove is formed in the first N-type drift region, the etching depth of the first fin structure is half the depth, and the etching depth of the second fin structure is full the depth.

[0095] In combination with the above preparation method, Figure 3 The preparation process of the semiconductor structure 10 is described below. Figure 3 The semiconductor structure 10 shown may be 4A to 4D The process shown is prepared 4A to 4DIt is a schematic diagram of the first preparation process of the semiconductor structure in the embodiment of the present application.

[0096] In one example, a first preparation process of the semiconductor structure 10 may include the following steps:

[0097] Step 1: Provide a Si substrate 21, coat the Si substrate 21 with photoresist, and perform two ion implantations in the lateral diffusion region to form a high-concentration P-type well region and a low-concentration N-type drift region (see Figure 4A (a) in the figure.

[0098] Step 2: remove the photoresist, etch the substrate 21, and form a fin structure 22. The fin structure 22 includes a first fin structure 221 and a second fin structure 222 (see Figure 4A (b) in the figure.

[0099] Step 3: Perform a first fin cutting process on the first fin-shaped structure 221 to form a first fin cutting groove 231 and a first groove 24 (see Figure 4A (c) in the figure). The depth of the photolithography is half the depth.

[0100] Step 4: Deposit oxide on the substrate 21 and the fin structure 22 to form a shallow trench isolation structure 25. The shallow trench isolation structure 25 wraps the fin structure 22, covers the substrate 21, and fills the first groove 24 and the first fin cut groove 231. Then, the shallow trench isolation structure 25 of a preset height is etched to expose the first fin structure 221. Oxide is deposited on the surface of the first fin structure 221 to form a first gate oxide layer 261. A first dummy gate structure 311, a first spacer 111, a second dummy gate structure 312, and a second spacer 121 are formed on the first gate oxide layer 261 (see Figure 4B (a) in the figure.

[0101] It should be noted that the first gate oxide layer 261 can be made of the same material as the shallow trench isolation structure 25 .

[0102] Step 5: Etch the first fin structure 221 to form a first source-drain groove and a second source-drain groove, perform source-drain epitaxial growth in the first source-drain groove and the second source-drain groove to form a first source-drain structure 112 and a second source-drain structure 122 (see Figure 4B (b) in the figure.

[0103] Step 6: Deposit dielectric material on the etched shallow trench isolation structure 25, the first source-drain structure 112 and the second source-drain structure 122 to form a first interlayer dielectric layer 113 and a second interlayer dielectric layer 123. Remove the first dummy gate structure 311 and the second dummy gate structure 312 to expose the gate groove, and deposit insulating material on the surface of the gate groove to form a first gate dielectric layer 114 and a second gate dielectric layer 124; then, deposit metal material in the gate groove to form a first gate structure 115 and a second gate structure 125. Deposit dielectric material on the first interlayer dielectric layer 113 and the second interlayer dielectric layer 123 to form a first contact layer 271. Photolithography is performed on the first contact layer 271, the first interlayer dielectric layer 113 and the second interlayer dielectric layer 123 to form a first through hole and a second through hole; deposit metal material in the first through hole and the second through hole to form a first source-drain metal 116 and a second source-drain metal 126 (see Figure 4B (c) in the figure). A back-end process is performed on the first contact layer 271 to form a first metal interconnection layer and a second metal interconnection layer (not shown in the figure).

[0104] It should be noted that the first contact layer 271 can be made of the same material as the spacers (such as the first spacers 111 and the second spacers 121 ).

[0105] Step 7: After forming the first transistor 11 and the lateral diffusion device 12, an insulating material is deposited on the first transistor 11 and the lateral diffusion device 12 to form a first insulating layer 15, and then the carrier wafer 16 is bonded to the first insulating layer 15 (see Figure 4C (a) in the figure.

[0106] Step 8: Flip the first transistor 11 and the lateral diffusion device 12, and remove the substrate 21, so that the second fin structure 222 is placed upward (see Figure 4C (b) in the figure.

[0107] Step 9: Perform a second fin cutting process on the second fin-shaped structure 222 to form a second fin cutting groove 232 (see Figure 4C (c) in the figure). The depth of the photolithography is the full-width depth.

[0108] Step 10: Fill the second fin cut trench 232 with oxide, then remove the shallow trench isolation structure 25 of a preset height and the oxide in the second fin cut trench 232 by etching, so that the second fin structure 222 is exposed, and a shallow trench isolation layer 251 is formed. Oxide is deposited on the surface of the exposed second fin structure 222 to form a second gate oxide layer 262. A third dummy gate structure 313 and a third spacer 131 are formed on the second gate oxide layer 262 in the core region (see Figure 4D (a) in the figure.

[0109] Step 11: Form the third source-drain structure 132 in the second transistor 13 by referring to the steps in step 5 above (see Figure 4D (b) in the figure.

[0110] Step 12: Referring to the steps of the sixth step, a third interlayer dielectric layer 133, a third gate dielectric layer 134, a third gate structure 135, a second contact layer 272, a third source-drain metal 136 and a fourth interlayer dielectric layer 143 in the isolation device 14 are formed in the second transistor 13 (see step 12). Figure 4D and forming a third metal interconnection layer in the second transistor 13 and a back dielectric layer in the isolation device 14 (not shown in the figure).

[0111] At this point, the semiconductor structure 10 is manufactured according to the first manufacturing method.

[0112] Figure 5 This is a schematic diagram of the second structure of the semiconductor structure in the embodiment of the present application. Figure 5 (a) is a cross-sectional view of the semiconductor structure made along the AA' direction of the lateral diffusion region; (b) is a cross-sectional view of the semiconductor structure made along the BB' direction of the lateral diffusion region; (c) is a cross-sectional view of the semiconductor structure made along the A1-A1' direction of the core region; (d) is a cross-sectional view of the semiconductor structure made along the B1-B1' direction of the core region.

[0113] Figure 5 In the semiconductor structure 10 shown, the first groove is formed in the first N-type drift region, the etching depth of the first fin structure is half the depth, and the etching depth of the second fin structure is half the depth.

[0114] In combination with the above preparation method, Figure 5 The preparation process of the semiconductor structure 10 is described below. Figure 5 The semiconductor structure 10 shown may be Figure 6 The process shown is prepared Figure 6 Schematic diagram of the second preparation process of the semiconductor structure in the embodiment of the present application.

[0115] In one example, the second preparation process of the semiconductor structure 10 may include the following steps:

[0116] Step 1: Referring to the first preparation method, the first transistor 11 and the lateral diffusion device 12 are formed. After the first transistor 11 and the lateral diffusion device 12 are flipped and the substrate is removed, the second fin structure 222 is subjected to a second fin cutting process, and the etching depth is half the width depth to form a second fin cutting groove 232 (see Figure 6 (a) in the figure.

[0117] Step 2: Form the second transistor 13 and the isolation device 14 by referring to the first preparation method described above (see Figure 6 (b) in the figure.

[0118] At this point, the semiconductor structure 10 is manufactured according to the second manufacturing method.

[0119] In the embodiment of the present application, when the first fin structure and the second fin structure are subjected to photolithography, the etching depth is selected to be half the depth, which will result in poor self-alignment between the front device (i.e., the first transistor and the lateral diffusion device) and the back device (i.e., the second transistor and the isolation device), and may cause etching misalignment (such as Figure 5 It should be noted that Figure 5 This is only one example of a semiconductor structure prepared by the second preparation method, and cannot be used to limit all examples of semiconductor structures prepared by the second preparation method. In some embodiments, in the semiconductor structure prepared by the second preparation method, there may be no misalignment between the front device and the back device.

[0120] Figure 7 This is a schematic diagram of the third structure of the semiconductor structure in the embodiment of the present application. Figure 7 (a) is a cross-sectional view of the semiconductor structure made along the AA' direction of the lateral diffusion region; (b) is a cross-sectional view of the semiconductor structure made along the BB' direction of the lateral diffusion region; (c) is a cross-sectional view of the semiconductor structure made along the A1-A1' direction of the core region; (d) is a cross-sectional view of the semiconductor structure made along the B1-B1' direction of the core region.

[0121] Figure 7 In the semiconductor structure 10 shown, the first groove is formed in the second N-type drift region, the etching depth of the first fin-shaped structure is half the depth, and the etching depth of the second fin-shaped structure is half the depth. Figure 7 In the semiconductor structure 10 shown, the lateral diffusion device 12 is arranged side by side with the second transistor 13, and the preparation method of the lateral diffusion device 12 can refer to the preparation method of the lateral diffusion device 12 in the above-mentioned first preparation method; the isolation device 14 is arranged side by side with the first transistor 11, and the preparation method of the isolation device 14 can refer to the preparation method of the isolation device 14 in the above-mentioned first preparation method. The preparation methods of other structures in the semiconductor structure 10 are the same as the above-mentioned first preparation method, and the embodiments of the present application will not be described in detail.

[0122] In an embodiment of the present application, by forming a first groove in the N-type drift region and filling the first groove with oxide while performing a first fin cut process on the first fin structure or a second fin cut process on the second fin structure, the formed lateral diffusion device can withstand higher voltages while being compatible with the process of preparing stacked transistors, thereby optimizing the preparation process of the semiconductor structure.

[0123] Furthermore, when the second fin structure is subjected to the second fin cutting process, different etching depths can be selected according to actual needs, that is, the etching depth of the second fin cutting process is equal to the height of the fin structure or equal to half the height of the fin structure, making the layout of the internal devices of the semiconductor structure more flexible.

[0124] Furthermore, the semiconductor structure provided in the embodiment of the present application can be detected using a detection and analysis instrument, such as a scanning electron microscope (SEM), a transmission electron microscope (TEM), a scanning transmission electron microscope (STEM), etc. Taking TEM as an example, the semiconductor structure provided in the embodiment of the present application can be detected by TEM slicing, such as the lateral diffusion device is only distributed on the front or back of the semiconductor structure, and the oxide in the first groove of the lateral diffusion device forms an A-shaped structure with the gate oxide layer (i.e., the first gate oxide layer or the second gate oxide layer).

[0125] Furthermore, the method for preparing the semiconductor structure described in the embodiment of the present application can be applied to the next generation integrated circuit process, and is a process-compatible LDMOS transistor solution with great application potential.

[0126] The present application embodiment provides a semiconductor device, including: a semiconductor structure as described in the above embodiment. The specific definition of the semiconductor structure can be found in the above Figure 3 , Figure 5 and Figure 7 The semiconductor structure shown will not be described in detail here.

[0127] The present application embodiment provides an electronic device, including: a circuit board and a semiconductor device as described in the above embodiment, wherein the semiconductor device is arranged on the circuit board. The semiconductor device includes the above semiconductor structure. The specific definition of the semiconductor structure can be found in the above Figure 3 , Figure 5 and Figure 7 , I will not go into details here.

[0128] In the description of the present application, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the embodiments of the present application. In the present application, the schematic representation of the above terms is not necessarily for the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine different embodiments or examples described in the present application and the features of different embodiments or examples without contradiction.

[0129] The above are only preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for preparing a semiconductor structure, characterized in that: The semiconductor structure includes a lateral diffusion device and a core device, wherein the core device includes a first transistor and a second transistor stacked in a first direction; the semiconductor structure also includes a lateral diffusion device, wherein the lateral diffusion device is arranged side by side with the first transistor or arranged side by side with the second transistor; The method comprises: A substrate is provided; the substrate comprises a lateral diffusion region and a core region; the lateral diffusion region and the core region are arranged adjacent to each other in a second direction; the second direction is perpendicular to the first direction; Performing ion implantation in the lateral diffusion region to form a P-type well region and an N-type drift region; Etching the lateral diffusion region and the core region to form a fin-shaped structure; the fin-shaped structure includes a first fin structure and a second fin structure stacked along the first direction; Performing a first fin cutting process on the first fin-shaped structure to form a first fin cutting groove; the first fin cutting groove is perpendicular to the extension direction of the first fin-shaped structure; the etching depth of the first fin cutting process is half of the height of the fin-shaped structure; filling the first fin cut trench with oxide; Based on the first fin structure, forming the first transistor; flipping the wafer and removing the substrate; Performing a second fin cutting process on the second fin-shaped structure to form a second fin cutting groove; the second fin cutting groove is perpendicular to the extension direction of the second fin-shaped structure; the etching depth of the second fin cutting process is equal to the height of the fin-shaped structure or equal to half of the height of the fin structure; filling the oxide in the second fin cut trench; Based on the second fin structure, forming the second transistor; The method further includes: while performing a first fin-cutting process on the first fin-shaped structure, forming a first groove in an N-type drift region corresponding to the first fin-shaped structure, and forming the lateral diffusion device based on the first groove, or, while performing a second fin-cutting process on the second fin-shaped structure, forming a first groove in an N-type drift region corresponding to the second fin-shaped structure, and forming the lateral diffusion device based on the first groove; the first groove is used to fill the oxide.

2. The method according to claim 1, characterized in that: The performing a first fin cutting process on the first fin-shaped structure to form a first fin cutting groove includes: Performing a first fin-cutting process on the first fin-shaped structure to form a first fin-cutting groove in a core region corresponding to the first fin-shaped structure, and forming the first groove in an N-type drift region corresponding to the first fin-shaped structure; The step of filling the first fin cut trench with oxide comprises: The oxide is deposited on the fin-shaped structure and the substrate to form a shallow trench isolation structure; the shallow trench isolation structure wraps the fin-shaped structure and fills the first recess and the first fin cut trench.

3. The method according to claim 2, characterized in that The forming of the first transistor based on the first fin structure includes: Based on the first fin structure, forming a first dummy gate structure in the first transistor and a second dummy gate structure in the lateral diffusion device; Etching a portion of the first fin structure to form a first source-drain groove and a second source-drain groove; Performing source-drain epitaxial growth in the first source-drain groove and the second source-drain groove to form a first source-drain structure in the first transistor and a second source-drain structure in the lateral diffusion device; removing the first dummy gate structure and the second dummy gate structure, and forming a first gate structure in the first transistor and a second gate structure in the lateral diffusion device; forming a first source-drain metal in a first transistor and a second source-drain metal in a lateral diffusion device on the first source-drain structure and the second source-drain structure; A back-end process is performed on the first gate structure, the second gate structure, the first source-drain metal, and the second source-drain metal to form a first metal interconnection layer in the first transistor and a second metal interconnection layer in the lateral diffusion device.

4. The method according to claim 2, characterized in that: The forming of a second transistor based on the second fin structure comprises: Based on the second fin structure, forming a third dummy gate structure in the second transistor; Etching a portion of the second fin structure to form a third source-drain groove; Performing source-drain epitaxial growth in the third source-drain groove to form a third source-drain structure in the second transistor; removing the third dummy gate structure and forming a third gate structure in the second transistor; forming a third source-drain metal in the second transistor on the third source-drain structure; A back-end process is performed on the third gate structure and the third source-drain metal to form a third metal interconnect layer in the second transistor and a back dielectric layer in the isolation device; the lateral diffusion device and the isolation device are stacked along the first direction.

5. The method according to claim 1, characterized in that The performing a second fin cutting process on the second fin-shaped structure to form a second fin cutting groove includes: Performing a second fin-cutting process on the second fin-shaped structure to form a second fin-cutting groove in a core region corresponding to the second fin-shaped structure, and forming the first groove in the N-type drift region corresponding to the second fin-shaped structure; The step of filling the oxide in the second fin cut trench comprises: The oxide is filled in the second fin cut trench and the first recess.

6. The method according to claim 5, characterized in that The forming of the first transistor based on the first fin structure includes: Based on the first fin structure, forming a first dummy gate structure in a first transistor; Etching a portion of the first fin structure to form a first source-drain groove; Performing source and drain epitaxial growth in the first source and drain grooves to form a first source and drain structure in the first transistor; removing the first dummy gate structure and forming a first gate structure in the first transistor; forming a first source-drain metal in a first transistor on the first source-drain structure; A back-end process is performed on the first gate structure and the first source-drain metal to form a first metal interconnection layer in the first transistor and a front dielectric layer in the isolation device; the isolation device and the lateral diffusion device are stacked along the first direction.

7. The method according to claim 5, characterized in that The forming of a second transistor based on the second fin structure comprises: Based on the second fin structure, forming a third dummy gate structure in the second transistor and a second dummy gate structure in the lateral diffusion device; Etching a portion of the second fin structure to form a third source-drain groove and a second source-drain groove; Performing source-drain epitaxial growth in the third source-drain groove and the second source-drain groove to form a third source-drain structure in the second transistor and a second source-drain structure in the lateral diffusion device; removing the third dummy gate structure and the second dummy gate structure, and forming a third gate structure in the second transistor and a second gate structure in the lateral diffusion device; forming a third source-drain metal in the second transistor and a second source-drain metal in the lateral diffusion device on the third source-drain structure and the second source-drain structure; A back-end process is performed on the third gate structure, the second gate structure, the third source-drain metal and the second source-drain metal to form a third metal interconnection layer in the second transistor and a second metal interconnection layer in the lateral diffusion device.

8. A semiconductor structure, characterized in that: The semiconductor structure is prepared by the method according to any one of claims 1 to 7, wherein the semiconductor structure comprises: A core device; the core device comprises a first transistor and a second transistor stacked along the first direction; A lateral diffusion device; the lateral diffusion device is arranged side by side with the first transistor or arranged side by side with the second transistor; An isolation device; the isolation device and the lateral diffusion device are stacked in the first direction; The lateral diffusion device includes a P-type well region and an N-type drift region; a first groove is arranged in the N-type drift region of the lateral diffusion device, and the first groove is used to fill oxide.

9. A semiconductor device, characterized in that: include: The semiconductor structure as claimed in claim 8.

10. An electronic device, characterized in that: include: A circuit board and a semiconductor device as claimed in claim 9, wherein the semiconductor device is arranged on the circuit board.

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