Light emitting diode, display device and manufacturing method thereof

Abstract

The invention relates to a light emitting diode, a display device and a manufacturing method thereof. A display device includes a substrate in which a plurality of sub-pixels are defined; a pair of low potential power supply lines disposed in a sub-pixel of the plurality of sub-pixels; and a plurality of light emitting diodes overlapping a region between the pair of low potential power supply lines. Each of the plurality of light emitting diodes includes a first semiconductor layer; a light emitting layer; a second semiconductor layer; a first insulating film surrounding side surfaces of the first semiconductor layer, the light emitting layer, and the second semiconductor layer; a side electrode on the first insulating film; and a first electrode in contact with a bottom surface of the first semiconductor layer and a lower portion of the side electrode.

Description

Technical Field

[0001] The present disclosure relates to a display device and a method of manufacturing the same, and more particularly, to a display device using a light emitting diode (LED) and a method of manufacturing the same. Background Art

[0002] As display devices for monitors of computers, televisions, or cellular phones, there are organic light emitting display devices (OLEDs) that are self-light emitting devices and liquid crystal display devices (LCDs) that require a separate light source.

[0003] The applicable range of the display device is diverse to personal digital assistants as well as monitors of computers and televisions, and display devices having a large display area and reduced volume and weight are being studied.

[0004] In addition, in recent years, display devices including LEDs have attracted attention as next-generation display devices. Since LEDs are formed of inorganic materials rather than organic materials, they are excellent in reliability, making their lifespan longer than that of liquid crystal display devices or organic light-emitting display devices. In addition, LEDs have a fast light emission speed, excellent light emission efficiency, and strong impact resistance, making them excellent in stability and capable of displaying images with high brightness. Summary of the invention

[0005] The present disclosure aims to provide a display device and a method for manufacturing the display device that improve the yield of a self-assembly process of light emitting diodes.

[0006] Another object to be achieved by the present disclosure is to provide a display device and a method of manufacturing the display device in which a light emitting diode is suppressed from adhering to a location other than an opening during self-assembly.

[0007] Another object to be achieved by the present disclosure is to provide a display device and a method of manufacturing the display device which improve light extraction efficiency by partially forming a ferromagnetic electrode having low reflectivity in a side portion of a light emitting diode.

[0008] Another object to be achieved by the present disclosure is to provide a display device and a method of manufacturing the display device that improves light extraction efficiency by forming an electrode with high reflection efficiency at a lower portion of a light emitting diode.

[0009] Another object of the present disclosure is to provide a display device and a method for manufacturing the display device, wherein an ohmic contact electrode is partially formed at the lower portion of a light emitting diode to minimize or at least reduce the reduction in light extraction efficiency caused by the ohmic contact electrode and improve resistance.

[0010] Another object of the present disclosure is to provide a display device having an irregular structure formed in a lower portion of a light emitting diode and a method for manufacturing the display device.

[0011] The objects of the present disclosure are not limited to the above objects, and other objects not mentioned above can be clearly understood by those skilled in the art from the following description.

[0012] In one embodiment, a display device includes: a substrate in which a plurality of sub-pixels are defined; a pair of low potential power lines in a sub-pixel of the plurality of sub-pixels, the pair of low potential power lines being spaced apart from each other; and a plurality of light emitting diodes included in the sub-pixels, the plurality of light emitting diodes in the sub-pixels overlapping with a region between the pair of low potential power lines in the sub-pixels, wherein at least one of the plurality of light emitting diodes includes: a first semiconductor layer; a light emitting layer on the first semiconductor layer; a second semiconductor layer on the light emitting layer; a first insulating film, the first insulating film surrounding a side surface of the first semiconductor layer, a side surface of the light emitting layer, and a side surface of the second semiconductor layer; a side electrode, the side electrode being on the first insulating film and overlapping with the side surface of the first semiconductor layer; and a first electrode, the first electrode contacting a lower surface of the first semiconductor layer and a lower portion of the side electrode. . Therefore, the side electrode is partially formed in a side portion of the light emitting diode to minimize or at least reduce a reduction in light emitting efficiency due to the side electrode.

[0013] In one embodiment, a method for manufacturing a display device includes the following steps: placing a substrate in a chamber, the chamber including a fluid and a plurality of light-emitting diodes, the substrate including a pair of low-potential power lines spaced apart from each other; using a magnet to move the plurality of light-emitting diodes to the substrate; and applying a voltage to the pair of low-potential power lines and forming an electric field between the pair of low-potential power lines, the plurality of light-emitting diodes self-assemble between the pair of low-potential power lines on the substrate in response to the electric field, wherein each of the plurality of light-emitting diodes includes: a first semiconductor layer; a light-emitting layer on the first semiconductor layer; a second semiconductor layer on the light-emitting layer; a first insulating film, the first insulating film surrounding the side surface of the first semiconductor layer, the side surface of the light-emitting layer, and the side surface of the second semiconductor layer; a side electrode, the side electrode is on the first insulating film and overlaps with the side surface of the first semiconductor layer; and a second insulating film, the second insulating film covering the side electrode and the first insulating film. Therefore, the second insulating film is formed so that the semiconductor layer of the light-emitting diode with polarity does not adhere to an incorrect position, and the yield of the self-assembly process can be improved. According to the present disclosure, the transfer process optimization of the light-emitting diode is performed to reduce the production energy of the display device.

[0014] In one embodiment, a light emitting diode includes: a first electrode; a first semiconductor layer on the first electrode; a second semiconductor layer on the first semiconductor layer; a light emitting layer between the first semiconductor layer and the second semiconductor layer, the light emitting layer being configured to emit light; a second electrode on the second semiconductor layer, the second semiconductor layer being between the second electrode and the light emitting layer; and a third electrode, the third electrode being on a side surface of the first semiconductor layer so that the third electrode is located between an end of the first electrode and a side surface of the first semiconductor layer.

[0015] Additional details of example embodiments are included in the detailed description and the accompanying drawings.

[0016] According to the present disclosure, the yield of the self-assembly process of light emitting diodes can be improved.

[0017] According to the present disclosure, the side electrode is formed on the first insulating film to protect the semiconductor layer of the light emitting diode when the side electrode and the contact electrode are connected.

[0018] According to the present disclosure, a side electrode having low reflection efficiency is partially formed only in a side portion of a light emitting diode to minimize a reduction in light extraction efficiency due to the side electrode.

[0019] According to the present disclosure, an ohmic contact electrode is partially formed on a lower side of a light emitting diode to improve resistance and minimize or at least reduce a reduction in light extraction efficiency due to the ohmic contact electrode.

[0020] According to the present disclosure, an irregular structure is formed under a light emitting diode to improve light extraction efficiency and reduce power consumption.

[0021] The effects of the present disclosure are not limited to the above-mentioned effects, and other effects not mentioned above will be clearly understood by those of ordinary skill in the art from the following description.

[0022] The above-described objects to be achieved by the present disclosure, means for achieving the objects, and effects of the present disclosure do not specify essential features of the claims, and therefore, the scope of the claims is not limited to the disclosed contents of the present disclosure.

[0023] The effects according to the present disclosure are not limited to the contents of the above examples, and more various effects are included in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The above and other aspects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0025] Figure 1 is a schematic diagram of a display device according to an exemplary embodiment of the present disclosure;

[0026] Figure 2A is a partial cross-sectional view of a display device according to an exemplary embodiment of the present disclosure;

[0027] Figure 2B is a perspective view of a tiled display device according to an exemplary embodiment of the present disclosure;

[0028] Figure 3 is an enlarged plan view of an active area of ​​a display device according to an exemplary embodiment of the present disclosure;

[0029] Figure 4 is a cross-sectional view of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure;

[0030] FIG. 5A to FIG. 5D is a cross-sectional view for explaining a method of manufacturing a light emitting diode of a display device according to an exemplary embodiment of the present disclosure;

[0031] FIG. 6A to FIG. 6E is a cross-sectional view for explaining a method of manufacturing a display device according to an exemplary embodiment of the present disclosure using a self-assembly process;

[0032] Figure 7 is a cross-sectional view of a display device according to an exemplary embodiment of the present disclosure;

[0033] Figure 8 is an enlarged plan view of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure;

[0034] Fig. 9 is a cross-sectional view of a display device according to still another exemplary embodiment of the present disclosure; and

[0035] Fig.10 is a cross-sectional view of a display device according to still another exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0036] By referring to the exemplary embodiments described in detail below in conjunction with the accompanying drawings, the advantages and features of the present disclosure and the methods for achieving these advantages and features will become clear. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. Exemplary embodiments are provided only by way of example so that those skilled in the art can fully understand the disclosure of the present disclosure and the scope of the present disclosure.

[0037] The shapes, sizes, ratios, angles, quantities, etc. shown in the accompanying drawings for describing the exemplary embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Throughout the specification, the same reference numerals generally represent the same elements. In addition, in the following description of the present disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure. Terms such as "including", "having" and "comprising" used herein are generally intended to allow the addition of other components unless the term is used together with the term "only". Unless otherwise expressly stated, any reference to the singular may include the plural.

[0038] Parts are interpreted as including ordinary tolerances even if not expressly stated.

[0039] When terms such as “on,” “above,” “below,” and “beside” are used to describe a positional relationship between two components, one or more components may be located between the two components unless the terms are used together with the terms “immediately” or “directly.”

[0040] When an element or a layer is described as being “on” another element or layer, the layer or the element may be directly on the other layer or the element, with other elements or layers interposed therebetween.

[0041] Although the terms "first", "second", etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components. Therefore, in the technical concept of the present disclosure, the first component mentioned below may be the second component.

[0042] Throughout the specification, like reference numerals generally refer to like elements.

[0043] The size and thickness of each component shown in the drawings are shown for convenience of description, and the present disclosure is not limited to the size and thickness of the components shown.

[0044] The features of the various embodiments of the present disclosure may be partially or entirely adhered to or combined with each other, and may be interlocked and operated in technically various ways, and the embodiments may be performed independently or in association with each other.

[0045] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0046] Figure 1 is a schematic diagram of a display device according to an exemplary embodiment of the present disclosure. Figure 1 , for convenience of description, among various components of the display device 100, a display panel PN, a gate driver GD, a data driver DD, and a timing controller TC are illustrated.

[0047] Reference Figure 1 , the display device 100 includes: a display panel PN, which includes a plurality of sub-pixels SP; a gate driver GD and a data driver DD, which provide various signals to the display panel PN; and a timing controller TC, which controls the gate driver GD and the data driver DD.

[0048] The gate driver GD supplies a plurality of scan signals to the plurality of scan lines SL according to a plurality of gate control signals supplied from the timing controller TC. Figure 1 2A and 2B illustrate that one gate driver GD is arranged to be spaced apart from one side of the display panel PN, but the number of the gate drivers GD and the arrangement thereof are not limited thereto.

[0049] The data driver DD provides data voltages to the plurality of data lines DL according to a plurality of data control signals and image data provided from the timing controller TC. The data driver DD converts the image data into data voltages using reference gamma voltages and may provide the converted data voltages to the plurality of data lines DL.

[0050] The timing controller TC adjusts the image data input from the outside to provide the image data to the data driver DD. The timing controller TC can generate a gate control signal and a data control signal using synchronization signals (such as a dot clock signal, a data enable signal, and a horizontal / vertical synchronization signal) input from the outside. In addition, the timing controller TC provides the generated gate control signal and data control signal to the gate driver GD and the data driver DD, respectively, to control the gate driver GD and the data driver DD.

[0051] The display panel PN is a configuration that displays an image to a user and includes a plurality of sub-pixels SP. In the display panel PN, a plurality of scan lines SL and a plurality of data lines DL cross each other, and a plurality of sub-pixels SP may be formed in crossing portions of the scan lines SL and the data lines DL.

[0052] In the display panel PN, an active area AA and a non-active area NA may be defined.

[0053] The active area AA is an area where an image is displayed in the display device 100. In the active area AA, a plurality of sub-pixels SP configuring a plurality of pixels PX and a pixel circuit for driving the plurality of sub-pixels SP may be arranged. The plurality of sub-pixels SP is the minimum unit configuring the active area AA, and n sub-pixels SP form one pixel PX. In each of the plurality of sub-pixels SP, a thin film transistor for driving a plurality of light emitting diodes 130 may be provided. The plurality of light emitting diodes 130 may be defined in different ways according to the type of the display panel PN. For example, when the display panel PN is an inorganic light emitting display panel PN, the light emitting diode 130 may be a light emitting diode (LED) or a micro light emitting diode (LED).

[0054] In the active area AA, a plurality of signal lines for transmitting various signals to the plurality of sub-pixels SP are arranged. For example, the plurality of signal lines include: a plurality of data lines DL, which provide a data voltage to each of the plurality of sub-pixels SP; and a plurality of scan lines, which provide a scan signal to each of the plurality of sub-pixels SP. The plurality of scan lines SL extend in one direction in the active area AA to be connected to the plurality of sub-pixels SP, and the plurality of data lines DL extend in a direction different from the one direction in the active area AA to be connected to the plurality of sub-pixels SP. In addition, in the active area AA, a low potential power line VSS and a high potential power line VDD may also be provided, but are not limited thereto.

[0055] The non-active area NA is an area where no image is displayed, so that the non-active area NA may be defined as an area extending from the active area AA. In the non-active area NA, a connection line, a pad electrode, or a driving IC (e.g., a gate driver IC or a data driver IC) that transmits a signal to the sub-pixel SP of the active area AA may be disposed.

[0056] Meanwhile, the non-active area NA may be located on the rear surface of the display panel PN (ie, a surface on which the sub-pixel SP is not disposed or may be omitted), and is not limited to that shown in the drawings.

[0057] Meanwhile, drivers such as a gate driver GD, a data driver DD, and a timing controller TC may be connected to the display panel PN in various ways. For example, the gate driver GD may be installed in the non-active area NA in a gate-in-panel (GIP) manner, or installed between a plurality of sub-pixels SP in an active area AA in a gate-in-area (GIA) manner.

[0058] For example, the data driver DD and the timing controller TC are formed in separate flexible films and printed circuit boards, and the display panel PN is electrically connected to the data driver DD and the timing controller TC by bonding the flexible films and printed circuit boards to pad electrodes formed in the non-active area NA of the display panel PN.

[0059] As another example, the gate driver GD is installed in the active area AA in a GIA manner, and a side line SRL is formed to connect the signal line on the front surface of the display panel PN to the pad electrode on the rear surface of the display panel PN to bond the flexible film and the printed circuit board to the rear surface of the display panel PN. At this time, the non-active area NA on the front surface of the display panel PN can be minimized or at least reduced. Therefore, when the gate driver GD, the data driver DD, and the timing controller TC are connected to the display panel PN as described above, a zero border without a border can be substantially achieved, which will refer to Figure 2A and Figure 2B Describe in more detail.

[0060] Figure 2A is a partial cross-sectional view of a display device according to an exemplary embodiment of the present disclosure. Figure 2B is a perspective view of a tiled display device according to an exemplary embodiment of the present disclosure.

[0061] In the non-active area NA of the display panel PN, a plurality of pad electrodes for transmitting various signals to the plurality of sub-pixels SP are provided. For example, in the non-active area NA of the front surface of the display panel PN, a first pad electrode PAD1 for transmitting signals to the plurality of sub-pixels SP is provided. In the non-active area NA of the rear surface of the display panel PN, a second pad electrode PAD2 is provided, which is electrically connected to a driving component such as a flexible film and a printed circuit board.

[0062] In this case, even though not shown in the drawings, various signal lines connected to the plurality of sub-pixels SP, such as the scan lines SL or the data lines DL, extend from the active area AA to the non-active area NA to be electrically connected to the first pad electrode PAD1.

[0063] In addition, the side line SRL is disposed along the side surface of the display panel PN. The side line SRL may electrically connect the first pad electrode PAD1 on the front surface of the display panel PN and the second pad electrode PAD2 on the rear surface of the display panel PN. Therefore, a signal from a driving component on the rear surface of the display panel PN may be transmitted to a plurality of sub-pixels SP through the second pad electrode PAD2, the side line SRL, and the first pad electrode PAD1. Therefore, a signal transmission path is formed from the front surface of the display panel PN to the side surface and the rear surface to minimize or at least reduce the area of ​​the non-active area NA on the front surface of the display panel PN.

[0064] In addition, reference Figure 2B , a tiled display device TD having a large screen size can be realized by connecting a plurality of display devices 100. Figure 2A As shown, when the tiled display device TD is implemented using the display device 100 with a minimized bezel, a seam area where no image is displayed between the display devices 100 is minimized or reduced, so that display quality can be improved.

[0065] For example, a plurality of sub-pixels SP form one pixel PX, and a distance D1 between an outermost pixel PX of one display device 100 and an outermost pixel PX of another display device 100 adjacent to the one display device may be implemented to be equal to a distance D1 between pixels PX in one display device 100. Therefore, a distance between pixels PX between display devices 100 is constantly configured to minimize or at least reduce a seam area.

[0066] However, Figure 2A and Figure 2B It is illustrative such that the display device 100 according to the exemplary embodiment of the present disclosure may be a general display device having a bezel, but is not limited thereto.

[0067] In the following, reference will be made to Figures 3 to 7 The display panel PN of the display device 100 according to the exemplary embodiment of the present disclosure is described in more detail.

[0068] Figure 3 is an enlarged plan view of an active area of ​​a display device according to an exemplary embodiment of the present disclosure. Figure 4 is a cross-sectional view of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure. Figure 3 In the figure, for the convenience of description, the hatching of the cover layer VSSb, the pixel electrode PE and the light emitting diode 130 are omitted, and the contact electrode CE is not shown.

[0069] Reference Figure 3 and Figure 4 , each of the plurality of sub-pixels SP includes a first transistor T1 , a second transistor T2 , a third transistor T3 , a storage capacitor Cst, and one or more light emitting diodes 130 .

[0070] In addition, the plurality of sub-pixels SP may be connected to the plurality of scan lines SL, the plurality of data lines DL, the plurality of reference lines RL, the plurality of high potential power lines VDD, and the plurality of low potential power lines VSS.

[0071] The plurality of sub-pixels SP include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. Each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 includes a light emitting diode 130 and a pixel circuit that independently emits light. For example, the first sub-pixel SP1 is a red sub-pixel SP, the second sub-pixel SP2 is a green sub-pixel SP, and the third sub-pixel SP3 is a blue sub-pixel SP, but exemplary embodiments are not limited thereto.

[0072] Reference Figure 3 and Figure 4 The substrate 110 is a component for supporting various components included in the display device 100, and may be formed of an insulating material. For example, the substrate 110 may be formed of glass or resin. In addition, the substrate 110 may be configured to include a polymer or plastic, or may be formed of a material having flexibility.

[0073] A high potential power line VDD, a plurality of data lines DL, a reference line RL, a light shielding layer LS, and a first capacitor electrode SC1 are disposed on the substrate 110 .

[0074] The high potential power line VDD is a wiring that sends a high potential power supply voltage to each of the plurality of sub-pixels SP. The plurality of high potential power lines VDD may transmit the high potential power supply voltage to the second transistor T2 of each of the plurality of sub-pixels SP. The high potential power line VDD may extend between the plurality of sub-pixels SP along the column direction. For example, the high potential power line VDD may be arranged to extend along the column direction between the first sub-pixel SP1 and the third sub-pixel SP3. In addition, the high potential power line VDD may send the high potential power supply voltage to each of the plurality of sub-pixels SP arranged along the row direction through the auxiliary high potential power line VDDA to be described below.

[0075] The plurality of data lines DL are wirings that send data voltages to the plurality of sub-pixels SP. The plurality of data lines DL may be connected to the first transistor T1 of each of the plurality of sub-pixels SP. The plurality of data lines DL may extend between the plurality of sub-pixels SP in a column direction. For example, the data line DL extending between the first sub-pixel SP1 and the high potential power line VDD in the column direction in the plan view of the display device sends a data voltage to the first sub-pixel SP1. In the plan view, the data line DL disposed between the second sub-pixel SP2 and the third sub-pixel SP3 sends a data voltage to the second sub-pixel SP2. In addition, the data line DL disposed between the third sub-pixel SP3 and the high potential power line VDD in the plan view may send a data voltage to the third sub-pixel SP3.

[0076] Each reference line RL is a wiring that sends a reference voltage to a plurality of sub-pixels SP. The reference line RL may be connected to a third transistor T3 of each of the plurality of sub-pixels SP. The reference line RL may extend in a column direction between the plurality of sub-pixels SP in a plan view. For example, in a plan view, the reference line RL may extend between a first sub-pixel SP1 and a second sub-pixel SP2 along a column direction. The third drain electrode DE3 of the third transistor T3 of each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 adjacent to the reference line RL extends in a row direction to be electrically connected to the reference line RL.

[0077] The light shielding layer LS is disposed on the substrate 110 in each of the plurality of sub-pixels SP. The light shielding layer LS blocks light incident to the transistor from the lower portion of the substrate 110 to minimize or at least reduce leakage current. For example, the light shielding layer LS may block light incident to the second active layer ACT2 of the second transistor T2 as a driving transistor.

[0078] In each of the plurality of sub-pixels SP, a first capacitor electrode SC1 is disposed on the substrate 110. The first capacitor electrode SC1 may form a storage capacitor Cst together with another capacitor electrode. The first capacitor electrode SC1 may be integrally formed with the light shielding layer LS.

[0079] The buffer layer 111 is disposed on the high potential power line VDD, the plurality of data lines DL, the reference line RL, the light shielding layer LS, and the first capacitor electrode SC1. The buffer layer 111 can reduce the penetration of moisture or impurities through the substrate 110. The buffer layer 111 can be composed of a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto. However, depending on the type of the substrate 110 or the type of the transistor, the buffer layer 111 can be omitted, but is not limited thereto.

[0080] The first transistor T1 is disposed in each of the plurality of sub-pixels SP on the buffer layer 111. The first transistor T1 is a transistor that transmits a data voltage to the second gate GE2 of the second transistor T2. The first transistor T1 is turned on by a scan signal from the scan line SL, and the data voltage from the data line DL is transmitted to the second gate GE2 of the second transistor T2 through the turned-on first transistor T1. Therefore, the first transistor T1 may be referred to as a switching transistor.

[0081] The first transistor T1 includes a first active layer ACT1, a first gate GE1, a first source SE1, and a first drain DE1.

[0082] The first active layer ACT1 is disposed on the buffer layer 111. The first active layer ACT1 may be formed of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polycrystalline silicon, but is not limited thereto.

[0083] The gate insulating layer 112 is disposed on the first active layer ACT1. The gate insulating layer 112 is an insulating layer that insulates the first active layer ACT1 from the first gate GE1 and may be composed of a single or double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0084] The first gate GE1 is disposed on the gate insulating layer 112. The first gate GE1 may be electrically connected to the scan line SL. The first gate GE1 may be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr) or an alloy thereof, but is not limited thereto.

[0085] An interlayer insulating layer 113 is disposed on the first gate electrode GE1. Contact holes are formed in the interlayer insulating layer 113 to allow the first source electrode SE1 and the first drain electrode DE1 to be connected to the first active layer ACT1. The interlayer insulating layer 113 is an insulating layer that protects elements below the interlayer insulating layer 113, and may be composed of a single layer or double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0086] A first source electrode SE1 and a first drain electrode DE1 electrically connected to the first active layer ACT1 are disposed on the interlayer insulating layer 113. The first drain electrode DE1 may be electrically connected to the data line DL and the first active layer ACT1, and the first source electrode SE1 may be electrically connected to the first active layer ACT1 and the second gate electrode GE2 of the second transistor T2. The first source electrode SE1 and the first drain electrode DE1 may be made of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but are not limited thereto.

[0087] The second transistor T2 is disposed in each of the plurality of sub-pixels SP on the buffer layer 111. The second transistor T2 is a transistor that provides a driving current to the light emitting diode 130. The second transistor T2 is turned on to control the driving current flowing to the light emitting diode 130. Therefore, the second transistor T2 that controls the driving current may be referred to as a driving transistor.

[0088] The second transistor T2 includes a second active layer ACT2, a second gate GE2, a second source SE2, and a second drain DE2.

[0089] The second active layer ACT2 is disposed on the buffer layer 111. The second active layer ACT2 may be formed of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polycrystalline silicon, but is not limited thereto.

[0090] The gate insulating layer 112 is disposed on the second active layer ACT2, and the second gate GE2 is disposed on the gate insulating layer 112. The second gate GE2 may be electrically connected to the first source electrode SE1 of the first transistor T1. The second gate GE2 may be made of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0091] The interlayer insulating layer 113 is disposed on the second gate electrode GE2, and the second source electrode SE2 and the second drain electrode DE2 electrically connected to the second active layer ACT2 are disposed on the interlayer insulating layer 113. The second drain electrode DE2 may be electrically connected to the second active layer ACT2 and the high potential power line VDD, and the second source electrode SE2 may be electrically connected to the second active layer ACT2 and the light emitting diode 130. The second source electrode SE2 and the second drain electrode DE2 may be made of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr) or an alloy thereof, but is not limited thereto.

[0092] The third transistor T3 is disposed in each of the plurality of sub-pixels SP on the buffer layer 111. The third transistor T3 is a transistor for compensating for the threshold voltage of the second transistor T2. The third transistor T3 is connected between the second source electrode SE2 of the second transistor T2 and the reference line RL. The third transistor T3 is turned on to send the reference voltage to the second source electrode SE2 of the second transistor T2, thereby sensing the threshold voltage of the second transistor T2. Therefore, the third transistor T3 that senses the characteristic of the second transistor T2 may be referred to as a sensing transistor.

[0093] The third transistor T3 includes a third active layer ACT3, a third gate GE3, a third source SE3, and a third drain DE3.

[0094] The third active layer ACT3 is disposed on the buffer layer 111. The third active layer ACT3 may be formed of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polycrystalline silicon, but is not limited thereto.

[0095] The gate insulating layer 112 is disposed on the third active layer ACT3, and the third gate GE3 is disposed on the gate insulating layer 112. The third gate GE3 may be electrically connected to the scan line SL. The third gate GE3 and the first gate GE1 are integrally formed to simultaneously turn on or off the third transistor T3 and the first transistor T1. The third gate GE3 may be made of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr) or an alloy thereof, but is not limited thereto.

[0096] An interlayer insulating layer 113 is disposed on the third gate electrode GE3, and a third source electrode SE3 and a third drain electrode DE3 electrically connected to the third active layer ACT3 are disposed on the interlayer insulating layer 113. The third drain electrode DE3 is electrically connected to the third active layer ACT3 and the reference line RL, and the third source electrode SE3 is electrically connected to the third active layer ACT3 and the second source electrode SE2 of the second transistor T2. The third source electrode SE3 and the third drain electrode DE3 may be made of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but are not limited thereto.

[0097] Next, the second capacitor electrode SC2 is disposed on the buffer layer 111. The second capacitor electrode SC2 is one of the electrodes forming the storage capacitor Cst and may be disposed to overlap with the first capacitor electrode SC1. The first capacitor electrode SC1 and the second capacitor electrode SC2 may be disposed to be spaced apart from each other with the buffer layer 111 therebetween. The second capacitor electrode SC2 is integrally formed with the first active layer ACT1 of the first transistor T1 to be electrically connected to the second gate GE2.

[0098] A plurality of scan lines SL, an auxiliary high potential power line VDDA, and a third capacitor electrode SC3 are disposed on the interlayer insulating layer 113 .

[0099] First, the scan line SL is a wiring that transmits a scan signal to each of the plurality of sub-pixels SP. The scan line SL may extend in a row direction while crossing the plurality of sub-pixels SP. The scan line SL may be electrically connected to the first gate GE1 of the first transistor T1 and the third gate GE3 of the third transistor T3 of each of the plurality of sub-pixels SP.

[0100] The auxiliary high potential power line VDDA is disposed on the interlayer insulating layer 113. The auxiliary high potential power line VDDA extends in the row direction to be disposed to cross the plurality of sub-pixels SP. That is, in a plan view, the auxiliary high potential power line VDDA overlaps the plurality of sub-pixels SP. The auxiliary high potential power line VDDA may be electrically connected to the high potential power line VDD extending in the column direction and the second drain electrode DE2 of the second transistor T2 of each of the plurality of sub-pixels SP disposed in the row direction.

[0101] The third capacitor electrode SC3 is disposed on the interlayer insulating layer 113. The third capacitor electrode SC3 is an electrode forming a storage capacitor Cst, and may be disposed to overlap the first capacitor electrode SC1 and the second capacitor electrode SC2. The third capacitor electrode SC3 is integrally formed with the second source electrode SE2 and the third source electrode SE3 of the second transistor T2 to be electrically connected to the second source electrode SE2. In addition, the second source electrode SE2 may be electrically connected to the first capacitor electrode SC1 through a contact hole formed in the interlayer insulating layer 113, the gate insulating layer 112, and the buffer layer 111. Therefore, the first capacitor electrode SC1 and the third capacitor electrode SC3 may be electrically connected to the second source electrode SE2 of the second transistor T2.

[0102] When the light emitting diode 130 emits light, the storage capacitor Cst stores the potential difference between the second gate electrode GE2 and the second source electrode SE2 of the second transistor T2, thereby providing a constant current to the light emitting diode 130. The storage capacitor Cst includes a first capacitor electrode SC1, a second capacitor electrode SC2, and a third capacitor electrode SC3 to store a voltage between the second gate electrode GE2 and the second source electrode SE2 of the second transistor T2. The first capacitor electrode SC1 is formed on the substrate 110 and is electrically connected to the second source electrode SE2, and the second capacitor electrode SC2 is formed on the buffer layer 111 and is electrically connected to the second gate electrode GE2. The third capacitor electrode SC3 is formed on the interlayer insulating layer 113 and is electrically connected to the second source electrode SE2.

[0103] The first passivation layer 114 is disposed on the first transistor T1, the second transistor T2, the third transistor T3 and the storage capacitor Cst. The first passivation layer 114 is an insulating layer that protects components below the first passivation layer 114 and may be composed of a single or double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0104] The first planarization layer 115 is disposed on the first passivation layer 114. The first planarization layer 115 may planarize an upper portion of the substrate 110 on which a plurality of transistors and the storage capacitor Cst are disposed. The first planarization layer 115 may be composed of a single layer or a double layer and may be formed of, for example, a photoresist or an acrylic-based organic material, but is not limited thereto.

[0105] Meanwhile, even though not shown in the figure, an additional passivation layer may be further disposed on the first planarization layer 115. For example, a passivation layer composed of a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx) is formed on the first planarization layer 115 to protect the structure below the passivation layer.

[0106] Next, a connection electrode 120 is disposed on the first planarization layer 115. The connection electrode 120 is disposed in each of the plurality of sub-pixels SP. The connection electrode 120 is an electrode electrically connecting the second transistor T2 and the pixel electrode PE. The connection electrode 120 may be electrically connected to the second source electrode SE2 through a contact hole formed in the first planarization layer 115 and the first passivation layer 114.

[0107] The connection electrode 120 may have a double-layer structure formed by a first connection layer 120a and a second connection layer 120b. The first connection layer 120a is disposed on the first planarization layer 115, and a second connection layer 120b covering the first connection layer 120a is disposed. In one embodiment, the second connection layer 120b directly contacts the first connection layer 120a. The second connection layer 120b may be disposed to surround all top surfaces and side surfaces of the first connection layer 120a. The second connection layer 120b includes a material that is more corrosion-resistant than the first connection layer 120a, so that when the display device 100 is manufactured, a short circuit defect caused by migration between the first connection layer 120a and the adjacent wiring line can be minimized or at least reduced. For example, the first connection layer 120a is formed of a conductive material such as copper (Cu) or chromium (Cr), and the second connection layer 120b is formed of molybdenum (Mo) or titanium molybdenum (MoTi), but is not limited thereto.

[0108] A plurality of low potential power lines VSS are provided on the first planarization layer 115. The plurality of low potential power lines VSS are wirings for transmitting a low potential power voltage to the light emitting diode 130. The plurality of low potential power lines VSS extend in a column direction in each of the plurality of sub-pixels SP. For example, a pair of low potential power lines VSS spaced apart from each other at a predetermined interval may be provided in each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3.

[0109] Each of the plurality of low potential power lines VSS includes a conductive layer VSSa and a cover layer VSSb. The conductive layer VSSa is disposed on the first planarization layer 115, and the cover layer VSSb covering all top and side surfaces of the conductive layer VSSa is disposed on the conductive layer VSSa. For example, the conductive layer VSSa is formed of a conductive material such as copper (Cu) and chromium (Cr). In addition, the cover layer VSSb is formed of a material more resistant to corrosion than the conductive layer VSSa, such as molybdenum (Mo) or titanium molybdenum (MoTi), but is not limited thereto.

[0110] The second passivation layer 116 is disposed on the connection electrode 120 and the low potential power line VSS. The second passivation layer 116 is an insulating layer that protects the components below the second passivation layer 116, and may be composed of a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto. In addition, the second passivation layer 116 may protect the low potential power line VSS and the connection electrode 120 from the influence of the fluid WT during the self-assembly process of the light emitting diode 130, which will be described in more detail below.

[0111] The second planarization layer 117 is disposed on the second passivation layer 116. The second planarization layer 117 includes a plurality of openings 117a, and each of the plurality of light emitting diodes 130 is disposed in the opening 117a. The plurality of openings 117a may be disposed in each of the plurality of sub-pixels SP. For example, the number of the openings 117a is the same as the number of the light emitting diodes 130 disposed in one sub-pixel SP.

[0112] The plurality of openings 117a are portions into which the plurality of light emitting diodes 130 are inserted, and are also referred to as pockets. The plurality of openings 117a may be formed to overlap with the plurality of low potential power lines VSS. One opening 117a may overlap with a region between a pair of low potential power lines VSS disposed adjacent to each other in one sub-pixel SP. For example, a cover layer VSSb of a pair of low potential power lines VSS may overlap with the opening 117a. The second planarization layer 117 may be composed of a single layer or a double layer, and may be formed of, for example, a photoresist or an acrylic-based organic material, but is not limited thereto.

[0113] Next, a plurality of light emitting diodes 130 are disposed in a plurality of openings 117a of the second planarization layer 117 on the second passivation layer 116. One or more light emitting diodes 130 are disposed in one sub-pixel SP. For example, two light emitting diodes 130 may be disposed in one sub-pixel SP. The light emitting diode 130 is an element that emits light by current. The light emitting diode 130 may include a light emitting diode 130 that emits red light, green light, and blue light, and various colors of light including white may be realized by a combination thereof. In addition, light of various colors may be realized using a light emitting diode 130 that emits a specific color of light and a light conversion member that converts light from the light emitting diode 130 into another color of light. The light emitting diode 130 is electrically connected between the second transistor T2 and the low potential power supply line VSS to emit light by providing a driving current provided by the second transistor T2.

[0114] At this time, the plurality of light emitting diodes 130 provided in one sub-pixel SP may be connected in parallel. That is, one electrode of each of the plurality of light emitting diodes 130 is connected to the source of the second transistor T2, and the other electrode may be connected to the same low potential power line VSS.

[0115] Meanwhile, the light emitting diode 130 may include a red light emitting diode, a green light emitting diode, and a blue light emitting diode. For example, the red light emitting diode may be disposed in a first sub-pixel of the plurality of sub-pixels SP, the green light emitting diode may be disposed in a second sub-pixel SP2 of the plurality of sub-pixels SP, and the blue light emitting diode may be disposed in a third sub-pixel SP3. However, the configuration of the light emitting diode 130 is illustrative, but not limited thereto.

[0116] At this time, the light emitting diode 130 disposed in each of the plurality of sub-pixels SP may have different sizes. For example, the red light emitting diode has the largest size (e.g., the first size), the blue light emitting diode has the smallest size (e.g., the second size), and the green light emitting diode may have a size between the red light emitting diode and the blue light emitting diode (e.g., the third size). The red light emitting diode, the green light emitting diode, and the blue light emitting diode have different sizes and different luminous efficiencies, so that the design of the second transistor T2 for driving the red light emitting diode, the green light emitting diode, and the blue light emitting diode may be changed. For example, the second transistor T2 of the first sub-pixel SP1 for driving the red light emitting diode includes a second active layer ACT2 having the largest size, and the second transistor T2 of the third sub-pixel SP3 for driving the blue light emitting diode may include a second active layer ACT2 having the smallest size. However, the size of the light emitting diode 130 is illustrative, and all the light emitting diodes 130 may have the same size or may have different sizes, but are not limited thereto.

[0117] In addition, despite the Figure 3 In the embodiment, for convenience of description, it is shown that two light emitting diodes 130 are provided in each of the plurality of sub-pixels SP, but the number of the light emitting diodes 130 provided in each of the plurality of sub-pixels SP is not limited thereto.

[0118] The light emitting diode 130 includes a first semiconductor layer 131 , a light emitting layer 132 , a second semiconductor layer 133 , a first electrode 134 , a second electrode 135 , a side electrode 136 , and a first insulating film PAS1 .

[0119] The first semiconductor layer 131 is disposed on the second passivation layer 116, and the second semiconductor layer 133 is disposed on the first semiconductor layer 131. The first semiconductor layer 131 and the second semiconductor layer 133 may be layers formed by doping n-type and p-type impurities into a specific material. For example, the first semiconductor layer 131 and the second semiconductor layer 133 may be layers formed by doping p-type and n-type impurities into a material such as gallium nitride (GaN), indium aluminum phosphide (InAlP), or gallium arsenide (GaAs). In addition, the p-type impurity may be magnesium (Mg), zinc (Zn), and beryllium (Be), and the n-type impurity may be silicon (Si), germanium (Ge), and tin (Sn), but is not limited thereto.

[0120] The light emitting layer 132 is disposed between the first semiconductor layer 131 and the second semiconductor layer 133. Holes and electrons are supplied from the first semiconductor layer 131 and the second semiconductor layer 133 to the light emitting layer 132 to emit light. The light emitting layer 132 may be formed of a single layer or a multi-quantum well (MQW) structure, and may be formed of, for example, indium gallium nitride (InGaN) or gallium nitride (GaN), but is not limited thereto.

[0121] The side electrode 136 (e.g., the third electrode) is disposed on the side surface of the first semiconductor layer 131 (not the second semiconductor layer 133). The side electrode 136 is disposed to correspond to (e.g., overlap) the side surface of the first semiconductor layer 131. The side electrode 136 is an electrode that causes the self-assembly of the light-emitting diode 130 by forming an attractive force (e.g., a magnetic force) with the magnet MG during the self-assembly of the light-emitting diode 130. The side electrode 136 is disposed at the lower portion of the light-emitting diode 130 to self-assemble the first semiconductor layer 131 of the light-emitting diode 130 so as to face the low potential power line VSS. Figure 4As shown, the side electrode 136 is located on the side surface of the first semiconductor layer 131, so that the side electrode 136 is located between the end of the first electrode 134 and the side surface of the first semiconductor layer 131. The side electrode 136 may include a ferromagnetic material, for example, formed of nickel (Ni). In addition, the side electrode 136 also includes a layer formed of a ferromagnetic material and an opaque conductive material with high reflectivity to form a double-layer structure. In this case, some of the light facing the side surface of the light emitted from the light emitting diode 130 is reflected from the side electrode 136 to be guided to the upper portion of the light emitting diode 130.

[0122] The first electrode 134 is disposed below the first semiconductor layer 131. The first electrode 134 is an electrode electrically connecting the light emitting diode 130 and the low potential power line VSS. The first electrode 134 may cover the entire lower portion of the light emitting diode 130. The first electrode 134 may cover the lower portion of the side electrode 136 from the bottom surface of the first semiconductor layer 131. Depending on whether a reflective layer is provided, the first electrode 134 may be formed of different materials. For example, as shown in the figure, when a separate reflective layer is not formed below the light emitting diode 130, the first electrode 134 may be composed of an opaque conductive material with high reflection efficiency, such as titanium (Ti), gold (Au), silver (Ag), copper (Cu) or an alloy thereof. That is, the first electrode 134 may be used as a reflective electrode. On the contrary, when a reflective layer is formed below the light emitting diode 130, the first electrode 134 may be composed of a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO), but is not limited thereto. Therefore, light guided to the lower portion of the light emitting diode 130 may be reflected toward the upper portion of the light emitting diode 130 by the first electrode 134 or a separate reflective layer, and light emitting efficiency may be improved.

[0123] The second electrode 135 is disposed on the top surface of the second semiconductor layer 133. The second electrode 135 is an electrode that electrically connects a pixel electrode PE to be described below and the second semiconductor layer 133. For example, the second electrode 135 is formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), but is not limited thereto.

[0124] A first insulating film PAS1 is provided to surround at least a portion of the first semiconductor layer 131, the light emitting layer 132, the second semiconductor layer 133, and the second electrode 135. The first insulating film PAS1 is formed of an insulating material to protect the first semiconductor layer 131, the light emitting layer 132, and the second semiconductor layer 133. The first insulating film PAS1 may cover a side surface of the first semiconductor layer 131, a side surface of the light emitting layer 132, a side surface of the second semiconductor layer 133, and a portion of an edge of the second electrode 135. Figure 4As shown, the end of the first insulating film PAS1 contacts the upper surface of the first electrode 134. A portion of the second electrode 135 is exposed from the first insulating film PAS1, and the pixel electrode PE formed later and the second electrode 135 can be electrically connected. In addition, the first insulating film PAS1 is disposed between the side electrode 136 and the first semiconductor layer 131, so that the side electrode 136 is not directly connected to the first semiconductor layer 131. The side electrode 136 may be disposed to be spaced apart from the first semiconductor layer 131 by the first insulating film PAS1. Alternatively, the side electrode 136 may be electrically connected to the first semiconductor layer 131 through the first electrode 134. As shown in FIG. Figure 4 As shown, in one embodiment, the side electrode 136 is directly connected to the first electrode 134 .

[0125] The contact electrode CE is disposed on the side surface of the light emitting diode 130. The contact electrode CE is an electrode for electrically connecting the light emitting diode 130 and the low potential power line VSS. The contact electrode CE may be electrically connected to the low potential power line VSS through a contact hole formed in the second passivation layer 116. In addition, the contact electrode CE is arranged to surround at least a portion of the lower side surface of the light emitting diode 130 to contact the side electrode 136 and the first electrode 134. Therefore, the low potential power line VSS and the light emitting diode 130 may be electrically connected through the contact electrode CE.

[0126] At the same time, Figure 4 , it is shown that only one low potential power line VSS between a pair of low potential power lines VSS is electrically connected to the light emitting diode 130 through the contact electrode CE. However, the contact electrode CE may be electrically connected to the pair of low potential power lines VSS, but is not limited thereto.

[0127] Next, a third planarization layer 118 is disposed on the second planarization layer 117, the light emitting diode 130, and the contact electrode CE. The third planarization layer 118 planarizes the upper portion of the substrate 110 on which the light emitting diode 130 is disposed, and can fix (attach) the light emitting diode 130 to the substrate 110. The third planarization layer 118 may be composed of a single layer or a double layer, and may be formed of, for example, a photoresist or an acrylic-based organic material, but is not limited thereto.

[0128] The pixel electrode CE is disposed on the third planarization layer 118. The pixel electrode PE is an electrode electrically connecting the plurality of light emitting diodes 130 and the connection electrode 120. The pixel electrode PE is electrically connected to the connection electrode 120 and the second transistor T2 through a contact hole formed in the third planarization layer 118, the second planarization layer 117, and the second passivation layer 116. In addition, the pixel electrode PE may be electrically connected to the second electrode 135 of the light emitting diode 130 exposed from the third planarization layer 118. Therefore, the second electrode 135 of the light emitting diode 130, the connection electrode 120, and the second source electrode SE2 of the second transistor T2 may be electrically connected to each other through the pixel electrode PE. The pixel electrode PE is formed of a conductive material, for example, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), but is not limited thereto.

[0129] The protective layer 119 is disposed on the pixel electrode PE. The protective layer 119 is a layer for protecting components below the protective layer 119 and may be composed of a single layer or a double layer of translucent epoxy resin, silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0130] Meanwhile, even though not shown in the figure, a black matrix may be further disposed on the third planarization layer 118. The black matrix is ​​disposed between the plurality of sub-pixels SP on the third planarization layer 118 to reduce color mixing between the plurality of sub-pixels SP. In addition, the black matrix covers the portion where the connection electrode 120 and the pixel electrode PE are connected to suppress light leakage from the portion. The black matrix may be formed of an opaque material, such as a black resin, but is not limited thereto.

[0131] Therefore, in the display device 100 according to the exemplary embodiment of the present disclosure, the side electrode 136 is formed on the side surface of the first semiconductor layer 131 to improve the light emitting efficiency of the light emitting diode 130. If the side electrode 136 is formed under the light emitting diode 130, the side electrode composed of nickel having low light reflection efficiency absorbs some light directed to the lower part of the light emitting diode 130 to reduce the light reflected to the upper part of the light emitting diode 130. Therefore, instead of the side electrode 136 having low light reflection efficiency, another electrode having high reflection characteristics is disposed under the first semiconductor layer 131 to improve the light emitting efficiency of the light emitting diode 130. Therefore, the side electrode 136 is partially formed on the lower side surface of the light emitting diode 130 to align the direction of the light emitting diode 130 during the self-assembly process. In this case, a separate reflective layer or a reflective electrode is formed under the light emitting diode 130 to improve the light emitting efficiency of the light emitting diode 130.

[0132] Meanwhile, in the display device 100 according to the exemplary embodiment of the present disclosure, a plurality of light emitting diodes 130 are self-assembled on the substrate 110 using a plurality of low potential power lines VSS. The plurality of light emitting diodes 130 are polarized by the electric field medium to have polarity. Therefore, the plurality of light emitting diodes 130 can be moved or fixed in a specific direction by the electric field, and the plurality of light emitting diodes 130 can be easily transferred to the display device 100 using this characteristic.

[0133] In the following, reference will be made to FIG. 5A to FIG. 6E A method of manufacturing the display device 100 according to an exemplary embodiment of the present disclosure is described.

[0134] FIG. 5A to FIG. 5D is a cross-sectional view for explaining a method of manufacturing a light emitting diode of a display device according to an exemplary embodiment of the present disclosure. FIG. 6A to FIG. 6E is a cross-sectional view for explaining a method of manufacturing a display device according to an exemplary embodiment of the present disclosure using a self-assembly process.

[0135] Reference FIG. 5A to FIG. 5D , the light emitting diode 130 to be self-assembled in the display device 100 may be formed on the wafer WF.

[0136] First, refer to Figure 5A , a first semiconductor layer 131 , a light emitting layer 132 , and a second semiconductor layer 133 of a light emitting diode 130 are formed on the wafer WF.

[0137] The wafer WF is a substrate for growing the plurality of light emitting diodes 130, and may be formed of various materials according to materials configuring the plurality of light emitting diodes 130. For example, the wafer WF may be formed of sapphire, gallium nitride (GaN), silicon (Si), or silicon carbide (SiC), but is not limited thereto.

[0138] An epitaxial layer is grown on the wafer WF. The epitaxial layer is a layer formed of a semiconductor material constituting the plurality of light emitting diodes 130. Semiconductor layers forming the first semiconductor layer 131, the light emitting layer 132, and the second semiconductor layer 133 may be sequentially formed by growing semiconductor crystals on the wafer WF. In addition, a conductive layer for forming the second electrode 135 may be formed on the epitaxial layer.

[0139] Next, the epitaxial layer and the conductive layer are patterned into a plurality of components to form a first semiconductor layer 131 , a light emitting layer 132 , a second semiconductor layer 133 , and a second electrode 135 of each of the plurality of light emitting diodes 130 .

[0140] Furthermore, a first insulating film PAS1 is provided to cover the first semiconductor layer 131, the light emitting layer 132, the second semiconductor layer 133, and the second electrode 135. At this time, a portion of the first insulating film PAS1 covering the second electrode 135 is patterned to expose the second electrode 135 from the first insulating film PAS1.

[0141] Reference together Figure 5A and Figure 5B , a metal ML is formed on the front surface of the wafer WF, and a first semiconductor layer 131, a light emitting layer 132, a second semiconductor layer 133, a second electrode 135, and a first insulating film PAS1 are formed on the front surface of the wafer WF. A photoresist pattern PR is formed adjacent to the lower side surface of the first semiconductor layer 131. Therefore, the remaining portion of the metal layer ML except for a portion of the metal layer ML corresponding to the photoresist pattern PR is etched to form a side electrode 136. In this case, the side electrode 136 may be formed of a portion in contact with the side surface of the first insulating film PAS1 and a portion protruding from the portion in contact with the side surface to contact with the top surface of the wafer WF. That is, the side electrode 136 may be formed in an L shape. A portion of the side electrode 136 in contact with the top surface of the wafer WF is a residual film formed by the processing process and may be removed by a subsequent process.

[0142] Next, refer to Figure 5C , the light emitting diode 130 is transferred to the first temporary substrate TS1, and a bonding material BD is formed on the first temporary substrate TS1 to arrange the light emitting diode 130 on the first temporary substrate TS1 so that the lower side of the light emitting diode 130 faces upward. The light emitting diode 130 is separated from the wafer WF to temporarily attach the bonding material BD on the first temporary substrate TS1. Therefore, the wafer WF and the light emitting diode 130 are separated, and one surface of the first semiconductor layer 131 of the light emitting diode 130 can be exposed to the outside.

[0143] Next, the protruding portion of the side electrode 136 in contact with the top surface of the wafer WF, that is, the remaining film, can be partially etched. In this case, only a portion of the L-shaped side electrode 136 in contact with the first insulating film PAS1 can be retained. The portion of the side electrode 136 that does not contact the first insulating film PAS1 and protrudes is removed so that the protruding portion of the side electrode 136 does not hinder the light emitting diode 130 from being placed in the opening 117a. In addition, in the self-assembly process device of the light emitting diode 130 using the magnet MG and the electric field, a deviation in the assembly rate of multiple light emitting diodes 130 may occur due to the remaining film of the side electrode 136. Therefore, the remaining film of the side electrode 136 is removed to retain only a portion of the side electrode 136 in contact with the first insulating film PAS1 to reduce the deviation in the assembly rate, and the light emitting diode 130 can be controlled to be easily placed in the opening 117a.

[0144] In addition, the first electrode 134 is formed on one surface (e.g., the lower surface) of the first semiconductor layer 131. At this time, when the first electrode 134 is formed of a transparent conductive material having a high step coverage, the first electrode 134 may be formed to cover the side of the light emitting diode 130. For example, the first electrode 134 may be formed to cover a portion of the side surface of the side electrode 136 while covering one surface of the first semiconductor layer 131 and one surface of the side electrode 136. However, the first electrode 134 may be formed on one surface of the side electrode 136 and one surface of the first semiconductor layer 131, but is not limited thereto.

[0145] Reference Figure 5D , the light emitting diode 130 may be transferred from the first temporary substrate TS1 to the second temporary substrate TS2. Therefore, the light emitting diode 130 may be arranged such that the second electrode 135 faces upward.

[0146] In addition, a second insulating film PAS2 is formed to cover the light emitting diode 130. The second insulating film PAS2 may cover the upper portion and the side of the light emitting diode 130. When the light emitting diode 130 is self-assembled in the fluid WT, the second insulating film PAS2 protects the light emitting diode 130 and suppresses the light emitting diode 130 from adhering to another light emitting diode 130 or adhering to a location other than the opening 117a on the substrate 110. The semiconductor layer of the plurality of light emitting diodes 130 is a material having polarity, and if the second insulating film PAS2 is not provided, it is adhered to another location. Therefore, the second insulating film PAS2 is formed to suppress the plurality of light emitting diodes 130 from adhering to each other to be configured into a block or adhering to a region other than the opening 117a, and the self-assembly yield of the light emitting diode 130 can be improved.

[0147] Next, refer to Fig. 6A , the light emitting diode 130 in which the second insulating film PAS2 is formed is placed in the chamber CB filled with the fluid WT. The fluid WT may include water, and the top of the chamber CB filled with the fluid is opened.

[0148] Next, the mother substrate 10 may be positioned on the cavity CB filled with the light emitting diode 130. The mother substrate 10 is a substrate 110 to which a plurality of substrates 110 forming the display device 100 are connected, and the mother substrate 10 is cut to be divided into a plurality of substrates 110. When the plurality of light emitting diodes 130 are self-assembled, the mother substrate 10 on which a plurality of low potential power lines VSS, the second passivation layer 116, and the second planarization layer 117 are formed may be used.

[0149] Specifically, refer to Figure 6B, a buffer layer 111, a gate insulating layer 112, an interlayer insulating layer 113, a first passivation layer 114, a first planarization layer 115, a plurality of connection electrodes 120 and a plurality of low potential power lines VSS, a second passivation layer 116 and a second planarization layer 117 may be sequentially formed on the substrate 110 together with the pixel circuit. At this time, a contact hole exposing the low potential power line VSS is not formed in the second passivation layer 116, and an opening 117a in which the light emitting diode 130 is located may be formed in the second planarization layer 117. The second passivation layer 116 is provided to cover the entire low potential power line VSS, and may protect the low potential power line VSS from being damaged by the fluid WT.

[0150] The plurality of low potential power lines VSS are used as assembly lines and assembly electrodes to self-assemble the light emitting diodes 130 during the manufacturing process of the display device 100, and may be used as the low potential power line VSS after the manufacturing process of the display device 100 is completed. During the manufacturing process of the display device 100, different voltages are applied to two adjacent low potential power lines VSS, and after the manufacturing process of the display device 100 is completed, the same low potential power supply voltage may be applied to the two adjacent low potential power lines VSS.

[0151] Next, the mother substrate 10 is placed in the chamber CB so that the second planarization layer 117 of the mother substrate 10 faces the fluid WT, and the magnet MG is located on the rear surface of the mother substrate 10. The light emitting diode 130 sinking or floating on the bottom of the chamber CB can be moved toward the assembly substrate 110 by the magnetic force of the magnet MG. That is, the magnet MG is used to move the light emitting diode 130 to the assembly substrate 110.

[0152] At this time, the light emitting diode 130 may include a conductive material that reacts to the magnet MG moved by the magnetic field. For example, the side electrode 136 of the light emitting diode 130 includes a ferromagnetic material such as nickel, iron, or cobalt to align the direction of the light emitting diode 130 pointing to the magnet MG. Specifically, the side electrode 136 is provided at the lower portion of the light emitting diode 130 to align the lower portion of the light emitting diode 130 to point to the mother substrate 10. Therefore, due to the magnetic attraction between the magnet MG and the side electrode 136 of the light emitting diode 130, the light emitting diode 130 can be initially moved to the mother substrate 10 using the magnet MG.

[0153] Next, let’s refer to Figure 6B and Figure 6C , AC voltage is applied to a plurality of low potential power lines VSS to form an electric field. Different voltages may be applied to a pair of low potential power lines VSS adjacent to each other. Therefore, an electric field may be formed between the pair of low potential power lines VSS adjacent to each other.

[0154] The light emitting diode 130 is polarized by the electric field medium to have polarity. In addition, by dielectrophoresis (DEP), that is, an electric field, the dielectric polarized light emitting diode 130 can be moved or fixed in a specific direction. Therefore, a plurality of light emitting diodes 130 are self-assembled on the low potential power line VSS using dielectrophoresis.

[0155] Next, refer to Figure 6C , after the light emitting diode 130 is self-assembled in the opening 117a of the second planarization layer 117, the second insulating film PAS2 may be removed. The second insulating film PAS2 is removed to expose the side surfaces of the side electrode 136 and the first electrode 134.

[0156] Reference Fig.6D , a contact hole is formed in the second passivation layer 116 to expose the capping layer VSSb of the low potential power line VSS, and the connection electrode 120 is formed. In this case, the contact hole can be formed in the second passivation layer 116 using a photoresist pattern that partially covers the opening 117a in which the light emitting diode 130 is disposed. For example, the photoresist pattern is formed to cover the upper portion of the light emitting diode 130 and a portion of the side surface of the light emitting diode 130, and the side surface of the light emitting diode 130 and the top surface of the second passivation layer 116 adjacent to one side surface can be exposed from the photoresist pattern. In addition, a portion of the second passivation layer 116 exposed from the photoresist pattern is etched to form a contact hole.

[0157] In addition, a contact hole of the second passivation layer 116 and a contact electrode CE covering the side surface of the light emitting diode 130 are formed to electrically connect the low potential power line VSS and the first semiconductor layer 131 of the light emitting diode 130, the side electrode 136 and the first electrode 134. That is, the contact electrode CE and the light emitting diode 130 can form a side contact through the side electrode 136.

[0158] Next, refer to Fig. 6E A third planarization layer 118 is formed on the front surface of the substrate 110, and a contact hole is formed in the third planarization layer 118 and the second planarization layer 117 to expose the connection electrode 120. In addition, a contact hole may be formed in the third planarization layer 118 to expose the second electrode 135 of the light emitting diode 130.

[0159] Next, a pixel electrode PE is formed on the third planarization layer 118 to electrically connect the light emitting diode 130 and the connection electrode 120. Finally, a protective layer 119 is formed on the pixel electrode PE to manufacture the display device 100.

[0160] At the same time, a side electrode 136 for contacting the contact electrode CE is formed on the first insulating film PAS1 to protect the light emitting diode 130 during the etching process. For example, when the side electrode 136 is formed to directly contact the side surface of the first semiconductor layer 131 and the first insulating film PAS1 is formed to cover both the side electrode 136 and the first semiconductor layer 131, the light emitting diode 130 may be damaged during a subsequent process. For example, after the self-assembly of the light emitting diode 130, the first insulating film PAS1 needs to be removed to connect the side electrode 136 and the contact electrode CE. In the process of removing the first insulating film PAS1, a portion of the first semiconductor layer 131, the light emitting layer 132, and the second semiconductor layer 133 may be damaged. In addition, due to the process margin, it is difficult to only partially etch the first insulating film PAS1 covering the side electrode 136, so that the first insulating film PAS1 needs to be completely removed, which inevitably causes damage to the light emitting diode 130.

[0161] Therefore, in the manufacturing method of the display device 100 according to the exemplary embodiment of the present disclosure, the first insulating film PAS1 that protects the first semiconductor layer 131, the light emitting layer 132, and the second semiconductor layer 133 is formed. The side electrode 136 and the second insulating film PAS2 are formed on the first insulating film PAS1. In order to connect the side electrode 136 and the contact electrode CE, only the second insulating film PAS2 can be removed, so that the first insulating film PAS1 does not need to be removed. Therefore, the first insulating film PAS1 remains unremoved to protect the first semiconductor layer 131, the light emitting layer 132, and the second semiconductor layer 133. In addition, during the manufacturing process, the second insulating film PAS2 is formed to protect the light emitting diode 130 from the influence of the fluid WT or to suppress the light emitting diode 130 from adhering to other structures. In addition, the side electrode 136 and the first semiconductor layer 131 are separated by the first insulating film PAS1, but at the same time, the first electrode 134 that contacts the side electrode 136 and one surface of the first semiconductor layer 131 is formed to electrically connect the side electrode 136 and the first semiconductor layer 131. Therefore, in the method of manufacturing the display device 100 according to the exemplary embodiment of the present disclosure, the side electrode 136 is formed on the first insulating film PAS1. Therefore, damage to the first semiconductor layer 131, the light emitting layer 132, and the second semiconductor layer 133 during the connection process of the side electrode 136 and the connection electrode CE can be suppressed.

[0162] Figure 7 is a cross-sectional view of a display device according to an exemplary embodiment of the present disclosure. Figure 8 is an enlarged plan view of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure. Figure 8 In FIG. 7 , only the ohmic contact electrode 737 of the light emitting diode 730 and the cover layer VSSb of the low potential power line VSS are shown. Figure 7 and Figure 8The display device 700 and Figures 1 to 4 The only difference between the display devices 100 is the light emitting diode 730, but other configurations are substantially the same, so redundant description will be omitted.

[0163] Reference Figure 7 and Figure 8 The light emitting diode 730 includes a first semiconductor layer 131 , a light emitting layer 132 , a second semiconductor layer 133 , a first electrode 134 , a second electrode 135 , a side electrode 136 and an ohmic contact electrode 737 .

[0164] In the cross-sectional view of the display device, the ohmic contact electrode 737 is disposed between the first portion of the first electrode 134 and the first portion of the first semiconductor layer 131, rather than between the second portion of the first electrode 134 and the second portion of the first semiconductor layer 131. Figure 7 As shown, the remaining portion of the first semiconductor layer 131 that is not in contact with the ohmic contact electrode 737 is in contact with the first electrode 134. The ohmic contact electrode 737 may be arranged to overlap with the region between a pair of low potential power lines VSS. That is, the ohmic contact electrode 737 is located between the pair of low potential power lines VSS in the cross-sectional view. The bottom surface of the first semiconductor layer 131 may be composed of a first portion in contact with the first electrode 134 and a second portion in contact with the ohmic contact electrode 737. The ohmic contact electrode 737 is formed in a portion of the bottom surface of the first semiconductor layer 131 to minimize or reduce the influence of the ohmic contact electrode 737 during the self-assembly process. The ohmic contact electrode 737 may be arranged to be spaced apart from the region where the first electrode 134 and the second passivation layer 116 are in contact with each other. The ohmic contact electrode 737 is arranged to overlap with the groove formed in the region between the pair of low potential power lines VSS. Therefore, when self-assembly is performed by minimizing interference of the ohmic contact electrode 737 and the second passivation layer 116 , the light emitting diode 730 may be easily positioned on the second passivation layer 116 of the opening 117 a .

[0165] The contact resistance between the ohmic contact electrode 737 and the first semiconductor layer 131 is low, so that current can be easily injected into the first semiconductor layer 131 through the ohmic contact electrode 737. The ohmic contact electrode 737 is formed of a conductive material such as chromium (Cr) or nickel (Ni) and is composed of a single layer or a double layer, but is not limited thereto. For example, the ohmic contact electrode 737 may be composed of a single layer of chromium or a double layer of chromium and nickel.

[0166] Meanwhile, the ohmic contact electrode 737 formed of a material such as chromium has low light reflection efficiency. If only the ohmic contact electrode 737 is disposed below the first semiconductor layer 131, light toward the lower portion of the first semiconductor layer 131 is not reflected by the ohmic contact electrode 737 but is partially absorbed, thereby reducing the light emitting efficiency of the light emitting diode 730. Therefore, the ohmic contact electrode 737 is disposed below the first semiconductor layer 131 having a minimum size, and the first electrode 134 formed of a conductive material having a high reflectivity is disposed below the ohmic contact electrode 737 to improve light extraction efficiency.

[0167] In the display device 700 according to another exemplary embodiment of the present disclosure, an ohmic contact electrode 737 is formed between the first electrode 134 of the light emitting diode 730 and the first semiconductor layer 131 to reduce resistance. The ohmic contact electrode 737 is partially formed to correspond to a region between a pair of low potential power lines VSS to minimize or at least reduce the reduction of light emitting efficiency by the ohmic contact electrode 737 while improving resistance.

[0168] Fig. 9 is a cross-sectional view of a display device according to still another exemplary embodiment of the present disclosure. Fig.10 is a cross-sectional view of a display device according to still another exemplary embodiment of the present disclosure. Fig. 9 The first semiconductor layer 931 and the first electrode 934 of the display device 900 are Figures 1 to 4 The first semiconductor layer 931 and the first electrode 934 of the display device 100 are different. Fig.10 The first semiconductor layer 1031 and the ohmic contact electrode 1037 of the display device 1000 are Figure 7 to Figure 8 The first semiconductor layer 931 and the first electrode 934 and the ohmic contact electrode 1037 of the display device 700 are different. However, other configurations are substantially the same, and thus redundant description will be omitted.

[0169] Reference Fig. 9, an irregular structure 901 is formed on the bonding surface between the first semiconductor layer 931 and the first electrode 934. The irregular structure 901 may be formed on a portion of the bottom surface of the first semiconductor layer 931, and therefore, the irregular structure 901 may also be formed on the first electrode 934 covering the irregular structure 901 of the first semiconductor layer 931. In one embodiment, the irregular structure 901 is an irregular portion in the bottom surface of the first semiconductor layer 931. The bottom surface of the first semiconductor layer 931 is substantially flat except for the irregular structure 901 including a jagged surface at a portion of the bottom surface of the first semiconductor layer 931 corresponding to the irregular structure 901. The irregular structure 901 overlaps with an area between a pair of low potential power lines VSS, and may be disposed to be spaced apart from the contact area of ​​the first electrode 934 and the second passivation layer 116. Due to the shape of the irregular structure, light guided to the lower portion of the light emitting diode 930 is reflected from the irregular structure between the first semiconductor layer 931 and the first electrode 934 to be easily extracted to the outside of the display device 900.

[0170] Reference Fig.10 , when the ohmic contact electrode 1037 is formed in the light emitting diode 1030, the irregular structure 1001 may be formed on the bonding surface of the ohmic contact electrode 1037 and the first semiconductor layer 1031. That is, the irregular structure 1001 is located at a position where the ohmic contact electrode 1037 contacts the first semiconductor layer 1031. The irregular structure 1001 is formed in a portion of the bottom surface of the first semiconductor layer 1031 in contact with the ohmic contact electrode 1037, and the irregular structure 1001 may be formed on the surface of the ohmic contact electrode 1037 in contact with the first semiconductor layer 1031. In this case, the irregular structure 1001 disposed to correspond to the ohmic contact electrode 1037 is disposed to overlap with a region between a pair of low potential power lines VSS.

[0171] Therefore, in the display devices 900 and 1000 according to another exemplary embodiment of the present disclosure, irregular structures 901 and 1001 are formed under the light emitting diodes 930 and 1030 to improve the light extraction efficiency. The irregular structure may be arranged to overlap with the area between a pair of low potential power lines VSS. In the irregular structure, light propagating to the bottom of the light emitting diodes 930 and 1030 is reflected to improve the light extraction efficiency. The irregular structure is spaced apart from the area where the light emitting diodes 930 and 1030 and the second passivation layer 116 contact to improve the light extraction efficiency without reducing the bonding strength of the light emitting diodes 930 and 1030. The irregular structure may be partially formed on the bottom surface of the first semiconductor layer 931 and 1031. For example, referring to Fig. 9 , an irregular structure 901 may be formed on the bonding surface of the first electrode 934 and the first semiconductor layer 931. As another example, referring to Fig.10 , an irregular structure 1001 may be formed on the bonding surface of the ohmic contact electrode 1037 and the first semiconductor layer 1031. Therefore, in the display devices 900 and 1000 according to still another exemplary embodiment of the present disclosure, an irregular structure is partially formed on the bottom surface of the first semiconductor layers 931 and 1031 of the light emitting diodes 930 and 1030 to improve the brightness of the display device and reduce power consumption.

[0172] Exemplary embodiments of the present disclosure may also be described as follows:

[0173] According to one aspect of the present disclosure, a display device includes: a substrate in which a plurality of sub-pixels are defined; a pair of low potential power lines, which are arranged in each of the plurality of sub-pixels and spaced apart from each other; and a plurality of light-emitting diodes, which are arranged in each of the plurality of sub-pixels and overlap with the area between the pair of low potential power lines. Each of the plurality of light-emitting diodes includes a first semiconductor layer; a light-emitting layer on the first semiconductor layer; a second semiconductor layer on the light-emitting layer; a first insulating film surrounding the side surfaces of the first semiconductor layer, the light-emitting layer, and the second semiconductor layer; a side electrode arranged on the first insulating film to correspond to the side surface of the first semiconductor layer; and a first electrode, which contacts the bottom surface of the first semiconductor layer and the lower portion of the side electrode.

[0174] The first electrode and the side electrodes may be formed of different materials.

[0175] The side electrodes may be formed of a ferromagnetic material.

[0176] The first electrode may be a reflective electrode.

[0177] The display device may further include a reflective layer disposed below the plurality of light emitting diodes. The first electrode may be formed of a transparent conductive material.

[0178] The side electrode may be disposed to be spaced apart from the first semiconductor layer by the first insulating film, and the side electrode may be electrically connected to the first semiconductor layer through the first electrode.

[0179] Each of the plurality of light emitting diodes may further include a second electrode disposed on the second semiconductor layer, and the first insulating film covers an edge of the second electrode.

[0180] The display device may further include an ohmic contact electrode disposed between the first electrode and the first semiconductor layer. The ohmic contact electrode may overlap a region between the pair of low potential power lines.

[0181] The bottom surface of the first semiconductor layer may be formed of a portion contacting the first electrode and a portion contacting the ohmic contact electrode.

[0182] A bonding surface of the ohmic contact electrode and the first semiconductor layer may be formed with an irregular structure.

[0183] A portion of the bonding surface of the first electrode and the first semiconductor layer corresponding to a region between the pair of low potential power supply lines may be formed with an irregular structure.

[0184] According to one aspect of the present disclosure, a method for manufacturing a display device includes the following steps: placing a substrate and a plurality of light-emitting diodes into a chamber in which a fluid is formed, in which a pair of low-potential power lines are arranged to be spaced apart from each other; moving the plurality of light-emitting diodes to the substrate using a magnet; and self-assembling the plurality of light-emitting diodes on the substrate by forming an electric field between the pair of low-potential power lines. The plurality of light-emitting diodes include: a first semiconductor layer; a light-emitting layer on the first semiconductor layer; a second semiconductor layer on the light-emitting layer; a first insulating film surrounding the side surfaces of the first semiconductor layer, the light-emitting layer, and the second semiconductor layer; a side electrode disposed on the first insulating film so as to correspond to the side surface of the first semiconductor layer; and a second insulating film covering the side electrode and the first insulating film.

[0185] The side electrodes may be formed of a ferromagnetic material such that the plurality of light emitting diodes are configured to move through the side electrodes to the magnet.

[0186] The method of manufacturing a display device may further include the steps of removing the second insulating film after self-assembling the plurality of light emitting diodes on the pair of low potential power lines, and forming a contact electrode electrically connecting the pair of low potential power lines and the side electrode.

[0187] A passivation layer may be further disposed between the pair of low potential power lines and the plurality of light emitting diodes, and the contact electrode may be connected to at least one of the pair of low potential power lines through a contact hole formed in the passivation layer.

[0188] Although the exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all aspects and do not limit the present disclosure. All technical concepts within the equivalent scope of the present disclosure should be interpreted as falling within the scope of the present disclosure.

[0189] CROSS-REFERENCE TO RELATED APPLICATIONS

[0190] This application claims the priority of Korean Patent Application No. 10-2023-0075026 filed on June 12, 2023 in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

Claims

1. A display device, comprising: a substrate having a plurality of sub-pixels defined therein; a pair of low potential power lines in a sub-pixel of the plurality of sub-pixels, the pair of low potential power lines being spaced apart from each other; as well as A plurality of light emitting diodes are included in the sub-pixel, the plurality of light emitting diodes in the sub-pixel overlap with a region between the pair of low potential power lines in the sub-pixel, Wherein, at least one of the plurality of light emitting diodes comprises: a first semiconductor layer; a light emitting layer on the first semiconductor layer; a second semiconductor layer on the light emitting layer; a first insulating film surrounding a side surface of the first semiconductor layer, a side surface of the light emitting layer, and a side surface of the second semiconductor layer; a side electrode on the first insulating film and overlapping the side surface of the first semiconductor layer; and A first electrode is in contact with a lower surface of the first semiconductor layer and a lower portion of the side electrode.

2. The display device according to claim 1, wherein: The first electrode and the side electrode include different materials.

3. The display device according to claim 1, wherein: The side electrodes include a ferromagnetic material.

4. The display device according to claim 1, wherein: The first electrode is a reflective electrode that reflects more light than the side electrodes.

5. The display device according to claim 1, further comprising: a reflective layer, wherein the reflective layer is below the plurality of light emitting diodes, Wherein, the first electrode comprises a transparent conductive material.

6. The display device according to claim 1, wherein: The first insulating film is between the side electrode and the first semiconductor layer, and the side electrode is electrically connected to the first semiconductor layer through the first electrode in contact with the bottom surface of the first semiconductor layer.

7. The display device according to claim 1, wherein: Each of the plurality of light emitting diodes further includes a second electrode on the second semiconductor layer, and the first insulating film covers an edge of the second electrode.

8. The display device according to claim 1, further comprising: an ohmic contact electrode between a portion of the first electrode and a portion of the first semiconductor layer, The ohmic contact electrode overlaps with a region between the pair of low-potential power lines.

9. The display device according to claim 8, wherein: A bottom surface of the first semiconductor layer includes a first portion in contact with the first electrode and a second portion in contact with the ohmic contact electrode.

10. The display device according to claim 8, wherein: A bottom surface of the first semiconductor layer includes an irregular structure at a position where the ohmic contact electrode and the first semiconductor layer contact each other, the irregular structure including a jagged surface.

11. The display device according to claim 1, wherein: The bottom surface of the first semiconductor layer includes an irregular structure at a position overlapping with a region between the pair of low potential power supply lines, the irregular structure including a jagged surface.

12. A method for manufacturing a display device, the method comprising the following steps: placing a substrate into a chamber, the chamber comprising a fluid and a plurality of light emitting diodes, the substrate comprising a pair of low potential power lines spaced apart from each other; Using a magnet to move the plurality of light emitting diodes to the substrate; as well as applying a voltage to the pair of low potential power lines and forming an electric field between the pair of low potential power lines, wherein the plurality of light emitting diodes are self-assembled between the pair of low potential power lines on the substrate in response to the electric field, Wherein, each of the plurality of light emitting diodes comprises: a first semiconductor layer; a light emitting layer on the first semiconductor layer; a second semiconductor layer on the light emitting layer; a first insulating film surrounding a side surface of the first semiconductor layer, a side surface of the light emitting layer, and a side surface of the second semiconductor layer; a side electrode on the first insulating film and overlapping the side surface of the first semiconductor layer; and A second insulating film covering the side electrodes and the first insulating film.

13. The method for manufacturing a display device according to claim 12, wherein: The side electrodes include a ferromagnetic material, and the plurality of light emitting diodes are moved to the substrate in response to magnetic attraction between the magnet and the side electrodes of each of the plurality of light emitting diodes.

14. The method for manufacturing a display device according to claim 12, further comprising the following steps: After the plurality of light emitting diodes are self-assembled between the pair of low potential power lines, removing the second insulating film of each of the plurality of light emitting diodes; as well as A contact electrode is formed to electrically connect the pair of low potential power lines and the side electrode of each of the plurality of light emitting diodes.

15. The method for manufacturing a display device according to claim 14, wherein: The method for manufacturing a display device further comprises the following steps: Disposing a passivation layer between the pair of low potential power lines and the plurality of light emitting diodes; forming a contact hole in the passivation layer; and The contact electrode is connected to at least one of the pair of low potential power supply lines through the contact hole formed in the passivation layer.

16. A light emitting diode, comprising: a first electrode; a first semiconductor layer on the first electrode; a second semiconductor layer on the first semiconductor layer; a light emitting layer between the first semiconductor layer and the second semiconductor layer, the light emitting layer being configured to emit light; a second electrode on the second semiconductor layer, wherein the second semiconductor layer is between the second electrode and the light emitting layer; as well as A third electrode is on the side surface of the first semiconductor layer so that the third electrode is located between an end of the first electrode and the side surface of the first semiconductor layer.

17. The light emitting diode according to claim 16, wherein: The third electrode includes a ferromagnetic material.

18. The light emitting diode according to claim 16, further comprising: An insulating layer is on a side surface of the first semiconductor layer, a side surface of the light emitting layer, a side surface of the second semiconductor layer, and a side surface of the second electrode, so that a portion of the insulating layer is located between the third electrode and the side surface of the first semiconductor layer.

19. The light emitting diode according to claim 18, wherein: The insulating layer overlaps a first portion of an upper surface of the second electrode, and does not overlap a second portion of an upper surface of the second electrode.

20. The light emitting diode according to claim 18, wherein: An end portion of the insulating layer contacts an upper surface of the first electrode.

21. The light emitting diode according to claim 16, wherein: The first electrode is reflective.

22. The light emitting diode according to claim 16, wherein: The first semiconductor layer includes an irregular structure at a portion of a lower surface of the first semiconductor layer, the irregular structure including a jagged surface.

23. The light emitting diode according to claim 16, further comprising: A fourth electrode is between the first portion of the first electrode and the first portion of the first semiconductor layer, but is not between the second portion of the first electrode and the second portion of the first semiconductor layer.

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