A data frame processing method and system

Abstract

The present invention relates to the field of communication technology, and specifically to a data frame processing method and system, the system comprising an FPGA, a micro control unit and two PHY chips; the method comprises: configuring the working modes of the two PHY chips through a chip configuration module, the working modes comprising a normal mode; generating interface data from a received data stream through the PHY chip, and sending the interface data to a frame processing module; in the normal mode, extracting a control frame and a correct data frame from the interface data through the frame processing module, and sending the control frame and the correct data frame to a frame insertion / frame interception module; and converting the received correct data frame into interface data and sending it to the PHY chip; forwarding the received correct data frame to another frame processing module through the frame insertion / frame interception module; the present invention optimizes the use of hardware resources and improves communication efficiency and stability.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a data frame processing method and system. Background Art

[0002] In the related art, in special applications where new MAC frames are inserted between multiple PHY chips, the use of a conventional microprocessor requires consideration of whether the microprocessor has Ethernet functionality. If it does not have Ethernet functionality, an external MAC chip is required, resulting in additional power consumption. In addition, due to the time-sharing processing characteristics of such chips, the speed at which data is transmitted in the processing domain is not ideal. Summary of the invention

[0003] In view of this, the purpose of the embodiments of the present invention is to provide a data frame processing method and system to solve one or more technical problems existing in the prior art and provide at least one beneficial option or create conditions.

[0004] On the one hand, an embodiment of the present invention provides a data frame processing system, the data frame processing system comprising an FPGA, a micro control unit and two PHY chips;

[0005] The FPGA includes a chip configuration module, a frame insertion / frame interception module, a serial port module, and two frame processing modules. The frame insertion / frame interception module is respectively connected to the serial port module and the two frame processing modules, and the serial port module is connected to the micro control unit; the chip configuration module is respectively connected to the two PHY chips, and the two PHY chips and the two frame processing modules are connected in a one-to-one correspondence;

[0006] The chip configuration module is used to configure the working modes of the two PHY chips, wherein the working modes include a normal mode;

[0007] The PHY chip is used to generate interface data from the received data stream and send the interface data to the frame processing module;

[0008] The frame processing module is used to extract the control frame and the correct data frame from the interface data in the normal mode, and send the control frame and the correct data frame to the frame insertion / frame interception module; and to convert the received correct data frame into interface data and send it to the PHY chip;

[0009] The frame insertion / frame interception module is used to forward the received correct data frame to another frame processing module.

[0010] Optionally, the data frame processing system further includes a micro control unit, and the working mode further includes a frame insertion mode;

[0011] The micro control unit is used to send control data, so that the control data is converted from serial to parallel through the serial port module and then sent to the frame insertion / frame interception module;

[0012] The frame insertion / frame interception module is used to parse the received control data to obtain the transmission direction of the interface data, and use the PHY chip corresponding to the transmission direction as the target PHY chip;

[0013] The frame processing module is used to receive the interface data sent by the PHY chip in the frame insertion mode, identify the indication signal of the interface data, determine the frame interval of the data frame if it is determined that the indication signal indicates that the frame insertion condition is met, insert the received interface data into the data frame queue to be sent according to the frame interval, and send the data frame queue with the inserted interface data to the target PHY chip.

[0014] Optionally, the working mode also includes a frame capture mode;

[0015] The PHY chip is used to generate interface data after receiving the data stream and send it to the frame processing module connected thereto;

[0016] The frame insertion / frame interception module is used to extract the control frame from the interface data sent by the frame processing module in the frame interception mode; identify the control frame and determine whether to send the correct data frame to another PHY chip;

[0017] If it is determined that the correct data frame is to be sent to another PHY chip, the control frame is copied, the control frame is input into a queue of data frames to be sent, and the control frame is parsed into control data and then transmitted to the micro control unit through a serial port module;

[0018] If it is determined not to send the correct data frame to another PHY chip, the control frame is parsed into control data and then sent to the micro control unit through the serial port module.

[0019] Optionally, the frame processing module includes a MAC module, a receiving buffer module, a sending buffer module and a frame parsing module; the PHY chip, the MAC module, the receiving buffer module, the frame parsing module and the frame insertion / frame interception module are connected in sequence, and the sending buffer module is respectively connected to the MAC module and the frame insertion / frame interception module;

[0020] The MAC module is used to convert the interface data sent by the PHY chip into a data frame of the MAC layer;

[0021] The receiving buffer module is used to buffer the data frames parsed by the MAC module;

[0022] The frame parsing module is used to parse the received data frame according to the MAC layer protocol to obtain the MAC address of the sending data frame;

[0023] The frame insertion / frame interception module is used to match the MAC address of the data frame to be sent with the MAC address of the MAC module, discard the data frames with wrong matching, and divide the data frames with consistent matching into control frames and correct data frames;

[0024] and used to match the MAC address in the control data with the MAC addresses of the two MAC modules respectively, determine a MAC module with consistent matching, and use the PHY chip connected to the MAC module as the target PHY chip;

[0025] The sending buffer module is used to buffer the data frames generated by the frame insertion / frame interception module;

[0026] The serial port module is used to implement data interaction between the frame insertion / frame interception module and the micro control unit, obtain the working mode according to the received control data analysis, and provide the working mode to the chip configuration module.

[0027] Optionally, the receiving cache module is further used to determine a frame interval for cached data frames.

[0028] On the other hand, an embodiment of the present invention provides a data frame processing method, which is applied to a data frame processing system, wherein the data frame processing system includes an FPGA, a micro control unit, and two PHY chips;

[0029] The FPGA includes a chip configuration module, a frame insertion / frame interception module, a serial port module, and two frame processing modules. The frame insertion / frame interception module is respectively connected to the serial port module and the two frame processing modules, and the serial port module is connected to the micro control unit; the chip configuration module is respectively connected to the two PHY chips, and the two PHY chips and the two frame processing modules are connected in a one-to-one correspondence;

[0030] The method comprises the following steps:

[0031] Configure the working modes of the two PHY chips through a chip configuration module, wherein the working modes include a normal mode;

[0032] Generate interface data from the received data stream through the PHY chip, and send the interface data to the frame processing module;

[0033] In normal mode, the frame processing module extracts control frames and correct data frames from the interface data, and sends the control frames and correct data frames to the frame insertion / frame interception module; and converts the received correct data frames into interface data and sends them to the PHY chip;

[0034] The received correct data frame is forwarded to another frame processing module through the frame insertion / frame interception module.

[0035] Optionally, the data frame processing system further includes a micro control unit, and the working mode further includes a frame insertion mode; and the method further includes:

[0036] The control data is sent through the micro control unit, so that the control data is converted into serial and parallel data through the serial port module and then sent to the frame insertion / frame interception module;

[0037] The frame insertion / frame interception module parses the received control data to obtain the transmission direction of the interface data, and uses the PHY chip corresponding to the transmission direction as the target PHY chip;

[0038] In the insertion mode, the interface data sent by the PHY chip is received through the frame processing module, and the indication signal of the interface data is identified. If it is determined that the indication signal indicates that the insertion condition is met, the frame interval of the data frame is determined, and the received interface data is inserted into the data frame queue to be sent according to the frame interval, and the data frame queue with the inserted interface data is sent to the target PHY chip.

[0039] Optionally, the working mode further includes a frame capture mode; and the method further includes:

[0040] After receiving the data stream, the PHY chip generates interface data and sends it to the frame processing module connected to it;

[0041] In the frame interception mode, a control frame is extracted from the interface data sent by the frame processing module through the frame insertion / frame interception module; the control frame is identified to determine whether to send the correct data frame to another PHY chip;

[0042] If it is determined that the correct data frame is to be sent to another PHY chip, the control frame is copied, the control frame is input into a queue of data frames to be sent, and the control frame is parsed into control data and then transmitted to the micro control unit through a serial port module;

[0043] If it is determined not to send the correct data frame to another PHY chip, the control frame is parsed into control data and then sent to the micro control unit through the serial port module.

[0044] Optionally, the frame processing module includes a MAC module, a receiving buffer module, a sending buffer module and a frame parsing module; the PHY chip, the MAC module, the receiving buffer module, the frame parsing module and the frame insertion / frame interception module are connected in sequence, and the sending buffer module is respectively connected to the MAC module and the frame insertion / frame interception module; the method further includes:

[0045] The interface data sent by the PHY chip is converted into data frames of the MAC layer through the MAC module;

[0046] The receiving buffer module caches the data frames parsed by the MAC module;

[0047] The frame parsing module performs MAC layer protocol parsing on the received data frame to obtain the MAC address of the sending data frame;

[0048] Matching the MAC address of the data frame to be sent with the MAC address of the MAC module through the frame insertion / frame interception module, discarding the data frame with wrong matching, and dividing the data frame with consistent matching into control frames and correct data frames; and matching the MAC address in the control data with the MAC addresses of the two MAC modules respectively, determining the MAC module with consistent matching, and taking the PHY chip connected to the MAC module as the target PHY chip;

[0049] Cache the data frames generated by the frame insertion / frame interception module by sending the cache module;

[0050] The data interaction between the frame insertion / frame interception module and the micro control unit is realized through the serial port module, the working mode is obtained according to the analysis of the received control data, and the working mode is provided to the chip configuration module.

[0051] Optionally, the method further comprises:

[0052] The receiving buffer module determines the frame interval for the buffered data frames.

[0053] The embodiments of the present invention include the following beneficial effects: the embodiments provided by the present invention can flexibly switch between different working modes through the chip configuration module; the stability and efficiency of data transmission are achieved through the precise control of the PHY chip. The continuity and integrity of the data stream are guaranteed through the efficient extraction and conversion of the frame processing module. The intelligent management of the frame insertion / frame interception module effectively reduces data loss and the transmission of error frames, and improves the reliability and throughput of the network. The present invention not only optimizes the use of hardware resources, but also improves the communication efficiency and stability of the entire system. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0055] Figure 1 is a structural diagram of a data frame processing system provided by an embodiment of the present invention;

[0056] Figure 2 is a connection interface diagram of a PHY chip and a MAC module in an embodiment of the present invention;

[0057] Figure 3 is a schematic diagram of a data frame of a MAC layer in an embodiment of the present invention;

[0058] Figure 4 is a working schematic diagram of a data frame processing system in an embodiment of the present invention;

[0059] Figure 5 It is a schematic diagram of the step flow of a data frame processing method provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0060] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0061] It should be noted that, although the device schematic diagram is divided into modules and the flow chart shows a logical order, in some cases, the steps shown or described may be performed in a different order than the module division in the device or the order in the flow chart. The terms "first", "second", etc. in the specification, claims and the above drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0062] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0063] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present application. However, those skilled in the art will appreciate that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps, etc. can be adopted. In other cases, known methods, devices, realizations or operations are not shown or described in detail to avoid blurring the various aspects of the application.

[0064] The block diagrams shown in the accompanying drawings are only functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in software form, or in one or more hardware charging modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0065] The flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps can be decomposed, and some operations / steps can be combined or partially combined, so the actual execution order may change according to actual conditions.

[0066] The PHY layer is the physical layer. The PHY interface refers to the physical layer interface for data transmission between chips or circuit boards. In special applications where new MAC frames are inserted between PHY and PHY, since new data frames need to be inserted on the Ethernet data path in the middle, in traditional commercial and industrial embedded applications, MAC chips plus ARM or other microprocessors are generally used to run programs for data processing.

[0067] The present invention provides a PHY interface based on FPGA and an Ethernet frame insertion solution to solve the problem of long delay period caused by using a traditional microprocessor, and reduce power consumption, cost and other issues.

[0068] All functions of the present invention can be completed by using one FPGA chip, and power consumption and cost are reduced compared with using an ordinary single-chip microcomputer. In addition, implementing the MAC function based on FPGA can provide the minimum delay in data interaction between MAC layers, and the frame insertion and frame interception functions can realize special communication between the PHY chip and the micro control unit.

[0069] To this end, the present invention provides a data frame processing method and system, through the control data sent by the micro control unit module, the frame insertion / frame cutting module performs corresponding frame insertion and frame cutting operations without affecting the normal data frames.

[0070] like Figure 1 As shown, an embodiment of the present invention provides a data frame processing system, wherein the data frame processing system includes an FPGA, a micro control unit and two PHY chips;

[0071] The FPGA includes a chip configuration module, a frame insertion / frame interception module, a serial port module, and two frame processing modules. The frame insertion / frame interception module is respectively connected to the serial port module and the two frame processing modules, and the serial port module is connected to the micro control unit; the chip configuration module is respectively connected to the two PHY chips, and the two PHY chips and the two frame processing modules are connected in a one-to-one correspondence;

[0072] The chip configuration module is used to configure the working modes of the two PHY chips, wherein the working modes include a normal mode;

[0073] The PHY chip is used to generate interface data from the received data stream and send the interface data to the frame processing module;

[0074] The frame processing module is used to extract the control frame and the correct data frame from the interface data in the normal mode, and send the control frame and the correct data frame to the frame insertion / frame interception module; and to convert the received correct data frame into interface data and send it to the PHY chip;

[0075] The frame insertion / frame interception module is used to forward the received correct data frame to another frame processing module.

[0076] Specifically, the frame insertion / frame interception module uses the TXEN, RXER, CRSDV and other signals of the RMII interface to select the appropriate actual insertion control frame or discard the control frame. The received control frame is parsed into control data and sent to the serial port module;

[0077] Compared with related technologies, the present invention realizes efficient data frame processing through original hardware architecture and control flow, especially in application scenarios with high bandwidth and low latency requirements. In the specific implementation process, through the chip configuration module, it can be flexibly switched in different working modes to further meet the special needs of specific network environments. Through the precise control of the PHY chip, the stability and efficiency of data transmission are achieved. Through the efficient extraction and conversion of the frame processing module, the continuity and integrity of the data stream are guaranteed. Through the intelligent management of the frame insertion / frame interception module, data loss and the transmission of error frames are effectively reduced, and the reliability and throughput of the network are improved.

[0078] In the embodiment provided by the present invention, the processing speed of data frames is significantly improved and the processing delay is reduced through the parallel processing capability of FPGA. The present invention provides a flexible frame insertion / frame interception strategy to adapt to various network environments, which not only optimizes the use of hardware resources, but also improves the communication efficiency and stability of the entire system.

[0079] In some embodiments, the data frame processing system further includes a micro control unit, and the working mode further includes a frame insertion mode;

[0080] The micro control unit is used to send control data, so that the control data is converted from serial to parallel through the serial port module and then sent to the frame insertion / frame interception module;

[0081] The frame insertion / frame interception module is used to parse the received control data to obtain the transmission direction of the interface data, and use the PHY chip corresponding to the transmission direction as the target PHY chip;

[0082] The frame processing module is used to receive the interface data sent by the PHY chip in the frame insertion mode, identify the indication signal of the interface data, determine the frame interval of the data frame if it is determined that the indication signal indicates that the frame insertion condition is met, insert the received interface data into the data frame queue to be sent according to the frame interval, and send the data frame queue with the inserted interface data to the target PHY chip.

[0083] Specifically, the indication signal includes TXEN (data transmission enable signal), RTER (data transmission error prompt) signal, RXER (data reception error prompt) signal, CRSDV (carrier sense signal), and the frame processing module determines whether to insert a frame by identifying the indication signal.

[0084] In the embodiment provided by the present invention, the introduction of the micro control unit greatly improves the flexibility of data processing, and can dynamically adjust the frame insertion strategy according to the real-time network status to optimize the data transmission efficiency while ensuring the smoothness and stability of network communication.

[0085] In some embodiments, the working mode further includes a frame capture mode;

[0086] The PHY chip is used to generate interface data after receiving the data stream and send it to the frame processing module connected thereto;

[0087] The frame insertion / frame interception module is used to extract the control frame from the interface data sent by the frame processing module in the frame interception mode; identify the control frame and determine whether to send the correct data frame to another PHY chip;

[0088] If it is determined that the correct data frame is to be sent to another PHY chip, the control frame is copied, the control frame is input into a queue of data frames to be sent, and the control frame is parsed into control data and then transmitted to the micro control unit through a serial port module;

[0089] If it is determined not to send the correct data frame to another PHY chip, the control frame is parsed into control data and then sent to the micro control unit through the serial port module.

[0090] Specifically, in the frame interception mode, the micro control unit can accurately monitor and analyze the data flow, thereby effectively preventing unnecessary data frame transmission and reducing the overall network load.

[0091] In the embodiment provided by the present invention, by intelligently processing the control frame, flexible data allocation between multiple PHY chips can be achieved, and the utilization efficiency of network resources can be enhanced. This technology not only optimizes the data transmission path, but also significantly reduces communication delays, providing users with a more stable and efficient network experience.

[0092] In some embodiments, the frame processing module includes a MAC module, a receiving buffer module, a sending buffer module and a frame parsing module; the PHY chip, the MAC module, the receiving buffer module, the frame parsing module and the frame insertion / frame interception module are connected in sequence, and the sending buffer module is respectively connected to the MAC module and the frame insertion / frame interception module;

[0093] The MAC module is used to convert the interface data sent by the PHY chip into a data frame of the MAC layer;

[0094] Specifically, the MAC module is responsible for the conversion of data frames between the PHY layer data and the MAC layer. The PHY chip and the MAC module use the RMII interface uniformly. The connection interface between the PHY chip and the MAC module is as follows: Figure 2 The MAC module generates the data frame of the MAC layer and stores it in the receiving buffer module for subsequent use. The data frame of the MAC layer uses the Ethernet V2 format, such as Figure 3 shown.

[0095] The receiving buffer module is used to buffer the data frames parsed by the MAC module;

[0096] The frame parsing module is used to parse the received data frame according to the MAC layer protocol to obtain the MAC address of the sending data frame;

[0097] The frame insertion / frame interception module is used to match the MAC address of the data frame to be sent with the MAC address of the MAC module, discard the data frames with wrong matching, and divide the data frames with consistent matching into control frames and correct data frames;

[0098] and used to match the MAC address in the control data with the MAC addresses of the two MAC modules respectively, determine a MAC module with consistent matching, and use the PHY chip connected to the MAC module as the target PHY chip;

[0099] The sending buffer module is used to buffer the data frames generated by the frame insertion / frame interception module;

[0100] The serial port module is used to implement data interaction between the frame insertion / frame interception module and the micro control unit, obtain the working mode according to the received control data analysis, and provide the working mode to the chip configuration module.

[0101] Specifically, the data interaction between the frame insertion / frame interception module and the micro control unit is completed through the serial port module, and the control data received by the serial port module can provide data to the chip configuration module to dynamically configure the PHY chip.

[0102] In the embodiment provided by the present invention, by optimizing the use of FPGA internal resources, the frame insertion / frame interception process does not require additional hardware support, which greatly reduces the complexity and cost of the system. At the same time, this design also significantly improves the real-time performance of data transmission, while ensuring data transmission efficiency, it also ensures the stability and reliability of the system.

[0103] In some embodiments, the receiving cache module is further used to determine the frame interval of the cached data frames.

[0104] In the embodiment provided by the present invention, by determining the frame interval of the cached data frames, a more flexible data processing strategy can be implemented, and the packet loss phenomenon caused by unclear frame interval can be effectively avoided.

[0105] like Figure 4 As shown, a data frame processing system provided by an embodiment of the present invention includes an FPGA, a micro control unit, a first PHY chip, and a second PHY chip;

[0106] The FPGA includes a chip configuration module, a frame insertion / frame interception module, a serial port module, a first frame processing module and a second frame processing module, wherein the frame insertion / frame interception module is respectively connected to the serial port module, the first frame processing module and the second frame processing module, and the serial port module is connected to the micro control unit;

[0107] The chip configuration module is connected to the first PHY chip and the second PHY chip respectively, the first PHY chip is connected to the first frame processing module, and the second PHY chip is connected to the second frame processing module;

[0108] The first frame processing module includes a first MAC module, a first receiving buffer module, a first sending buffer module and a first frame parsing module; the second frame processing module includes a second MAC module, a second receiving buffer module, a second sending buffer module and a second frame parsing module;

[0109] The chip configuration module is used to configure the working modes of the first PHY chip and the second PHY chip, where the working modes include a normal mode, a frame insertion mode, and a frame capture mode;

[0110] The first PHY chip is used to generate interface data after receiving the data stream under normal working conditions, and send the interface data to the first frame processing module;

[0111] The first frame processing module is used to extract the control frame and the correct data frame from the interface data, and send the control frame and the correct data frame to the frame insertion / frame interception module; and to convert the received correct data frame into interface data and send it to the first PHY chip;

[0112] The frame insertion / frame interception module is used to forward the received correct data frame between the first frame processing module and the second frame processing module;

[0113] Workflow: First, the chip configuration module configures the working mode of the two PHY chips, and after the configuration is completed, they enter the normal working mode.

[0114] Under normal circumstances, the data exchange between the two PHY chips is as follows:

[0115] Taking the workflow of sending data from the first PHY chip to the second PHY chip as an example, after receiving the data stream, the first PHY chip generates interface data and transmits it to the first MAC module. The first MAC module parses the data frame and stores it in the first receiving buffer module. The frame parsing module distinguishes the data frame type by judging the MAC address, discards the wrong data frame, and the remaining data frames are divided into control frames and correct data frames. The correct data frame flows to the second sending buffer module and supplies it to the second MAC module, which converts it into the interface data of the RMII interface for use by the second PHY chip. The workflow of the second PHY chip flowing to the first PHY chip is similar.

[0116] In the case of frame insertion, the workflow is as follows: the microcontroller sends control data, which is sent to the frame insertion / frame interception module after serial-to-parallel conversion by the serial port module. The frame insertion / frame interception module first determines the sending direction of the control data, and then obtains the indication signal according to the interface data of the RMII interface. The indication signal includes TXEN (data transmission enable signal), RTER (data transmission error prompt) signal, RXER (data reception error prompt) signal, CRSDV (carrier sense signal), etc., and determines whether the frame insertion condition is met according to the indication signal, and determines the frame interval according to the data frame in the sending buffer module in the sending direction, so that the interface data can be correctly inserted into the data frame queue to be sent in the sending buffer module.

[0117] In the case of frame interception, the workflow is as follows: after receiving the data stream, the first PHY chip generates interface data and transmits it to the first MAC module. The frame insertion / frame interception module processes the data frame input by the frame parsing module and filters out the control frame according to the MAC address. This control frame can choose whether to flow to the second PHY chip in the end according to the demand. If the control frame chooses to flow to the second PHY chip, it is equivalent to the control frame flowing directly from the first PHY chip to the second PHY chip. The control frame is copied in the frame insertion / frame interception module, and the control frame then flows to the second sending buffer module to enter the queue of data frames to be sent. At the same time, the control frame is parsed into control data and then transmitted to the micro control unit through the serial port module. If the control frame does not choose to flow to the second PHY chip, it is equivalent to the control frame flowing from the first PHY chip to the micro control unit. At this time, the control frame in the frame insertion / frame interception module will not flow to the second sending buffer module, but the control frame will be parsed into control data and then enter the serial port module, and finally transmitted to the micro control unit.

[0118] like Figure 5 As shown, a data frame processing method provided by an embodiment of the present invention is applied to a data frame processing system, wherein the data frame processing system includes an FPGA, a micro control unit and two PHY chips;

[0119] The FPGA includes a chip configuration module, a frame insertion / frame interception module, a serial port module, and two frame processing modules. The frame insertion / frame interception module is respectively connected to the serial port module and the two frame processing modules, and the serial port module is connected to the micro control unit; the chip configuration module is respectively connected to the two PHY chips, and the two PHY chips and the two frame processing modules are connected in a one-to-one correspondence;

[0120] The method comprises the following steps:

[0121] S100, configuring the working modes of the two PHY chips through a chip configuration module, wherein the working modes include a normal mode;

[0122] S200, generating interface data from the received data stream through the PHY chip, and sending the interface data to the frame processing module;

[0123] S300, in normal mode, extracting a control frame and a correct data frame from the interface data through a frame processing module, sending the control frame and the correct data frame to a frame insertion / frame interception module; and converting the received correct data frame into interface data and sending the converted data to a PHY chip;

[0124] S400, forwarding the received correct data frame to another frame processing module through the frame insertion / frame interception module.

[0125] In some embodiments, the data frame processing system further includes a micro control unit, the working mode further includes a frame insertion mode; and the method further includes:

[0126] The control data is sent through the micro control unit, so that the control data is converted into serial and parallel data through the serial port module and then sent to the frame insertion / frame interception module;

[0127] The frame insertion / frame interception module parses the received control data to obtain the transmission direction of the interface data, and uses the PHY chip corresponding to the transmission direction as the target PHY chip;

[0128] In the insertion mode, the interface data sent by the PHY chip is received through the frame processing module, and the indication signal of the interface data is identified. If it is determined that the indication signal indicates that the insertion condition is met, the frame interval of the data frame is determined, and the received interface data is inserted into the data frame queue to be sent according to the frame interval, and the data frame queue with the inserted interface data is sent to the target PHY chip.

[0129] In some embodiments, the working mode further includes a frame capture mode; and the method further includes:

[0130] After receiving the data stream, the PHY chip generates interface data and sends it to the frame processing module connected to it;

[0131] In the frame interception mode, a control frame is extracted from the interface data sent by the frame processing module through the frame insertion / frame interception module; the control frame is identified to determine whether to send the correct data frame to another PHY chip;

[0132] If it is determined that the correct data frame is to be sent to another PHY chip, the control frame is copied, the control frame is input into a queue of data frames to be sent, and the control frame is parsed into control data and then transmitted to the micro control unit through a serial port module;

[0133] If it is determined not to send the correct data frame to another PHY chip, the control frame is parsed into control data and then sent to the micro control unit through the serial port module.

[0134] In some embodiments, the frame processing module includes a MAC module, a receiving buffer module, a sending buffer module and a frame parsing module; the PHY chip, the MAC module, the receiving buffer module, the frame parsing module and the frame insertion / frame interception module are connected in sequence, and the sending buffer module is respectively connected to the MAC module and the frame insertion / frame interception module; the method also includes:

[0135] The interface data sent by the PHY chip is converted into data frames of the MAC layer through the MAC module;

[0136] The receiving buffer module caches the data frames parsed by the MAC module;

[0137] The frame parsing module performs MAC layer protocol parsing on the received data frame to obtain the MAC address of the sending data frame;

[0138] Matching the MAC address of the data frame to be sent with the MAC address of the MAC module through the frame insertion / frame interception module, discarding the data frame with wrong matching, and dividing the data frame with consistent matching into control frames and correct data frames; and matching the MAC address in the control data with the MAC addresses of the two MAC modules respectively, determining the MAC module with consistent matching, and taking the PHY chip connected to the MAC module as the target PHY chip;

[0139] Cache the data frames generated by the frame insertion / frame interception module by sending the cache module;

[0140] The data interaction between the frame insertion / frame interception module and the micro control unit is realized through the serial port module, the working mode is obtained according to the analysis of the received control data, and the working mode is provided to the chip configuration module.

[0141] In some embodiments, the method further comprises:

[0142] The receiving buffer module determines the frame interval for the buffered data frames.

[0143] It can be seen that the contents of the above system embodiments are all applicable to the present method embodiments, the functions specifically implemented by the present method embodiments are the same as those of the above system embodiments, and the beneficial effects achieved are also the same as those achieved by the above system embodiments.

[0144] The device embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separated, that is, they may be located in one place or distributed on multiple network units. Some or all of the charging modules may be selected according to actual needs to achieve the purpose of the present embodiment.

[0145] Those skilled in the art will appreciate that all or some of the steps in the methods disclosed above, and the functional charging modules / units in the systems and devices may be implemented as software, firmware, hardware, or appropriate combinations thereof.

[0146] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example: a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0147] It should be understood that in this application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0148] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0149] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0150] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0151] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including multiple instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, referred to as ROM), random access memory (Random Access Memory, referred to as RAM), disk or optical disk and other media that can store programs.

[0152] The preferred embodiments of the present invention are described above with reference to the accompanying drawings, but the scope of the rights of the present invention is not limited thereto. Any modification, equivalent substitution and improvement made by a person skilled in the art without departing from the scope and essence of the present invention should be within the scope of the rights of the present invention.

Claims

1. A data frame processing system, characterized in that: The data frame processing system includes an FPGA, a micro control unit and two PHY chips; The FPGA includes a chip configuration module, a frame insertion / frame interception module, a serial port module, and two frame processing modules. The frame insertion / frame interception module is respectively connected to the serial port module and the two frame processing modules, and the serial port module is connected to the micro control unit; the chip configuration module is respectively connected to the two PHY chips, and the two PHY chips and the two frame processing modules are connected in a one-to-one correspondence; The chip configuration module is used to configure the working modes of the two PHY chips, wherein the working modes include a normal mode; The PHY chip is used to generate interface data from the received data stream and send the interface data to the frame processing module; The frame processing module is used to extract the control frame and the correct data frame from the interface data in the normal mode, and send the control frame and the correct data frame to the frame insertion / frame interception module; And used to convert the received correct data frame into interface data and send it to the PHY chip; The frame insertion / frame interception module is used to forward the received correct data frame to another frame processing module; The data frame processing system further includes a micro control unit, and the working mode further includes a frame insertion mode; The micro control unit is used to send control data, so that the control data is converted from serial to parallel through the serial port module and then sent to the frame insertion / frame interception module; The frame insertion / frame interception module is used to parse the received control data to obtain the transmission direction of the interface data, and use the PHY chip corresponding to the transmission direction as the target PHY chip; The frame processing module is used to receive the interface data sent by the PHY chip in the frame insertion mode, identify the indication signal of the interface data, determine the frame interval of the data frame if it is determined that the indication signal indicates that the frame insertion condition is met, insert the received interface data into the data frame queue to be sent according to the frame interval, and send the data frame queue with the inserted interface data to the target PHY chip.

2. The system according to claim 1, characterized in that The working mode also includes a frame capture mode; The PHY chip is used to generate interface data after receiving the data stream and send it to the frame processing module connected thereto; The frame insertion / frame interception module is used to extract the control frame from the interface data sent by the frame processing module in the frame interception mode; Identify the control frame and determine whether to send the correct data frame to another PHY chip; If it is determined that the correct data frame is to be sent to another PHY chip, the control frame is copied, the control frame is input into a queue of data frames to be sent, and the control frame is parsed into control data and then transmitted to the micro control unit through a serial port module; If it is determined not to send the correct data frame to another PHY chip, the control frame is parsed into control data and then sent to the micro control unit through the serial port module.

3. The system according to claim 1, characterized in that The frame processing module includes a MAC module, a receiving buffer module, a sending buffer module and a frame parsing module; the PHY chip, the MAC module, the receiving buffer module, the frame parsing module and the frame insertion / frame interception module are connected in sequence, and the sending buffer module is respectively connected to the MAC module and the frame insertion / frame interception module; The MAC module is used to convert the interface data sent by the PHY chip into a data frame of the MAC layer; The receiving buffer module is used to buffer the data frames parsed by the MAC module; The frame parsing module is used to parse the received data frame according to the MAC layer protocol to obtain the MAC address of the sending data frame; The frame insertion / frame interception module is used to match the MAC address of the data frame to be sent with the MAC address of the MAC module, discard the data frames with wrong matching, and divide the data frames with consistent matching into control frames and correct data frames; and used to match the MAC address in the control data with the MAC addresses of the two MAC modules respectively, determine a MAC module with consistent matching, and use the PHY chip connected to the MAC module as the target PHY chip; The sending buffer module is used to buffer the data frames generated by the frame insertion / frame interception module; The serial port module is used to implement data interaction between the frame insertion / frame interception module and the micro control unit, obtain the working mode according to the received control data analysis, and provide the working mode to the chip configuration module.

4. The system according to claim 3, characterized in that The receiving buffer module is also used to determine the frame interval of the buffered data frames.

5. A data frame processing method, characterized in that: Applied to a data frame processing system, the data frame processing system includes an FPGA, a micro control unit and two PHY chips; The FPGA includes a chip configuration module, a frame insertion / frame interception module, a serial port module, and two frame processing modules. The frame insertion / frame interception module is respectively connected to the serial port module and the two frame processing modules, and the serial port module is connected to the micro control unit; the chip configuration module is respectively connected to the two PHY chips, and the two PHY chips and the two frame processing modules are connected in a one-to-one correspondence; The method comprises the following steps: Configure the working modes of the two PHY chips through a chip configuration module, wherein the working modes include a normal mode; Generate interface data from the received data stream through the PHY chip, and send the interface data to the frame processing module; In normal mode, the frame processing module extracts control frames and correct data frames from the interface data, and sends the control frames and correct data frames to the frame insertion / frame interception module; and converts the received correct data frames into interface data and sends them to the PHY chip; Forwarding the received correct data frame to another frame processing module through the frame insertion / frame interception module; The data frame processing system further includes a micro control unit, and the working mode further includes a frame insertion mode; the method further includes: The control data is sent through the micro control unit, so that the control data is converted into serial and parallel data through the serial port module and then sent to the frame insertion / frame interception module; The frame insertion / frame interception module parses the received control data to obtain the transmission direction of the interface data, and uses the PHY chip corresponding to the transmission direction as the target PHY chip; In the insertion mode, the interface data sent by the PHY chip is received through the frame processing module, and the indication signal of the interface data is identified. If it is determined that the indication signal indicates that the insertion condition is met, the frame interval of the data frame is determined, and the received interface data is inserted into the data frame queue to be sent according to the frame interval, and the data frame queue with the inserted interface data is sent to the target PHY chip.

6. The method according to claim 5, characterized in that The working mode also includes a frame capture mode; the method also includes: After receiving the data stream, the PHY chip generates interface data and sends it to the frame processing module connected to it; In the frame interception mode, a control frame is extracted from the interface data sent by the frame processing module through the frame insertion / frame interception module; the control frame is identified to determine whether to send the correct data frame to another PHY chip; If it is determined that the correct data frame is to be sent to another PHY chip, the control frame is copied, the control frame is input into a queue of data frames to be sent, and the control frame is parsed into control data and then transmitted to the micro control unit through a serial port module; If it is determined not to send the correct data frame to another PHY chip, the control frame is parsed into control data and then sent to the micro control unit through the serial port module.

7. The method according to claim 5, characterized in that The frame processing module includes a MAC module, a receiving buffer module, a sending buffer module and a frame parsing module; the PHY chip, the MAC module, the receiving buffer module, the frame parsing module and the frame insertion / frame interception module are connected in sequence, and the sending buffer module is connected to the MAC module and the frame insertion / frame interception module respectively; the method also includes: The interface data sent by the PHY chip is converted into data frames of the MAC layer through the MAC module; The receiving buffer module caches the data frames parsed by the MAC module; The frame parsing module performs MAC layer protocol parsing on the received data frame to obtain the MAC address of the sending data frame; Matching the MAC address of the data frame to be sent with the MAC address of the MAC module through the frame insertion / frame interception module, discarding the data frame with incorrect matching, and dividing the data frame with consistent matching into control frames and correct data frames; and matching the MAC address in the control data with the MAC addresses of the two MAC modules respectively, determining the MAC module with consistent matching, and taking the PHY chip connected to the MAC module as the target PHY chip; Cache the data frames generated by the frame insertion / frame interception module by sending the cache module; The data interaction between the frame insertion / frame interception module and the micro control unit is realized through the serial port module, the working mode is obtained according to the analysis of the received control data, and the working mode is provided to the chip configuration module.

8. The method according to claim 7, characterized in that The method further comprises: The receiving buffer module determines the frame interval for the buffered data frames.

Images