Three-dimensional semiconductor memory device and electronic system including same

Abstract

The invention discloses a three-dimensional semiconductor memory device and an electronic system. The three-dimensional semiconductor memory device includes: a stack structure including interlayer dielectric layers and gate electrodes alternately stacked on a substrate; a vertical channel structure penetrating the stack structure; and a separation structure extending in the first direction across between the stacked structures. The separation structure includes: a first portion extending in a vertical direction from the substrate; and a second portion on the first portion and including a material different from a material of the first portion. A top surface of the second portion is at the same level as a top surface of the vertical channel structure.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0074704 filed in the Korean Intellectual Property Office on June 12, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a three-dimensional semiconductor memory device, and more particularly, to a nonvolatile three-dimensional semiconductor memory device including a vertical channel structure, a method for manufacturing the nonvolatile three-dimensional semiconductor memory device, and an electronic system for implementing the nonvolatile three-dimensional semiconductor memory device. Background Art

[0004] Semiconductor devices capable of storing large amounts of data in electronic systems requiring data storage are needed. Semiconductor devices have been highly integrated to meet high performance and low manufacturing cost standards. The integration level of typical two-dimensional or planar semiconductor devices is mainly determined by the area occupied by the unit memory cell, so that the integration level is largely affected by the available technology for forming fine patterns. However, the processing equipment for fine patterns is expensive and limits the integration level of two-dimensional or planar semiconductor devices. Therefore, three-dimensional semiconductor memory devices with three-dimensionally arranged memory cells have been proposed. Summary of the invention

[0005] The present disclosure provides a three-dimensional semiconductor memory device having improved electrical performance and increased reliability.

[0006] The present disclosure provides an electronic system including a three-dimensional semiconductor memory device having improved electrical performance and increased reliability.

[0007] The objects of the present disclosure are not limited to the above contents, and other objects not mentioned above will be clearly understood by those skilled in the art from the following description.

[0008] In general, aspects of the subject matter described in this specification can be embodied in a three-dimensional semiconductor memory device, which includes: a plurality of stacked structures, including a plurality of interlayer dielectric layers and a plurality of gate electrodes alternately stacked on a substrate; a plurality of vertical channel structures, penetrating the stacked structures; and a separation structure, extending along a first direction across the stacked structures. The separation structure may include: a first portion, extending from the substrate in a vertical direction; and a second portion on the first portion, the second portion including a material different from that of the first portion. The top surface of the second portion of the separation structure is at the same level as the top surface of the vertical channel structure.

[0009] Another general aspect can be embodied in a three-dimensional semiconductor memory device, the three-dimensional semiconductor memory device comprising: a substrate including a cell array region and a contact region adjacent to the cell array region in a first direction; a peripheral circuit structure on the substrate, the peripheral circuit structure including a plurality of peripheral circuit transistors; a source structure on the peripheral circuit structure; a plurality of stacked structures including a plurality of interlayer dielectric layers and a plurality of gate electrodes alternately stacked on the source structure; a plurality of vertical channel structures penetrating the stacked structures and connected to the source structures; a separation structure extending along the first direction across the stacked structures; a selection molding structure on the stacked structure, the selection molding structure including a selection semiconductor layer; an upper separation structure penetrating the selection molding structure and contacting the separation structure; a plurality of upper vertical channel structures penetrating the selection molding structure and correspondingly connected to the vertical channel structure; and a separation dielectric pattern in the selection molding structure, the separation dielectric pattern penetrating the selection semiconductor layer. The separation structure may include: a first portion on a second substrate; and a second portion between the first portion and the selection molding structure. The top surface of the second portion may be at the same level as the top surface of the vertical channel structure.

[0010] Another general aspect may be embodied in an electronic system, the electronic system comprising: a three-dimensional semiconductor memory device, comprising: a substrate; a plurality of stacked structures, comprising a plurality of interlayer dielectric layers and a plurality of gate electrodes alternately stacked on the substrate; a plurality of vertical channel structures, penetrating the stacked structures; a separation structure between the stacked structures; and an input / output pad on the stacked structure; and a controller, electrically connected to the three-dimensional semiconductor memory device through the input / output pad and controlling the three-dimensional semiconductor memory device. The separation structure may include: a first portion extending from the substrate in a vertical direction; and a second portion on the first portion, the second portion including a material different from that of the first portion. The top surface of the separation structure may be at the same level as that of the top surface of the stacked structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 A simplified schematic diagram illustrating an example of an electronic system including a three-dimensional semiconductor memory device is shown.

[0012] Figure 2 A simplified perspective view illustrating an example of an electronic system including a three-dimensional semiconductor memory device is shown.

[0013] Figure 3 and Figure 4 Shown are Figure 2 2 , cross-sectional views taken along lines II' and II-II' illustrate a three-dimensional semiconductor memory device.

[0014] Figure 5 A plan view illustrating an example of a three-dimensional semiconductor memory device is shown.

[0015] Figure 6 and Figure 7 Shown are Figure 5 2 , cross-sectional views taken along lines II' and II-II' illustrate a three-dimensional semiconductor memory device.

[0016] FIG. 8A to FIG. 8C Shows Figure 6 0 is an enlarged cross-sectional view of a portion A depicted in FIG. 1 , partially illustrating a three-dimensional semiconductor memory device.

[0017] Fig. 9 Shows Figure 6 0 is an enlarged cross-sectional view of portion B depicted in FIG. 1 , partially illustrating a three-dimensional semiconductor memory device.

[0018] FIG. 10A to FIG. 13C Plan views and cross-sectional views illustrating an example of a method of manufacturing a three-dimensional semiconductor memory device are shown.

[0019] Fig. 10A , Fig.11A , Fig. 12A and Fig.13A A plan view illustrating an example of a three-dimensional semiconductor memory device is shown.

[0020] Fig. 10B Shown along Fig. 10A A cross-sectional view taken along line II'.

[0021] Fig. 11B Shown along Fig.11A A cross-sectional view taken along line II'.

[0022] Fig. 12B , Fig. 12C and Fig.12D Shown along Fig. 12A A cross-sectional view taken along line II'.

[0023] Fig. 13B and Fig. 13C Shown along Fig.13A A cross-sectional view taken along line II'. DETAILED DESCRIPTION

[0024] Hereinafter, the same reference numerals may refer to the same components throughout the description.

[0025] Figure 1 A simplified schematic diagram illustrating an example of an electronic system including a three-dimensional semiconductor memory device is shown.

[0026] Reference Figure 1, the electronic system 1000 includes a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The electronic system 1000 may be a storage device including a single or a plurality of semiconductor devices 1100 or may be an electronic device including the storage device. For example, the electronic system 1000 may be a solid state drive (SSD) device, a universal serial bus (USB), a computing system, a medical device, or a communication device, each of which includes a single or a plurality of semiconductor devices 1100.

[0027] The semiconductor device 1100 may be a nonvolatile memory device, such as a NAND flash memory device. The semiconductor device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F. Alternatively, the first structure 1100F may be disposed on one side of the second structure 1100S.

[0028] The first structure 1100F may be a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. The second structure 1100S may be a memory cell structure including a bit line BL, a common source line CSL, a word line WL, a first gate upper line UL1 and a second gate upper line UL2, a first gate lower line LL1 and a second gate lower line LL2, and a memory cell string CSTR between the bit line BL and the common source line CSL.

[0029] In the second structure 1100S, each memory cell string CSTR may include lower transistors LT1 and LT2 adjacent to a common source line CSL, upper transistors UT1 and UT2 adjacent to a bit line BL, and memory cell transistors MCT disposed between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. Figure 1 Each of the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2 is depicted as two, but the number of each of the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2 may vary.

[0030] The upper transistors UT1 and UT2 may include string selection transistors, and the lower transistors LT1 and LT2 may include ground selection transistors. The first gate lower line LL1 and the second gate lower line LL2 may be gate electrodes of the lower transistors LT1 and LT2, respectively. The word line WL may be a gate electrode of the memory cell transistor MCT, and the first gate upper line UL1 and the second gate upper line UL2 may be gate electrodes of the upper transistors UT1 and UT2, respectively.

[0031] For example, the lower transistors LT1 and LT2 may include a lower erase control transistor and a ground selection transistor connected in series. The upper transistors UT1 and UT2 may include a string selection transistor and an upper erase control transistor connected in series. One or both of the lower erase control transistor and the upper erase control transistor may be used to perform an erase operation in which data stored in the memory cell transistor MCT is erased using a gate induced drain leakage (GIDL) phenomenon.

[0032] The common source line CSL, the first and second gate lower lines LL1 and LL2, the word lines WL, and the first and second gate upper lines UL1 and UL2 may be electrically connected to the decoder circuit 1110 through a first connection line 1115 extending from the first structure 1100F to the second structure 1100S. The bit line BL may be electrically connected to the page buffer 1120 through a second connection line 1125 extending from the first structure 1100F to the second structure 1100S.

[0033] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 may perform a control operation on at least one selected memory cell transistor among the plurality of memory cell transistors MCT. The logic circuit 1130 may control the decoder circuit 1110 and the page buffer 1120. The semiconductor device 1100 may communicate with the controller 1200 through an input / output pad 1101 electrically connected to the logic circuit 1130. The input / output pad 1101 may be electrically connected to the logic circuit 1130 through an input / output connection line 1135 extending from the first structure 1100F to the second structure 1100S.

[0034] Although not shown, the first structure 1100F may include a voltage generator. The voltage generator may generate a program voltage, a read voltage, a pass voltage, and a verification voltage required to operate the memory cell string CSTR. The program voltage may be relatively higher (e.g., about 20V to about 40V) than the read voltage, the pass voltage, and the verification voltage.

[0035] For example, the first structure 1100F may include a high voltage transistor and a low voltage transistor. The decoder circuit 1110 may include a pass transistor connected to the word line WL of the memory cell string CSTR. The pass transistor may include a high voltage transistor capable of withstanding a high voltage such as a programming voltage applied to the word line WL in a programming operation. The page buffer 1120 may also include a high voltage transistor capable of withstanding a high voltage.

[0036] The controller 1200 may include a processor 1210 , a NAND controller 1220 , and a host interface 1230 . For example, the electronic system 1000 may include a plurality of semiconductor devices 1100 , and in this case, the controller 1200 may control the plurality of semiconductor devices 1100 .

[0037] The processor 1210 may control the overall operation of the electronic system 1000 including the controller 1200. The processor 1210 may operate based on a predetermined firmware and may control the NAND controller 1220 to access the semiconductor device 1100. The NAND controller 1220 may include a NAND interface 1221 that processes communication with the semiconductor device 1100. The NAND interface 1221 may be used to transmit therethrough a control command for controlling the semiconductor device 1100, data intended to be written on the memory cell transistor MCT of the semiconductor device 1100, and / or data intended to be read from the memory cell transistor MCT of the semiconductor device 1100. The host interface 1230 may provide the electronic system 1000 with communication with an external host. When a control command is received from the external host through the host interface 1230, the processor 1210 may control the semiconductor device 1100 in response to the control command.

[0038] Figure 2 A simplified perspective view illustrating an example of an electronic system including a three-dimensional semiconductor memory device is shown.

[0039] Reference Figure 2 , the electronic system 2000 may include a main board 2001, a controller 2002 mounted on the main board 2001, one or more semiconductor packages 2003, and a dynamic random access memory (DRAM) 2004. The semiconductor package 2003 and the DRAM 2004 may be connected to the controller 2002 through a wiring pattern 2005 formed on the main board 2001.

[0040] The mainboard 2001 may include a connector 2006 including a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins on the connector 2006 may be changed based on the communication interface between the electronic system 2000 and the external host. The electronic system 2000 may communicate with the external host through one or more interfaces (e.g., a universal serial bus (USB), a peripheral component interconnect fast (PCI-Express), a serial advanced technology attachment (SATA), and an M-PHY for universal flash memory (UFS)). In addition, the electronic system 2000 may operate using power supplied from an external host through the connector 2006. The electronic system 2000 may also include a power management integrated circuit (PMIC), by which the power supplied from the external host is distributed to the controller 2002 and the semiconductor package 2003.

[0041] The controller 2002 may write data to the semiconductor package 2003 , may read data from the semiconductor package 2003 , or may increase the operation speed of the electronic system 2000 .

[0042] The DRAM 2004 may be a buffer memory that reduces a speed difference between an external host and the semiconductor package 2003 used as a data storage space. The DRAM 2004 included in the electronic system 2000 may operate as a cache memory and may provide a space for temporary data storage in a control operation of the semiconductor package 2003. When the DRAM 2004 is included in the electronic system 2000, the controller 2002 may include not only a NAND controller for controlling the semiconductor package 2003 but also a DRAM controller for controlling the DRAM 2004.

[0043] The semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, a semiconductor chip 2200 on the package substrate 2100, an adhesive layer 2300 disposed on the bottom surface of the semiconductor chip 2200, a connection structure 2400 electrically connecting the semiconductor chip 2200 to the package substrate 2100, and a mold layer 2500 located on the package substrate 2100 and covering the semiconductor chip 2200 and the connection structure 2400.

[0044] The package substrate 2100 may be a printed circuit board including an upper pad 2130. Each semiconductor chip 2200 may include one or more input / output pads 2210. The input / output pads 2210 may correspond to Figure 1 The input / output pads 1101 are provided. Each semiconductor chip 2200 may include a gate stack structure 3210 and a vertical channel structure 3220. Each semiconductor chip 2200 may include a three-dimensional semiconductor memory device.

[0045] For example, the connection structure 2400 may include a bonding wire that electrically connects the input / output pad 2210 to the upper pad 2130. Therefore, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other in a wire bonding manner and may be electrically connected to the upper pad 2130 of the package substrate 2100. Alternatively, on each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other through a connection structure such as a through silicon via (TSV) instead of a connection structure 2400 shaped like a bonding wire.

[0046] For example, the controller 2002 and the semiconductor chip 2200 may be included in a single package. In some embodiments, the controller 2002 and the semiconductor chip 2200 may be mounted on a separate interposer substrate other than the main board 2001 and may be electrically connected through wiring lines formed on the interposer substrate.

[0047] Figure 3 and Figure 4 Shown are Figure 2 The cross-sectional views taken along the lines II' and II-II' illustrate a three-dimensional semiconductor memory device.

[0048] Reference Figure 3 and Figure 4 , the semiconductor package 2003 may include a package substrate 2100 , a plurality of semiconductor chips 2200 on the package substrate 2100 , and a mold layer 2500 covering the package substrate 2100 and the plurality of semiconductor chips 2200 .

[0049] The package substrate 2100 may include a package substrate body 2120, an upper pad 2130 disposed on the top surface of the package substrate body 2120, a lower pad 2125 disposed or exposed on the bottom surface of the package substrate body 2120, and an internal wiring line 2135 located in the package substrate body 2120 and electrically connecting the upper pad 2130 to the lower pad 2125. The upper pad 2130 may be electrically connected to the plurality of connection structures 2400. The lower pad 2125 may be connected to the conductive connector 2800. Figure 2 2005 in the main board 2001 of the electronic system 2000 depicted in FIG.

[0050] Each semiconductor chip 2200 may include a semiconductor substrate 3010, and may also include a first structure 3100 and a second structure 3200 sequentially stacked on the semiconductor substrate 3010. The first structure 3100 may include a peripheral circuit region including a peripheral wiring line 3110. The second structure 3200 may include a common source line 3205, a gate stack structure 3210 on the common source line 3205, a vertical channel structure 3220 and a separation structure 3230 penetrating the gate stack structure 3210, a bit line 3240 electrically connected to the vertical channel structure 3220, and a word line (see FIG. 3 ) connected to the gate stack structure 3210. Figure 1 WL) electrically connected gate connection line 3235 and wire 3250.

[0051] Each semiconductor chip 2200 may include one or more through-wiring lines 3245 extending into the second structure 3200 and electrically connected to the peripheral wiring lines 3110 of the first structure 3100. The through-wiring lines 3245 may penetrate the gate stack structure 3210, and may also be arranged outside the gate stack structure 3210. Each semiconductor chip 2200 may also include an input / output connection line 3265 extending into the second structure 3200 and electrically connected to the peripheral wiring lines 3110 of the first structure 3100, and may also include an input / output pad 2210 electrically connected to the input / output connection line 3265.

[0052] Figure 5 A plan view illustrating an example of a three-dimensional semiconductor memory device is shown. Figure 6 and Figure 7 Shown are Figure 5 2 , cross-sectional views taken along lines II' and II-II' illustrate a three-dimensional semiconductor memory device.

[0053] Reference Figure 5 , Figure 6 and Figure 7 , a three-dimensional semiconductor memory device may include a first substrate 10, a peripheral circuit structure PS on the first substrate 10, and a cell array structure CS on the peripheral circuit structure PS.

[0054] The first substrate 10 may include a cell array region CAR and a contact region CCR. The first substrate 10 may extend along a first direction D1 directed from the cell array region CAR to the contact region CCR and a second direction D2 intersecting the first direction D1. The top surface of the first substrate 10 may be parallel to the first direction D1 and the second direction D2, and may be perpendicular to a third direction D3 intersecting the first direction D1 and the second direction D2. For example, the first direction D1, the second direction D2, and the third direction D3 may be orthogonal to each other.

[0055] From a plan view, the contact region CCR may extend from the cell array region CAR along the first direction D1. The vertical channel structure VS and the bit line BL electrically connected to the vertical channel structure VS may be provided in the cell array region CAR. The contact region CCR may be a region on which a step structure including a pad portion ELp to be discussed below is provided. Alternatively, the contact region CCR may extend from the cell array region CAR along the second direction D2.

[0056] The first substrate 10 may be, for example, a silicon substrate, a silicon germanium substrate, a germanium substrate, or a single crystal epitaxial layer grown on a single crystal silicon substrate.

[0057] The device isolation layer 11 may be disposed in the first substrate 10. The device isolation layer 11 may define an active portion of the first substrate 10. For example, the device isolation layer 11 may include silicon oxide.

[0058] The peripheral circuit structure PS may be disposed on the first substrate 10. The peripheral circuit structure PS may include a peripheral circuit transistor PTR on an active portion of the first substrate 10, a peripheral contact plug 31, a peripheral circuit line 33 electrically connected to the peripheral circuit transistor PTR through the peripheral contact plug 31, and a first dielectric layer 30 surrounding the peripheral circuit transistor PTR, the peripheral contact plug 31, and the peripheral circuit line 33. The peripheral circuit structure PS may correspond to Figure 1 The first structure 1100F, and the peripheral circuit line 33 may correspond to Figure 3 and Figure 4 Peripheral wiring line 3110.

[0059] The peripheral circuit may be composed of a peripheral circuit transistor PTR, a peripheral contact plug 31, and a peripheral circuit line 33. For example, the peripheral circuit transistor PTR may be composed of Figure 1 The decoder circuit 1110, the page buffer 1120 and the logic circuit 1130 are shown in FIG. 1 . More specifically, each peripheral circuit transistor PTR may include a peripheral gate dielectric layer 21, a peripheral gate electrode 23, a peripheral capping pattern 25, a peripheral gate spacer 27 and a peripheral source / drain portion 29. In the embodiments shown herein, the phrase source / drain portion may be understood to mean a source terminal portion or a drain terminal portion of a transistor.

[0060] The peripheral gate dielectric layer 21 may be disposed between the peripheral gate electrode 23 and the first substrate 10. The peripheral capping pattern 25 may be disposed on the peripheral gate electrode 23. The peripheral gate spacer 27 may cover the sidewalls of the peripheral gate dielectric layer 21, the sidewalls of the peripheral gate electrode 23, and the sidewalls of the peripheral capping pattern 25. The peripheral source / drain portion 29 may be disposed in the first substrate 10 adjacent to the opposite side of the peripheral gate electrode 23.

[0061] The peripheral circuit line 33 may be electrically connected to the peripheral circuit transistor PTR through the peripheral contact plug 31. Each peripheral circuit transistor PTR may be, for example, an NMOS transistor, a PMOS transistor, or a full-surround gate transistor. For example, the peripheral contact plug 31 may have a width that increases with increasing distance from the first substrate 10 in both the first direction D1 or the second direction D2. The peripheral contact plug 31 and the peripheral circuit line 33 may include a conductive material, such as a metal.

[0062] The first dielectric layer 30 may be disposed on the top surface of the first substrate 10. On the first substrate 10, the first dielectric layer 30 may cover the peripheral circuit transistor PTR, the peripheral contact plug 31, and the peripheral circuit line 33. The first dielectric layer 30 may include a plurality of dielectric layers constituting a multilayer structure. For example, the first dielectric layer 30 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, and a low-k dielectric material.

[0063] The first dielectric layer 30 may be disposed in a cell array region CAR having a cell array structure CS, the cell array structure CS including a second substrate 100 and a stacked structure ST on the second substrate 100. The second substrate 100 may extend along a first direction D1 and a second direction D2. The second substrate 100 may not be disposed on a portion of the contact region CCR. The second substrate 100 may be a semiconductor substrate including a semiconductor material. The second substrate 100 may include, for example, silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs) or a mixture thereof.

[0064] The stack structure ST may be disposed on the second substrate 100. The stack structure ST may extend from the cell array region CAR to the contact region CCR. The stack structure ST may correspond to Figure 3 and Figure 4 The gate stack structure 3210. The stack structure ST may be provided in plurality, and the plurality of stack structures ST may be arranged along the second direction D2 and spaced apart from each other in the second direction D2 across the separation structure 150 to be discussed below. For ease of description, the following description will focus on a single stack structure ST, but the description may also be applicable to other stack structures ST.

[0065] The stacked structure ST may include interlayer dielectric layers ILDa and ILDb and gate electrodes ELa and ELb that are alternately stacked. The gate electrodes ELa and ELb may correspond to Figure 1 The first gate lower line LL1 and the second gate lower line LL2, the first gate upper line UL1 and the second gate upper line UL2, and the word line WL.

[0066] The stacked structure ST may include a first stacked structure ST1 on a second substrate 100 and a second stacked structure ST2 on the first stacked structure ST1. The first stacked structure ST1 may include first interlayer dielectric layers ILDa and first gate electrodes ELa that are alternately stacked, and the second stacked structure ST2 may include second interlayer dielectric layers ILDb and second gate electrodes ELb that are alternately stacked. The first gate electrode ELa and the second gate electrode ELb may have substantially the same thickness in a third direction D3.

[0067] The first gate electrode ELa and the second gate electrode ELb may have a length in the first direction D1 that decreases as they move away from the second substrate 100 in the third direction D3. For example, each of the first gate electrode ELa and the second gate electrode ELb may have a length in the first direction D1 that is longer than a length of a directly overlying gate electrode in the first direction D1. The lowermost first gate electrode among the first gate electrodes ELa in the first stacked structure ST1 may have a maximum length in the first direction D1, and the uppermost second gate electrode among the second gate electrodes ELb in the second stacked structure ST2 may have a minimum length in the first direction D1.

[0068] The first gate electrode ELa and the second gate electrode ELb may have a pad portion ELp on the contact region CCR. The pad portions ELp of the first gate electrode ELa and the second gate electrode ELb may be disposed at positions different from each other in the horizontal and vertical directions. The pad portion ELp may constitute a step structure along the first direction D1.

[0069] The step structures may be arranged so that each of the first stacked structure ST1 and the second stacked structure ST2 may have a thickness that decreases as the distance from the outermost vertical channel structure in the vertical channel structure VS to be discussed below increases, and so that the first gate electrode ELa and the second gate electrode ELb may have sidewalls spaced apart from each other at regular intervals along the first direction D1 as seen from a plan view. For example, the first gate electrode ELa and the second gate electrode ELb may include at least one selected from a doped semiconductor (e.g., doped silicon), a metal (e.g., tungsten, copper, aluminum), a conductive metal nitride (e.g., titanium nitride and tantalum nitride), and a transition metal (e.g., titanium and tantalum), and may include tungsten, for example.

[0070] The first interlayer dielectric layer ILDa and the second interlayer dielectric layer ILDb may be disposed between the first gate electrode ELa and the second gate electrode ELb, and the sidewall of each of the first interlayer dielectric layer ILDa and the second interlayer dielectric layer ILDb may be aligned with the sidewall of the underlying gate electrode of the first gate electrode ELa and the second gate electrode ELb. For example, similar to the first gate electrode ELa and the second gate electrode ELb, the first interlayer dielectric layer ILDa and the second interlayer dielectric layer ILDb may have a length in the first direction D1 that decreases as the distance from the second substrate 100 increases.

[0071] The bottommost second interlayer dielectric layer in the second interlayer dielectric layer ILDb may contact the topmost first interlayer dielectric layer in the first interlayer dielectric layer ILDa. For example, the thickness of each of the first interlayer dielectric layer ILDa and the second interlayer dielectric layer ILDb may be less than the thickness of each of the first gate electrode ELa and the second gate electrode ELb. For example, the thickness of the bottommost first interlayer dielectric layer in the first interlayer dielectric layer ILDa may be less than the thickness of each of the other first interlayer dielectric layers ILDa and the second interlayer dielectric layers ILDb. For example, the thickness of the topmost second interlayer dielectric layer in the second interlayer dielectric layer ILDb may be greater than the thickness of each of the other first interlayer dielectric layers ILDa and the second interlayer dielectric layers ILDb.

[0072] Except for the bottommost first interlayer dielectric layer ILDa and the topmost second interlayer dielectric layer ILDb, the other first interlayer dielectric layers ILDa and the second interlayer dielectric layers ILDb may have substantially the same thickness. However, the inventive concept is not limited thereto. The thickness of the first interlayer dielectric layer ILDa and the second interlayer dielectric layer ILDb may depend on the characteristics of the semiconductor device.

[0073] For example, the first interlayer dielectric layer ILDa and the second interlayer dielectric layer ILDb may include one or more of silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric material, a high density plasma (HDP) oxide, and tetraethyl orthosilicate (TEOS).

[0074] Alternatively, the first stacked structure ST1 and the second stacked structure ST2 may have different step structures on the contact region CCR. For example, the length of the lowest second gate electrode among the second gate electrodes ELb in the second stacked structure ST2 in the first direction D1 may be substantially the same as the length of the lowest first gate electrode among the first gate electrodes ELa in the first stacked structure ST1 in the first direction D1. The lowest second gate electrode among the second gate electrodes ELb in the second stacked structure ST2 may be longer in the first direction D1 than the highest first gate electrode among the first gate electrodes ELa in the first stacked structure ST1.

[0075] The source structure SC may be disposed between the stack structure ST and the second substrate 100 on the cell array region CAR. The source structure SC may correspond to Figure 1 The common source line CSL or Figure 3 and Figure 4 The common source line 3205 of the first substrate 100 is provided. The source structure SC may include a first source conductive pattern SCP1 and a second source conductive pattern SCP2 sequentially stacked on the second substrate 100. The second source conductive pattern SCP2 may be disposed between the first source conductive pattern SCP1 and the lowermost first interlayer dielectric layer in the first interlayer dielectric layer ILDa. The thickness of the first source conductive pattern SCP1 may be greater than the thickness of the second source conductive pattern SCP2. The first source conductive pattern SCP1 and the second source conductive pattern SCP2 may include a semiconductor material such as silicon or a semiconductor material doped with impurities. When the first source conductive pattern SCP1 and the second source conductive pattern SCP2 include semiconductor materials doped with impurities, the impurity concentration of the first source conductive pattern SCP1 may be greater than the impurity concentration of the second source conductive pattern SCP2.

[0076] The first source conductive pattern SCP1 of the source structure SC may be disposed only on the cell array region CAR and may not be disposed on the contact region CCR. The second source conductive pattern SCP2 of the source structure SC may extend from the cell array region CAR toward the contact region CCR. For example, the second source conductive pattern SCP2 on the cell array region CAR may be substantially the same as the semiconductor layer 121 on the contact region CCR to be discussed below.

[0077] The first buffer dielectric layer 111, the second buffer dielectric layer 113, the third buffer dielectric layer 115, and the semiconductor layer 121 may be disposed between the lowermost first interlayer dielectric layer in the first interlayer dielectric layer ILDa and the second substrate 100 on the contact region CCR. The first buffer dielectric layer 111, the second buffer dielectric layer 113, the third buffer dielectric layer 115, and the semiconductor layer 121 may be sequentially stacked on the second substrate 100. The second buffer dielectric layer 113 may include a dielectric material different from that of the first buffer dielectric layer 111 and the third buffer dielectric layer 115. The second buffer dielectric layer 113 may be thicker than the first buffer dielectric layer 111 and the third buffer dielectric layer 115, but the present disclosure is not limited thereto. The first buffer dielectric layer 111, the second buffer dielectric layer 113, and the third buffer dielectric layer 115 may include, for example, at least one selected from silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, and silicon-germanium.

[0078] On the cell array region CAR, a plurality of vertical channel structures VS may be provided to penetrate the stacked structure ST and the source structure SC. The vertical channel structure VS may penetrate at least a portion of the second substrate 100, and the bottom surface of each vertical channel structure VS may be located at a level lower than that of the top surface of the second substrate 100 and the bottom surface of the source structure SC. For example, the vertical channel structure VS may directly contact the second substrate 100.

[0079] From a plan view, the vertical channel structure VS may be arranged in a zigzag manner along the first direction D1 or the second direction D2. The vertical channel structure VS may not be disposed on the contact region CCR. The vertical channel structure VS may correspond to Figures 2 to 4 The vertical channel structure VS may correspond to Figure 1 1 and 2 , the lower transistors LT1 and LT2 , the upper transistors UT1 and UT2 , and the channels of the memory cell transistor MCT are depicted in FIG.

[0080] The vertical channel structure VS may be disposed in the vertical channel holes CH penetrating the stack structure ST. Each vertical channel hole CH may include a first vertical channel hole CH1 penetrating the first stack structure ST1 and a second vertical channel hole CH2 penetrating the second stack structure ST2. The first vertical channel hole CH1 and the second vertical channel hole CH2 of each vertical channel hole CH may be connected to each other in the third direction D3.

[0081] Each vertical channel structure VS may include a first vertical channel structure VSa and a second vertical channel structure VSb. The first vertical channel structure VSa may be disposed in the first vertical channel hole CH1, and the second vertical channel structure VSb may be disposed in the second vertical channel hole CH2. The second vertical channel structure VSb may be disposed on the first vertical channel structure VSa and connected to the first vertical channel structure VSa.

[0082] For example, each of the first vertical channel structure VSa and the second vertical channel structure VSb may have a width in the first direction D1 or the second direction D2, and the width of each of the first vertical channel structure VSa and the second vertical channel structure VSb may increase along the third direction D3. The width of the uppermost portion of the first vertical channel structure VSa may be greater than the width of the lowermost portion of the second vertical channel structure VSb. For example, each vertical channel structure VS may have a sidewall having a step difference at a boundary between the first vertical channel structure VSa and the second vertical channel structure VSb. However, the inventive concept is not limited thereto, and each vertical channel structure VS may have a sidewall having three or more step differences at different levels or each vertical channel structure VS may be flat without a step difference.

[0083] On the contact region CCR, a second dielectric layer 170 may be provided to cover the stacked structure ST and a portion of the first dielectric layer 30. For example, the second dielectric layer 170 may be provided on the pad portion ELp of the first gate electrode ELa and the second gate electrode ELb while covering the stepped structure of the stacked structure ST. The second dielectric layer 170 may have a substantially planarized top surface. The top surface of the second dielectric layer 170 may be substantially coplanar with the top surface of the stacked structure ST. For example, the top surface of the second dielectric layer 170 may be substantially coplanar with the top surface of the uppermost second interlayer dielectric layer in the second interlayer dielectric layer ILDb in the stacked structure ST.

[0084] The second dielectric layer 170 may include a single or multiple stacked dielectric layers. For example, the second dielectric layer 170 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, and a low-k dielectric material. The second dielectric layer 170 may include a dielectric material different from the dielectric material of the first interlayer dielectric layer ILDa and the second interlayer dielectric layer ILDb of the stacked structure ST. For example, when the first interlayer dielectric layer ILDa and the second interlayer dielectric layer ILDb of the stacked structure ST include a high-density plasma oxide, the second dielectric layer 170 may include tetraethyl orthosilicate (TEOS).

[0085] The dummy vertical channel structure DVS may be disposed around the cell contact plug CCP to be discussed. The dummy vertical channel structure DVS may not be disposed on the cell array region CAR. The dummy vertical channel structure DVS and the vertical channel structure VS may be formed simultaneously with each other and may have substantially the same structure. For example, on the contact region CCR, the dummy vertical channel structure DVS may penetrate the second dielectric layer 170 and the stacked structure ST. Alternatively, the vertical channel structure VS and the dummy vertical channel structure DVS may not be formed simultaneously with each other, or the dummy vertical channel structure DVS may not be disposed.

[0086] The cell contact plugs CCP may be disposed to penetrate the second dielectric layer 170 to be connected to the first gate electrode ELa and the second gate electrode ELb. Each cell contact plug CCP may penetrate one of the first interlayer dielectric layer ILDa and the second interlayer dielectric layer ILDb to contact one of the pad portions ELp of the first gate electrode ELa and the second gate electrode ELb. The cell contact plugs CCP may correspond to Figure 3 and Figure 4 The gate connection line.

[0087] Each cell contact plug CCP may be spaced apart in a horizontal direction, which is a direction on a plane parallel to the first direction D1 and the second direction D2, and electrically separated from the first gate electrode ELa and the second gate electrode ELb under the pad portion ELp across the first dielectric pattern IP1. Each cell contact plug CCP may be spaced apart in a horizontal direction, and electrically separated from the second substrate 100 across the second dielectric pattern IP2. The first dielectric pattern IP1 and the second dielectric pattern IP2 may include the same material as the first interlayer dielectric layer ILDa and the second interlayer dielectric layer ILDb of the stacked structure ST. The bottom surface of each cell contact plug CCP may be located at a level lower than the level of the bottom surface of the second substrate 100. The height of each cell contact plug CCP in the third direction D3 may be substantially the same as the height of the peripheral contact plug TCP in the third direction D3, which will be discussed below.

[0088] The peripheral contact plug TCP may be provided to penetrate the second dielectric layer 170 and at least a portion of the first dielectric layer 30 to be electrically connected to the peripheral circuit transistor PTR of the peripheral circuit structure PS. Alternatively, a plurality of peripheral contact plugs TCP may be provided. The peripheral contact plug TCP may be spaced apart from the second substrate 100, the source structure SC, and the stack structure ST in the first direction D1. The peripheral contact plug TCP may correspond to Figure 3 The through wiring line 3245.

[0089] The cell contact plug CCP and the peripheral contact plug TCP may each include a conductive pattern including at least one metal selected from aluminum, copper, tungsten, molybdenum and cobalt, and may further include a barrier pattern including a metal layer and a metal nitride layer. The metal layer may include at least one selected from titanium, tantalum, tungsten, nickel, cobalt and platinum. The metal nitride layer may include at least one selected from titanium nitride (TiN) layer, tantalum nitride (TaN) layer, tungsten nitride (WN) layer, nickel nitride (NiN) layer, cobalt nitride (CoN) layer and / or platinum nitride (PtN) layer.

[0090] When the stacked structure ST is provided in plurality, the separation structure 150 may be provided in the first trench TR1, and the first trench TR1 extends along the first direction D1 across the plurality of stacked structures ST. The first trench TR1 may extend from the cell array region CAR toward the contact region CCR of the first substrate 10 along the first direction D1. The separation structure 150 may be spaced apart from the vertical channel structure VS in the second direction D2. For example, the top surface of the separation structure 150 may be located at the same level as the top surface of the vertical channel structure VS. The bottom surface of the separation structure 150 may be located at substantially the same level as the bottom surface of the first source conductive pattern SCP1.

[0091] The separation structure 150 may have a seam AR therein. The seam AR may be located at the center of the separation structure 150. The separation structure 150 may be provided in plurality, and the plurality of separation structures 150 may be spaced apart from each other in the second direction D2 across the stacked structure ST. Therefore, the stacked structure ST may be located between the plurality of separation structures 150.

[0092] The interface dielectric layer HP may be disposed between the first gate electrode ELa and the first interlayer dielectric layer ILDa and between the second gate electrode ELb and the second interlayer dielectric layer ILDb. The interface dielectric layer HP may extend between the vertical channel structure VS and the first gate electrode ELa and the second gate electrode ELb. The interface dielectric layer HP may extend between the separation structure 150 and the first interlayer dielectric layer ILDa and the second interlayer dielectric layer ILDb. The interface dielectric layer HP may cover the lower portion of the separation structure 150. For example, the interface dielectric layer HP may include a metal oxide layer, such as an aluminum oxide layer or a hafnium oxide layer.

[0093] The selection mold structure SSLM, the third dielectric layer 260, and the bit line BL may be disposed on the second dielectric layer 170 and the stacked structure ST. The selection mold structure SSLM may include a first capping dielectric layer 210, a second capping dielectric layer 220, a third capping dielectric layer 230, a selection semiconductor layer 240, and a mold dielectric layer 250, which are sequentially stacked. The first capping dielectric layer 210 may cover a top surface of the second dielectric layer 170, a top surface of the uppermost second interlayer dielectric layer among the second interlayer dielectric layers ILDb in the stacked structure ST, and a top surface of the vertical channel structure VS.

[0094] The first capping dielectric layer 210, the second capping dielectric layer 220, the third capping dielectric layer 230, the molded dielectric layer 250, and the third dielectric layer 260 may each include a single dielectric layer or a plurality of stacked dielectric layers. The first capping dielectric layer 210, the third capping dielectric layer 230, the molded dielectric layer 250, and the third dielectric layer 260 may each include substantially the same dielectric material. For example, the first capping dielectric layer 210, the second capping dielectric layer 220, the third capping dielectric layer 230, the molded dielectric layer 250, and the third dielectric layer 260 may each include one or more of silicon oxide, silicon oxynitride, and low-k dielectric materials. The semiconductor layer 240 may include polysilicon.

[0095] On the cell array area CAR, a plurality of upper vertical channel structures UVS may be provided to penetrate the selection molding structure SSLM. The upper vertical channel structure UVS may overlap the vertical channel structure VS vertically (or in the third direction D3). From a plan view, since the upper vertical channel structure UVS is located at a position substantially the same as that of the corresponding vertical channel structure VS, the upper vertical channel structure UVS may be arranged in a zigzag manner along the first direction D1 or the second direction D2. The upper vertical channel structure UVS may be electrically connected to the vertical channel structure VS. The upper vertical channel structure UVS may have a top surface coplanar with the top surface of the molding dielectric layer 250. The upper vertical channel structure UVS may have a bottom surface coplanar with the bottom surface of the first capping dielectric layer 210. For example, each upper vertical channel structure UVS may have a thickness substantially the same as that of the selection molding structure SSLM. The upper vertical channel structure UVS may not be provided on the contact region CCR.

[0096] The separation dielectric pattern 241 may be disposed to penetrate the selection semiconductor layer 240 along the third direction D3 and extend along the first direction D1 across the selection semiconductor layer 240. The separation dielectric pattern 241 may extend along the first direction D1. The upper vertical channel structure UVS may not be disposed on an area where the separation dielectric pattern 241 is disposed. For example, the separation dielectric pattern 241 may be spaced apart from the upper vertical channel structure UVS in the second direction D2. The separation dielectric pattern 241 may have a thickness substantially the same as that of the upper vertical channel structure UVS. The separation dielectric pattern 241 may penetrate the first capping dielectric layer 210, the second capping dielectric layer 220, and the third capping dielectric layer 230 and the molded dielectric layer 250. Alternatively, the thickness of the separation dielectric pattern 241 may be substantially the same as that of the selection semiconductor layer 240. In this case, the separation dielectric pattern 241 may not penetrate any of the first, second, and third capping dielectric layers 210 , 220 , and 230 and the mold dielectric layer 250 , and may penetrate only the selection semiconductor layer 240 .

[0097] Between the two separation structures 150 spaced apart from each other along the second direction D2, the separation dielectric pattern 241 may separate the selection semiconductor layer 240 along the second direction D2. For example, the separation dielectric pattern 241 may be used to separate the string selection line of the three-dimensional NAND flash memory device. The separation dielectric pattern 241 may include a dielectric material, such as one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0098] The stacked structure ST may be disposed on the peripheral circuit structure PS together with an upper separation structure 160, and the upper separation structure 160 penetrates the selection molding structure SSLM. The upper separation structure 160 may overlap the separation structure 150 vertically (e.g., in the third direction D3) while contacting the separation structure 150. From a plan view, the upper separation structure 160 may be disposed at the same position as the separation structure 150. For example, the upper separation structure 160 may extend along the first direction D1. The upper separation structure 160 may penetrate the first capping dielectric layer 210, the second capping dielectric layer 220, and the third capping dielectric layer 230, the selection semiconductor layer 240, and the molding dielectric layer 250 included in the selection molding structure SSLM. The upper separation structure 160 may have a thickness substantially the same as that of the selection molding structure SSLM. The upper separation structure 160 may have a width in the first direction D1 or the second direction D2, and the width of the upper separation structure 160 may increase along the third direction D3. Likewise, the separation dielectric pattern 241 and the upper separation structure 160 may include a dielectric material, such as one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0099] On the contact region CCR, a contact plug CP may be provided to penetrate the selection molding structure SSLM. Each contact plug CP may be electrically connected to a cell contact plug CCP or a peripheral contact plug TCP. Each contact plug CP may be provided on the cell contact plug CCP or the peripheral contact plug TCP and vertically (e.g., in a third direction D3) overlap the cell contact plug CCP or the peripheral contact plug TCP.

[0100] The spacer dielectric layer CPS may be disposed to surround the contact plug CP. The spacer dielectric layer CPS may be located between the selection molding structure SSLM and the sidewall of the contact plug CP. The spacer dielectric layer CPS may electrically insulate the contact plug CP from the selection semiconductor layer 240 .

[0101] On the cell array region CAR, the bit line contact plug BLCP may be provided to penetrate the third dielectric layer 260 to be electrically connected to the upper vertical channel structure UVS. On the contact region CCR, the conductive line contact plug CLCP may be provided to penetrate the third dielectric layer 260 to be electrically connected to the contact plug CP. The bit line contact plug BLCP and the conductive line contact plug CLCP may include a metal material, such as tungsten.

[0102] The bit line BL may be disposed on the third dielectric layer 260 to be connected to the bit line contact plug BLCP. The bit line BL may correspond to Figure 1 The bit line BL and / or Figure 3 and Figure 4 bit line 3240.

[0103] The third dielectric layer 260 may contact the first conductive line CL1 and the second conductive line CL2 connected to the conductive line contact plug CLCP. The first conductive line CL1 may be electrically connected to the cell contact plug CCP through the contact plug CP corresponding to the first conductive line CL1. The second conductive line CL2 may be electrically connected to the peripheral contact plug TCP through the contact plug CP corresponding to the second conductive line CL2. The first conductive line CL1 and the second conductive line CL2 may correspond to Figure 3 and Figure 4 3250 wires.

[0104] FIG. 8A to FIG. 8C Shows Figure 6 An enlarged cross-sectional view of a portion A depicted in FIG. 1 partially illustrates a three-dimensional semiconductor memory device.

[0105] Reference FIG. 8A to FIG. 8C The second vertical channel structure VSb may include a data storage pattern DSP and a vertical semiconductor pattern VSP sequentially disposed on an inner sidewall of the second vertical channel hole CH2, a buried dielectric pattern VI filling an inner space surrounded by the vertical semiconductor pattern VSP, and a conductive pad PAD on the buried dielectric pattern VI.

[0106] The data storage pattern DSP may include a blocking dielectric layer BLK, a charge storage layer CIL, and a tunneling dielectric layer TIL sequentially stacked on the inner sidewall of the second vertical channel hole CH2. The blocking dielectric layer BLK may be adjacent to the second interlayer dielectric layer ILDb, and the tunneling dielectric layer TIL may be adjacent to the vertical semiconductor pattern VSP. The charge storage layer CIL may be located between the blocking dielectric layer BLK and the tunneling dielectric layer TIL. The blocking dielectric layer BLK may cover the inner sidewall of the second vertical channel hole CH2.

[0107] The blocking dielectric layer BLK, the charge storage layer CIL, and the tunnel dielectric layer TIL may extend along the third direction D3 between the second interlayer dielectric layer ILDb and the vertical semiconductor pattern VSP. The data storage pattern DSP may be formed by using Figure 6 The vertical semiconductor pattern VSP and the first and second gate electrodes ELa and ELb may store and / or change data by a Fowler-Nordheim tunneling effect caused by a voltage difference between the vertical semiconductor pattern VSP and the first and second gate electrodes ELa and ELb. For example, the blocking dielectric layer BLK and the tunneling dielectric layer TIL may include silicon oxide, and the charge storage layer CIL may include silicon nitride or silicon oxynitride.

[0108] The conductive pad PAD may be disposed in a space surrounded by the buried dielectric pattern VI and the data storage pattern DSP (or the vertical semiconductor pattern VSP). From a plan view, the top surface VSt of the second vertical channel structure VSb may have a circular shape, an elliptical shape, or a strip shape. The data storage pattern DSP may cover the sidewall of the second interlayer dielectric layer ILDb. The vertical semiconductor pattern VSP may conformally cover the inner sidewall of the data storage pattern DSP.

[0109] The vertical semiconductor pattern VSP may be disposed between the data storage pattern DSP and the buried dielectric pattern VI. The vertical semiconductor pattern VSP may have a tubular shape or a pipe shape with a closed bottom end. The data storage pattern DSP may have a tubular shape or a pipe shape with an open bottom end.

[0110] The vertical semiconductor pattern VSP may include, for example, a semiconductor material doped with impurities, an intrinsic semiconductor material not doped with impurities, or a polycrystalline semiconductor material. The conductive pad PAD may include a semiconductor material doped with impurities or a conductive material.

[0111] The upper vertical channel structure UVS may be disposed on the second vertical channel structure VSb. The upper vertical channel structure UVS may include an upper channel pattern UVP, a selection gate dielectric pattern GIL surrounding the sidewall of the upper channel pattern UVP, and an upper buried dielectric pattern UVI filling the interior of the upper channel pattern UVP. The upper channel pattern UVP of the upper vertical channel structure UVS may contact the conductive pad PAD of the second vertical channel structure VSb. The upper vertical channel structure UVS may also include an upper pad on the upper buried dielectric pattern UVI.

[0112] The upper channel pattern UVP may include a semiconductor material and may be used as Figure 1 The upper channel pattern UVP may have a tubular shape or a pipe shape with a closed bottom. The selection gate dielectric pattern GIL may be formed of a single layer and may include one or more of silicon oxide, silicon oxynitride, and a high-k dielectric material.

[0113] The separation structure 150 may include a first portion P1 and a second portion P2. The first portion P1 may be disposed at Figure 6 The first portion P1 may be located below the second portion P2. For example, the first portion P1 may be located below the second portion P2. Figure 6 between the second portion P2 and the second substrate 100 .

[0114] The second portion P2 may be disposed in the recess RS of the separation structure 150 and may be located between the first portion P1 and the upper separation structure 160. Since the recess RS is located in the second interlayer dielectric layer ILDb, the second portion P2 may be disposed in the uppermost interlayer dielectric layer of the interlayer dielectric layers ILDa and ILDb. The second portion P2 may have a shape that changes according to the shape of the recess RS. Fig. 8A , the bottom of the second portion P2 may have a Figure 6 The second substrate 100 has a convex shape (for example, the second portion P2 faces the Figure 6 The surface of the second substrate 100 is convex). Figure 8B , the second portion P2 may have a bottom surface inclined relative to the third direction D3. For example, the second portion P2 may have a wedge shape. Figure 8C , the bottom surface P2b of the second portion P2 may be parallel to the top surface P2t of the second portion P2. The bottom surface P2b of the second portion P2 may be parallel to the first direction D1 and the second direction D2.

[0115] The top surface P2t of the second portion P2 may be located at a level substantially the same as that of the top surface VSt of the second vertical channel structure VSb. The top surface P2t of the second portion P2 may be located at a level substantially the same as that of the top surface ILDt of the second interlayer dielectric layer ILDb. In the present description, the top surface P2t of the second portion P2 may be the same as the top surface of the separation structure 150, and the top surface VSt of the second vertical channel structure VSb may be the same as that of the second interlayer dielectric layer ILDb. Figure 6 The top surface of the vertical channel structure VS depicted is the same, and the top surface ILDt of the second interlayer dielectric layer ILDb may be the same as Figure 6 The top surface of the stacked structure ST depicted is the same as the top surface of the uppermost interlayer dielectric layer of the interlayer dielectric layers ILDa and ILDb. For example, the top surface of the separation structure 150 may be located at a position similar to that of the uppermost interlayer dielectric layer of the interlayer dielectric layers ILDa and ILDb. Figure 6 The level of the top surface of the depicted vertical channel structure VS and Figure 6 The top surface level of the uppermost interlayer dielectric layer among the depicted interlayer dielectric layers ILDa and ILDb is at substantially the same level.

[0116] The separation structure 150 may have a first width W1 at a level lower than the level of the top surface P2t of the second portion P2. The separation structure 150 may have a second width W2 on the top surface P2t of the second portion P2. The first width W1 may be greater than the second width W2. The first width W1 may be the maximum width of the separation structure 150. For example, the width of the separation structure 150 may not have a maximum value at the top surface of the separation structure 150. The separation structure 150 may have a high aspect ratio to cause a bending phenomenon. Therefore, the first portion P1 may have a seam AR therein. The seam AR may be located at the center of the first portion P1 in the second direction D2. Since the second portion P2 is formed in the recess RS after the first portion P1 is formed, the second portion P2 may cover the seam AR of the first portion P1. The second portion P2 may contact the seam AR of the first portion P1.

[0117] The first portion P1 and the second portion P2 of the separation structure 150 may include a dielectric material. For example, the dielectric material may include one or more of silicon oxide, silicon nitride, and silicon oxynitride. The first portion P1 and the second portion P2 may include dielectric materials different from each other. For example, the first portion P1 may include silicon nitride, and the second portion P2 may include silicon oxide.

[0118] The interface dielectric layer HP may be located between the separation structure 150 and the second interlayer dielectric layer ILDb. The interface dielectric layer HP may contact the first portion P1 and the second portion P2 of the separation structure 150. The interface dielectric layer HP may cover the inner wall of the first trench TR1 while having a constant thickness in the second direction D2.

[0119] An etching process may be performed to form the recess RS of the separation structure 150. For example, the etching process may be a wet etching process without using fluorine. Figure 6 The first gate electrode ELa and the second gate electrode ELb of the depicted stacked structure ST are fluorine-degraded by the separation structure 150. In addition, since the first capping dielectric layer 210 on the separation structure 150 includes silicon oxide, and since the second portion P2 in contact with the upper separation structure 160 includes silicon oxide, subsequent processes may not be changed. In summary, the three-dimensional semiconductor memory device may improve reliability and electrical performance without changing subsequent processes.

[0120] Fig. 9 Shows Figure 6 An enlarged cross-sectional view of portion B is depicted, partially illustrating a three-dimensional semiconductor memory device.

[0121] Reference Fig. 9 , each of the first vertical channel structures VSa may include a data storage pattern DSP, a vertical semiconductor pattern VSP, and a buried dielectric pattern VI.

[0122] The data storage pattern DSP may include a blocking dielectric layer BLK, a charge storage layer CIL, and a tunneling dielectric layer TIL stacked in sequence. The blocking dielectric layer BLK may be adjacent to the first interlayer dielectric layer ILDa, and the tunneling dielectric layer TIL may be adjacent to the vertical semiconductor pattern VSP. The charge storage layer CIL may be located between the blocking dielectric layer BLK and the tunneling dielectric layer TIL. The blocking dielectric layer BLK may cover the inner sidewall of the first vertical channel hole CH1.

[0123] The first vertical channel structure VSa may have FIG. 8A to FIG. 8C The structure of the second vertical channel structure VSb discussed in is basically the same structure.

[0124] The first source conductive pattern SCP1 of the source structure SC may be in contact with the vertical semiconductor pattern VSP, and the second source conductive pattern SCP2 of the source structure SC may be spaced apart from the vertical semiconductor pattern VSP across the data storage pattern DSP. The first source conductive pattern SCP1 may be spaced apart from the buried dielectric pattern VI across the vertical semiconductor pattern VSP. The first source conductive pattern SCP1 may include a protrusion located at a level higher than that of the bottom surface of the second source conductive pattern SCP2 and a protrusion located at a level lower than that of the bottom surface of the first source conductive pattern SCP1. The protrusion of the first source conductive pattern SCP1 may be located at a level lower than that of the top surface of the second source conductive pattern SCP2. For example, the protrusion may have a curved shape at a surface in contact with the data storage pattern DSP.

[0125] FIG. 10A to FIG. 13C Plan views and cross-sectional views illustrating an example of a method of manufacturing a three-dimensional semiconductor memory device are shown. Fig. 10A , Fig.11A , Fig. 12A and Fig.13A A plan view showing a three-dimensional semiconductor memory device is shown. Fig. 10B Shown along Fig. 10A A cross-sectional view taken along line II'. Fig. 11B Shown along Fig.11A A cross-sectional view taken along line II'. Fig. 12B , Fig. 12C and Fig.12D Shown along Fig. 12A A cross-sectional view taken along line II'. Fig. 13B and Fig. 13C Shown along Fig.13A A cross-sectional view taken along line II'.

[0126] Reference Fig. 10A and Fig. 10B , a first substrate 10 including a cell array region CAR and a contact region CCR may be provided. A device isolation layer 11 defining an active portion may be formed in the first substrate 10. The device isolation layer 11 may be formed by forming a trench on an upper portion of the first substrate 10 and filling the trench with silicon oxide.

[0127] A peripheral circuit transistor PTR may be formed on an active portion defined by the device isolation layer 11. A peripheral contact plug 31 and a peripheral circuit line 33 may be formed and connected to the peripheral circuit transistor PTR. A first dielectric layer 30 may be formed to cover the peripheral circuit transistor PTR, the peripheral contact plug 31, and the peripheral circuit line 33.

[0128] The second substrate 100 may be formed on the first dielectric layer 30. The second substrate 100 may extend from the cell array region CAR toward the contact region CCR.

[0129] A lower sacrificial layer 117 and a semiconductor layer 121 may be formed on the second substrate 100. A mold structure MS may be formed on the semiconductor layer 121. Forming the mold structure MS may include: forming a first mold structure MS1 by alternately stacking first interlayer dielectric layers ILDa and first sacrificial layers SLa on the second substrate 100; and forming a second mold structure MS2 by alternately stacking second interlayer dielectric layers ILDb and second sacrificial layers SLb on the first mold structure MS1.

[0130] The first sacrificial layer SLa and the second sacrificial layer SLb may be formed of a dielectric material different from the dielectric material of the first interlayer dielectric layer ILDa and the second interlayer dielectric layer ILDb. The first sacrificial layer SLa and the second sacrificial layer SLb may be formed of a material having an etching selectivity relative to the first interlayer dielectric layer ILDa and the second interlayer dielectric layer ILDb. For example, the first sacrificial layer SLa and the second sacrificial layer SLb may be formed of silicon nitride, and the first interlayer dielectric layer ILDa and the second interlayer dielectric layer ILDb may be formed of silicon oxide. The first sacrificial layer SLa and the second sacrificial layer SLb may be formed to have substantially the same thickness. The first interlayer dielectric layer ILDa and the second interlayer dielectric layer ILDb may have a thickness that varies over a specific area.

[0131] A trimming process may be performed on the mold structure MS on the contact region CCR. The trimming process may include: forming a mask pattern partially covering the top surface of the mold structure MS on the cell array region CAR and the contact region CCR; patterning the mold structure MS using the mask pattern; reducing the area of ​​the mask pattern; and patterning the mold structure MS using the reduced mask pattern. Reducing the area of ​​the mask pattern and patterning the mold structure MS using the reduced mask pattern may be performed alternately and repeatedly. The trimming process may cause the mold structure MS to have a step structure on the contact region CCR.

[0132] The vertical channel hole CH may be formed to penetrate the mold structure MS, and the first vertical channel structures VSa and VSb may be formed to fill the vertical channel hole CH. On the cell array region CAR, the vertical channel hole CH may penetrate the mold structure MS, the semiconductor layer 121, and the lower sacrificial layer 117. The vertical channel hole CH may penetrate at least a portion of the second substrate 100, and bottom surfaces of the vertical channel holes CH may each be at a level lower than that of the top surface of the second substrate 100.

[0133] Forming the first vertical channel structure VSa and the second vertical channel structure VSb may include forming a data storage pattern conformally covering an inner sidewall of each vertical channel hole CH (refer to FIG. 8A to FIG. 8C DSP); forming a vertical semiconductor pattern conformally covering the sidewall of the data storage pattern DSP (refer to FIG. 8A to FIG. 8C forming a buried dielectric pattern filling at least a portion of the space surrounded by the vertical semiconductor pattern VSP (refer to FIG. 8A to FIG. 8C and forming a conductive pad (reference to the space surrounded by the vertical semiconductor pattern VSP and the buried dielectric pattern VI) to fill the space; FIG. 8A to FIG. 8C of PAD).

[0134] Reference Fig.11A and Fig. 11B, a plurality of first trenches TR1 may be formed to penetrate the mold structure MS, the semiconductor layer 121, and the lower sacrificial layer 117. The first trenches TR1 may be formed by an anisotropic etching process. The first trenches TR1 may extend along the first direction D1 and may be spaced apart from each other in the second direction D2. The first trenches TR1 may expose a portion of the top surface of the second substrate 100 to the outside. The first trenches TR1 may penetrate at least a portion of the second substrate 100. For example, the first trenches TR1 may each have a bottom surface located at a level lower than that of the top surface of the second substrate 100, but the present disclosure is not limited thereto.

[0135] The sacrificial pattern 150a may be formed to fill the first trench TR1. The sacrificial pattern 150a may include a material having an etch selectivity with respect to the first and second interlayer dielectric layers ILDa and ILDb and the first and second sacrificial layers SLa and SLb. The sacrificial pattern 150a may include, for example, polysilicon.

[0136] Although not shown, before forming the sacrificial pattern 150 a , a spacer may be formed to cover the sidewalls of the first trench TR1 and expose the bottom surface of the first trench TR1 .

[0137] Reference Fig. 12A and Fig. 12B , an upper support layer TS may be formed to cover the mold structure MS and the vertical channel structure VS. The upper support layer TS may contact the uppermost interlayer dielectric layer of the first interlayer dielectric layer ILDa and the second interlayer dielectric layer ILDb. The upper support layer TS may be formed by chemical vapor deposition (CVD) and / or atomic layer deposition (ALD). For example, the upper support layer TS may include at least one selected from silicon oxide, silicon oxynitride, and silicon carbonitride.

[0138] An opening OP penetrating the support layer TS along the third direction D3 may be formed. The opening OP may be formed by an anisotropic etching process, such as plasma etching or reactive ion etching. The opening OP may extend along the first direction D1 and may be spaced apart from each other in the first direction D1 and the second direction D2. The opening OP may overlap the first trench TR1 vertically (e.g., in the third direction D3). The upper support layer TS may include a bridge BG between the openings OP adjacent to each other in the first direction D1.

[0139] The sacrificial pattern 150a may be removed through the opening OP. Thus, the first trench TR1 may be exposed to the outside again. The bridge portion BG of the upper support layer TS may support the mold structure MS on the first trench TR1 which becomes an empty space due to the removal of the sacrificial pattern 150a. The selective removal of the sacrificial pattern 150a may be achieved by performing an etching process using hydrofluoric acid as an etchant.

[0140] The first source conductive pattern SCP1 may replace the lower sacrificial layer 117 whose side surface is exposed by the first trench TR1. For example, the lower sacrificial layer 117 may be selectively removed through the first trench TR1. Removing the lower sacrificial layer 117 may expose the lower portion of the vertical channel structure VS to the outside. Fig. 9 As shown, a portion of the data storage pattern DSP of the vertical channel structure VS may also be removed. The first source conductive pattern SCP1 may be formed in the space where the lower sacrificial layer 117 is removed. The semiconductor layer 121 may be referred to as a second source conductive pattern SCP2. Therefore, the source structure SC including the first source conductive pattern SCP1 and the second source conductive pattern SCP2 may also be removed.

[0141] The first sacrificial layer SLa and the second sacrificial layer SLb exposed by the first trench TR1 may be selectively removed. The removal of the first sacrificial layer SLa and the second sacrificial layer SLb may be achieved by performing a wet etching process using an etching solution having etching selectivity.

[0142] Selectively removing the first sacrificial layer SLa and the second sacrificial layer SLb may bring structural weaknesses to the first mold structure MS1 and the second mold structure MS2 spaced apart from each other across the first trench TR1. Therefore, the first mold structure MS1 and the second mold structure MS2 may collapse or tilt. Since the bridge portion BG of the upper support layer TS supports the first mold structure MS1 and the second mold structure MS2 on the first trench TR1, the first mold structure MS1 and the second mold structure MS2 can be supported during the formation of the first gate electrode ELa and the second gate electrode ELb, which will be discussed below.

[0143] Reference Fig. 12A and Fig. 12C , an interface dielectric layer HP may be formed to cover the surfaces of the first interlayer dielectric layer ILDa and the second interlayer dielectric layer ILDb. The interface dielectric layer HP may extend toward the space where the first sacrificial layer SLa and the second sacrificial layer SLb are removed, and thus may cover portions of the side surfaces of the first vertical channel structure VSa and the second vertical channel structure VSb.

[0144] The first and second gate electrodes ELa and ELb may be formed to fill spaces where the first and second sacrificial layers SLa and SLb are removed. In summary, the stacked structure ST may be formed to include the first and second gate electrodes ELa and ELb and the first and second interlayer dielectric layers ILDa and ILDb.

[0145] A first preliminary dielectric pattern P1a may be formed in the first trench TR1. The first preliminary dielectric pattern P1a may cover a top surface of the upper supporting layer TS while filling the first trench TR1. The first preliminary dielectric pattern P1a may cover a side surface of the upper supporting layer TS exposed by the opening OP.

[0146] The first preliminary dielectric pattern P1a may be formed by, for example, chemical vapor deposition (CVD) and / or atomic layer deposition (ALD). Due to the high aspect ratio of the first trench TR1, a seam AR may be formed in the first preliminary dielectric pattern P1a. The first preliminary dielectric pattern P1a may include, for example, silicon nitride.

[0147] Reference Fig. 12A and Fig.12D , a first planarization process may be performed on the first preliminary dielectric pattern P1a and the upper supporting layer TS. The first planarization process may remove a portion of the upper supporting layer TS and the first preliminary dielectric pattern P1a. The first planarization process may expose the top surface of the uppermost interlayer dielectric layer of the interlayer dielectric layers ILDa and ILDb and the top surface of the vertical channel structure VS to the outside. Therefore, the first preliminary dielectric pattern P1a may have a top surface located at a level substantially the same as the level of the top surface of the uppermost interlayer dielectric layer of the interlayer dielectric layers ILDa and ILDb and the top surface of the vertical channel structure VS. In this case, the seam AR may not be exposed to the outside. The first planarization process may include, for example, a chemical mechanical polishing (CMP) process or an etch-back process.

[0148] A portion of the first preliminary dielectric pattern P1a may also be removed. Thus, the first portion P1 may be formed by the first preliminary dielectric pattern P1a. An etching process may be performed to remove a portion of the first preliminary dielectric pattern P1a. The etching process may be, for example, a wet etching process using a highly selective nitride etchant (HSN). The HSN may not include fluorine and may selectively remove only silicon nitride. Thus, the uppermost interlayer dielectric layer of the interlayer dielectric layers ILDa and ILDb may remain in place. A portion of the first preliminary dielectric pattern P1a may be removed to form a recess RS. In this case, the recess RS may expose the seam AR to the outside.

[0149] Since fluorine is not used in the etching process of removing a portion of the first preliminary dielectric pattern P1a to form the first portion P1, degradation of the first and second gate electrodes ELa and ELb due to fluorine can be prevented. In conclusion, the three-dimensional semiconductor memory device can improve reliability and electrical performance.

[0150] Reference Fig.13A and Fig. 13B, a second preliminary dielectric pattern P2a may be formed to fill the recess RS. The second preliminary dielectric pattern P2a may cover the top surface of the uppermost interlayer dielectric layer of the interlayer dielectric layers ILDa and ILDb and the top surface of the vertical channel structure VS. When the second preliminary dielectric pattern P2a fills the recess RS, the second preliminary dielectric pattern P2a may contact the first portion P1 and the seam AR. Therefore, the seam AR may be isolated from external contact.

[0151] The second preliminary dielectric pattern P2a may be formed by chemical vapor deposition (CVD) and / or atomic layer deposition (ALD).The second preliminary dielectric pattern P2a may include a dielectric material different from the dielectric material of the first portion P1, such as silicon oxide.

[0152] Reference Fig.13A and Fig. 13C , a second planarization process may be performed on the second preliminary dielectric pattern P2a. The second planarization process may remove a portion of the second preliminary dielectric pattern P2a. A portion of the second preliminary dielectric pattern P2a may be removed from the second preliminary dielectric pattern P2a to form a second portion P2. The second planarization process may include, for example, a chemical mechanical polishing (CMP) process or an etch-back process.

[0153] The second planarization process may expose the top surface ILDt of the uppermost interlayer dielectric layer of the interlayer dielectric layers ILDa and ILDb and the top surface VSt of the vertical channel structure VS to the outside. Therefore, the second preliminary dielectric pattern P2a may have a top surface P2t located at a level substantially the same as that of the top surface ILDt of the uppermost interlayer dielectric layer of the interlayer dielectric layers ILDa and ILDb and the top surface VSt of the vertical channel structure VS.

[0154] Since the second portion P2 includes silicon oxide, a common manufacturing method can be used to form a selective molding structure SSLM, which will be discussed below. After forming the second portion P2, subsequent processes may not change. As a result, a three-dimensional semiconductor memory device can be easily manufactured.

[0155] Return to reference Figures 5 to 7 A selective molding structure SSLM may be provided on the stack structure ST, the selective molding structure SSLM including a first capping dielectric layer 210, a second capping dielectric layer 220, a third capping dielectric layer 230, a selective semiconductor layer 240 and a molding dielectric layer 250 formed sequentially.

[0156] The separation dielectric pattern 241 and the upper separation structure 160 may be formed to penetrate the selective molding structure SSLM. From a plan view, the separation dielectric pattern 241 and the upper separation structure 160 may extend along the first direction D1 and may be spaced apart from each other in the second direction D2. The separation dielectric pattern 241 may be located between the upper separation structures 160. The separation dielectric pattern 241 and the upper separation structure 160 may include the same dielectric material. The separation dielectric pattern 241 and the upper separation structure 160 may be formed simultaneously with each other, but the present disclosure is not limited thereto.

[0157] On the cell array region CAR, an upper vertical channel structure UVS may be formed to penetrate the selection mold structure SSLM. The formation of the upper vertical channel structure UVS may be substantially the same as the formation of the vertical channel structure VS discussed above.

[0158] On the contact region CCR, a contact plug CP may be formed to penetrate the selection molding structure SSLM. The contact plug CP may be electrically connected to the cell contact plug CCP or the peripheral contact plug TCP. A third dielectric layer 260 may be formed to cover the molding dielectric layer 250, the upper vertical channel structure UVS, the separation dielectric pattern 241, the upper separation structure 160, and the contact plug CP.

[0159] On the cell array region CAR, a bit line contact plug BLCP may be formed to penetrate the third dielectric layer 260 to be connected to the upper vertical channel structure UVS. On the contact region CCR, a conductive line contact plug CLCP may be formed to penetrate the third dielectric layer 260 to be connected to the contact plug CP. A bit line BL and a first conductive line CL1 and a second conductive line CL2 may be provided on the third dielectric layer 260, the bit line BL is formed to be connected to the bit line contact plug BLCP, and the first conductive line CL1 and the second conductive line CL2 are formed to be connected to the conductive line contact plug CLCP.

[0160] In a three-dimensional semiconductor memory device, a stacked structure having a separation structure therebetween may be provided, the separation structure including a first portion and a second portion. The second portion may be located on the first portion and may include a dielectric material different from that of the first portion.

[0161] For example, since the first portion includes silicon nitride, fluorine may not be used to remove a portion of the first portion. Therefore, the gate electrode of the stacked structure may be prevented from being degraded due to fluorine. In addition, since the second portion includes silicon oxide, subsequent processes after forming the separation structure may not change. In summary, the three-dimensional semiconductor memory device may improve reliability and electrical performance.

[0162] Although the present disclosure includes many specific implementation details, these should not be interpreted as limiting the scope of possible protection. In a single embodiment, the specific features described in the context of independent embodiments in the present disclosure can also be combined to achieve. On the contrary, the different features described in the context of a single implementation can also be implemented separately in multiple implementations, or implemented in appropriate sub-combinations. In addition, although the features may be described above as working in certain combinations and even initially claimed as such, one or more features from the combination can be deleted from the combination in some cases, and the combination can be for sub-combinations or variants of sub-combinations.

[0163] Although the present disclosure has been described in conjunction with the embodiments of the inventive concept shown in the accompanying drawings, it should be understood by those skilled in the art that various changes and modifications may be made without departing from the technical spirit and basic features of the inventive concept. Therefore, it should be understood that the above embodiments are merely illustrative and not restrictive in all aspects.

Claims

1. A three-dimensional semiconductor memory device, include: A plurality of stacked structures, including a plurality of interlayer dielectric layers and a plurality of gate electrodes alternately stacked on a substrate; A plurality of vertical channel structures penetrating the plurality of stacked structures; as well as a separation structure extending along a first direction across adjacent stacking structures among the plurality of stacking structures, Wherein, the separation structure comprises: A first portion extending from the substrate in a vertical direction; and a second portion on the first portion, the second portion comprising a material different from the material of the first portion, and The level of the top surface of the second portion is the same as the level of the top surfaces of the plurality of vertical channel structures.

2. The three-dimensional semiconductor memory device according to claim 1, in, The separation structure is spaced apart from the plurality of vertical channel structures in a second direction, the second direction crossing the first direction.

3. The three-dimensional semiconductor memory device according to claim 2, in, The first portion is in contact with the gate electrodes adjacent to each other in the second direction.

4. The three-dimensional semiconductor memory device according to claim 1, in, The first portion has a seam therein, and wherein the seam is in contact with the second portion.

5. The three-dimensional semiconductor memory device according to claim 1, in, The first portion comprises silicon nitride, and wherein the second portion comprises silicon oxide.

6. The three-dimensional semiconductor memory device according to claim 1, in, The second portion has a shape that is convex toward the substrate.

7. The three-dimensional semiconductor memory device according to claim 1, in, The bottom surface of the second portion is parallel to the top surface of the second portion.

8. The three-dimensional semiconductor memory device according to claim 1, further comprising an interface dielectric layer between the plurality of vertical channel structures and the gate electrode, in, The interface dielectric layer extends between the interlayer dielectric layer and the separation structure.

9. The three-dimensional semiconductor memory device according to claim 1, in, The separation structure has a maximum width at a level below the top surface of the second portion.

10. The three-dimensional semiconductor memory device according to claim 1, in, The second portion is in an uppermost interlayer dielectric layer among the interlayer dielectric layers.

11. The three-dimensional semiconductor memory device according to claim 1, further comprising: include: a selective molding structure on the plurality of stacked structures, the selective molding structure comprising a selective semiconductor layer; as well as An upper separation structure penetrates the selection molding structure and contacts the second portion.

12. The three-dimensional semiconductor memory device according to claim 11, in, The first portion is spaced apart from the selection molding structure in the vertical direction.

13. A three-dimensional semiconductor memory device, include: A substrate including a cell array region and a contact region adjacent to the cell array region in a first direction; a peripheral circuit structure on the substrate, the peripheral circuit structure comprising a plurality of peripheral circuit transistors; A source structure on the peripheral circuit structure; A plurality of stacked structures, including a plurality of interlayer dielectric layers and a plurality of gate electrodes alternately stacked on the source structure; a plurality of vertical channel structures penetrating the plurality of stacked structures and connected to the source structure; A separation structure extending along the first direction across adjacent stacking structures among the plurality of stacking structures; a selective molding structure on the plurality of stacked structures, the selective molding structure comprising a selective semiconductor layer; an upper separation structure penetrating the selection molding structure and contacting the separation structure; a plurality of upper vertical channel structures penetrating the selection molding structure and correspondingly connected to the plurality of vertical channel structures; as well as a separation dielectric pattern in the selection molding structure, the separation dielectric pattern penetrating the selection semiconductor layer, Wherein, the separation structure comprises: A first portion on the source structure; and A second portion is between the first portion and the selection molding structure, and wherein a top surface of the second portion is at the same level as a level of top surfaces of the plurality of vertical channel structures.

14. The three-dimensional semiconductor memory device according to claim 13, in, The first portion and the second portion include different materials from each other.

15. The three-dimensional semiconductor memory device according to claim 13, in, The second portion has a shape that protrudes toward the source structure.

16. The three-dimensional semiconductor memory device according to claim 13, further comprising: include: A planarized dielectric layer covering the plurality of stacked structures; as well as A plurality of cell contact plugs are formed on the contact region, wherein the cell contact plugs penetrate the planarization dielectric layer and contact the gate electrodes correspondingly.

17. The three-dimensional semiconductor memory device according to claim 16, in, The cell contact plug is electrically connected to the peripheral circuit transistor of the peripheral circuit structure.

18. An electronic system, include: A three-dimensional semiconductor memory device, comprising: a substrate; a plurality of stacked structures, comprising a plurality of interlayer dielectric layers and a plurality of gate electrodes alternately stacked on the substrate; a plurality of vertical channel structures penetrating the plurality of stacked structures; a separation structure between adjacent stacked structures in the plurality of stacked structures; and input / output pads on the plurality of stacked structures; and a controller electrically connected to the three-dimensional semiconductor memory device through the input / output pad and controlling the three-dimensional semiconductor memory device, Wherein, the separation structure comprises: a first portion extending vertically from the substrate, and a second portion on the first portion, the second portion comprising a material different from that of the first portion, Wherein, a level of a top surface of the separation structure is the same as a level of top surfaces of the plurality of stacked structures.

19. The electronic system according to claim 18, in, The first portion includes silicon nitride, and wherein the second portion includes silicon oxide and has a shape protruding toward the substrate. 20 . The electronic system of claim 18 , further comprising a selective molding structure on the plurality of stacked structures, the selective molding structure comprising a selective semiconductor layer.

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