Superconducting quantum chip, quantum computer and manufacturing method

Abstract

The invention provides a superconducting quantum chip, a quantum computer and a manufacturing method of the superconducting quantum chip, the superconducting quantum chip comprises a chip module and a first heat dissipation layer, the chip module comprises a core particle layer and a substrate, and the substrate is connected with the core particle layer through salient points; the core particle layer is connected with the first heat dissipation layer through a first bonding layer. According to the superconducting quantum chip, the quantum computer and the manufacturing method of the superconducting quantum chip provided by the embodiment of the invention, the first heat dissipation layer is arranged on the core particle layer, so that the effective heat exchange area is increased, and the heat dissipation efficiency of the superconducting quantum chip is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a superconducting quantum chip, a quantum computer and a method for manufacturing the superconducting quantum chip. Background Art

[0002] At present, quantum computing solutions with high cryogenic requirements include: superconducting, topological, semiconductor quantum computing, etc. Taking superconducting quantum computing as an example, the energy level difference between the quantum bit from the ground state to the first excited state is very small. In order to maintain the stability of the quantum state, the noise fluctuation amplitude in the environment needs to be much lower than the energy level difference, which requires the superconducting quantum chip to serve in an extremely low temperature environment at the mK level.

[0003] For the above quantum computing scheme, the operation of quantum computers needs to be carried out in an extremely low temperature environment, and a dilution refrigerator is usually used to achieve low temperature conditions. The cooling process of the dilution refrigerator is very slow and often takes several days. The Joule heat continuously generated by some electrical structures that have not entered the superconducting state or have no superconducting properties will further prolong the cooling time and affect the stability of the electrical structures that have entered the superconducting state. Therefore, quickly dissipating the heat of the superconducting quantum chip in the quantum computer is not only beneficial for the dilution refrigerator to reach the mK operating temperature faster, but also conducive to the stable and reliable operation of the quantum computer.

[0004] Therefore, for superconducting quantum chips, especially complex quantum chips with three-dimensional integrated architecture, how to solve their heat dissipation problem has become an important issue that needs to be urgently addressed in this field. Summary of the invention

[0005] In view of the problems in the prior art, the embodiments of the present invention provide a superconducting quantum chip, a quantum computer and a method for manufacturing a superconducting quantum chip, which can at least partially solve the problems in the prior art.

[0006] In a first aspect, the present invention provides a superconducting quantum chip, comprising a chip module and a first heat dissipation layer, wherein:

[0007] The chip module comprises a core particle layer and a substrate, wherein the substrate is connected to the core particle layer via bumps;

[0008] The core particle layer is connected to the first heat dissipation layer via a first bonding layer.

[0009] Furthermore, the superconducting quantum chip provided by the embodiment of the present invention further includes a crystal back layer, the crystal back layer is connected to the substrate, and the thermal expansion coefficient of the substrate is greater than the thermal expansion coefficient of the crystal back layer and the thermal expansion coefficient of the first heat dissipation layer.

[0010] Furthermore, the superconducting quantum chip provided in the embodiment of the present invention further includes a second heat dissipation layer, and the second heat dissipation layer is connected to the crystal back layer through a second bonding layer.

[0011] Furthermore, the superconducting quantum chip provided in the embodiment of the present invention further includes a base, and the base is connected to the second heat dissipation layer.

[0012] Furthermore, a second transition layer is provided between the base and the second heat dissipation layer.

[0013] Furthermore, the base at least wraps a portion of the structure from the substrate to the base.

[0014] Furthermore, a thermoelectric zone is arranged between the base and the wrapped structure.

[0015] Furthermore, the crystal back layer includes an optical waveguide area, which is connected to an off-chip optical fiber through a first coupler. A photonic integrated chip bridge structure is arranged on the substrate, and the photonic integrated chip bridge structure is connected to corresponding bumps. A second coupler corresponding to the photonic integrated chip bridge structure is arranged in the optical waveguide area, and the second coupler is used to realize optical signal transmission between the photonic integrated chip bridge structure and the optical waveguide area.

[0016] Furthermore, the superconducting quantum chip provided in the embodiment of the present invention further includes a first transition layer, and the first transition layer is connected to the first heat dissipation layer.

[0017] Furthermore, the core particle layer is provided with a plurality of heat dissipation parts, each heat dissipation part is in contact with the first bonding layer, and the heat dissipation part is filled with a thermal conductive material.

[0018] Furthermore, an electrical interconnection line is arranged on the substrate, a first end of the electrical interconnection line is connected to the bump, and a second end of the electrical interconnection line is connected to the coaxial line through a lead wire.

[0019] In a second aspect, the present invention provides a quantum computer, comprising the superconducting quantum chip and a dilution refrigerator according to any one of the above embodiments, wherein the dilution refrigerator comprises a first cold plate and a second cold plate, and the superconducting quantum chip is arranged between the first cold plate and the second cold plate and contacts the first cold plate and the second cold plate respectively.

[0020] In a third aspect, the present invention provides a method for manufacturing a superconducting quantum chip, comprising:

[0021] Making each core particle;

[0022] Based on each core particle and the first heat dissipation layer, a first component is obtained; the first component includes the first heat dissipation layer and the core particle layer composed of each core particle;

[0023] Based on the substrate material, a second component is obtained; the second component includes a substrate;

[0024] Producing bumps on each core particle of the core particle layer, and producing bumps on the substrate corresponding to the bumps of each core particle;

[0025] Based on the bumps on each core particle of the core particle layer and the bumps on the substrate, the first component and the second component are integrated to obtain the superconducting quantum chip.

[0026] Further, the manufacturing of each core particle includes:

[0027] A hole is punched at a preset position on a side of the core particle opposite to the first heat dissipation layer and filled with a heat conductive material to form a heat dissipation portion.

[0028] Further, obtaining the first component based on each core particle and the first heat dissipation layer material includes:

[0029] sputtering metal nanoparticles on one side surface of the first heat dissipation layer, and sputtering metal nanoparticles on one side surface of each core particle;

[0030] The surface of the first heat dissipation layer having metal nanoparticles is bonded to the surface of each core particle having metal nanoparticles at a preset temperature to obtain the first component.

[0031] Furthermore, the method for manufacturing a superconducting quantum chip provided by an embodiment of the present invention further includes:

[0032] A first transition layer is manufactured on the first heat dissipation layer.

[0033] Furthermore, the second component further includes a back layer; accordingly, obtaining the second component based on the substrate material includes:

[0034] Based on the substrate material, manufacturing a substrate;

[0035] A crystal back layer is manufactured on the substrate; wherein the thermal expansion coefficient of the substrate is greater than the thermal expansion coefficient of the crystal back layer and the thermal expansion coefficient of the first heat dissipation layer.

[0036] Furthermore, the second component further includes a second heat dissipation layer; accordingly, based on the substrate material, obtaining the second component further includes:

[0037] sputtering metal nanoparticles on the surface of the non-functional area of ​​the crystal back layer, and sputtering metal nanoparticles on the surface of a corresponding area on one side of the second heat dissipation layer;

[0038] The surface of the second heat dissipation layer having metal nanoparticles is bonded to the surface of the non-functional region of the crystal back layer having metal nanoparticles.

[0039] Furthermore, the method for manufacturing a superconducting quantum chip provided by an embodiment of the present invention further includes:

[0040] A second transition layer is formed on the surface of the second heat dissipation layer.

[0041] Further, the step of manufacturing a back-end layer on the substrate includes:

[0042] An optical waveguide region is fabricated on the crystal back layer.

[0043] Furthermore, the method for manufacturing a superconducting quantum chip provided by an embodiment of the present invention further includes:

[0044] The whole structure including the first component and the second component is arranged on a base.

[0045] A superconducting quantum chip, a quantum computer and a method for manufacturing a superconducting quantum chip provided by an embodiment of the present invention include a chip module and a first heat dissipation layer. The chip module includes a core particle layer and a substrate. The substrate is connected to the core particle layer through bumps; the core particle layer and the first heat dissipation layer are connected through a first bonding layer. Since the first heat dissipation layer is provided on the core particle layer, the effective heat exchange area is increased, thereby improving the heat dissipation efficiency of the superconducting quantum chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the prior art descriptions. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0047] Figure 1 It is a schematic diagram of the structure of a superconducting quantum chip provided by the first embodiment of the present invention.

[0048] Figure 2 Schematic diagram of the structure of a superconducting quantum chip provided by the second embodiment of the present invention.

[0049] Figure 3 Schematic diagram of the structure of a superconducting quantum chip provided in the third embodiment of the present invention.

[0050] Figure 4 Schematic diagram of the structure of a superconducting quantum chip provided by the fourth embodiment of the present invention.

[0051] Figure 5 Schematic diagram of the structure of a superconducting quantum chip provided by the fifth embodiment of the present invention.

[0052] Figure 6Schematic diagram of the structure of a superconducting quantum chip provided by the sixth embodiment of the present invention.

[0053] Figure 7 Schematic diagram of the structure of a superconducting quantum chip provided by the seventh embodiment of the present invention.

[0054] Figure 8 Schematic diagram of the structure of a superconducting quantum chip provided by the eighth embodiment of the present invention.

[0055] Fig. 9 Schematic diagram of the structure of a superconducting quantum chip provided by the ninth embodiment of the present invention.

[0056] Fig.10 Schematic diagram of the structure of a superconducting quantum chip provided by the tenth embodiment of the present invention.

[0057] Fig.11 It is a schematic diagram of the structure of a superconducting quantum chip provided by the eleventh embodiment of the present invention.

[0058] Fig.12 It is a schematic diagram of the structure of a quantum computer provided by the twelfth embodiment of the present invention.

[0059] Fig.13 It is a schematic diagram of the structure of a quantum computer provided by the thirteenth embodiment of the present invention.

[0060] Fig.14 It is a schematic flow chart of a method for manufacturing a superconducting quantum chip provided in the fourteenth embodiment of the present invention.

[0061] Fig.15 It is a schematic flow chart of a method for manufacturing a superconducting quantum chip provided in the fifteenth embodiment of the present invention.

[0062] Fig.16 It is a schematic flow chart of a method for manufacturing a superconducting quantum chip provided in the sixteenth embodiment of the present invention.

[0063] Fig.17 It is a schematic flow chart of a method for manufacturing a superconducting quantum chip provided in the seventeenth embodiment of the present invention. DETAILED DESCRIPTION

[0064] In order to make the purpose, technical scheme and advantages of the embodiments of the present invention clearer, the embodiments of the present invention are further described in detail with reference to the accompanying drawings. Here, the illustrative embodiments of the present invention and their descriptions are used to explain the present invention, but are not intended to limit the present invention. It should be noted that, in the absence of conflict, the embodiments in this application and the features in the embodiments can be combined with each other arbitrarily. The acquisition, storage, use, and processing of data in the technical scheme in this application comply with the relevant provisions of laws and regulations. The user information in the embodiments of the present application is obtained through legal and compliant channels, and the acquisition, storage, use, and processing of user information are authorized and agreed by the customer.

[0065] In order to facilitate understanding of the technical solution provided by this application, the relevant contents of the technical solution of this application are first explained below.

[0066] The cooling of a dilution refrigerator is difficult and slow. For superconducting quantum computing, it often takes several days to cool down to the mK level using a dilution refrigerator. Due to the different superconducting transition temperatures required for different materials to enter the superconducting state, the uneven temperature distribution in different parts of the superconducting quantum chip, and the possible existence of some non-superconducting components inside the quantum computer, the Joule heat continuously generated by some electrical structures that have not entered the superconducting state or have no superconducting properties will further prolong the cooling time and affect the stability of the electrical structures that have entered the superconducting state. This problem is more obvious in the complex chip structure of the three-dimensional integrated architecture. Therefore, it is urgent to explore an effective conductive heat dissipation mechanism to optimize the heat dissipation path of the superconducting quantum chip during the cooling process, especially the heat dissipation problem of complex superconducting quantum chips using a three-dimensional integrated architecture.

[0067] Figure 1 Schematic diagram of the structure of the superconducting quantum chip provided by the first embodiment of the present invention. Figure 1 As shown, the superconducting quantum chip provided by the embodiment of the present invention includes a chip module 1 and a first heat dissipation layer 2, wherein:

[0068] The chip module 1 includes a core particle layer 1-1 and a substrate 1-2, and the substrate 1-2 is connected to the core particle layer 1-1 through a bump 1-3;

[0069] The core particle layer 1 - 1 and the first heat dissipation layer 2 are connected via a first bonding layer 3 .

[0070] Specifically, the core particle layer 1-1 includes a quantum integrated circuit (QIC) and an electronic integrated circuit (EIC). QIC and EIC can be integrated on the same carrier or on different carriers. The substrate 1-2 is used to carry the core particle layer 1-1. The substrate 1-2 can be made of sapphire and other materials, which can be selected according to actual needs and is not limited in the embodiment of the present invention. The substrate 1-2 is connected to the core particle layer 1-1 through the bumps 1-3. The bumps 1-3 can be solder bumps, nail head bumps, etc., which can be selected according to actual needs and are not limited in the embodiment of the present invention. The specific number of bumps 1-3 is set according to actual needs and is not limited in the embodiment of the present invention. The substrate 1-2 can support the core particle layer 1-1 through the bumps 1-3, and the bumps 1-3 can also realize electrical interconnection between chips.

[0071] The first heat dissipation layer 2 is used to dissipate heat from the chip module 1. The heat generated by the chip module 1 can be transferred to the first heat dissipation layer 2 through the first bonding layer 3. The heat can diffuse laterally in the first heat dissipation layer 2, increasing the effective heat exchange area between the heat source and the outside world, thereby improving the heat dissipation efficiency of the superconducting quantum chip. The first heat dissipation layer 2 can be made of materials with high thermal conductivity, such as diamond. Diamond has excellent insulation and ultra-high thermal conductivity. The thermal conductivity of single crystal diamond at room temperature is as high as 2400W / (m·K), and the thermal conductivity of polycrystalline diamond at room temperature is close to 2000W / (m·K), which is an ideal heat dissipation material. After the core particle layer 1-1 is integrated with the diamond, the heat generated by the core particle layer 1-1 will quickly diffuse laterally in the first heat dissipation layer 2 due to the ultra-high thermal conductivity of the diamond, thereby increasing the effective heat exchange area between the first heat dissipation layer 2 and the outside world, thereby greatly improving the heat exchange capacity of the superconducting quantum chip.

[0072] The first bonding layer 3 can be made of a metal nanostructure, and the core particle layer 1-1 and the first heat dissipation layer 2 are sputtered with metal nanoparticles on the surface, and then bonded to form the first bonding layer 3. Since the quantum bits in the core particle layer 1-1 are very fragile and cannot withstand long-term high-temperature treatment, the temperature during bonding needs to be lower than the preset temperature, such as 150°C. When metal nanoparticles are used for bonding, the melting point of the metal nanostructure will be greatly reduced due to the existence of the nano effect. In addition, the surface energy of the metal nanostructure is relatively high, and it is easy to combine with other atoms, which helps to achieve the bonding of the first heat dissipation layer and the core particle layer 1-1 at a lower temperature. Since metal nanoparticles can fill the surface depressions and micropores after low-temperature sintering, it helps to flatten the surface of the pad to be bonded, thereby reducing the requirements for flattening (such as chemical mechanical polishing process) before the bonding process between the first heat dissipation layer 2 and the core particle layer 1-1, and alleviates the adverse effects caused by the chip surface still being less flat after the flattening process, as well as the adverse mechanical damage that may be caused to the Josephson junction during the high-precision flattening process. Since the first bonding layer 3 adopts a metal nanostructure, it has good thermal conductivity and can ensure heat conduction between the core particle layer 1 - 1 and the first heat dissipation layer 2 .

[0073] The superconducting quantum chip provided by the embodiment of the present invention includes a chip module and a first heat dissipation layer, wherein the chip module includes a core particle layer and a substrate, wherein the substrate is connected to the core particle layer through bumps; the core particle layer is connected to the first heat dissipation layer through a first bonding layer, and since the first heat dissipation layer is provided on the core particle layer, the effective heat exchange area is increased, thereby improving the heat dissipation efficiency of the superconducting quantum chip. In addition, the core particle layer and the first heat dissipation layer are connected through the first bonding layer, which reduces the difficulty of the manufacturing process.

[0074] Figure 2 is a schematic diagram of the structure of a superconducting quantum chip provided by the second embodiment of the present invention, such as Figure 2 As shown, on the basis of the above embodiments, further, the superconducting quantum chip provided by the embodiment of the present invention further includes a crystal back layer 4, the crystal back layer 4 is connected to the substrate 1-2, and the thermal expansion coefficient of the substrate 1-2 is greater than the thermal expansion coefficient of the crystal back layer 4 and the thermal expansion coefficient of the first heat dissipation layer 2. The substrate 1-2 and the core particle layer 1-1 can use the same substrate material, such as sapphire, which is conducive to improving the preparation quality of the quantum bit, so that there will be no large mechanical stress between the two due to the difference in thermal expansion coefficients.

[0075] Specifically, the crystal back layer 4 can be made of silicon nitride material. The thermal expansion coefficient of the substrate 1-2 is greater than the thermal expansion coefficient of the crystal back layer 4, and the thermal expansion coefficient of the substrate 1-2 is greater than the thermal expansion coefficient of the first heat dissipation layer 2. Since the superconducting quantum chip requires an extremely low temperature service environment, the superconducting quantum chip will be subjected to a thermal load in the temperature range of room temperature to the mK order of magnitude. At this time, due to the mismatch between the thermal expansion coefficient of the substrate 1-2 and the thermal expansion coefficient of the first heat dissipation layer 2, the warping and thermal stress caused have a great adverse effect. However, the present application realizes the first heat dissipation layer-chip module-crystal back layer structure by adding a crystal back layer 4. The thermal expansion coefficient of the substrate 1-2 is greater than the thermal expansion coefficient of the crystal back layer 4 and the thermal expansion coefficient of the first heat dissipation layer 2. During the thermal cycle, the first heat dissipation layer 2 and the crystal back layer 4 have opposite stress directions on the intermediate substrate 1-2. The presence of the crystal back layer 4 can alleviate the warping degree of the first heat dissipation layer-chip module structure to a certain extent, thereby reducing the risk of mechanical failure. Specifically, according to the physical properties of the first heat dissipation layer 2 such as size and thermal conductivity, the warping degree of the overall structure of the first heat dissipation layer-chip module can be reduced by adjusting parameters such as shape, size, and position distribution of the back layer 4 .

[0076] For example, the first heat dissipation layer 2 is made of diamond material, the substrate 1-2 is made of sapphire material, and the back layer 4 is made of silicon nitride material. The thermal expansion coefficient of diamond is about 0.8×10 -6 / K, the thermal expansion coefficient of sapphire is about 7.5×10 -6 / K, the thermal expansion coefficient of silicon nitride is about 2.35×10 -6 / K. It can be ensured that the thermal expansion coefficient of the substrate 1 - 2 finally manufactured is greater than the thermal expansion coefficient of the first heat dissipation layer 2 and greater than the thermal expansion coefficient of the wafer back layer 4.

[0077] Figure 3 is a schematic diagram of the structure of a superconducting quantum chip provided by the third embodiment of the present invention, such as Figure 3 As shown, based on the above embodiments, the superconducting quantum chip provided in the embodiment of the present invention further includes a second heat dissipation layer 5 , and the second heat dissipation layer 5 is connected to the crystal back layer 4 through a second bonding layer 6 .

[0078] Specifically, the second heat dissipation layer 5 is used to dissipate heat from the chip module 1. The heat generated by the chip module 1 can be transferred to the second heat dissipation layer 5 through the crystal back layer 4 and the second bonding layer 6. The heat can diffuse laterally in the second heat dissipation layer 5, thereby increasing the effective heat exchange area between the heat source and the outside world, thereby improving the heat dissipation efficiency of the superconducting quantum chip. The second heat dissipation layer 5 can be made of a material with high thermal conductivity, such as diamond. The diamond can be a single crystal diamond sheet or a polycrystalline diamond sheet, preferably a single crystal diamond sheet.

[0079] The second bonding layer 6 can be made of a metal nanostructure, and metal nanoparticles are sputtered on the surface of the second heat dissipation layer 5 and the crystal back layer 4, and then bonded to form the second bonding layer 6. When metal nanoparticles are used for bonding, the melting point of the metal nanostructure will be greatly reduced due to the existence of the nano effect. In addition, the surface energy of the metal nanostructure is relatively high, and it is easy to combine with other atoms, which helps to achieve the bonding of the second heat dissipation layer and the crystal back layer 4 at a lower temperature.

[0080] Figure 4 is a schematic diagram of the structure of a superconducting quantum chip provided by the fourth embodiment of the present invention, such as Figure 4 As shown, on the basis of the above embodiments, further, the superconducting quantum chip provided in the embodiment of the present invention further includes a base 7 , and the base 7 is connected to the second heat dissipation layer 5 .

[0081] Specifically, the base 7 can be made of a material with good heat dissipation. For example, copper is used. Copper still has a high thermal conductivity at low temperatures, so it can bear the function of rapid heat dissipation. The base is used to carry the superconducting quantum chip and provides a close contact thermal interface, which helps to accelerate the heat dissipation of the superconducting quantum chip.

[0082] Figure 5 is a schematic diagram of the structure of a superconducting quantum chip provided by the fifth embodiment of the present invention, such as Figure 5 As shown, on the basis of the above embodiments, a second transition layer 8 is further provided between the base 7 and the second heat dissipation layer 5 .

[0083] Specifically, the second transition layer 8 can be made of thermal interface materials (TIM). The second transition layer 8 is used to fill the micro gaps and holes with uneven surfaces generated when the base 7 and the second heat dissipation layer 5 are in contact, reduce the contact thermal resistance, and improve the heat dissipation performance of the device. The thermal interface material is selected according to actual needs and is not limited in the embodiment of the present invention.

[0084] Figure 6 is a schematic diagram of the structure of a superconducting quantum chip provided by a sixth embodiment of the present invention, such as Figure 6 As shown. On the basis of the above embodiments, further, the base 7 at least wraps the partial structure from the substrate 1-2 to the base 7. By the base 7 wrapping the partial structure from the substrate 1-2 to the base 7, it is beneficial to increase the effective heat dissipation area and heat dissipation path, and further improve the heat dissipation efficiency of the superconducting quantum chip.

[0085] For example, the base 7 may wrap the substrate 1 - 2 , the wafer back layer 4 , the second bonding layer 6 and the second heat dissipation layer 5 .

[0086] For example, the base 7 may wrap the wafer back layer 4 , the second bonding layer 6 and the second heat dissipation layer 5 .

[0087] For example, the base 7 may wrap the second bonding layer 6 , the second heat dissipation layer 5 and the second transition layer 8 .

[0088] Figure 7 is a schematic diagram of the structure of a superconducting quantum chip provided by the seventh embodiment of the present invention, such as Figure 7 As shown, a thermoelectric zone 9 is provided between the base 7 and the wrapped structure. The thermoelectric zone 9 is provided with a thermoelectric conversion device, which is a functional device that can convert heat energy and electrical energy into each other. Thermoelectric refrigeration is an application of the Peltier effect. Unlike traditional compressor refrigeration, the thermoelectric refrigeration device has no moving parts and does not require refrigerant. It has the advantages of simple structure, small size and light weight, no noise, no pollution, and rapid refrigeration. The switching between cooling and heating can be easily achieved by changing the direction of the current. Thermoelectric conversion devices can be made of materials such as Bi2Te3, SiGe, PbTe, clathrate, skutterudite, Half-Heusler, SnSe, Zn4Sb4 and In4Se3.

[0089] Figure 8 is a schematic diagram of the structure of a superconducting quantum chip provided by the eighth embodiment of the present invention, such as Figure 8 As shown, on the basis of the above embodiments, further, the crystal back layer 4 includes an optical waveguide area 4-1, the optical waveguide area 4-1 is connected to the off-chip optical fiber 10 through a first coupler 15, a photonic integrated circuit (Photonic Integrated Circuit, referred to as PIC) bridge structure 1-21 is arranged on the substrate 1-2, the PIC bridge structure 1-21 is connected to the corresponding bump 1-3, and a second coupler 4-2 corresponding to the PIC bridge structure 1-21 is arranged in the optical waveguide area 4-1, and the second coupler 4-2 is used to realize the optical signal transmission between the PIC bridge structure 1-21 and the optical waveguide area 4-1.

[0090] Specifically, the crystal back layer 4 includes an optical waveguide area 4-1, and the optical waveguide area 4-1 is connected to the off-chip optical fiber 10 through the first coupler 15, and can receive optical signals from the outside through the off-chip optical fiber 10. It is understandable that the optical waveguide area 4-1 can be a part of the crystal back layer 4. A PIC bridge structure 1-21 can be set on the substrate 1-2, and the PIC bridge structure 1-21 can convert electrical signals into optical signals, and can also convert optical signals into electrical signals, and has ports for electrical signal input and output and ports for optical signal input and output. The PIC bridge structure is selected as the embedded bridge structure inside the substrate 1-2, which can convert the input optical signal from the off-chip optical fiber 10 into an electrical signal and transmit it to the core particle layer 1-1 through the corresponding bump 1-3. The PIC bridge structure 1-21 can also convert the electrical signal from the core particle layer 1-1 into an optical signal and finally output it through the off-chip optical fiber 10, thereby improving the flexibility and multiplexing of the design. The first coupler 15 can adopt an end face coupler.

[0091] In order to realize the transmission of optical signals between the PIC bridge structure 1-21 and the optical waveguide area 4-1, a through hole can be set in the substrate 1-2, and a second coupler 4-2 can be set at the position corresponding to the through hole in the optical waveguide area 4-1. The second coupler 4-2 is used to change the transmission direction of the optical signal. The second coupler 4-2 can transmit the optical signal from the optical waveguide area 4-1 to the PIC bridge structure 1-21, and can also transmit the optical signal from the PIC bridge structure 1-21 to the optical waveguide area 4-1. The second coupler 4-2 is selected according to actual needs, and the embodiment of the present invention does not limit it.

[0092] Furthermore, a ball lens can be arranged in the through hole provided in the substrate 1-2, and the second coupler 4-2 transmits the optical signal from the optical waveguide area 4-1 to the ball lens, and transmits it to the PIC bridge structure 1-21 through the ball lens. The optical signal from the PIC bridge structure 1-21 is transmitted to the second coupler 4-2 through the ball lens, and the second coupler 4-2 transmits the optical signal to the optical waveguide area 4-1. In order to ensure the stability of the ball lens, the through hole provided in the substrate 1-2 is inclined, and the diameter of the hole close to the optical waveguide area 4-1 is smaller, and the diameter of the hole close to the PIC bridge structure 1-21 is larger.

[0093] Fig. 9 is a schematic diagram of the structure of a superconducting quantum chip provided by the ninth embodiment of the present invention, such as Fig. 9 As shown, on the basis of the above embodiments, further, the superconducting quantum chip provided in the embodiment of the present invention further includes a first transition layer 11 , and the first transition layer 11 is connected to the first heat dissipation layer 2 .

[0094] Specifically, the first transition layer 11 can be made of TIM. The first transition layer 11 is used to fill the micro gaps and holes with uneven surfaces generated when the first heat dissipation layer 2 contacts the cold plate of the dilution refrigerator, reduce the heat transfer contact resistance, and improve the heat dissipation performance of the device. The thermal interface material is selected according to actual needs and is not limited in the embodiment of the present invention.

[0095] Fig.10 is a schematic diagram of the structure of a superconducting quantum chip provided by the tenth embodiment of the present invention, such as Fig.10 As shown, on the basis of the above embodiments, further, the core particle layer 1-1 is provided with a plurality of heat dissipation parts 1-11, each heat dissipation part 1-11 is in contact with the first bonding layer 3, and the heat dissipation part 1-11 is filled with thermal conductive material.

[0096] Specifically, the heat dissipation part 1-11 can be made by drilling holes on the core particle layer 1-1 and filling them with heat-conducting materials. The heat-conducting material can be made of a material with high thermal conductivity, such as diamond. The specific position and number of the heat dissipation part 1-11 are selected according to actual conditions, and the embodiment of the present invention does not limit it. By adding the heat dissipation part 1-11 to the core particle layer 1-1, a local heat dissipation channel at the micron level can be provided, which helps to achieve rapid conduction of heat in the vertical direction within the chip, and is beneficial to improving the thermal stability of the core particles. At the same time, the existence of the first heat dissipation layer 2 provides an off-chip heat dissipation channel, which helps to achieve rapid and uniform distribution of heat in the horizontal direction. The setting of dual heat dissipation paths inside and outside the chip will significantly improve the overall heat dissipation efficiency of the superconducting quantum chip.

[0097] Fig.11 is a schematic diagram of the structure of a superconducting quantum chip provided by the eleventh embodiment of the present invention, such as Fig.11 As shown, on the basis of the above embodiments, an electrical interconnection line 12 is further provided on the substrate 1-2, a first end of the electrical interconnection line 12 is connected to the bump 1-3, and a second end of the electrical interconnection line 12 is connected to the coaxial line 14 through a lead 13.

[0098] The core particle layer 1-1 can achieve electrical communication through the bumps 1-3, the electrical interconnection wires 12, the leads 13 and the coaxial line 14. The QIC and the EIC of the core particle layer 1-1 can achieve electrical communication through the corresponding bumps and the electrical interconnection wires.

[0099] Fig.12 is a schematic diagram of the structure of a quantum computer provided by the twelfth embodiment of the present invention, such as Fig.12As shown, a quantum computer provided by an embodiment of the present invention includes the superconducting quantum chip 1201 and a dilution refrigerator as described in any of the above embodiments, the dilution refrigerator includes a first cold plate 1202 and a second cold plate 1203, the superconducting quantum chip 1201 is arranged between the first cold plate 1202 and the second cold plate 1203, and is in contact with the first cold plate 1202 and the second cold plate 1203 respectively. The superconducting quantum chip 1201 is cooled by heat conduction with the first cold plate 1202 and the second cold plate 1203.

[0100] For example, Fig.13 is a schematic diagram of the structure of a quantum computer provided by the thirteenth embodiment of the present invention, such as Fig.13 As shown, the quantum computer provided by the embodiment of the present invention includes a superconducting quantum chip 101, a first cold plate 102 and a second cold plate 103, wherein:

[0101] The upper surface of the superconducting quantum chip 101 is in contact with the first cold plate 102 , and the lower surface of the superconducting quantum chip 101 is in contact with the second cold plate 103 .

[0102] The superconducting quantum chip 101 includes a chip module 1, a first heat dissipation layer 2, a first bonding layer 3, a crystal back layer 4, a second heat dissipation layer 5, a second bonding layer 6, a base 7, a second transition layer 8, a thermoelectric region 9 and a first transition layer 11. The chip module 1 includes a core particle layer 1-1 and a substrate 1-2, and the substrate 1-2 is connected to the core particle layer 1-1 through a bump 1-3. The crystal back layer 4 is connected to the substrate 1-2, and the thermal expansion coefficient of the substrate 1-2 is greater than the thermal expansion coefficient of the crystal back layer 4 and the thermal expansion coefficient of the first heat dissipation layer 2. The base 7 wraps the second bonding layer 6, the second heat dissipation layer 5 and the second transition layer 8.

[0103] The core particle layer 1-1 is provided with a plurality of heat dissipation parts 1-11, each heat dissipation part 1-11 is in contact with the first bonding layer 3, and the heat dissipation part 1-11 is filled with a thermal conductive material.

[0104] The crystal back layer 4 includes an optical waveguide area 4-1, which is connected to the off-chip optical fiber 10 through a first coupler 15. A PIC bridge structure 1-21 is arranged on the substrate 1-2, and the PIC bridge structure 1-21 is connected to the corresponding bumps. A second coupler 4-2 corresponding to the PIC bridge structure 1-21 is arranged in the optical waveguide area 4-1, and the second coupler 4-2 is used to realize the optical signal transmission between the PIC bridge structure 1-21 and the optical waveguide area 4-1.

[0105] An electrical interconnection line 12 is arranged on the substrate 1 - 2 , a first end of the electrical interconnection line 12 is connected to the bump 1 - 3 , and a second end of the electrical interconnection line 12 is connected to the coaxial line 14 through a lead line 13 .

[0106] The heat generated by the chip module 1 can be transferred to the first heat dissipation layer 2 through the first bonding layer 3, and then transferred from the first heat dissipation layer 2 to the first cold plate 102 through the first transition layer 11. The heat generated by the chip module 1 can be transferred to the second heat dissipation layer 5 through the crystal back layer 4 and the second bonding layer 6, and then transferred from the second heat dissipation layer 5 to the base 7 through the second transition layer 8, and the base 7 then transfers the heat to the second cold plate 103. Since a plurality of heat dissipation parts 1-11 are provided in the core particle layer 1-1, the heat generated by the core particle layer 1-1 can be transferred to the first bonding layer 3 through the plurality of heat dissipation parts 1-11, and then transferred to the first heat dissipation layer 2. The heat in the second heat dissipation layer 5, the second bonding layer 6 and the second transition layer 8 can also be transferred to the base 7 through the thermoelectric region 9.

[0107] The base 7 can facilitate the routing and fixing of the off-chip optical fiber 10 and the coaxial line 14. The second cold plate 103 can facilitate the routing and fixing of the coaxial line 14. The first cold plate 102 is provided with a through hole to facilitate the routing of the off-chip optical fiber 10 and the coaxial line 14.

[0108] Fig.14 is a schematic flow chart of a method for manufacturing a superconducting quantum chip provided in the fourteenth embodiment of the present invention, such as Fig.14 As shown, the method for manufacturing a superconducting quantum chip provided by an embodiment of the present invention includes:

[0109] 1401. Making each core particle;

[0110] Specifically, a QIC and / or an EIC is fabricated on a spare wafer to obtain a core particle. The core particle may include an active region, and a bump is fabricated on one side of the core particle including the active region.

[0111] 1402. Based on each core particle and the first heat dissipation layer, a first component is obtained; the first component includes the first heat dissipation layer and a core particle layer composed of each core particle;

[0112] Specifically, each core particle is bonded to the first heat dissipation layer to obtain a first component. The first component includes the first heat dissipation layer and a core particle layer composed of each core particle. The first heat dissipation layer can be made of a material with high thermal conductivity.

[0113] For example, the first heat dissipation layer is made of diamond. Since diamond is very hard and difficult to process, no special machining requirements are made for the entire piece of diamond sheet.

[0114] 1403. Based on the substrate material, obtain a second component; the second component includes a substrate;

[0115] Specifically, electrical interconnects, wiring layers, PIC bridge structures, through holes corresponding to the PIC bridge structures, and other structures are manufactured based on the substrate material to obtain a second component. The second component includes a substrate. The substrate material can be sapphire, silicon, etc., which can be selected according to actual needs and is not limited in the embodiment of the present invention.

[0116] 1404, preparing bumps on each core particle of the core particle layer, and making bumps on the substrate corresponding to the bumps of each core particle;

[0117] Specifically, a bump material is deposited on each core particle to obtain a bump on each core particle. A bump material is deposited on the substrate to obtain bumps corresponding to the bumps of each core particle. Since the bonding process requires a higher bump thickness, a bump material with a thickness of 5-10 μm can be selected. The bump material can be deposited by a process such as thermal evaporation, electron beam evaporation or electroplating to quickly complete the deposition of the bump material.

[0118] 1405. Based on the bumps on each core particle of the core particle layer and the bumps on the substrate, the first component and the second component are integrated to obtain the superconducting quantum chip.

[0119] Specifically, the bumps on each core particle are bonded to the bumps on the substrate in an inert atmosphere or a reducing atmosphere, so that the first component and the second component are integrated together to form the superconducting quantum chip. Solid-state bonding or liquid bonding can be selected. The temperature of solid-state bonding is lower, which can avoid the adverse effects of high-temperature processes on quantum components. Among them, the inert atmosphere can be nitrogen, and the reducing atmosphere can be formic acid.

[0120] The embodiment of the present invention provides the production of each core particle; based on each core particle and the first heat dissipation layer, a first component is obtained; the first component includes a core particle layer composed of the first heat dissipation layer and each core particle; based on the substrate material, a second component is obtained; the second component includes a substrate; bumps are prepared on each core particle of the core particle layer, and bumps corresponding to the bumps of each core particle are made on the substrate; based on the bumps on each core particle of the core particle layer and the bumps on the substrate, the first component and the second component are integrated to obtain the superconducting quantum chip. Since the first heat dissipation layer is set on the core particle layer, the effective heat exchange area is increased, thereby improving the heat dissipation efficiency of the superconducting quantum chip. In addition, the core particle layer and the first heat dissipation layer are connected by the first bonding layer to reduce the difficulty of the manufacturing process.

[0121] On the basis of the above embodiments, further, the manufacturing of each core particle includes:

[0122] A hole is punched at a preset position on a side of the core particle opposite to the first heat dissipation layer and filled with a heat conductive material to form a heat dissipation portion.

[0123] Specifically, for each core particle, during the manufacturing process, a hole can be punched at a preset position on the side of the core particle opposite to the first heat dissipation layer, and a heat conductive material can be filled to form a heat dissipation portion. When filling the heat conductive material, diamond particles can be deposited in the hole by microwave plasma chemical vapor deposition (MPCVD) technology. The holes can be punched by an etching process. Among them, the heat conductive material can be diamond. The preset position is set according to the actual situation, and the embodiment of the present invention is not limited.

[0124] Fig.15 is a schematic flow chart of a method for manufacturing a superconducting quantum chip provided in the fifteenth embodiment of the present invention, such as Fig.15 As shown, on the basis of the above embodiments, further, the obtaining of the first component based on each core particle and the first heat dissipation layer material includes:

[0125] S1501, sputtering metal nanoparticles on one side surface of the first heat dissipation layer, and sputtering metal nanoparticles on one side surface of each core particle;

[0126] Specifically, metal nanoparticles are sputtered on one side surface of the first heat dissipation layer, and metal nanoparticles are sputtered on one side surface of each core particle. The side surface of each core particle on which the metal nanoparticles are sputtered is not the active area of ​​the core particle. The first heat dissipation layer can be made of a material with high thermal conductivity such as diamond. The metal nanoparticles can be selected from Au and Ag nanoparticles.

[0127] The preparation of metal nanoparticles can be obtained by physical vapor deposition or pulsed laser deposition. Compared with the preparation of metal nanoparticles by solution method, the preparation of metal nanoparticles by physical vapor deposition or pulsed laser deposition solves the problem of easy agglomeration of metal nanoparticles and the problem of metal nanoparticles being contaminated by insufficiently volatilized organic solvents when organic solvents are introduced by solution method. At the same time, the metal nanoparticles prepared by physical vapor deposition or pulsed laser deposition are loosely dispersed, have a large surface area, and have high surface energy and activity, which helps to reduce the bonding temperature.

[0128] It should be noted that the redundant metal nanoparticles on the first heat dissipation layer do not need to be processed.

[0129] Further, before the metal nanoparticles are sputtered on the side surface of the first heat dissipation layer and / or the core particle, TiW or Cu can be sputtered on the side surface of the first heat dissipation layer and / or the core particle as a primer layer, and then the metal nanoparticles are sputtered on the primer layer. The stripping process rather than the wet etching process can be adopted to realize the graphicization of the TiW / Cu primer layer, thereby the metal nanoparticles on the bonding area can be effectively protected. If the wet etching process is adopted, it is necessary to first deposit TiW / Cu, then carry out the high-pressure sputtering nanoparticle process, and then carry out photolithography, and the nanoparticles on the bonding area surface are protected with photoresist, so as to remove the unnecessary TiW / Cu outside the bonding area with wet etching. In this case, the metal nanoparticles in the protected area are likely to be contaminated by the photoresist, and a certain degree of desorption occurs along with the dissolving and removal of the photoresist. In the scheme of the present application, the photolithography process is performed first, and the bonding area is not covered with photoresist. After the high-voltage sputtering of metal nanoparticles, it only needs to be immersed in acetone + ethanol once, and the photoresist in the non-bonding area will be dissolved, and the nanoparticles on the surface of the non-bonding area can be taken away, without causing significant adverse effects on the nanoparticles in the bonding area; in addition, the residual ethanol is easy to evaporate and will not affect the subsequent bonding process.

[0130] S1502: Bonding the surface of the first heat dissipation layer having metal nanoparticles to the surfaces of each core particle having metal nanoparticles at a preset temperature to obtain the first component.

[0131] Specifically, the surface of the first heat dissipation layer material having metal nanoparticles and the surface of each core particle having metal nanoparticles are bonded at a preset temperature to obtain the first component. The layer bonded between the first heat dissipation layer and each core particle is used as the first bonding layer. During the bonding process, the core particles are first aligned, then pre-bonded, and finally low-temperature annealing is performed. Since metal nanoparticles have a low melting point and can make up for the problem of flatness of the concave surface in the CMP process, it helps to reduce the annealing temperature required for bonding. It helps to ensure that the annealing process does not adversely affect the Josephson junction on the quantum functional core particle. The preset temperature is, for example, 150 degrees Celsius, which is set according to actual needs and is not limited in the embodiment of the present invention.

[0132] Since the qubits in the core particles are very fragile and cannot withstand long-term high-temperature treatment, low-temperature bonding at a preset temperature will not cause damage to the qubits. When metal nanoparticles are used for bonding, the melting point of the metal nanostructure will be greatly reduced due to the existence of the nano effect. In addition, the surface energy of the metal nanostructure is relatively high, and it is easy to combine with other atoms, which helps to achieve the bonding of the first heat dissipation layer and each core particle at a preset temperature. Since metal nanoparticles can fill surface depressions and micropores after low-temperature sintering, it helps to flatten the surface of the area to be bonded, reducing the requirements for flattening before the bonding process between the first heat dissipation layer and the core particles, and alleviating the adverse effects caused by the chip surface still being uneven after the flattening process.

[0133] On the basis of the above embodiments, further, the method for manufacturing a superconducting quantum chip provided in an embodiment of the present invention further includes:

[0134] A first transition layer is manufactured on the first heat dissipation layer.

[0135] Specifically, the thermal interface material can be a viscous body or solid with high viscosity, which can be brought into good contact with the substrate and tightly bonded together by applying pressure to form a first transition layer. The thermal interface material includes but is not limited to thermally conductive gel, thermally conductive silicone grease, thermally conductive glue, indium sheet, etc.

[0136] Fig.16 is a schematic flow chart of a method for manufacturing a superconducting quantum chip provided by the sixteenth embodiment of the present invention, such as Fig.16 As shown, based on the above embodiments, further, the second component also includes a back layer; accordingly, based on the substrate material, obtaining the second component includes:

[0137] S1601, manufacturing a substrate based on the substrate material;

[0138] Specifically, a substrate is manufactured based on the substrate material, and electrical interconnects, wiring layers, PIC bridge structures, through holes corresponding to the PIC bridge structures and other structures may also be manufactured on the substrate.

[0139] S1602, manufacturing a crystal back layer on the substrate; wherein the thermal expansion coefficient of the substrate is greater than the thermal expansion coefficient of the crystal back layer and the thermal expansion coefficient of the first heat dissipation layer.

[0140] Specifically, a back layer is produced on a surface of the substrate opposite to the surface where the bumps are produced by a material growth technique, wherein the material growth technique includes but is not limited to CVD, PVD, ALD, etc., and is selected according to actual needs.

[0141] It should be noted that the thermal expansion coefficient of the substrate is greater than the thermal expansion coefficient of the crystal back layer and the thermal expansion coefficient of the first heat dissipation layer. By manufacturing the crystal back layer and the thermal expansion coefficient of the substrate being greater than the thermal expansion coefficient of the crystal back layer and the thermal expansion coefficient of the first heat dissipation layer, the warping degree of the first heat dissipation layer-chip module structure can be alleviated to a certain extent, thereby reducing the risk of mechanical failure.

[0142] Fig.17 is a schematic flow chart of a method for manufacturing a superconducting quantum chip provided by the seventeenth embodiment of the present invention, such as Fig.17 As shown, based on the above embodiments, further, the second component also includes a second heat dissipation layer; accordingly, the second component obtained based on the substrate material also includes:

[0143] S1701, sputtering metal nanoparticles on the surface of the non-functional area of ​​the crystal back layer, and sputtering metal nanoparticles on the surface of a corresponding area on one side of the second heat dissipation layer;

[0144] Specifically, after the crystal back layer is manufactured on the substrate, metal nanoparticles are sputtered on the surface of the non-functional area of ​​the crystal back layer, and metal nanoparticles are sputtered on the surface of the corresponding area on one side of the second heat dissipation layer. The surface of the corresponding area on one side of the second heat dissipation layer is the surface that is bonded to the surface of the non-functional area of ​​the crystal back layer. The second heat dissipation layer can be made of a material with high thermal conductivity such as diamond. The metal nanoparticles can be selected from Au and Ag nanoparticles. In the present application, the non-functional area of ​​the crystal back layer refers to an area that will not be adversely affected by the sputtering of metal nanoparticles, such as an area outside the optical waveguide area.

[0145] Further, before the surface of the non-functional area of ​​the crystal back layer and / or the corresponding area on one side of the second heat dissipation layer is sputtered with metal nanoparticles, TiW or Cu can be sputtered as a base layer on the surface of one side of the crystal back layer and / or the second heat dissipation layer, and then the metal nanoparticles are sputtered on the base layer. The stripping process rather than the wet etching process can be adopted to realize the graphicization of the TiW / Cu base layer, so that the metal nanoparticles on the bonding area can be effectively protected. If the wet etching process is adopted, it is necessary to deposit TiW / Cu first, then perform the high-pressure sputtering nanoparticle process, and then perform photolithography, and the nanoparticles on the bonding area surface are protected with photoresist, so that the redundant TiW / Cu outside the bonding area is removed by wet etching. In this case, the metal nanoparticles in the protected area are likely to be contaminated by the photoresist, and a certain degree of desorption occurs as the photoresist is dissolved and removed. In the scheme of the present application, the photolithography process is performed first, and the bonding area is not covered with photoresist. After the high-voltage sputtering of metal nanoparticles, it only needs to be immersed in acetone + ethanol once, and the photoresist in the non-bonding area will be dissolved, and the nanoparticles on the surface of the non-bonding area can be taken away, without causing significant adverse effects on the nanoparticles in the bonding area; in addition, the residual ethanol is easy to evaporate and will not affect the subsequent bonding process.

[0146] S1702, bonding the surface of the second heat dissipation layer having metal nanoparticles to the surface of the crystal back layer having metal nanoparticles.

[0147] Specifically, the surface of the second heat dissipation layer with metal nanoparticles is bonded to the surface of the crystal back layer with metal nanoparticles. During the bonding process, the second heat dissipation layer is first aligned, then pre-bonded, and finally low-temperature annealed. Since the metal nanoparticles have a low melting point and can make up for the problem of flatness of the concave surface in the CMP process, it helps to reduce the annealing temperature required for bonding.

[0148] On the basis of the above embodiments, further, the method for manufacturing a superconducting quantum chip provided in an embodiment of the present invention further includes:

[0149] A second transition layer is formed on the surface of the second heat dissipation layer.

[0150] Specifically, the thermal interface material can be a viscous body or solid with high viscosity, and can be brought into good contact with the second heat dissipation layer and tightly bonded together by applying pressure to form a first transition layer. The thermal interface material includes but is not limited to thermally conductive gel, thermally conductive silicone grease, thermally conductive glue, indium sheet, etc.

[0151] On the basis of the above embodiments, further, the step of manufacturing a back layer on the substrate includes:

[0152] An optical waveguide region is fabricated on the crystal back layer.

[0153] Specifically, in the process of manufacturing the back layer on the substrate, the signal line required for optical communication can be prepared on the back layer by photolithography technology to obtain the optical waveguide area. Since it is not necessary to realize optical signal communication on the entire back layer, a part of the back layer can be selected to manufacture the optical waveguide area. The specific position of the optical waveguide area on the back layer is selected according to actual needs, and the embodiment of the present invention does not limit it.

[0154] Furthermore, after the optical waveguide region is manufactured, a second coupler may be manufactured at the position of the through hole corresponding to the optical waveguide region and the PIC bridge structure of the substrate.

[0155] The back layer of the crystal can be made of silicon nitride material. The integrated optical waveguide based on silicon nitride material has the characteristics of broadband low loss, no double photon absorption, and has a certain localization ability for light. In addition, silicon nitride material can also be used to prepare other types of on-chip optical devices as needed. As a common CMOS-compatible optical thin film dielectric material, it has very rich optical properties. The refractive index of silicon nitride is between silicon dioxide and silicon, with a lower refractive index, a larger energy band gap and a large range of transparent optical windows. In addition, by adjusting the relevant gas parameters during the preparation process, a silicon-rich silicon nitride thin film material with a relatively high refractive index that retains the optical properties of ordinary silicon nitride can also be prepared, thereby expanding the refractive index range of silicon nitride materials to between 1.9 and 3.2, and the corresponding extinction coefficient and nonlinear coefficient also have an adjustable range, which greatly enriches the freedom of device design.

[0156] On the basis of the above embodiments, further, the method for manufacturing a superconducting quantum chip provided in an embodiment of the present invention further includes:

[0157] The whole structure including the first component and the second component is arranged on a base.

[0158] Specifically, the base can be processed according to actual needs, and then the overall structure including the first component and the second component can be installed on the base. The base is used to support the above-mentioned overall structure. The base can be made of heat-conducting metal materials, such as copper. The thermal conductivity of copper is still high at low temperatures, so it can bear the function of rapid heat dissipation. The base can also be processed with through holes for the coaxial line and the off-chip optical fiber to pass through, which is convenient for the fixation and routing of the coaxial line and the off-chip optical fiber.

[0159] Furthermore, the cross section of the base may be concave, and the concave portion of the base is provided with an integral structure including the first component and the second component. The protruding portion of the concave portion of the base at least wraps around a portion of the structure from the substrate to the base to increase the heat dissipation area. A thermoelectric conversion device may be provided between the protruding portion of the concave portion of the base and the wrapped structure.

[0160] In the description of this specification, the description with reference to the terms "one embodiment", "a specific embodiment", "some embodiments", "for example", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0161] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A superconducting quantum chip, characterized in that: It includes a chip module and a first heat dissipation layer, wherein: The chip module comprises a core particle layer and a substrate, wherein the substrate is connected to the core particle layer via bumps; The core particle layer is connected to the first heat dissipation layer via a first bonding layer.

2. The superconducting quantum chip according to claim 1, characterized in that: It also includes a crystal back layer, which is connected to the substrate, and the thermal expansion coefficient of the substrate is greater than the thermal expansion coefficient of the crystal back layer and the thermal expansion coefficient of the first heat dissipation layer.

3. The superconducting quantum chip according to claim 2, characterized in that: It also includes a second heat dissipation layer, which is connected to the wafer back layer through a second bonding layer.

4. The superconducting quantum chip according to claim 3, characterized in that: It also includes a base, which is connected to the second heat dissipation layer.

5. The superconducting quantum chip according to claim 4, characterized in that: A second transition layer is disposed between the base and the second heat dissipation layer.

6. The superconducting quantum chip according to claim 4, characterized in that: The base at least wraps a portion of the structure from the substrate to the base.

7. The superconducting quantum chip according to claim 6, characterized in that: A thermoelectric zone is disposed between the base and the wrapped structure.

8. The superconducting quantum chip according to claim 2, characterized in that: The crystal back layer includes an optical waveguide area, and the optical waveguide area is connected to an off-chip optical fiber through a first coupler. A photonic integrated chip bridge structure is arranged on the substrate, and the photonic integrated chip bridge structure is connected to corresponding bumps. A second coupler corresponding to the photonic integrated chip bridge structure is arranged in the optical waveguide area, and the second coupler is used to realize optical signal transmission between the photonic integrated chip bridge structure and the optical waveguide area.

9. The superconducting quantum chip according to claim 1, characterized in that: It also includes a first transition layer, wherein the first transition layer is connected to the first heat dissipation layer.

10. The superconducting quantum chip according to claim 1, characterized in that: The core particle layer is provided with a plurality of heat dissipation parts, each heat dissipation part is in contact with the first bonding layer, and the heat dissipation part is filled with a thermal conductive material.

11. The superconducting quantum chip according to any one of claims 1 to 10, characterized in that: An electrical interconnection line is arranged on the substrate, a first end of the electrical interconnection line is connected to the bump, and a second end of the electrical interconnection line is connected to the coaxial line through a lead wire.

12. A quantum computer, characterized in that: The invention comprises the superconducting quantum chip according to any one of claims 1 to 11 and a dilution refrigerator, wherein the dilution refrigerator comprises a first cold plate and a second cold plate, and the superconducting quantum chip is arranged between the first cold plate and the second cold plate and contacts the first cold plate and the second cold plate respectively.

13. A method for manufacturing a superconducting quantum chip, characterized in that: include: Making each core particle; Based on each core particle and the first heat dissipation layer, a first component is obtained; the first component includes the first heat dissipation layer and the core particle layer composed of each core particle; Based on the substrate material, a second component is obtained; the second component includes a substrate; Producing bumps on each core particle of the core particle layer, and producing bumps on the substrate corresponding to the bumps of each core particle; Based on the bumps on each core particle of the core particle layer and the bumps on the substrate, the first component and the second component are integrated to obtain the superconducting quantum chip.

14. The method according to claim 13, characterized in that The manufacturing of each core particle comprises: A hole is punched at a preset position on a side of the core particle opposite to the first heat dissipation layer and filled with a heat conductive material to form a heat dissipation portion.

15. The method according to claim 13, characterized in that The step of obtaining the first component based on the core particles and the first heat dissipation layer material includes: sputtering metal nanoparticles on one side surface of the first heat dissipation layer, and sputtering metal nanoparticles on one side surface of each core particle; The surface of the first heat dissipation layer having metal nanoparticles is bonded to the surface of each core particle having metal nanoparticles at a preset temperature to obtain the first component.

16. The method according to claim 13, characterized in that Also includes: A first transition layer is manufactured on the first heat dissipation layer.

17. The method according to claim 13, characterized in that The second component further includes a back layer; accordingly, based on the substrate material, obtaining the second component includes: Based on the substrate material, manufacturing a substrate; A crystal back layer is manufactured on the substrate; wherein the thermal expansion coefficient of the substrate is greater than the thermal expansion coefficient of the crystal back layer and the thermal expansion coefficient of the first heat dissipation layer.

18. The method according to claim 17, characterized in that The second component further includes a second heat dissipation layer; accordingly, based on the substrate material, obtaining the second component further includes: sputtering metal nanoparticles on the surface of the non-functional area of ​​the crystal back layer, and sputtering metal nanoparticles on the surface of the corresponding area on one side of the second heat dissipation layer; The surface of the second heat dissipation layer having metal nanoparticles is bonded to the surface of the non-functional region of the crystal back layer having metal nanoparticles.

19. The method according to claim 18, characterized in that Also includes: A second transition layer is formed on the surface of the second heat dissipation layer.

20. The method according to claim 17, characterized in that The step of manufacturing a back layer on the substrate comprises: An optical waveguide region is fabricated on the crystal back layer.

21. The method according to any one of claims 13 to 20, characterized in that Also includes: The whole structure including the first component and the second component is arranged on a base.

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