Ferroelectric capacitor preparation method and ferroelectric capacitor
By replacing dry engraving with wet engraving, the inner membrane layer of the three-dimensional capacitance hole is protected by liquid film tension, the membrane layer damage and short circuit problems caused by dry engraving are solved, and more efficient ferroelectric capacitor preparation is achieved, reducing costs and time, and enhancing capacitor characteristics are enhanced. .
Patent Information
- Application Number
- CN202311164128.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-09-11
- Publication Date
- 2024-12-13
AI Technical Summary
In the existing ferroelectric capacitor preparation methods, the dry engraving process leads to the risk of film layer damage and short circuit, and the boundaries of etching without masks are not easy to distinguish, affecting the capacitance characteristics.
Wet etching instead of dry etching, using the liquid film tension of the etching liquid to prevent the etching liquid from entering the stereo capacitor hole, only the wafer surface is etched, the inner film layer of the stereo capacitor hole is retained, and the wet etching and atomic layer deposition is used. simplify the process flow with other technologies.
Reduce manufacturing costs, reduce capacitive film damage, shorten process time, improve efficiency, avoid short circuit risk, and enhance film uniformity.
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Figure CN119136655A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of ferroelectric capacitors, and in particular to a method for preparing a ferroelectric capacitor and a capacitor thereof. Background Art
[0002] High-steady-state memory is a new type of memory based on logic chips, using High-K ferroelectric materials as capacitor dielectrics and using the polarity of ferroelectric materials to achieve storage functions. Its capacitor structure is embedded in the top winding layer, and ferroelectric capacitors are embedded in the top winding layer. Ferroelectric capacitors are used as core storage devices. First, deep holes are etched on the dielectric layer, and then metal barrier layers, lower electrode layers, high dielectric material layers, upper electrodes, etc. are filled in sequence. Since the aspect ratio of the three-dimensional capacitor holes is very high (greater than 10:1), it is impossible to use a masked lithography solution when etching the electrode material on the wafer surface, so the only way to remove the surface electrode material is to use a maskless solution for direct dry etching.
[0003] For the maskless version, the electrode plate film layer in the three-dimensional capacitor hole will also be etched during the dry etching process. Although the etching rate in the three-dimensional capacitor hole is slower than that on the wafer surface, based on the etching area ratio, the area in the cell (storage array area) capacitor hole is more than 10 times the surface area of the adjacent area. Therefore, the surface etching rate is estimated to be 10 times that in the hole, that is, 10nm thick TiN (titanium nitride) is etched on the surface, and 1nm titanium nitride is etched in the hole. This damage is unavoidable for the dry etching process, but it will still cause damage. The current method is to thicken the deposition thickness of the titanium nitride film on the electrode plate to ensure the thickness after etching in the three-dimensional capacitor hole. However, this solution cannot solve the problem of poor uniformity of the film layer caused by dry etching, which affects the capacitance characteristics. In addition, due to maskless etching, the etching boundary is not easy to distinguish. If the high dielectric material layer is etched too much, it will cause a short circuit between the upper and lower electrode plates. This is also a major potential risk. Summary of the invention
[0004] In view of the problem that the boundary of the existing ferroelectric capacitor preparation method and capacitor is difficult to distinguish due to maskless etching, and if the high-k layer is etched too much, a short circuit will occur between the upper and lower electrode plates, the present invention is proposed.
[0005] Therefore, the purpose of the present invention is to provide a method for preparing a ferroelectric capacitor and a capacitor thereof, the purpose of which is to replace the dry etching scheme with wet etching to solve the problem of too many dry etching steps in the entire process and the film damage that is easily caused.
[0006] In order to solve the above technical problems, the present invention provides the following technical solution: utilizing the liquid film tension caused by the viscosity of the etching liquid to prevent the etching liquid from entering the three-dimensional capacitor hole, and only etching the wafer surface to retain the film layer inside the three-dimensional capacitor hole.
[0007] As a preferred solution of the ferroelectric capacitor preparation method and the capacitor thereof of the present invention, wherein: a three-dimensional capacitor hole is prepared on the dielectric layer of the storage unit and an isolation layer and a lower electrode are deposited;
[0008] Etching the isolation layer and the lower electrode by wet etching to deposit a high dielectric material;
[0009] The upper electrode is deposited and the plate line is prepared by wet etching the high dielectric material.
[0010] As a preferred solution of the ferroelectric capacitor preparation method and the capacitor thereof of the present invention, wherein: a three-dimensional capacitor hole is prepared on the dielectric layer of the storage unit and an isolation layer and a lower electrode are deposited;
[0011] Etching the isolation layer and the lower electrode by dry etching to deposit high dielectric material;
[0012] The upper electrode is deposited and the plate line is prepared by wet etching the high dielectric material.
[0013] As a preferred solution of the ferroelectric capacitor preparation method and capacitor described in the present invention, the uniformity of the film layer is ensured by wet etching of the structural layer deposited on the surface of the wafer, and the electrode film in the three-dimensional capacitor hole is protected.
[0014] As a preferred solution of the ferroelectric capacitor preparation method and the capacitor thereof of the present invention, the ferroelectric capacitor preparation steps include:
[0015] Etching a three-dimensional capacitor hole on the dielectric layer of the storage unit;
[0016] That is, the isolation layer and the lower electrode are deposited continuously;
[0017] Etching the lower electrode and then etching the isolation layer by wet etching;
[0018] After etching is completed, high dielectric material is deposited by atomic layer deposition;
[0019] The high dielectric material is etched by wet etching and an upper electrode is deposited;
[0020] The sheet wire is prepared by physical vapor deposition to form metallic titanium;
[0021] Patterning was achieved by yellow light lithography and photoresist stripping of the board lines by wet etching.
[0022] As a preferred solution of the ferroelectric capacitor preparation method and the capacitor thereof of the present invention, the specific steps of preparing the ferroelectric capacitor include:
[0023] Etching a three-dimensional capacitor hole on the dielectric layer of the storage unit and depositing an isolation layer;
[0024] depositing a lower electrode on the isolation layer;
[0025] Etching the lower electrode and then etching the isolation layer by dry etching;
[0026] After etching is completed, high dielectric material is deposited by atomic layer deposition;
[0027] The high dielectric material is etched by wet etching and an upper electrode is deposited;
[0028] The sheet wire is prepared by physical vapor deposition to form metallic titanium;
[0029] Patterning was achieved by yellow light lithography and photoresist stripping of the board lines by wet etching.
[0030] As a preferred solution of the ferroelectric capacitor preparation method and capacitor described in the present invention, the three-dimensional capacitor hole is a cylindrical hole with a pore size less than 200 nm formed by etching on the dielectric layer, which is used to make an embedded capacitor.
[0031] As a preferred solution of the ferroelectric capacitor preparation method and capacitor described in the present invention, wherein: the isolation layer is deposited by atomic layer deposition of a tantalum nitride film with a thickness of 10nm, and the aperture of the three-dimensional capacitor hole is preferably 150nm.
[0032] As a preferred solution of the ferroelectric capacitor preparation method and capacitor described in the present invention, wherein: the lower electrode is formed by depositing a layer of titanium nitride with a thickness of 10 nm by atomic layer deposition.
[0033] As a preferred solution of the ferroelectric capacitor preparation method and capacitor described in the present invention, the lower electrode is wet-etched with SPM solution to remove the titanium nitride film layer, and the liquid film tension is used to prevent the etching solution from entering the three-dimensional capacitor hole and reacting with the titanium nitride in the hole.
[0034] As a preferred solution of the ferroelectric capacitor preparation method and capacitor described in the present invention, the isolation layer uses potassium hydroxide solution to wet etch to remove tantalum nitride, and the titanium nitride film layer in the three-dimensional capacitor hole is used to block the potassium hydroxide solution from contacting the underlying tantalum nitride.
[0035] As a preferred solution of the ferroelectric capacitor preparation method and capacitor described in the present invention, the high dielectric material is formed into a 9-11 nm thin film in the three-dimensional capacitor hole by atomic layer deposition, which serves as the dielectric of the capacitor.
[0036] As a preferred solution of the ferroelectric capacitor preparation method and the capacitor thereof of the present invention, wherein: the high dielectric material is wet-etched with a sulfuric acid solution, and the sulfuric acid solution cannot enter the interior of the three-dimensional capacitor hole due to liquid tension, and can only react with the high dielectric material on the wafer;
[0037] And sulfuric acid does not react with silicon nitride to protect the dielectric layer.
[0038] As a preferred solution of the ferroelectric capacitor preparation method and capacitor described in the present invention, the high dielectric material is wet-etched with a sulfuric acid solution, and the small pore size of the three-dimensional capacitor holes is used to prevent the sulfuric acid solution from entering the interior due to liquid tension, and can only react with the high dielectric material on the wafer.
[0039] As a preferred solution of the ferroelectric capacitor preparation method and capacitor described in the present invention, the high dielectric material is wet-etched with a sulfuric acid solution, and the small pore size of the three-dimensional capacitor holes is used to prevent the sulfuric acid solution from entering the interior due to liquid tension, and only react with the high dielectric material on the wafer.
[0040] As a preferred solution of the ferroelectric capacitor preparation method and capacitor of the present invention, wherein: the upper electrode is formed by depositing 10nm of titanium nitride on the high dielectric material by atomic layer deposition.
[0041] As a preferred solution of the ferroelectric capacitor preparation method and capacitor of the present invention, wherein: the plate line is deposited with 300nm of metal titanium on the upper electrode by physical vapor deposition, and patterned by yellow light photolithography and wet etching to strip the photoresist.
[0042] The beneficial effects of the ferroelectric capacitor preparation method of the present invention are as follows: by adopting a wet etching process instead of a dry etching process, in addition to reducing the manufacturing cost, the damage to the capacitor film can be reduced, the process time can be shortened, and the efficiency can be improved; at the same time, a metal titanium material similar to the top electrode is used for plate line connection, and the wet etching step is combined to simplify the process and avoid an additional etching step.
[0043] In view of the above-mentioned problems existing in the existing ferroelectric capacitor preparation method and capacitor, the present invention is proposed.
[0044] Therefore, another object of the present invention is to provide a method for preparing a ferroelectric capacitor and a capacitor thereof, wherein different materials are used so that the etching solution does not react with the underlying film during wet etching.
[0045] In order to solve the above technical problems, the present invention provides the following technical solutions: comprising: a storage unit, which includes a three-dimensional capacitor hole opened on a dielectric layer, an isolation layer arranged on the inner surface of the three-dimensional capacitor hole, a lower electrode arranged on the inner side of the isolation layer, a high dielectric material arranged on the inner wall of the lower electrode, the upper electrode arranged on the inner wall of the lower electrode, and a plate line arranged on the outer side of the upper electrode;
[0046] The high dielectric material is preferably a ferroelectric material with a relatively high K value.
[0047] As a preferred solution of the ferroelectric capacitor preparation method and the capacitor of the present invention, wherein: the three-dimensional capacitor hole is opened on the dielectric layer with a thickness of 1200nm, and the hole diameter is 150nm;
[0048] The isolation layer is made of tantalum nitride material, and the lower electrode and the upper electrode are made of titanium nitride material, and the thickness of the three is 10nm;
[0049] The high dielectric material is preferably a zirconium oxide material, and the thickness is preferably 10 nm;
[0050] The plate wire is preferably made of a metallic titanium material with a thickness of 300 nm.
[0051] The beneficial effects of the capacitor of the present invention are as follows: by combining the plate line connection and electrode preparation steps, the process flow is simplified, consistency is increased, potential problems are reduced, the inner membrane structure of the three-dimensional capacitor hole is prevented from being contaminated, and short circuits are effectively prevented. BRIEF DESCRIPTION OF THE DRAWINGS
[0052] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. Among them:
[0053] Figure 1 Schematic diagram of capacitor structure in prior art.
[0054] Figure 2 It is a schematic diagram of the method for preparing a ferroelectric capacitor and the three-dimensional capacitor hole etching structure of the capacitor of the present invention.
[0055] Figure 3 The present invention is a schematic diagram of the method for preparing a ferroelectric capacitor and the isolation layer deposition structure of the capacitor.
[0056] Figure 4 It is a schematic diagram of the method for preparing a ferroelectric capacitor and the lower electrode deposition structure of the capacitor according to the present invention.
[0057] Figure 5 The present invention is a schematic diagram of the method for preparing a ferroelectric capacitor and the etching structure of the lower electrode of the capacitor.
[0058] Figure 6 The present invention is a schematic diagram of the method for preparing a ferroelectric capacitor and the etching structure of the isolation layer of the capacitor.
[0059] Figure 7 It is a schematic diagram of the method for preparing a ferroelectric capacitor and the high dielectric material deposition structure of the capacitor of the present invention.
[0060] Figure 8It is a schematic diagram of the method for preparing a ferroelectric capacitor and the etching structure of the high dielectric material of the capacitor of the present invention.
[0061] Fig. 9 The diagram is a schematic diagram of the method for preparing a ferroelectric capacitor and the upper electrode deposition structure of the capacitor according to the present invention.
[0062] Fig.10 It is a schematic diagram of the plate-line structure of the ferroelectric capacitor preparation method and the capacitor of the present invention.
[0063] Fig.11 The present invention is a schematic diagram of the method for preparing a ferroelectric capacitor and the etching structure of the plate line and upper electrode of the capacitor.
[0064] Fig.12 It is a schematic diagram of the overall structure of the ferroelectric capacitor preparation method and the capacitor of the present invention. DETAILED DESCRIPTION
[0065] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are described in detail below in conjunction with the accompanying drawings.
[0066] In the following description, many specific details are set forth to facilitate a full understanding of the present invention, but the present invention may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.
[0067] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a
[0068] The specific features, structures or characteristics of at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor does it refer to a separate or selective embodiment that is mutually exclusive with other embodiments.
[0069] Secondly, the present invention is described in detail with reference to the schematic diagram. When describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional diagrams showing the device structure will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.
[0070] Example 1
[0071] Reference Figures 1 to 12, which is the first embodiment of the present invention, provides a method for preparing a ferroelectric capacitor and its capacitor. This method mainly uses wet etching to the structural layer deposited on the surface of the wafer during the preparation of the ferroelectric capacitor, and utilizes the liquid film tension caused by the viscosity of the etching solution to prevent the etching solution from entering the three-dimensional capacitor hole 101, and only etches the wafer surface to retain the inner film layer of the three-dimensional capacitor hole 101.
[0072] Among them, the structural layers deposited on the surface of the wafer are the isolation layer 102, the lower electrode 103, the high dielectric material 104, the upper electrode 105 and the plate line 106 deposited on the three-dimensional capacitor hole 101 and the wafer surface. The structural layers deposited on the surface of the wafer are wet-etched to ensure the uniformity of the film layer and protect the electrode film inside the three-dimensional capacitor hole 101.
[0073] The main steps are to prepare a three-dimensional capacitor hole 101 on the dielectric layer of the storage unit 100 and continuously deposit an isolation layer 102 and a lower electrode 103 therein; etch the isolation layer 102 and the lower electrode 103 using wet etching and then deposit a high dielectric material 104; deposit an upper electrode 105 and prepare a plate line 106 after wet etching the high dielectric material 104.
[0074] The specific preparation steps are as follows:
[0075] refer to Figure 2 , since photoresist has been coated on the surface of the storage unit 100 substrate by using photolithography technology, and a photolithography pattern on the dielectric layer of the array region is formed by using a photolithography mask and ultraviolet light irradiation, including the position and size of the three-dimensional capacitor hole 101, dry etching is performed at this time, and the dielectric layer is etched by plasma or ion beam to form cylindrical three-dimensional capacitor holes 101 for making embedded capacitors, and the hole diameter is usually 150nm;
[0076] Then, refer to Figure 3 , by using atomic layer deposition, a tantalum nitride film with a thickness of 10 nm is deposited on the inner wall of the three-dimensional capacitor hole 101 and the dielectric layer in the array area, that is, the isolation layer 102, which serves as a metal barrier layer to prevent metal from diffusing in the dielectric layer;
[0077] Here, reference Figure 4 , also using the atomic layer deposition method, a layer of titanium nitride with a thickness of 10nm is deposited on the isolation layer 102 as the lower electrode 103 of the capacitor, and titanium nitride is used to improve good conductivity and stability;
[0078] refer to Figure 5After the isolation layer 102 and the lower electrode 103 are deposited, the titanium nitride film layer of the lower electrode 103 is wet-etched and removed using an SPM solution. At the same time, due to the tension of the liquid film, the etching solution cannot enter the three-dimensional capacitor hole 101 and react with the titanium nitride in the hole. Therefore, the lower electrode 103 layer of the three-dimensional capacitor hole 101 will not be affected in any way. The SPM solution can be a mixture of H2SO4 (sulfuric acid) / H2O2 (hydrogen peroxide) / H2O.
[0079] refer to Figure 6 After the lower electrode 103 is wet-etched, the tantalum nitride film layer of the isolation layer 102 is wet-etched and removed using a potassium hydroxide solution. Due to the tension of the liquid film, the etching solution cannot enter the three-dimensional capacitor hole 101 to react with the tantalum nitride in the hole. Moreover, due to the barrier of the titanium nitride film layer in the three-dimensional capacitor hole 101, the potassium hydroxide solution cannot contact the lower tantalum nitride layer, and the potassium hydroxide solution does not react with titanium nitride, so the tantalum nitride in the three-dimensional capacitor hole 101 will not be etched.
[0080] refer to Figure 7 , by using atomic layer deposition again, a ferroelectric material with a higher K value is deposited in the three-dimensional capacitor hole 101 to form a 9-11 nm thin film, that is, a high dielectric material 104, as a dielectric of the capacitor, and the ferroelectric material can be zirconium oxide or hafnium oxide, and the thickness is preferably 10 nm;
[0081] refer to Figure 8 After the high dielectric material 104 is deposited, a sulfuric acid solution, namely H2SO4, is used to wet-etch away the high dielectric material 104 in the three-dimensional capacitor hole 101. In this method, since the three-dimensional capacitor hole 101 has a small aperture, the concentrated sulfuric acid cannot enter the three-dimensional capacitor hole 101 for etching due to the influence of liquid tension, so it can only react with the high dielectric material 104 layer on the upper surface of the wafer. At the same time, since sulfuric acid does not react with silicon nitride, it will not attack the lower layer during the etching process;
[0082] refer to Fig. 9 , further, a 10 nm titanium nitride film layer is deposited on the high dielectric material 104 by atomic layer deposition to serve as the upper electrode 105 of the capacitor;
[0083] Final Reference Fig.10 , a 300nm layer of titanium is formed on the upper electrode 105 by physical vapor deposition, and then Fig.11 , through yellow light process exposure and development and SPM solution wet etching, after the final photoresist stripping, pattern optimization and routing formation are achieved Fig.12 , and externally connected to a pad to facilitate subsequent packaging.
[0084] Among them, the SPM solution mainly reacts with H2O2 hydrogen peroxide to generate free titanium oxide ions. Tantalum nitride is etched using potassium hydroxide solution. Since tantalum nitride is dissolved in potassium hydroxide solution, the components in the SPM solution will not react with tantalum nitride, nor with the lower layer of silicon nitride, and potassium hydroxide solution can only react with ferroelectric materials but not with titanium nitride.
[0085] Plasma treatment should be avoided before wet etching. Wet etching adopts immersion method and spraying cannot be used. Keep static during etching and do not increase the vibration and circulation of the etching solution.
[0086] Compared with the existing preparation methods, see Table 1 and Figure 1 .
[0087]
[0088]
[0089] Table 1 Comparison between existing technology and improved technology
[0090] In the improved technology, etching has a micro-load effect. The original process plan is to use this micro-load effect to perform maskless etching. According to the etching area ratio, the area inside the cell (storage array area) capacitor hole is more than 10 times the surface area of the adjacent area. Therefore, the surface etching rate is estimated to be 10 times that inside the hole, that is, 10nm thick TiN (titanium nitride) is etched on the surface, and 1nm titanium nitride is etched inside the hole. This damage is unavoidable for the dry etching process. At the same time, the top diameter of the three-dimensional capacitor hole 101 is larger than the middle and bottom of the three-dimensional capacitor hole 101. Therefore, the etching load effect is relatively weak, so the etching rate is faster than that inside the hole, and the damage caused is more serious.
[0091] The improved process utilizes wet etching instead of dry etching and etches each material layer separately, thereby avoiding too many dry etching steps in the entire process and the possible damage to the film layer. It also solves the problem that the preparation process of the three-dimensional capacitor hole 101 and the upper and lower electrode plates requires two maskless dry etchings, and the problem that the maskless dry etching causes damage to the electrode film inside the three-dimensional capacitor hole 101.
[0092] Example 2
[0093] Reference Figures 2 to 12 , which is the second embodiment of the present invention. This embodiment is different from the first embodiment in that the structural layer deposited on the surface of the wafer includes any one or more combinations of the isolation layer 102, the lower electrode 103, the high dielectric material 104, the upper electrode 105 and the plate line 106 deposited on the three-dimensional capacitor hole 101 and the wafer surface.
[0094] Compared with Example 1, further, wet etching is used to remove the structural layers deposited on the wafer surface, including the high dielectric material 104, the upper electrode 105 and the plate line 106 deposited on the three-dimensional capacitor hole 101 and the wafer surface, to ensure the uniformity of the film layer.
[0095] The main steps are to prepare a three-dimensional capacitor hole 101 on the dielectric layer of the storage unit 100 and continuously deposit an isolation layer 102 and a lower electrode 103 therein; etch the isolation layer 102 and the lower electrode 103 by dry etching and then deposit a high dielectric material 104; and deposit an upper electrode 105 and prepare a plate line 106 after wet etching the high dielectric material 104.
[0096] The specific preparation steps are as follows:
[0097] refer to Figure 2 , since photoresist has been coated on the surface of the storage unit 100 substrate by using photolithography technology, and a photolithography pattern on the dielectric layer of the array region is formed by using a photolithography mask and ultraviolet light irradiation, including the position and size of the three-dimensional capacitor hole 101, dry etching is performed at this time, and the dielectric layer is etched by plasma or ion beam to form cylindrical three-dimensional capacitor holes 101 for making embedded capacitors, and the hole diameter is usually 150nm;
[0098] Then, refer to Figure 3 , by using atomic layer deposition, a tantalum nitride film with a thickness of 10 nm is deposited on the inner wall of the three-dimensional capacitor hole 101 and the dielectric layer in the array area, that is, the isolation layer 102, which serves as a metal barrier layer to prevent metal from diffusing in the dielectric layer;
[0099] Here, reference Figure 4 , also using the atomic layer deposition method, a layer of titanium nitride with a thickness of 10nm is deposited on the isolation layer 102 as the lower electrode 103 of the capacitor, and titanium nitride is used to improve good conductivity and stability;
[0100] After the isolation layer 102 and the lower electrode 103 are deposited, the titanium nitride of the lower electrode 103 and the isolation layer 102 on the surface of the wafer are etched by plasma or ion beam, and the titanium nitride layer and the isolation layer 102 on the inner side of the wall of the three-dimensional capacitor hole 101 are retained;
[0101] refer to Figure 7 , by using atomic layer deposition again, a ferroelectric material with a higher K value is deposited in the three-dimensional capacitor hole 101 to form a 9-11 nm thin film, that is, a high dielectric material 104, as a dielectric of the capacitor, and the ferroelectric material can be zirconium oxide or hafnium oxide, and the thickness is preferably 10 nm;
[0102] refer to Figure 8After the high dielectric material 104 is deposited, the high dielectric material 104 in the three-dimensional capacitor hole 101 is wet-etched by using sulfuric acid solution / hydrochloric acid. In this method, since the three-dimensional capacitor hole 101 has a small aperture, the concentrated sulfuric acid cannot enter the three-dimensional capacitor hole 101 for etching due to the influence of liquid tension, so it can only react with the high dielectric material 104 layer on the upper surface of the wafer. At the same time, since sulfuric acid does not react with silicon nitride, it will not attack the lower layer during the etching process;
[0103] refer to Fig. 9 , further, a 10 nm titanium nitride film layer is deposited on the high dielectric material 104 by atomic layer deposition to serve as the upper electrode 105 of the capacitor;
[0104] Final Reference Fig.10 , a 300nm layer of titanium is formed on the upper electrode 105 by physical vapor deposition, and then Fig.11 Through yellow light process (exposure and development) and SPM solution wet etching, after the final photoresist stripping, pattern optimization and routing formation are achieved. Fig.12 , and externally connected to a pad to facilitate subsequent packaging.
[0105] Furthermore, the most important thing is the etching of the high dielectric material 104 ferroelectric material. Since the uneven film thickness of the lower electrode 103 and the isolation layer 102 does not directly affect the electrical properties of the capacitor, the capacitance formula is used:
[0106] C=εA / d
[0107] Among them, ε is the dielectric capacitance constant; A represents the parallel plate area; d represents the parallel plate spacing (i.e., dielectric thickness).
[0108] The etching of the lower electrode 103 and the isolation layer 102 can be understood as etching of the entire lower electrode plate, which will mainly affect the film thickness and film uniformity, but will not affect the parallel plate area, so there is no direct impact on the capacitance. The etching of the high dielectric material 104 will directly affect the film thickness of the dielectric layer and will affect the ferroelectric material, so it has the greatest impact. The use of wet etching can directly avoid this problem. The lower electrode 103 and the isolation layer 102 are dry-etched, which will cause damage to the film layer but will not affect the electrical properties.
[0109] The remaining structures are the same as those of Example 1.
[0110] Example 3
[0111] Reference Fig.12 , which is the third embodiment of the present invention, and this embodiment is different from the second embodiment in that: the overall structure is prepared.
[0112] Compared to Example 2, further, the storage unit 100 includes a three-dimensional capacitor hole 101 opened on the dielectric layer, an isolation layer 102 arranged on the inner surface of the three-dimensional capacitor hole 101, a lower electrode 103 arranged on the inner side of the isolation layer 102, a high dielectric material 104 arranged on the inner wall of the lower electrode 103, an upper electrode 105 arranged on the inner wall of the lower electrode 103, and a plate line 106 arranged on the outer side of the upper electrode 105.
[0113] The three-dimensional capacitor hole 101 is opened on a dielectric layer with a thickness of 1200 nm. In order to cooperate with wet etching, the aperture of the three-dimensional capacitor hole 101 needs to be less than 100 nm, while the aperture of this technical solution is 150 nm.
[0114] The isolation layer 102 is made of tantalum nitride material, the lower electrode 103 and the upper electrode 105 are made of titanium nitride material, and the thickness of the three is 10nm; the high dielectric material 104 is preferably zirconium oxide material, preferably 10nm thick; the plate line 106 is preferably a metal titanium material with a thickness of 300nm.
[0115] Through the different materials set up above, when selecting the etching solution, it is necessary to fully consider that when etching the current film layer, the etching solution cannot react with the underlying film, that is, when etching the lower electrode 103 metal and the isolation layer 102, the etching solution cannot react with silicon nitride, that is, there cannot be hydrofluoric acid in the etching solution, and when etching the high dielectric material 104, the etching solution also cannot react with the underlying silicon nitride. Therefore, sulfuric acid etching can be selected to finally form the overall structure.
[0116] The remaining structure is the same as that of Example 2.
[0117] Based on the above, the beneficial effects of the present invention are:
[0118] 1. Compared with the mainstream etching process in the prior art, which is a dry etching process, since the size of the transistor is always being compressed, a relatively high-precision dry etching process has to be adopted. At the same time, dry etching will indeed cause some film layer damage in the three-dimensional capacitor hole 101, especially damage to the high-K ferroelectric material, which will lead to changes in the electrical properties of the capacitor. In the preparation process of the entire embedded capacitor of the present invention, except for the deep hole etching of the three-dimensional capacitor hole 101, all other etching processes are carried out by wet etching. The cost of wet etching is only 1 / 10 of the cost of dry etching, which can greatly reduce the production cost. It is very difficult to replace dry etching with wet etching, but by using the steps of the present invention, it is possible to solve the problem of too many dry etching steps and possible film layer damage in the entire process while ensuring accuracy.
[0119] 2. Since the maskless dry etching of the upper and lower electrode plates is eliminated, the damage to the electrode film of the three-dimensional capacitor hole 101 caused by dry etching before does not exist, and the thickness of the titanium nitride film layer can be reduced from 15nm to 10nm, effectively shortening the process time and improving production efficiency.
[0120] 3. The key point to be considered from the prior art to the technology of the present invention is that wet etching is more difficult to control more accurately than dry etching. Therefore, when selecting the etching solution, it is necessary to fully consider that when etching the film layer, the etching solution cannot react with the underlying film. By using immersion wet etching instead of spray wet etching, and maintaining static state during etching without increasing the vibration and circulation of the etching solution, tension can be used to prevent the etching solution from entering the 150nm three-dimensional capacitor hole 101, and only the material on the crystal is etched.
[0121] 4. The plate-line connection uses a metal titanium material similar to the top electrode, which can be combined for wet etching, saving a production process and avoiding maskless etching of the upper electrode plate.
[0122] Importantly, it should be noted that the construction and arrangement of the present application shown in a plurality of different exemplary embodiments are only exemplary. Although only a few embodiments are described in detail in this disclosure, it should be readily understood by those who refer to this disclosure that many modifications are possible (e.g., the size, scale, structure, shape and proportion of various elements, and parameter values (e.g., temperature, pressure, etc.), installation arrangement, use of materials, color, directional changes, etc.) without substantially departing from the novel teachings and advantages of the subject matter described in the application. For example, the element shown as integrally formed can be composed of multiple parts or elements, the position of the element can be inverted or otherwise changed, and the nature or number or position of the discrete element can be changed or changed. Therefore, all such modifications are intended to be included in the scope of the present invention. The order or sequence of any process or method steps can be changed or reordered according to alternative embodiments. In the claims, any "device plus function" clause is intended to cover the structure of performing the function described herein, and is not only structurally equivalent but also equivalent structure. Without departing from the scope of the present invention, other replacements, modifications, changes and omissions can be made in the design, operating conditions and arrangement of the exemplary embodiments. Therefore, the invention is not limited to a specific embodiment, but extends to numerous modifications still falling within the scope of the appended claims.
[0123] Additionally, in order to provide a concise description of exemplary embodiments, all features of an actual embodiment (ie, those features that are not relevant to the best mode presently contemplated for carrying out the invention or those that are not relevant to implementing the invention) may not be described.
[0124] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present invention, which should all be included in the scope of the claims of the present invention.
Claims
1. A method for preparing a ferroelectric capacitor, characterized in that: Liquid film tension caused by the viscosity of the etching liquid is utilized to prevent the etching liquid from entering the three-dimensional capacitor hole (101), and only the wafer surface is etched to retain the inner film layer of the three-dimensional capacitor hole (101).
2. The method for preparing a ferroelectric capacitor according to claim 1, wherein: Preparing a three-dimensional capacitor hole (101) on the dielectric layer of the storage unit (100) and depositing an isolation layer (102) and a lower electrode (103); Etching the isolation layer (102) and the lower electrode (103) by wet etching to deposit a high dielectric material (104); The upper electrode (105) is deposited and the plate line (106) is prepared by wet etching the high dielectric material (104).
3. The method for preparing a ferroelectric capacitor according to claim 1, wherein: Preparing a three-dimensional capacitor hole (101) on the dielectric layer of the storage unit (100) and depositing an isolation layer (102) and a lower electrode (103); Etching the isolation layer (102) and the lower electrode (103) by dry etching, and depositing a high dielectric material (104); The upper electrode (105) is deposited and the plate line (106) is prepared by wet etching the high dielectric material (104).
4. The method for preparing a ferroelectric capacitor according to any one of claims 1 to 3, characterized in that: The uniformity of the film layer is ensured by wet etching of the structural layer deposited on the surface of the wafer, thereby protecting the electrode film inside the three-dimensional capacitor hole (101).
5. The method for preparing a ferroelectric capacitor according to claim 2, wherein: The ferroelectric capacitor preparation steps include: Etching a three-dimensional capacitor hole (101) on the dielectric layer of the storage unit (100); That is, the isolation layer (102) and the lower electrode (103) are continuously deposited; Etching the lower electrode (103) and then etching the isolation layer (102) by wet etching; After the etching is completed, a high dielectric material (104) is deposited by atomic layer deposition; Etching the high dielectric material (104) by wet etching and depositing an upper electrode (105); The plate wire (106) is prepared by physical vapor deposition to form metallic titanium; Patterning is achieved by stripping the photoresist of the board line (106) through yellow light lithography and wet etching.
6. The method for preparing a ferroelectric capacitor according to claim 3, characterized in that: The specific steps of preparing the ferroelectric capacitor include: Etching a three-dimensional capacitor hole (101) on the dielectric layer of the storage unit (100) and depositing an isolation layer (102); Depositing a lower electrode (103) on the isolation layer (102); Etching the lower electrode (103) and then etching the isolation layer (102) by dry etching; After the etching is completed, a high dielectric material (104) is deposited by atomic layer deposition; Etching the high dielectric material (104) by wet etching and depositing an upper electrode (105); The plate wire (106) is prepared by physical vapor deposition to form metallic titanium; Patterning is achieved by yellow light photolithography and wet etching of the photoresist stripping of the board line (106).
7. The method for preparing a ferroelectric capacitor according to claim 5, characterized in that: The three-dimensional capacitor hole (101) is a cylindrical hole with a hole diameter less than 200 nm formed on a dielectric layer by etching, and is used to manufacture an embedded capacitor.
8. The method for preparing a ferroelectric capacitor according to claim 7, characterized in that: The isolation layer (102) is formed by depositing a tantalum nitride film with a thickness of 10 nm by atomic layer deposition, and the aperture of the three-dimensional capacitor hole (101) is preferably 150 nm.
9. The method for preparing a ferroelectric capacitor according to claim 8, characterized in that: The lower electrode (103) is formed by depositing a layer of titanium nitride with a thickness of 10 nm by atomic layer deposition, thereby forming the lower electrode (103) of the capacitor.
10. The method for preparing a ferroelectric capacitor according to claim 9, characterized in that: The lower electrode (103) is wet-etched with an SPM solution to remove the titanium nitride film layer, and the liquid film tension is used to prevent the etching solution from entering the three-dimensional capacitor hole (101) and reacting with the titanium nitride in the hole.
11. The method for preparing a ferroelectric capacitor according to claim 10, characterized in that: The isolation layer (102) is wet-etched with potassium hydroxide solution to remove the tantalum nitride, and the titanium nitride film layer in the three-dimensional capacitor hole (101) is used to prevent the potassium hydroxide solution from contacting the lower tantalum nitride layer.
12. The method for preparing a ferroelectric capacitor according to any one of claims 5 to 11, characterized in that: The high dielectric material (104) is a ferroelectric material formed into a 9-11 nm thin film in the three-dimensional capacitor hole (101) by atomic layer deposition, which serves as the dielectric of the capacitor.
13. The method for preparing a ferroelectric capacitor according to claim 12, characterized in that: The high dielectric material (104) is wet-etched with a sulfuric acid solution, and the sulfuric acid solution cannot enter the three-dimensional capacitor hole (101) due to liquid tension because the hole diameter is small, and can only react with the high dielectric material (104) on the wafer; And sulfuric acid does not react with silicon nitride to protect the dielectric layer.
14. The method for preparing a ferroelectric capacitor according to claim 13, characterized in that: The upper electrode (105) is formed by depositing 10 nm of titanium nitride on the high dielectric material (104) by atomic layer deposition, thereby forming the upper electrode (105) of the capacitor.
15. The method for preparing a ferroelectric capacitor according to claim 13 or 14, characterized in that: The plate line (106) is formed by depositing 300 nm of metal titanium on the upper electrode (105) by physical vapor deposition, and patterning is performed by yellow light photolithography and wet etching to strip the photoresist.
16. A capacitor, characterized in that: A method for preparing a ferroelectric capacitor according to any one of claims 5 to 15, comprising: A storage unit (100) comprises a three-dimensional capacitor hole (101) opened on a dielectric layer, an isolation layer (102) arranged on the inner surface of the three-dimensional capacitor hole (101), a lower electrode (103) arranged on the inner side of the isolation layer (102), a high dielectric material (104) arranged on the inner wall of the lower electrode (103), an upper electrode (105) arranged on the inner wall of the lower electrode (103), and a plate line (106) arranged on the outer side of the upper electrode (105); The high dielectric material (104) is preferably a ferroelectric material with a relatively high K value.
17. The capacitor according to claim 16, characterized in that: The three-dimensional capacitor hole (101) is opened on a dielectric layer with a thickness of 1200nm, and the hole diameter is 150nm; The isolation layer (102) is made of tantalum nitride material, and the lower electrode (103) and the upper electrode (105) are made of titanium nitride material, and the thickness of the three is 10 nm; The high dielectric material (104) is preferably a zirconium oxide material, and the thickness is preferably 10 nm; The plate wire (106) is preferably made of a metallic titanium material with a thickness of 300 nm.