Signal acquisition and processing system based on FPGA

Abstract

A signal collecting and processing system based on an FPGA comprises a processing module, an interface module and a multi-channel position sensor which are connected in sequence, the processing module adopts an FPGA control module and is used for collecting and processing sensor signals output through optical coupler isolation and conducting time sequence synchronization, filtering and state checking on the sensor signals, and the multi-channel position sensor is connected with the interface module. And the FPGA control module is provided with an HB6096 communication bus interface circuit, the HB6096 communication bus interface circuit adopts a dual-redundancy design and is used for communicating with an onboard system, and the FPGA control module is provided with a power supply module. According to the signal acquisition and processing system based on the FPGA, the communication reliability is enhanced, key working information can be stored, software loading and fault downloading are facilitated, the power supply compatibility is good, meanwhile, the BIT function is achieved, health management can be conducted on the system, and the system reliability is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of signal acquisition, and in particular to a signal acquisition and processing system based on FPGA. Background Art

[0002] Signal acquisition and processing devices are widely used in aircraft hydraulic and landing gear retraction and extension systems for the acquisition and processing of onboard sensor signals. With the development of society and the advancement of science and technology, aircraft functions are becoming increasingly powerful, and the number of sensors is gradually increasing. Signal acquisition and processing devices need to have multi-channel sensor signal acquisition functions, real-time detection of sensor position status, and reliable reception of instructions sent by the aircraft control system. Output corresponding system accessory drive instructions to achieve simultaneous control of aircraft landing gear doors, etc., and provide sensor position information and system maintenance information to the onboard system through the bus. At the same time, it should have a BIT function to diagnose the health status of the system and have good ground maintainability, that is, software can be loaded on the ground and key working parameters can be downloaded for troubleshooting and data analysis. In this regard, we propose a signal acquisition and processing system based on FPGA. Summary of the invention

[0003] The purpose of the present invention is to propose a signal acquisition and processing system based on FPGA, which is used to detect the position status of the sensor in real time, can reliably receive the instructions sent by the aircraft control system, and output the corresponding system accessory drive instructions to realize the simultaneous control of the aircraft landing gear door, etc.

[0004] To achieve the above purpose, the following technical scheme is adopted: a signal acquisition and processing system based on FPGA, including a processing module, an interface module and a multi-channel position sensor connected in sequence, the processing module adopts an FPGA control module, which is used to collect and process the sensor signal output through optical coupling isolation, perform timing synchronization, filtering and status check on the sensor signal, and calculate the position information corresponding to the sensor, the FPGA control module is designed with an HB6096 communication bus interface circuit, the HB6096 communication bus interface circuit adopts a dual redundancy design, and is used to communicate with the onboard system, as well as a power supply module.

[0005] Preferably, the receiving interface chip of the HB6096 communication bus interface circuit is HKA3328, and the sending interface chip is HKA32133.

[0006] Preferably, the interface module is provided with a series-connected filtering and protection circuit and a multi-channel interface isolation circuit, and the filtering and protection circuit is used to filter and protect the multi-channel sensor signals from transient voltages, and the multi-channel interface isolation circuit is used to isolate the multi-channel sensor signals and send them to the FPGA control module for synchronous sampling.

[0007] Preferably, the power module is provided with a power conversion circuit and a power protection circuit. The power conversion circuit completes the power input processing and converts it into a secondary power supply of 5V / 20W used by the internal control component through a DC / DC module. The input voltage range is 15-50V and the output is 5V. The power protection circuit adopts a switching diode to prevent reverse connection, a transient voltage suppression diode to achieve overvoltage surge suppression function, a tantalum capacitor energy storage circuit to achieve undervoltage surge suppression function, and an EMI filter circuit for electromagnetic protection.

[0008] Preferably, a flash information storage circuit is provided in the processing module, and the flash information storage circuit is connected to the FPGA control module.

[0009] Preferably, the processing module is provided with an RS232 interface circuit, and the RS232 interface circuit is connected to the FPGA control module.

[0010] Beneficial effects achieved by the present invention: The present invention provides a signal acquisition and processing system based on FPGA. The dual-redundancy HB6096 communication bus design enhances the communication reliability. The information storage circuit can store key working information. The RS232 interface circuit is convenient for software loading and fault downloading. The power protection circuit has good power supply compatibility. At the same time, it has a BIT function, which can manage the health of the system and improve the system reliability. It solves the current problems of small number of sensor detection channels, low communication reliability, difficult ground maintenance, and no health management function. It can be widely used in work occasions with high requirements for reliability and power supply compatibility, such as aircraft landing gear retraction and extension control. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 This is a logic block diagram of the present invention. DETAILED DESCRIPTION

[0012] The technical solutions in the embodiments of the present invention are described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments.

[0013] In the description of the present invention, it is necessary to understand that the terms "upper", "lower", "front", "back", "left", "right", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0014] See attached Figure 1, a signal acquisition and processing system based on FPGA, including a processing module, an interface module and a multi-channel position sensor connected in sequence, The processing module adopts an FPGA control module, which is used to collect and process the sensor signals output by the optical coupler isolation, perform timing synchronization, filtering and status check on the sensor signals, and solve the corresponding position information of the sensor. The FPGA control module is designed with an HB6096 communication bus interface circuit. The HB6096 communication bus interface circuit adopts a dual-redundancy design and is used to communicate with the onboard system; to improve the communication reliability, two independent units work simultaneously, each unit includes an independent 1-transmit 1-receive function, and includes a complete HB6096 transceiver protocol, and each transceiver unit is configured with an independent FIFO to ensure the integrity of data transmission and reception; And a power supply module is used for powering and protecting the above-mentioned processing module and multi-channel position sensor, etc.

[0015] Among them, the HB6096 communication bus interface is implemented as FPGA+peripheral interface chip, that is, the HB6096 protocol part and control and decoding logic are implemented by writing code through FPGA. The receiving interface chip of the HB6096 communication bus interface circuit uses HKA3328, and the sending interface chip uses HKA32133.

[0016] In this embodiment, a series-connected filtering and protection circuit and a multi-channel interface isolation circuit are provided in the interface module. The filtering and protection circuit is used to filter the multi-channel sensor signals and protect them from transient voltages. The multi-channel interface isolation circuit is used to isolate the multi-channel sensor signals and send them to the FPGA control module for synchronous sampling. The multi-channel interface isolation circuit uses a GH302 photoelectric coupler with a response time of less than 3us, which can realize high-speed transmission of position sensor signals.

[0017] In this embodiment, the power module is provided with a power conversion circuit and a power protection circuit. The power conversion circuit completes the power input processing and converts it into a secondary power supply of 5V / 20W used by the internal control component through the DC / DC module. The input voltage range is 15-50V and the output is 5V. The power protection circuit uses a switching diode to prevent reverse connection, a transient voltage suppression diode to achieve overvoltage surge suppression function, a tantalum capacitor energy storage circuit to achieve undervoltage surge suppression function, and an EMI filter circuit for electromagnetic protection.

[0018] In this embodiment, a flash information storage circuit is provided in the processing module, and the flash information storage circuit is connected to the FPGA control module. The flash information storage circuit is used to store key working information and realize fault recording function. The flash uses a NAND FLASH with a capacity of 512MB to realize the storage of key working information of multiple flights.

[0019] In this embodiment, the processing module is provided with an RS232 interface circuit, and the RS232 interface circuit is connected to the FPGA control module for realizing functions such as software loading and fault downloading.

[0020] The FPGA control module is equipped with a BIT detection module, which executes the power-on BIT when powered on. The power-on BIT covers the following items: position sensor, HB6096 bus, FLASH memory, etc. The signal acquisition and processing system provides a basis for aircraft dispatch by checking its own working status and the working status of the position sensor. After the power-on BIT is completed, the signal acquisition and processing system enters the normal working state and executes the periodic BIT in the mission background at a periodic interval of 200ms. The periodic BIT covers the following items: position sensor, bus, etc.

[0021] The signal acquisition and processing system of the present invention can sample the position state signal of the multi-channel position sensor in real time, receive the instruction from the RIU through the dual-redundancy HB6096 bus, execute the logic processing function according to the instruction, and send the position indication, maintenance information and alarm information to the RIU through the HB6096 bus at a fixed period. The flash information storage circuit is used to store the key working information during the working process, and the RS232 interface circuit is used to complete the ground maintenance functions such as software loading and fault downloading.

[0022] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical scheme and inventive concept of the present invention within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims

1. A signal acquisition and processing system based on FPGA, characterized in that: It includes a processing module, an interface module and a multi-channel position sensor connected in sequence; The processing module adopts an FPGA control module, which is used to collect and process the sensor signals output by the optical coupler isolation, perform timing synchronization, filtering and status check on the sensor signals, and calculate the position information corresponding to the sensor. The FPGA control module is designed with an HB6096 communication bus interface circuit, which adopts a dual-redundancy design and is used to communicate with the onboard system; and power modules.

2. The FPGA-based signal acquisition and processing system according to claim 1, characterized in that: The receiving interface chip of the HB6096 communication bus interface circuit is HKA3328, and the sending interface chip is HKA32133.

3. The FPGA-based signal acquisition and processing system according to claim 1, characterized in that: The interface module is provided with a series-connected filtering and protection circuit and a multi-channel interface isolation circuit. The filtering and protection circuit is used to filter and protect the multi-channel sensor signals from transient voltages, and the multi-channel interface isolation circuit is used to isolate the multi-channel sensor signals and send them to the FPGA control module for synchronous sampling.

4. The FPGA-based signal acquisition and processing system according to claim 1, characterized in that: The power module is provided with a power conversion circuit and a power protection circuit. The power conversion circuit completes the processing of the power input and converts it into a secondary power supply of 5V / 20W used by the internal control component through the DC / DC module. The input voltage range is 15-50V and the output is 5V. The power protection circuit adopts a switching diode to prevent reverse connection, a transient voltage suppression diode to achieve overvoltage surge suppression function, a tantalum capacitor energy storage circuit to achieve undervoltage surge suppression function, and an EMI filter circuit for electromagnetic protection.

5. The FPGA-based signal acquisition and processing system according to claim 1, characterized in that: A flash information storage circuit is arranged in the processing module, and the flash information storage circuit is connected to the FPGA control module.

6. The FPGA-based signal acquisition and processing system according to claim 5, characterized in that: The processing module is provided with an RS232 interface circuit, and the RS232 interface circuit is connected with the FPGA control module.

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