Processor performance test method and system, electronic equipment and storage medium

Abstract

The invention provides a processor performance test method and system, electronic equipment and a storage medium, and the method comprises the steps: firstly, responding to a first test request sent by first test equipment through a UART unit in tested equipment, and sending first to-be-processed data corresponding to the first test request to a CPLD unit in the tested equipment; the first test device is in wireless communication connection with the UART unit, the ARM responds to first to-be-processed data sent by the CPLD unit and processes the first to-be-processed data to obtain a first test result, the first test result is sent to the CPLD unit, and the UART unit responds to the first test result sent by the CPLD unit and sends the first test result to the first test device. According to the technical scheme, the wireless communication connection between the test equipment CPU and the tested equipment is completed through the UART controller, and the purposes of avoiding frequent disassembly of the shell and improving the test efficiency during the ARM test of the FPGA are achieved.

Description

Technical Field

[0001] The present application relates to the field of hardware testing technology, and in particular to a method, system, electronic device and storage medium for testing processor performance. Background Art

[0002] A Field-Programmable Gate Array (FPGA) is an integrated circuit that can be programmed by users after manufacturing to implement specific logic functions and data processing. It allows users to configure logic functions, circuits, and device connections within it to implement specific hardware functions. It is widely used in switches, servers, and single cards or systems of Advanced RISC Machine (ARM) using FPGAs. Testing ARM for FPGAs is particularly important, as it can facilitate R&D and later factory production line testing.

[0003] In the prior art, the data information input and output of the ARM of the FPGA are directly connected to the external pin header through a complex programmable logic device (CPLD), and then connected to the test equipment through the external pin header. However, this method is complicated to operate, wastes time, and has low test efficiency.

[0004] Therefore, how to solve the low efficiency of ARM testing of FPGA and achieve efficient batch testing has become a technical problem that needs to be solved urgently. Summary of the invention

[0005] The embodiments of the present application provide a method, system, electronic device and storage medium for testing processor performance to solve the problems of the prior art in solving the low efficiency of ARM testing of FPGA and achieving efficient batch testing.

[0006] In a first aspect, an embodiment of the present application provides a method for testing processor performance, which is applied to a device under test, wherein a processor ARM to be tested is deployed in the device under test, and the method includes:

[0007] The unified asynchronous receiver / transmitter (UART) unit in the device under test responds to a first test request sent by a first test device, sending first to-be-processed data corresponding to the first test request to a complex programmable logic device (CPLD) unit in the device under test, and the first test device is connected to the UART unit through wireless communication;

[0008] The ARM processes the first data to be processed sent by the CPLD unit in response to obtaining a first test result and sends the first test result to the CPLD unit;

[0009] The UART unit sends the first test result to the first test device in response to the first test result sent by the CPLD unit.

[0010] In a possible design of the first aspect, the UART unit sends the first test result to the first test device in response to the first test result sent by the CPLD unit, including:

[0011] The UART unit receives the first test result sent by the CPLD unit, and when the amount of data in the information queue where the first test result is located is greater than a preset threshold, sends an interrupt request to the first test device to enable the first test device to obtain the first test result.

[0012] In another possible design of the first aspect, the UART unit sends the first test result to the first test device in response to the first test result sent by the CPLD unit, including:

[0013] The UART unit receives the first test result sent by the CPLD unit, and when the data storage time of the information queue where the first test result is located is greater than a preset time, sends an interrupt request to the first test device to enable the first test device to obtain the first test result.

[0014] In another possible design of the first aspect, the UART unit in the device under test sends the first to-be-processed data corresponding to the first test request to the CPLD unit in response to the first test request sent by the first test device, including:

[0015] The UART unit receives the first test request and stores it in an information queue;

[0016] When it is detected that the information queue is not empty, the first test request is taken out from the information queue and sent to the CPLD unit.

[0017] In another possible design of the first aspect, the CPLD unit sends second to-be-processed data corresponding to the second test request to the ARM unit in response to a second test request sent by a second test device, and the second test device is connected to the CPLD unit in wired communication;

[0018] In response to processing the second data to be processed sent by the CPLD unit, the ARM obtains a second test result and sends the second test result to the CPLD unit, so that the CPLD unit sends the second test result to the second test device.

[0019] In yet another possible design of the first aspect, the CPLD unit aggregates the first test request and the second test request to obtain a third test request;

[0020] The CPLD unit uses the third test request as a new first test request and sends it to the ARM unit.

[0021] In another possible design of the first aspect, the wireless communication connection method is a high-speed serial computer expansion bus standard PCIE method.

[0022] In a second aspect, an embodiment of the present application provides a system for testing processor performance, the system comprising: a device under test as described in any one of the first aspects and a first testing device.

[0023] In a third aspect, an embodiment of the present application provides an electronic device, comprising: a processor, and a memory communicatively connected to the processor.

[0024] The memory stores computer-executable instructions;

[0025] The processor executes the computer-executable instructions stored in the memory to implement the method as described in the first aspect or any one of the above methods.

[0026] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by a processor, they are used to implement the method described in the first aspect or any one of the methods.

[0027] The processor performance testing method, system, electronic device and storage medium provided in the embodiment of the present application, the method firstly responds to the first test request sent by the first test device through the UART unit in the tested device, sends the first to-be-processed data corresponding to the first test request to the CPLD unit in the tested device, the first test device is wirelessly connected with the UART unit, secondly, the ARM responds to the first to-be-processed data sent by the CPLD unit to obtain the first test result, and sends it to the CPLD unit, and finally the UART unit responds to the first test result sent by the CPLD unit and sends the first test result to the first test device. In this technical solution, the wireless communication connection between the test device CPU and the tested device is completed through the UART controller, so as to avoid frequent disassembly of the shell when performing the ARM test of the FPGA and improve the test efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0029] Figure 1 A schematic diagram of the architecture of the prior art of the method for testing processor performance provided in an embodiment of the present application;

[0030] Figure 2 Schematic diagram of the process of testing the processor performance provided in the embodiment of the present application Figure 1 ;

[0031] Figure 3 Schematic diagram of the processor performance testing method provided in the embodiment of the present application Figure 1 ;

[0032] Figure 4 A schematic diagram of wireless communication connection for a method for testing processor performance provided in an embodiment of the present application;

[0033] Figure 5 Schematic diagram of the process of testing the processor performance provided in the embodiment of the present application Figure 2 ;

[0034] Figure 6 A schematic diagram of the UART controller architecture of the processor performance testing method provided in an embodiment of the present application;

[0035] Figure 7 Schematic diagram of the process of testing the processor performance provided in the embodiment of the present application Figure 3 ;

[0036] Figure 8 Schematic diagram of the processor performance testing method provided in the embodiment of the present application Figure 2 ;

[0037] Fig. 9 Schematic diagram of the process of testing the processor performance provided in the embodiment of the present application Figure 4 ;

[0038] Fig.10 Schematic diagram of the process of testing the processor performance provided in the embodiment of the present application Figure 5 ;

[0039] Fig.11 A schematic diagram of a processor performance testing system provided in an embodiment of the present application;

[0040] Fig.12 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application.

[0041] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0043] Before introducing the embodiments of the present application, the application background of the embodiments of the present application is first explained:

[0044] FPGA is an integrated circuit that can be programmed by users after manufacturing to implement specific logic functions and data processing, allowing users to configure logic functions, circuits and device connections inside it to implement specific hardware functions. It is widely used in application scenarios such as switches, servers, and single cards or systems using ARM of FPGA. FPGA can be used for high-speed packet processing and traffic management of network switches and routers, and can also be used to implement customized processors and hardware accelerators in embedded devices, design and implement specific peripheral interfaces, and has the advantages of high performance, high flexibility, and high integration. Testing of ARM for FPGA is particularly important, which can facilitate R&D and later factory production line testing.

[0045] In the prior art, the data information input and output of the ARM of the FPGA are directly connected to the external pin header through the CPLD, and then connected to the serial port tool of the test equipment through a serial port line for testing. This method requires disassembling the board casing or the whole machine to find the pin header and connect it to the test equipment to perform the test, resulting in low test efficiency.

[0046] Specifically, Figure 1 A schematic diagram of the prior art architecture of a method for testing processor performance provided in an embodiment of the present application, combined with Figure 1 A brief introduction to the existing technology:

[0047] The data of FPGA's ARM is transmitted to CPLD's Receive (Receive, RX) through FPGA's Transmit (Transmit, TX). CPLD processes the received data and transmits it to the test equipment connected to the pin header. The test data of the test equipment can also be transmitted to CPLD through the pin header for processing. CPLD's TX transmits the processed test data to FPGA's RX to receive the test data, and then transmits the test data to FPGA's ARM.

[0048] Among them, TX can be a line or port for sending data, and RX can be a line or port for receiving data.

[0049] Therefore, how to solve the low efficiency of ARM testing of FPGA and achieve efficient batch testing has become a technical problem that needs to be solved urgently.

[0050] In view of the technical problems existing in the prior art, the inventors of the present application have the following ideas: in order to optimize the PCB wiring design, minimize the use of pin headers, avoid frequent disassembly of the casing, and improve the test efficiency, a universal asynchronous receiver / transmitter (UART) controller is used to receive the data processed by the CPLD, and transmit it to the peripheral component interconnect express (PCIE) through the bus standard (APB). The central processing unit (CPU) of the test equipment obtains the data processed by the CPLD through the PCIE, and the CPU of the test equipment can also write data to the UART register through the PCIE, and then the FPGA sends the data to the CPLD, and the CPLD summarizes the received data and sends it to the ARM of the FPGA.

[0051] The technical solution of the present application is described in detail below through specific embodiments. It should be noted that the following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0052] It is worth noting that the application fields of the processor performance testing method, system, electronic device and storage medium of the present application are not limited.

[0053] Among them, the executor of this application is an electronic device, which can be a server, terminal device, etc. The terminal device can be a computer, smart phone and other devices.

[0054] Figure 2 Schematic diagram of the process of testing the processor performance provided in the embodiment of the present application Figure 1 ,like Figure 2 As shown, the method may include the following steps:

[0055] Step 21, the UART unit in the device under test responds to the first test request sent by the first test device, sends the first to-be-processed data corresponding to the first test request to the CPLD unit in the device under test, and the first test device is connected to the UART unit by wireless communication.

[0056] In this step, Figure 3 Schematic diagram of the processor performance testing method provided in the embodiment of the present application Figure 1 , combined with Figure 3 A detailed explanation of this step:

[0057] like Figure 3 As shown, the UART unit in the device under test responds to the test request sent by the test device, and uses TX2 of the FPGA to send the test request to RX2 of the CPLD, so that the CPLD can process the test request data.

[0058] The devices under test include CPLD and FPGA. The CPU implements UART communication by configuring read-write control and data registers. Each UART controller provides registers to adjust the baud rate, parameterize parity, stop and data bits, and the UART controller frequency divider register (English: Divisor) calculation formula is:

[0059]

[0060] In a possible implementation, the UART controller has a transmission data width of 8 bits, a stop bit of 1 bit, odd parity, a system frequency of 125 MHz, a UART baud rate of 115200, and a Divisor of 1084 = 0x043C.

[0061] Optionally, step 21 may also be implemented as follows:

[0062] Step 1: The UART unit receives the first test request and stores it in the information queue;

[0063] In this step, after receiving the test request, the UART unit caches the received test request data into an RX First-In-First-Out (FIFO) buffer in the UART.

[0064] The information queue may be a FIFO, and the function of the FIFO is to store data received from the serial interface until the processor can read the data, thereby ensuring that the data is not lost and improving the efficiency of the system. The size of the FIFO may be configured according to chip resources.

[0065] Step 2: When the detection information queue is not empty, the first test request is taken out from the information queue and sent to the CPLD unit.

[0066] In this step, when the FIFO detects that the information queue of the FIFO is not empty, the FPGA will automatically take out the first test request from the FIFO and send it to the CPLD unit at a specific baud rate.

[0067] Optionally, the wireless communication connection mentioned in step 21 may be implemented as follows:

[0068] The wireless communication connection method is the high-speed serial computer expansion bus standard PCIE method.

[0069] In this step, the PCIE interface is mainly used for data transmission between internal components, providing a high-bandwidth and low-latency connection method that can be used to connect wireless network adapters or other related devices to ensure efficient data transmission and processing.

[0070] In one possible implementation, Figure 4 A wireless communication connection diagram of a method for testing processor performance provided in an embodiment of the present application, such as Figure 4 As shown, the UART controller of the FPGA establishes a communication connection with the PCIE unit through the bus standard APB, and then the PCIE unit establishes a communication connection with the CPU of the test equipment through the PCIE protocol.

[0071] Step 22: In response to processing the first data to be processed sent by the CPLD unit, the ARM obtains a first test result and sends it to the CPLD unit.

[0072] In this step, if Figure 3 As shown, TX1 of CPLD receives the first data to be processed through RX1 of FPGA and transmits it to ARM. ARM processes the first data to be processed to obtain a first test result, and then transmits it to RX1 of CPLD through TX1 of FPGA. CPLD receives the first test result.

[0073] Step 23: The UART unit sends the first test result to the first test device in response to the first test result sent by the CPLD unit.

[0074] In this step, combine Figure 3 and Figure 4 , TX2 of CPLD receives the first test result through RX2 of FPGA and transmits it to UART controller, UART controller transmits the first test result to PCIE unit through APB, and then PCIE unit transmits the first test result to CPU of test equipment through wireless communication connection.

[0075] The processor performance testing method provided in the embodiment of the present application first responds to the first test request sent by the first test device through the UART unit in the tested device, sends the first to-be-processed data corresponding to the first test request to the CPLD unit in the tested device, and the first test device is wirelessly connected with the UART unit, and then the ARM responds to the first to-be-processed data sent by the CPLD unit to obtain the first test result, and sends it to the CPLD unit, and finally the UART unit responds to the first test result sent by the CPLD unit and sends the first test result to the first test device. In this technical solution, the wireless communication connection between the test device CPU and the tested device is completed through the UART controller, so as to avoid frequent disassembly of the shell when performing the ARM test of the FPGA and improve the test efficiency.

[0076] Based on the above embodiments, Figure 5 Schematic diagram of the process of testing the processor performance provided in the embodiment of the present application Figure 2 , Figure 6 A schematic diagram of the UART controller architecture of the processor performance testing method provided in the embodiment of the present application is shown in FIG. Figure 5 As shown, the above step 22 may include the following steps:

[0077] Step 51, the UART unit receives the first test result sent by the CPLD unit, and when the amount of data in the information queue where the first test result is located is greater than a preset threshold, sends an interrupt request to the first test device to enable the first test device to obtain the first test result.

[0078] In this step, if Figure 6 As shown, the baud rate setting module is used to set the baud rate of the UART, and the register status module is used to determine the status of the register storage data. After receiving the first test result sent by the CPLD, the UART unit will use the shift register to write the RX data into the RX FIFO. When the storage data amount of the RX FIFO where the first test result is located is greater than the preset threshold, the FPGA will use the interrupt mechanism (Message Signaled Interrupts eXtended, MSI-X) in the PCIE to send an interrupt request (Interrupt Request, IRQ). After receiving the interrupt request, the CPU of the test device will actively read the first test result data stored in the RX FIFO.

[0079] The data is stored in the RX FIFO 1 byte at a time, and the preset threshold may be 128 bytes. The CPU of the test device reads the data stored in the RX FIFO in batches in sequence, 8 bits at a time, and the number of reads depends on the value of the RX data register.

[0080] Optionally, the above step 22 may also be implemented as follows:

[0081] The UART unit receives the first test result sent by the CPLD unit, and when the data storage time of the information queue where the first test result is located is greater than a preset time, sends an interrupt request to the first test device to enable the first test device to obtain the first test result.

[0082] Among them, if the RX FIFO is not empty and no new data is stored in it for more than a preset time, the RX FIFO will use the MSI-X function in PCIE to report an interrupt information to the CPU of the test device.

[0083] Specifically, the preset time length may be 1 second.

[0084] In the processor performance testing method provided by the embodiment of the present application, the UART unit receives the first test result sent by the CPLD unit, and when the amount of data in the information queue where the first test result is located is greater than a preset threshold, an interrupt request is sent to the first test device to enable the first test device to obtain the first test result. In this technical solution, the interrupt request can be controlled by setting the data threshold to avoid frequent interrupt triggering. The system only processes data when the data amount reaches a certain level, thereby improving the efficiency of data processing.

[0085] Based on the above embodiments, Figure 7 Schematic diagram of the process of testing the processor performance provided in the embodiment of the present application Figure 3 , Figure 8 Schematic diagram of the processor performance testing method provided in the embodiment of the present application Figure 2 , the method may include the following steps:

[0086] Step 71: The CPLD unit responds to the second test request sent by the second test device by sending the second to-be-processed data corresponding to the second test request to the ARM unit, and the second test device is connected to the CPLD unit by wired communication.

[0087] In this step, if Figure 8 As shown, the connection method between the second test device and the device under test is to connect the pin header of the device under test using a serial port line. The test device transmits the test request to the pin header of the device under test through the serial port line, and then the pin header transmits it to the CPLD unit. The CPLD processes the test request into second data to be processed, and TX1 of the CPLD transmits the second data to be processed to the ARM unit through RX1 of the FPGA.

[0088] The wired communication connection may be a serial line connection or a USB connection.

[0089] Step 72 , the ARM processes the second data to be processed sent by the CPLD unit, obtains a second test result, and sends the second test result to the CPLD unit, so that the CPLD unit sends the second test result to the second test device.

[0090] In this step, after CPLD transmits the second data to be processed to ARM, ARM processes the second data to be processed to obtain the second test result, and then sends it to RX1 of CPLD through TX1 of PGFA. CPLD sends the received second test result to the second test device through the pin header.

[0091] Optionally, before the above step 22, the method may also be implemented as follows:

[0092] The CPLD unit aggregates and processes the first test request and the second test request to obtain a third test request;

[0093] The CPLD unit takes the third test request as a new first test request and sends it to the ARM unit.

[0094] Specifically, the summary processing is also called AND processing. After receiving the first test request from the first test device and the second test request from the second test device, the CPLD will perform a logic "AND" operation on the two received signals according to the pre-configured logic design based on the internal logic unit of the CPLD. This means that only when both input signals are at a logic high level (that is, 1), the output signal will be a logic high level; if any one of the signals is at a logic low level (that is, 0), the output signal will be a logic low level, and the result of the logic "AND" operation will be used as the third test request, and then the CPLD will use the third test request as a new first test request and send it to the ARM unit.

[0095] The processor performance testing method provided in the embodiment of the present application is that the CPLD unit responds to the second test request sent by the second test device, sends the second data to be processed corresponding to the second test request to the ARM unit, the second test device is connected to the CPLD unit by wired communication, and then the ARM responds to the second data to be processed sent by the CPLD unit to obtain the second test result, and sends it to the CPLD unit, so that the CPLD unit sends the second test result to the second test device. In this technical solution, the ARM unit is tested by the second test device, and the test request obtained by the CPLD is adjusted by summary processing, which enriches the test method of the ARM while ensuring accurate logic control, reducing erroneous or unnecessary test requests, and reducing the probability of false triggering of test requests.

[0096] In one possible implementation, Fig. 9Schematic diagram of the process of testing the processor performance provided in the embodiment of the present application Figure 4 , combined with Fig. 9 A detailed introduction to the implementation:

[0097] Step 1. Get started.

[0098] Step 2. Configure the UART baud rate.

[0099] Step 3. Confirm TX status.

[0100] In this step, the test device CPU confirms the TX state, and if the TX state is ready, execute step 4.

[0101] Step 4. Calculate the remaining space in TX FIFO.

[0102] In this step, the test equipment CPU calculates the remaining space of the TX FIFO.

[0103] Step 5. Write data to TX FIFO.

[0104] In this step, the test equipment CPU writes the test data into the TX FIFO.

[0105] Step 6: Determine whether the TX FIFO is empty.

[0106] In this step, if the TX FIFO is empty, then write data into the TX FIFO. If the TX FIFO is not empty, execute step 7.

[0107] Step 7. Load TX data into the buffer.

[0108] Step 8: TX data shift processing.

[0109] Step 9: Determine whether the shift is completed.

[0110] If the process is completed, the next data storage process will be executed; if not, the shift process will continue.

[0111] Step 10. End.

[0112] In one possible implementation, Fig.10 Schematic diagram of the process of testing the processor performance provided in the embodiment of the present application Figure 5 , combined with Fig.10 A detailed introduction to the implementation:

[0113] Step 1. Get started.

[0114] Step 2. Configure the UART baud rate.

[0115] Step 3: RX data input.

[0116] In this step, the FPGA receives the RX data from the test equipment.

[0117] Step 4: RX shift processing.

[0118] Step 5: Determine whether the shift is completed.

[0119] In this step, if the shift is not completed, the shift process continues; if the shift is completed, step 6 is executed.

[0120] Step 6. Write to RX FIFO.

[0121] In this step, the FPGA writes the received test data into the RX FIFO.

[0122] Step 7: Determine whether an interrupt request report is required.

[0123] In this step, the FPGA checks the status of the RX FIFO to determine whether an interrupt request needs to be reported.

[0124] Step 8: Interrupt request reception.

[0125] In this step, the CPU of the test device receives the interrupt request sent by the FPGA, and executes step 9 after the reception is completed.

[0126] Step 9. Read the RX data register.

[0127] In this step, the CPU of the test equipment reads the value of the RX data register.

[0128] Step 10. Read RX FIFO data.

[0129] In this step, the CPU of the test equipment reads the data stored in the RX FIFO.

[0130] Fig.11 A schematic diagram of a processor performance testing system provided in an embodiment of the present application includes: a device under test and a first testing device.

[0131] The processor performance testing system provided in the embodiment of the present application, the device under test in the system can be used to execute the processor performance testing method provided in any of the above method embodiments, and its implementation principles and technical effects are similar and will not be repeated here.

[0132] Fig.12 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application, such as Fig.12As shown, the electronic device may include: a processor 121, a memory 122, and computer program instructions stored in the memory 122 and executable on the processor 121, and the processor 121 implements the method provided in any of the foregoing embodiments when executing the computer program instructions.

[0133] Optionally, the above-mentioned components of the electronic device may be connected via a system bus.

[0134] The memory 122 may be a separate storage unit or a storage unit integrated in the processor 121. The number of the processor 121 is one or more.

[0135] It should be understood that the processor 121 may be a central processing unit (CPU), or other general-purpose processors 121, digital signal processors 121 (DSP), application-specific integrated circuits (ASIC), etc. The general-purpose processor 121 may be a microprocessor 121 or the processor 121 may be any conventional processor 121, etc. The steps of the method disclosed in the present application may be directly embodied as being executed by the hardware processor 121, or may be executed by a combination of hardware and software modules in the processor 121.

[0136] The system bus may be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The system bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, only one thick line is used in the figure, but it does not mean that there is only one bus or one type of bus. The memory 122 may include a random access memory 122 (RAM), and may also include a non-volatile memory 122 (NVM), such as at least one disk storage 122.

[0137] All or part of the steps of the above-mentioned method embodiments can be completed by hardware related to program instructions. The above-mentioned program can be stored in a readable memory 122. When the program is executed, the steps of the above-mentioned method embodiments are executed; and the above-mentioned memory 122 (storage medium) includes: read-only memory 122 (ROM), RAM, flash memory 122, hard disk, solid state hard disk, magnetic tape, floppy disk, optical disc and any combination thereof.

[0138] The electronic device provided in the embodiment of the present application can be used to execute the method provided in any of the above method embodiments. Its implementation principles and technical effects are similar and will not be repeated here.

[0139] An embodiment of the present application provides a computer-readable storage medium, in which computer instructions are stored. When the computer instructions are executed on a computer, the computer executes the above method.

[0140] The computer-readable storage medium mentioned above can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory, electrically erasable programmable read-only memory, erasable programmable read-only memory, programmable read-only memory, read-only memory, magnetic memory, flash memory, magnetic disk or optical disk. The readable storage medium can be any available medium that can be accessed by a general or special-purpose computer.

[0141] Optionally, a readable storage medium is coupled to a processor so that the processor can read information from the readable storage medium and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can be located in an application specific integrated circuit (ASIC). Of course, the processor and the readable storage medium can also exist in the device as discrete components.

[0142] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A method for testing processor performance, characterized in that: Applied to a device under test, wherein a processor ARM to be tested is deployed in the device under test, the method comprises: The unified asynchronous receiver / transmitter (UART) unit in the device under test responds to a first test request sent by a first test device, sending first to-be-processed data corresponding to the first test request to a complex programmable logic device (CPLD) unit in the device under test, and the first test device is connected to the UART unit through wireless communication; The ARM processes the first data to be processed sent by the CPLD unit in response to obtaining a first test result and sends the first test result to the CPLD unit; The UART unit sends the first test result to the first test device in response to the first test result sent by the CPLD unit.

2. The method according to claim 1, characterized in that The UART unit sends the first test result to the first test device in response to the first test result sent by the CPLD unit, including: The UART unit receives the first test result sent by the CPLD unit, and when the amount of data in the information queue where the first test result is located is greater than a preset threshold, sends an interrupt request to the first test device to enable the first test device to obtain the first test result.

3. The method according to claim 1, characterized in that The UART unit sends the first test result to the first test device in response to the first test result sent by the CPLD unit, including: The UART unit receives the first test result sent by the CPLD unit, and when the data storage time of the information queue where the first test result is located is greater than a preset time, sends an interrupt request to the first test device to enable the first test device to obtain the first test result.

4. The method according to any one of claims 1 to 3, characterized in that: The UART unit in the device under test sends first to-be-processed data corresponding to the first test request to the CPLD unit in response to the first test request sent by the first test device, including: The UART unit receives the first test request and stores it in an information queue; When it is detected that the information queue is not empty, the first test request is taken out from the information queue and sent to the CPLD unit.

5. The method according to any one of claims 1 to 3, characterized in that: The method further comprises: The CPLD unit sends second to-be-processed data corresponding to the second test request to the ARM unit in response to a second test request sent by a second test device, and the second test device is connected to the CPLD unit by wired communication; In response to processing the second data to be processed sent by the CPLD unit, the ARM obtains a second test result and sends the second test result to the CPLD unit, so that the CPLD unit sends the second test result to the second test device.

6. The method according to claim 5, characterized in that The method further comprises: The CPLD unit aggregates and processes the first test request and the second test request to obtain a third test request; The CPLD unit uses the third test request as a new first test request and sends it to the ARM unit.

7. The method according to any one of claims 1 to 3, characterized in that: The wireless communication connection mode is a high-speed serial computer expansion bus standard PCIE mode.

8. A processor performance testing system, characterized in that: The system comprises: a device under test as described in any one of claims 1 to 7 and a first testing device.

9. An electronic device, characterized in that: include: A processor, and a memory communicatively connected to the processor; The memory stores computer-executable instructions; The processor executes the computer-executable instructions stored in the memory to implement the method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, which are used to implement the method according to any one of claims 1 to 7 when executed by a processor.

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