Bus interconnection module, computing device, system on chip and bus communication method

Abstract

The embodiment of the invention provides a bus interconnection module, computing equipment, a system on chip and a bus communication method, and the scheme is suitable for various chips including a CISC instruction set, an RISC reduced instruction set (especially an RISC-V instruction set) or a VLIM instruction set architecture, such as an Internet of Things chip, an audio / video chip and the like. The bus interconnection module comprises a plurality of master control units and a plurality of slave control units, the main control unit is used for temporarily storing an address read-write request if the address read-write request meets a reverse channel deadlock condition after receiving the address read-write request, and sending the address read-write request to the corresponding slave control unit after determining that the address read-write request does not meet the reverse channel deadlock condition; and the slave control unit is used for issuing the address read-write request after receiving the address read-write request. According to the scheme, the bus utilization rate can be ensured while reverse channel deadlock is avoided.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of chip technology, and in particular to a bus interconnection module, a computing device, a system on chip, and a bus communication method. Background Art

[0002] The Advanced eXtensible Interface (AXI) bus protocol is a high-performance, high-bandwidth on-chip bus protocol that is widely used in system-on-chip (SOC). The AXI bus adopts a transmission mechanism that separates reads and writes, and separates addresses / controls from data. It improves transmission efficiency through five independent transmission channels: read address channel (AR), read data channel (R), write address channel (AW), write data channel (W), and write response channel (B). Data is exchanged between multiple master devices (master) and multiple slave devices (slave) through the bus interconnection module. Since the bus interconnection module supports the out-of-order (OoO) access mechanism, it is easy to cause reverse channel deadlock in the AXI bus.

[0003] Currently, backchannel deadlock is circumvented through a single slave device or a Single Slave PerID (SPI) mechanism where the same transaction identifier can only be used for a single slave device.

[0004] However, when the SPI mechanism is triggered, the entire bus of the master device will be blocked, causing subsequent transactions without the possibility of deadlock to be blocked, resulting in low bus utilization. Summary of the invention

[0005] In view of this, embodiments of the present application provide a bus interconnection module, a computing device, a system on chip, and a bus communication method to at least solve or alleviate the above-mentioned problems.

[0006] According to a first aspect of an embodiment of the present application, a bus interconnection module is provided, comprising: a plurality of master control units and a plurality of slave control units; the master control unit is used to, after receiving an address read / write request, temporarily store the address read / write request if the address read / write request satisfies a reverse channel deadlock condition, and after determining that the address read / write request does not satisfy the reverse channel deadlock condition, send the address read / write request to the corresponding slave control unit; the slave control unit is used to issue the address read / write request after receiving the address read / write request.

[0007] According to a second aspect of an embodiment of the present application, there are provided a plurality of master devices, a plurality of slave devices and a bus interconnection module according to the first aspect above; the master device is used to send an address read / write request to the slave device through the bus interconnection module; the slave device is used to send the stored data to be read to the master device through the bus interconnection module in response to the address read / write request, or to receive the data to be written sent by the master device through the bus interconnection module.

[0008] According to a third aspect of an embodiment of the present application, a system on chip is provided, comprising: multiple master devices and a bus interconnection module according to the first aspect above; the master device is used to send address read and write requests to a slave device through the bus interconnection module, and the slave device is included in the system on chip or connected to the system on chip through an I / O interface on the system on chip; the slave device is used to respond to the address read and write request, send stored data to be read to the master device through the bus interconnection module, or receive data to be written sent by the master device through the bus interconnection module.

[0009] According to the fourth aspect of an embodiment of the present application, a bus communication method is provided, comprising: after receiving an address read / write request, if the address read / write request satisfies a reverse channel deadlock condition, the master control unit temporarily stores the address read / write request, and after determining that the address read / write request does not satisfy the reverse channel deadlock condition, sends the address read / write request to a corresponding slave control unit; after receiving the address read / write request, the slave control unit sends the address read / write request.

[0010] According to the bus interconnection module provided by the embodiment of the present application, after receiving the address read / write request, the main control unit can determine whether the address read / write request satisfies the reverse channel deadlock condition. If the address read / write request satisfies the reverse channel deadlock condition, the address read / write request is temporarily stored, and after the address read / write request no longer satisfies the reverse channel deadlock condition, the address read / write request is sent to the slave control unit, and the slave control unit issues the address read / write request. By temporarily storing the address read / write request that may cause the reverse channel deadlock, the occurrence of the reverse channel deadlock can be avoided. After temporarily storing the address read / write request that may cause the reverse channel deadlock, the subsequent address read / write request without the possibility of deadlock can still be transmitted normally, thereby avoiding the reverse channel deadlock while improving the bus utilization rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of the present application. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0012] Figure 1 is a schematic diagram of a computing device according to an embodiment of the present application;

[0013] Figure 2 is a schematic diagram of a system on a chip according to an embodiment of the present application;

[0014] Figure 3 is a schematic diagram of a bus interconnection module according to an embodiment of the present application;

[0015] Figure 4 is a schematic diagram of a reverse channel deadlock in one embodiment of the present application;

[0016] Figure 5 is a schematic diagram of a main control unit of an embodiment of the present application;

[0017] Figure 6 is a schematic diagram of a bus interconnection module according to another embodiment of the present application;

[0018] Figure 7 is a schematic diagram of a forward channel deadlock in one embodiment of the present application;

[0019] Figure 8 is a schematic diagram of a slave control unit according to an embodiment of the present application;

[0020] Fig. 9 is a schematic diagram of a bus interconnection module of yet another embodiment of the present application;

[0021] Fig.10 It is a flowchart of a bus communication method according to an embodiment of the present application. DETAILED DESCRIPTION

[0022] The present application is described below based on embodiments, but the present application is not limited to these embodiments. In the detailed description of the present application below, some specific details are described in detail. It is possible for a person skilled in the art to fully understand the present application without the description of these details. In order to avoid confusing the essence of the present application, known methods, processes, and flows are not described in detail. In addition, the drawings are not necessarily drawn to scale.

[0023] First, some nouns or terms that appear in the process of describing the embodiments of the present application are subject to the following explanations.

[0024] Advanced eXtensible Interface bus protocol: The Advanced eXtensible Interface (AXI) bus protocol is a high-performance, high-bandwidth on-chip bus protocol that is widely used in system-on-chip (SOC).

[0025] Bus interconnect module: In the AXI bus protocol, multiple master devices (Master) and multiple slave devices (Slave) exchange data through a bus interconnect module (Interconnect), which is also called a bus matrix (BusMatrix).

[0026] Deadlock: In the AXI bus protocol, deadlock refers to a state in which at least one master device (Master) and / or at least one slave device (Slave) cannot continue to communicate effectively due to improper management of bus transactions or defects in the protocol implementation.

[0027] Reverse channel deadlock: During the AXI bus transmission process, the master device uses an ID number to mark each transmission. The bus interconnection module distinguishes different master devices by extending the ID number of each master device. For different transmissions sent by the same master device using the same ID, different transmissions need to be performed in sequence, and the slave device can return transmissions with different ID numbers in an out-of-order (OoO) manner. This mechanism may form a cyclic dependency (Cyclic Dependence) between handshake signals when multiple master devices access multiple slave devices at the same time, thereby causing deadlock. Since this type of deadlock is caused by the out-of-order mechanism of the slave device in the write response channel (B), this type of deadlock is called a reverse channel deadlock.

[0028] Forward channel deadlock: During the AXI bus transmission process, for the same slave device, it is allowed to receive the write data of the next transmission only after the write data of one transmission is received. Therefore, although a master device can simultaneously initiate multiple address / control commands on the write address channel (AW) to negotiate access rights to multiple slave devices, within a transmission cycle, a slave device is only allowed to exchange data with the only master device that has been granted access rights on the write data channel (W). Due to the above mechanism, there is a risk of deadlock when multiple master devices and multiple slave devices exchange data. This type of deadlock is called forward channel deadlock.

[0029] Computing equipment

[0030] Figure 1A schematic block diagram of a computing device 10 according to an embodiment of the present application is shown. The computing device 10 is, for example, a computer system, which can be constructed based on various types of processors currently on the market and driven by operating systems such as WINDOWS operating system, UNIX operating system, Linux operating system, etc. The computing device 10 can be a laptop computer, a desktop computer, a workbench, a personal digital assistant (PDA), a server, a blade server, a mainframe computer, and a mobile communication device. The computing device 10 in the embodiment of the present application is not limited to any specific combination of hardware circuits and software.

[0031] like Figure 1 As shown, the computing device 10 includes a plurality of main devices 12. The main device 12 has a data processing capability known in the art. The main device 12 may be a CISC architecture, a RISC architecture, a VLIW architecture, or an architecture of the above instruction set combination, or any processor device built for a dedicated purpose. Exemplarily, the main device 12 includes a central processing unit (CPU), a graphics processing unit (GPU), a general-purpose graphics processing unit (GPGPU), a neural network processor (NPU), a tensor processor (TPU), a deep learning processor (DPU) or an infrastructure processor (IPU). The main device 12 may include one or more processor cores, and the main device 12 is used to process and execute instructions, and the processing and execution of instructions can be controlled by a user (e.g., by an application) and / or a system platform.

[0032] The computing device 10 further includes a plurality of slave devices 14 and a bus interconnection module 16. The master device 12 and the slave device 14 are coupled to the bus interconnection module 16. The bus interconnection module 16 may be an interconnection circuit for connecting the master device 12 and the slave device 14, and the interconnection circuit may support various interconnection protocols and interface circuits, thereby realizing communication between the master device 12 and the slave device 14. In one example, the bus interconnection module 16 supports the AXI bus protocol, and the master device 12 and the slave device 14 communicate through the bus interconnection module 16 based on the AXI bus protocol.

[0033] The slave device 14 may be various types of input / output (I / O) devices, such as a memory, an input device, an output device, a storage device, a communication device, etc. The memory is used to store instruction information and / or data information represented by a digital signal, and the memory may be a dynamic random access memory (DRAM), a static random access memory (SRAM), a flash memory or other memory. The input device may be a keyboard, a mouse, a microphone, a camera, etc. The output device may be various types of displays, speakers, etc. The storage device may be a disk, an optical disk, etc. The communication device may be a network card, a modem, a wireless communication transceiver, etc. The communication device allows the computing device 10 to exchange information or data with other devices or systems through a computer network such as the Internet and / or various telecommunication networks.

[0034] It should be noted that the structure of different computing devices 10 may vary according to the motherboard, operating system and instruction set architecture. For example, some computing devices 10 are currently provided with an input-output control center connected between the bus interconnection module 16 and the master device 12 or the slave device 14, and the input-output control center may be integrated into the master device 12 or the slave device 14 or be independently provided from the master device 12 and the slave device 14, which is not limited in the embodiments of the present application.

[0035] The embodiment of the present application mainly focuses on the process of the bus interconnection module 16 transmitting requests and data between the master device 12 and the slave device 14, so as to reduce the risk of reverse channel deadlock and forward channel deadlock during the communication process between multiple devices 12 and multiple slave devices 14. The specific details of the structure of the bus interconnection module 16 and the data transmission process will be described in detail later.

[0036] System on Chip

[0037] Figure 2A schematic block diagram of a system on a chip 20 of an embodiment of the present application is shown. A system on a chip (System on a chip, SOC) can be produced and sold as an independent device, or it can be combined with other components to form a new device for production and sales. The system on a chip 20 can be manufactured using a variety of processor models currently on the market, and can be driven by operating systems such as WINDOWSTM, UNIX, Linux, Android, and RTOS. The system on a chip 20 can be implemented in computer devices, handheld devices, and embedded devices. Some examples of handheld devices include cellular phones, Internet protocol devices, digital cameras, PDAs, and handheld computers (Personal Computer, PC). Some examples of embedded devices can include network computers (Net PC), set-top boxes, network hubs, wide area networks (Wide Area Network, WAN) switches, etc., and embedded devices can also be any other systems that execute one or more instructions.

[0038] like Figure 2 As shown, the system on chip 20 includes multiple main devices 22. The main device 22 has data processing capabilities known in the art. The main device 22 can be a CISC architecture, a RISC architecture, a VLIW architecture, or an architecture of a combination of the above instruction sets, or any processor device built for a dedicated purpose. Exemplarily, the main device 22 includes a CPU, a GPU, a GPGPU, an NPU, a TPU, a DPU, an IPU, etc. The main device 22 may include one or more processor cores, and the main device 22 is used to process and execute instructions, and the processing and execution of instructions can be controlled by a user (e.g., by an application) and / or a system platform.

[0039] The system on chip 20 also includes a bus interconnection module 26, the master device 22 is coupled to the bus interconnection module 26, and the bus interconnection module 26 may be an interconnection circuit for connecting the master device 22 and the slave device 24. Exemplarily, the bus interconnection module 26 may support the AXI bus protocol, and the master device 22 and the slave device 24 communicate based on the AXI bus protocol through the bus interconnection module 26. With the increase in the complexity of SOC design and the continuous improvement of processor capabilities, the SOC may have various choices for the bus interconnection module 26, which is not limited in this application.

[0040] The slave device 24 may be an I / O device such as a DRAM, SRAM or flash memory included in the system on chip 20. The SRAM and flash memory are used to store instruction information and / or data information represented by digital signals. For example, the SRAM can be used as a running space for various applications (Application, APP), creating a heap, a stack, storing intermediate data, etc. for various applications. The flash memory can store executable codes of various applications and executable codes of the operating system.

[0041] The system on chip 20 may also include various input / output (I / O) interfaces 28 coupled to the bus interconnection module 26, and the I / O interfaces 28 include but are not limited to the following interface types: Secure Digital High Capacity (SDHC) interface, two-wire serial bus (Inter-Integrated Circuit, I2C), serial peripheral interface (Serial Peripheral Interface, SPI), Universal Asynchronous Receiver Transmitter (UART), Universal Serial Bus (USB), General-purpose input / output (GPIO) and Bluetooth UART. Based on the I / O interface 28, the system on chip 20 can be coupled to peripheral devices of corresponding interface types, such as USB devices, memory cards, message transceivers, Bluetooth devices, etc. The slave device 24 can be an I / O device coupled to the system on chip 20 through the I / O interface 28.

[0042] It should be noted that Figure 1 The computing device 10 and Figure 2 The system on chip 20 shown is used to exemplarily describe some application scenarios of the embodiment of the present application, but is not intended to limit the embodiment of the present application. The embodiment of the present application realizes the improvement of the bus interconnection module, so in theory it can be applied to any device or system including a bus interconnection module.

[0043] Bus interconnection module

[0044] Figure 3 It is a schematic block diagram of a bus interconnection module 30 according to an embodiment of the present application. The bus interconnection module 30 may have the same or similar structure as the above-mentioned bus interconnection module 16 and bus interconnection module 26.

[0045] like Figure 3As shown, the bus interconnection module 30 includes multiple master control units 32 and multiple slave control units 34. After receiving the address read / write request, the master control unit 32 can determine whether the address read / write request meets the reverse channel deadlock condition, and after determining that the address read / write request meets the reverse channel deadlock condition, temporarily store the address read / write request. During the temporary storage of the address read / write request, the master control unit 32 will also determine whether the address read / write request meets the reverse channel deadlock condition, and after determining that the address read / write request does not meet the reverse channel deadlock condition, send the address read / write request to the corresponding slave control unit 34. After receiving the address read / write request sent by the master control unit 32, the slave control unit 34 sends the address read / write request.

[0046] The reverse channel deadlock condition is used to determine whether an address read or write request may trigger a reverse channel deadlock. If an address read or write request meets the reverse channel deadlock condition, the address read or write request may trigger a reverse channel deadlock after being issued. If the address read or write request does not meet the reverse channel deadlock condition, the address read or write request will not trigger a reverse channel deadlock after being issued.

[0047] An address read / write request can be an address read request or an address write request. Both address read requests and address write requests may cause a back channel deadlock. An address read request is transmitted through the read address channel (AR) to obtain the read address of the slave device. After the master device obtains the read address, it can perform a read operation on the read address on the slave device through the read data channel (R) to obtain the data to be read. An address write request is transmitted through the write address channel (AW) to obtain the write address of the slave device. After the master device obtains the write address, it can perform a write operation on the write address on the slave device through the write data channel (W) to write the data to be written into the slave device.

[0048] The following example illustrates the occurrence of reverse channel deadlock. Figure 4As shown, master device 0 and master device 1 use the same ID to send address read / write requests to slave device A and slave device B, and slave device A and slave device B return responses to master device 0 and master device 1. Master device 0 first sends address read / write request M01 to slave device A, and then sends address read / write request M02 to slave device B. Master device 0 needs to get response SA0 from slave device A first, and then get response SB0 from slave device B. Master device 1 first sends address read / write request M11 to slave device B, and then sends address read / write request M12 to slave device A. Master device 1 needs to get response SB1 from slave device B first, and then get SA1 from slave device A. Since slave devices can return responses to received address read / write requests in a disordered manner, the order in which slave devices return responses may be different from the order in which address read / write requests are issued. Slave device A needs to respond to master device 1 first, and slave device B needs to respond to master device 0 first. At this time, master device 0, master device 1, slave device A, and slave device B have a circular dependency, resulting in a reverse channel deadlock.

[0049] After receiving an address read / write request that may cause a reverse channel deadlock, the master control unit 32 will first temporarily store the address read / write request. As the slave device completes responding to other address read / write requests, the address read / write request will no longer cause a reverse channel deadlock. Then the master control unit 32 sends the address read / write request to the corresponding slave control unit 34, which is then sent down by the slave control unit 34. After the master control unit 32 temporarily stores an address read / write request that may cause a reverse channel deadlock, the master control unit 32 can also receive a subsequent address read / write request of the address read / write request. If the subsequent address read / write request will not cause a reverse channel deadlock, the master control unit 32 can send the subsequent address read / write request to the slave control unit 32 before the temporarily stored address read / write request, and then the slave control unit 32 sends the subsequent address read / write request before the temporarily stored address read / write request.

[0050] In the embodiment of the present application, after receiving the address read / write request, the master control unit 32 can determine whether the address read / write request satisfies the reverse channel deadlock condition. If the address read / write request satisfies the reverse channel deadlock condition, the address read / write request is temporarily stored, and after the address read / write request no longer satisfies the reverse channel deadlock condition, the address read / write request is sent to the slave control unit 34, and the slave control unit 34 issues the address read / write request. By temporarily storing the address read / write request that may cause the reverse channel deadlock, the occurrence of the reverse channel deadlock can be avoided. After temporarily storing the address read / write request that may cause the reverse channel deadlock, the subsequent address read / write request without the possibility of deadlock can still be transmitted normally, thereby avoiding the reverse channel deadlock and improving the bus utilization.

[0051] In one possible implementation, Figure 5The schematic block diagram of the main control unit 32 shown in FIG. 3 includes a first detection subunit 321 , a second detection subunit 322 , a first buffer 323 , a first output subunit 324 and a first arbitration subunit 325 .

[0052] The first detection subunit 321 can receive an address write request and update the detection information of the received address write request into the first detection information. The detection information of the address write request includes the identification information of the address write request and the identification information of the destination slave device of the address write request. The identification information of the address write request is used to identify the address write request. Different address write requests correspond to different identification information. The destination slave device of the address write request is the transmission destination of the address write request. The first detection information may include the detection information of multiple address write requests.

[0053] After the first detection sub-unit 321 updates the detection information of the received address write request to the first detection information, it can detect whether the address write request meets the reverse channel deadlock condition based on the first detection information. If the address write request does not meet the reverse channel deadlock condition, the address write request is sent to the first output sub-unit 324. If the address write request meets the reverse channel deadlock condition, the address write request is temporarily stored at the end of the first buffer 323.

[0054] The first detection information includes the detection information of the address write request that has been temporarily stored, and the detection information of the address write request that has been sent to the slave control unit 34 but has not received the corresponding response information. The response information is sent by the destination slave device of the address write request based on the address write request. The first detection subunit 321 can match the first detection information with the reverse channel deadlock condition to determine whether the address write request just received may cause the reverse channel deadlock. The address write request of a single slave device (singleslave) or the same ID can only be used for a single slave device (single slave per ID) will not cause the reverse channel deadlock. The reverse channel deadlock condition can be set based on the rule. The first detection subunit 321 can detect whether the address write request may cause the reverse channel deadlock by various deadlock detection algorithms based on the reverse channel deadlock condition. If the address write request may cause the reverse channel deadlock, the address write request meets the reverse channel deadlock condition. If the address write request does not cause the reverse channel deadlock, the address write request does not meet the reverse channel deadlock condition.

[0055] The first buffer 323 temporarily stores address write requests in the form of a queue, and the address write request that is temporarily stored first is located before the address write request that is temporarily stored later. After the first detection sub-unit 321 determines that the received address write request meets the reverse channel deadlock condition, it temporarily stores the address write request at the end of the first buffer 323, that is, temporarily stores the address write request at the end of the address write request queue in the first buffer 323.

[0056] The second detection subunit 322 can detect whether the address write request at the first position in the first buffer 323 meets the reverse channel deadlock condition according to the first detection information, and after determining that the address write request at the first position in the first buffer 323 does not meet the reverse channel deadlock condition, send the address write request at the first position in the first buffer 323 to the first output subunit 324. The address write request at the first position in the first buffer 323 refers to the address write request at the head of the address write request queue in the first buffer 323.

[0057] The detection information of the address write request for which the corresponding response information is received will be deleted from the first detection information. After the corresponding detection information is deleted from the first detection information, it indicates that the address write request has been transmitted. The completion of the transmission of the address write request may make one or more temporarily stored address write requests no longer cause a reverse channel deadlock. After the detection information of the address write request is deleted from the first detection information, the second detection subunit 322 detects whether the address write request at the first position in the first buffer 323 meets the reverse channel deadlock condition based on the first detection information. After determining that the address write request at the first position in the first buffer 323 does not meet the reverse channel deadlock condition, the address write request is sent to the first output subunit 324.

[0058] After receiving the address write request from the first detection subunit 321 or the second detection subunit 322, the first output subunit 324 sends the address write request to the corresponding slave control unit 34, and the slave control unit 34 sends the address write request. The transmission path corresponding to the address write request is determined based on the type of the address write request, the master device that issues the address write request, and the destination slave device of the address write request. The transmission path is composed of at least one group of master control units 32 and slave control units 34, so that the first output subunit 324 can send the address write request to the corresponding slave control unit 34 according to the transmission path corresponding to the address write request.

[0059] The first arbitration sub-unit 325 can receive response information corresponding to the address write request sent from the control unit 34, and after receiving the response information corresponding to a certain address write request, delete the detection information of the address write request from the first detection information, so that the address write request in the first buffer 323 that has a circular dependency on the address write request can be determined by the second detection sub-unit 322 as no longer satisfying the reverse channel deadlock condition, and can thus continue to be transmitted.

[0060] After receiving the response information corresponding to a certain address write request, the first arbitration subunit 325 will upload the response information. The address write request and the corresponding response information are transmitted through the same transmission path. The address write request is transmitted through the write address channel constructed by the master control unit 32 and the slave control unit 34 in the transmission path, and the response information is transmitted through the write response channel constructed by the master control unit 32 and the slave control unit 34 in the transmission path. The transmission direction of the write address channel is from the master device to the slave device, and the transmission direction of the write response channel is from the slave device to the master device.

[0061] The first arbitration subunit 325 can be connected to a master device, in which case the first arbitration subunit 325 uploads the received response information to the connected master device. The first arbitration subunit 325 can also be connected to another slave control unit 34, in which case the first arbitration subunit 325 receives response information from one slave control unit 34 and uploads the received response information to another slave control unit 34.

[0062] When the first arbitration subunit 325 receives multiple response messages at the same time, it will delete the detection information of the address write request corresponding to each response message from the first detection information in turn based on the arbitration algorithm, and upload each response message accordingly. The arbitration algorithm can be any suitable algorithm, for example, the priority of the response information can be determined according to the priority of the corresponding master device or slave device, and the response information can be uploaded according to the priority. The embodiment of the present application does not limit the arbitration algorithm.

[0063] In an embodiment of the present application, after receiving an address write request, the first detection subunit 321 detects whether the address write request satisfies the reverse channel deadlock condition. If the address write request does not satisfy the reverse channel deadlock condition, the address write request is sent to the first output subunit 324. If the address write request satisfies the reverse channel deadlock condition, the address write request is temporarily stored in the first buffer 323. After the second detection subunit 322 determines that the address write request no longer satisfies the reverse channel deadlock condition, the address write request is sent to the first output subunit 324. After receiving the address write request, the second output subunit 324 sends the received address write request to the corresponding slave control unit 34, thereby ensuring that the reverse channel deadlock does not occur and the bus is not blocked. Address write requests without the possibility of deadlock can still be transmitted normally, thereby improving the utilization rate of the bus.

[0064] The first detection sub-unit 321 stores the detection information of the temporarily stored address write request and the detection information of the address write request that has been sent to the slave control unit 34 but has not received the corresponding response information in the first detection information, and the first arbitration sub-unit 325 deletes the detection information of the address write request corresponding to the received response information from the first detection information, so that the first detection sub-unit 321 can accurately determine whether the received address write request will cause a reverse channel deadlock based on the first detection information, and the second detection sub-unit 322 can accurately determine whether the temporarily stored address write request will cause a reverse channel deadlock based on the first detection information, thereby avoiding the sending of the address write request that may cause a reverse channel deadlock and reducing the risk of a reverse channel deadlock.

[0065] In one possible implementation, Figure 5 As shown, the main control unit 32 further includes a third detection subunit 326 , a second buffer 327 , a third buffer 328 and a second output subunit 329 .

[0066] After the first detection subunit 321 determines that the address write request meets the reverse channel deadlock condition, it will temporarily store the address write request at the end of the first buffer 323, and at the same time store the identification information of the destination slave device of the address write request at the end of the third buffer 328. After receiving the data to be written, the third detection subunit 326 will compare the number of data to be written in the second buffer 327 with the number of identification information of the slave device in the third buffer 328. If the number of data to be written in the second buffer 327 is less than the number of identification information of the slave device in the third buffer 328, the received data to be written will be temporarily stored at the end of the second buffer 327. If the number of data to be written in the second buffer 327 is equal to the number of identification information of the slave device in the third buffer 328, the received data to be written will be sent to the second output subunit 329.

[0067] The order in which the same main control unit 32 receives multiple address write requests matches the order in which the data to be written corresponding to the multiple address write requests are received, that is, the nth data to be written received by the third detection subunit 326 is the data to be written corresponding to the nth address write request received by the first detection subunit 321. After the first detection subunit 321 temporarily stores the received nth address write request at the end of the first buffer 323, it stores the identification information of the destination slave device of the address write request at the end of the third buffer 328. After the third detection subunit 326 receives the nth data to be written, since the number of data to be written in the second buffer 327 is less than the number of identification information of the slave device in the third buffer 328, the third detection subunit 326 temporarily stores the received nth data to be written at the end of the second buffer 327.

[0068] If the number of identification information of the slave device in the third buffer 328 is equal to the number of data to be written in the second buffer 327, it means that the address write request newly received by the first detection subunit 321 has not been temporarily stored in the first buffer 323, and the corresponding third detection subunit 326 does not need to temporarily store the newly received data to be written in the second buffer 327, but directly sends the newly received data to be written to the second output subunit 329. If the number of identification information of the slave device in the third buffer 328 is greater than the number of data to be written in the second buffer 327, it means that the address write request corresponding to the data to be written newly received by the third detection subunit 326 has been temporarily stored in the first buffer 323, so the third detection subunit 326 temporarily stores the newly received data to be written at the end of the second buffer 327.

[0069] The second buffer 327 temporarily stores the data to be written in the form of a queue, and the data to be written that is temporarily stored first is located before the data to be written that is temporarily stored later. The third buffer 328 temporarily stores the identification information of the slave device in the form of a queue, and the identification information of the slave device that is temporarily stored first is located before the identification information of the slave device that is temporarily stored later. The slave device identified by the identification information of the i-th slave device in the third buffer 328 is the destination slave device of the i-th data to be written in the second buffer 327.

[0070] When the first output subunit 324 sends the address write request from the first detection subunit 321 to the corresponding slave control unit 34, the second output subunit 329 sends the data to be written from the third detection subunit 326 to the corresponding slave control unit 34. When the first output subunit 324 sends the address write request from the second detection subunit, the second output subunit 329 takes out the data to be written at the first position in the second buffer 327 from the second buffer 327 and sends it to the corresponding slave control unit 34.

[0071] If the first detection subunit 321 sends the address write request to the first output subunit 324, it means that the address write request does not meet the reverse channel deadlock condition, and the address write request will be sent to the corresponding slave control unit 34 by the first output subunit 324, and the to-be-written data sent by the corresponding third detection subunit 326 to the second output subunit 329 is the to-be-written data corresponding to the address write request, so that the second output subunit 329 sends the to-be-written data from the third detection subunit 326 to the corresponding slave control unit 34. If the second detection subunit 322 sends the address write request to the first output subunit 324, it means that the address write request no longer meets the reverse channel deadlock condition after being temporarily stored, and the address write request will be sent to the corresponding slave control unit 34 by the first output subunit 324, and the to-be-written data at the first position in the corresponding second buffer 327 is the to-be-written data corresponding to the address write request, so that the second output subunit 329 takes out the to-be-written data at the first position from the second buffer 327 and sends it to the corresponding slave control unit 34.

[0072] After the second output sub-unit 329 sends the write data to be written at the first position in the second buffer 327 to the corresponding slave control unit 34, the third detection sub-unit 326 deletes the identification information of the slave device at the first position in the third buffer 328, to ensure that the identification information of the i-th slave device in the third buffer 328 can indicate the slave device corresponding to the i-th data to be written in the second buffer 327.

[0073] In the embodiment of the present application, after the first detection subunit 321 temporarily stores the address write request that satisfies the reverse channel deadlock in the first buffer 323, the third detection subunit 326 temporarily stores the data to be written corresponding to the address write request in the second buffer 327. When the first output subunit 324 sends the address write request from the first detection subunit 321 to the slave control unit 34, the second output subunit 329 sends the data to be written from the third detection subunit 326 to the slave control unit 34. When the first output subunit 324 sends the address write request from the second detection subunit 322 to the slave control unit 34, the second output subunit 329 sends the data to be written at the first position in the second buffer 327 to the slave control unit 34, ensuring that the data to be written corresponding to the address write request is issued in the order in which the address write request is issued, thereby avoiding the occurrence of reverse channel deadlock and ensuring the correctness of the data written to the slave device.

[0074] In one possible implementation, Figure 5 As shown, the main control unit 32 includes a fourth detection subunit 3210 , a fifth detection subunit 3211 , a fourth buffer 3212 , a third output subunit 3213 and a second arbitration subunit 3214 .

[0075] After receiving the address read request, the fourth detection subunit 3210 updates the detection information of the address read request into the second detection information, and detects whether the address read request meets the reverse channel deadlock condition according to the second detection information. If the address read request does not meet the reverse channel deadlock condition, the address read request is sent to the third output subunit 3213. If the address read request meets the reverse channel deadlock condition, the address read request is temporarily stored at the end of the fourth buffer 3212. The detection information of the address read request includes the identification information of the address read request and the identification information of the destination slave device of the address read request.

[0076] The fifth detection sub-unit 3211 can detect whether the address read request at the first position in the fourth buffer 3212 meets the reverse channel deadlock condition based on the second detection information, and after determining that the address read request at the first position in the fourth buffer 3212 does not meet the reverse channel deadlock condition, send the address read request at the first position in the fourth buffer 3212 to the third output sub-unit 3213.

[0077] The third output subunit 3213 may send the address read request from the fourth detection subunit 3210 or the fifth detection subunit 3211 to the corresponding slave control unit 34 .

[0078] After receiving the to-be-read data corresponding to the address read request, the second arbitration sub-unit 3214 may delete the detection information of the address read request from the second detection information, and upload the to-be-read data corresponding to the address read request.

[0079] It should be noted that the processing method for address read requests is similar to the processing method for address write requests. The difference is that there is no need to temporarily store the data to be written when processing address read requests. The processing process of address read requests can refer to the processing process of address write requests in the aforementioned embodiment, and the processing process of address read requests will not be repeated here.

[0080] In an embodiment of the present application, after receiving an address read request, the fourth detection sub-unit 3210 detects whether the address read request satisfies the reverse channel deadlock condition. If the address read request does not satisfy the reverse channel deadlock condition, the address write request is sent to the third output sub-unit 3213. If the address read request satisfies the reverse channel deadlock condition, the address write request is temporarily stored in the fourth buffer 3212. After the fifth detection sub-unit 3211 determines that the address read request no longer satisfies the reverse channel deadlock condition, the address read request is sent to the third output sub-unit 3213. After receiving the address read request, the third output sub-unit 3213 sends the received address read request to the corresponding slave control unit 34, thereby ensuring that the reverse channel deadlock does not occur and the bus will not be blocked. Address read requests without the possibility of deadlock can still be transmitted normally, thereby improving the utilization rate of the bus.

[0081] In one possible implementation, Figure 6 The schematic block diagram of the bus interconnection module 30 shown in the figure, the bus interconnection module 30 may also include a timing maintenance module 36, the timing maintenance module 36 may generate timing information corresponding to the slave device, different slave devices correspond to different timing information, the timing information of the slave device may indicate the order in which the address write request sent to the slave device is issued by the master device. After receiving the address write request sent by the master control unit 32, the slave control unit 34 may issue the address write request according to the timing information corresponding to the destination slave device of the address write request, so that the address write request that can cause the forward channel deadlock is issued in sequence according to the order in which it is issued.

[0082] The following example illustrates the occurrence of forward channel deadlock. Figure 7 As shown, the master device 0 first sends an address write request M01 to the slave device 0, and then sends an address write request M02 to the slave device 0. However, the address write request M01 is temporarily stored between the switching module A and the switching module B included in the bus interconnection module for at least one clock cycle, resulting in the slave device 0 receiving the address write request M02 first, thereby causing a forward channel deadlock.

[0083] In an embodiment of the present application, the forward channel deadlock is caused by the fact that address write requests issued by different or the same master devices are sent first and arrive at the slave device later. The timing maintenance module 36 can generate corresponding timing information for each slave device, and record the order of address write requests sent by different or the same master devices to the slave device through the timing information. Then, the slave control unit 34 sends address write requests to the slave device in the order in which the address write requests are issued according to the timing information corresponding to the slave device, so that the address write requests are sent first and arrive first, thereby avoiding the occurrence of forward channel deadlock.

[0084] In one possible implementation, Figure 8The schematic block diagram of the slave control unit 34 is shown, and the slave control unit 34 includes a first selection subunit 341, a second selection subunit 342 and a fifth buffer 343.

[0085] After receiving the address write request from the first detection subunit 321 or the second detection subunit 322, if the third buffer 328 does not include any identification information of the slave device, the first output subunit 324 sets a priority mark for the received address write request and sends it to the corresponding slave control unit 34. The third buffer 328 is used to store the identification information of the destination slave device of the temporarily stored address write request. After the to-be-written data corresponding to the temporarily stored address write request is sent to the slave control unit 34, the third detection subunit 326 will delete the identification information of the destination slave device of the address write request from the third buffer 328. Therefore, when the third buffer 328 does not include any identification information of the slave device, it means that there is no temporarily stored address write request in the first buffer 323. At this time, the first output subunit 324 sending the received address write request will not cause the forward channel deadlock, so the first output subunit 324 can set a priority mark for the received address write request, so that the slave control unit 34 can quickly send the address write request after receiving it.

[0086] After receiving the address write request from the first output subunit 324, the first selection subunit 341 detects whether the address write request includes a priority identifier. If the address write request includes a priority identifier, the address write request is directly issued, and the path identifier of the transmission path of the address write request in the bus interconnection module 30 is stored in the fifth buffer 343. After the first selection subunit 341 issues the address write request including the priority identifier, the second selection subunit 342 receives the data to be written transmitted through the transmission path indicated by the path identifier according to the path identifier of the address write request in the fifth buffer 343, issues the received data to be written, and then deletes the path identifier of the address write request from the fifth buffer 343.

[0087] It should be noted that the path identifiers of address write requests issued by different master devices are different, and when there are multiple transmission paths from the same master device to a certain slave device for transmitting address write requests, the path identifiers of these multiple transmission paths are different from each other to prevent self-locking in the forward channel deadlock.

[0088] In the embodiment of the present application, when the first output subunit 324 receives an address write request, if the third buffer 328 does not include any identification information of the slave device, the address write request will not cause a deadlock in the forward channel. The first output subunit 324 sets a priority mark on the address write request and sends it to the first selection subunit 341. After the first selection subunit 341 receives the address write request with a priority mark, it directly sends the address write request without waiting, thereby improving the transmission efficiency. After the first selection subunit 341 sends the address write request, it stores the path mark of the address write request in the fifth buffer 343. The second selection subunit 342 receives the data to be written transmitted through the transmission path indicated by the path mark, sends the received data to be written, and then deletes the path mark of the address write request from the fifth buffer 343, ensuring that the data to be written corresponding to the address write request is sent in the order in which the address write request is sent, thereby ensuring the correctness of data writing.

[0089] In one possible implementation, Figure 8 As shown, the timing information includes a full queue. After the master device sends an address write request whose destination slave device is the slave device corresponding to the timing information, if the address write request does not include a priority identifier, the timing maintenance module 36 stores the path identifier of the transmission path of the address write request in the bus interconnection module 30 to the tail of the full queue. The first selection subunit 341 receives the address write request transmitted through the transmission path indicated by the path identifier according to the path identifier at the head of the full queue, sends the received address write request, and stores the path identifier in the fifth buffer 343.

[0090] In an embodiment of the present application, for a certain slave control unit 34, the timing maintenance module 36 stores the path identifier corresponding to the address write request sent by each master device to a certain slave device at the end of the full queue corresponding to the slave control unit 34 and the slave device in the order in which the address write request is sent by the master device. The slave control unit 34 includes a first selection subunit 341, which receives the address write request transmitted through the transmission path indicated by the path identifier according to the path identifier at the head of the full queue, sends the received address write request, stores the path identifier in the fifth buffer 343, and deletes the path identifier from the full queue, to ensure that the address write request sent first is sent first by the slave control unit 34, thereby avoiding the occurrence of forward channel deadlock.

[0091] In one possible implementation, Figure 8 As shown, the timing information includes not only the full queue but also the priority queue. The timing maintenance module 36 updates the timing information according to the following rules:

[0092] If multiple master devices send address write requests to the same slave device in one clock cycle, the waiting time is determined according to the logical length and / or physical distance between the master device and the slave device. The waiting time can be one clock cycle or multiple clock cycles.

[0093] If the waiting time is one clock cycle, or the waiting time is greater than one clock cycle but the multiple address write requests issued in the same clock cycle do not include an address write request with a priority flag, the multiple address write requests are stored in order at the end of the full queue.

[0094] If the waiting time is greater than one clock cycle, and multiple address write requests issued within the same clock cycle include an address write request with a priority flag, and the time it takes for the address write request with a priority flag to be transmitted to the first selection subunit 341 is less than the waiting time, then after the first selection subunit 341 sends down the address write request with the priority flag, the path flag of the address write request with the priority flag is stored in the priority queue.

[0095] After the waiting time, according to the path identifiers stored in the priority queue, the other address write requests among the multiple address write requests except the address write requests whose corresponding path identifiers are recorded in the priority queue are sequentially stored at the end of the full queue, and the path identifiers stored in the priority queue are deleted.

[0096] When one or more master devices and slave devices are unable to determine the address write request issued by the master device in one beat due to logical length or physical distance, it is necessary to beat all the master devices as a whole and then update the full queue, that is, update the full queue after waiting for a certain period of time. If the time for the address write request with a priority identifier to be transmitted to the first selection subunit 341 is less than the waiting period of time, the address write request with a priority identifier has been issued by the first selection subunit 341 during the waiting period of time, and the path identifier of the address write request will be stored in the priority queue. When updating the full queue after the waiting period of time, since the address write request with a priority identifier has been issued, there is no need to store the path identifier of the address write request in the full queue.

[0097] It should be noted that the priority queue is used to store path identifiers of address write requests that are set with priority identifiers and are transmitted to the first selection subunit 341 for a time that is less than the waiting time. Since the number of address write requests that meet the above requirements is small, the priority queue only needs a shallower depth.

[0098] In the embodiment of the present application, the timing maintenance module 36 maintains the priority queue so that the address write request with a priority identifier can be quickly issued while preventing the path identifier of the address write request that has been issued and set with a priority identifier from being stored in the full queue, thereby avoiding the occurrence of repeated issuance of address write requests and ensuring the correctness of data transmission.

[0099] In one possible implementation, Figure 8 As shown, the slave control unit 34 also includes a third arbitration sub-unit 344, which can receive an address read request sent by the main control unit 32 (the third output 3213) and send the received address read request down, and can also receive data to be read corresponding to the address read request, and send the received data to be read to the second arbitration sub-unit 3214.

[0100] In the embodiment of the present application, since the address read request will not cause the forward channel deadlock, the third arbitration sub-unit 344 directly sends the address read request after receiving it, and directly sends it to the second arbitration sub-unit 3214 after receiving the data to be read corresponding to the address read request, thereby avoiding the occurrence of forward channel deadlock and ensuring the normal transmission of address read and write requests, data to be written and data to be read.

[0101] In one possible implementation, Fig. 9 As shown, one end of the master control unit 32 is connected to a master device or a slave control unit 34, and the other end of the master control unit 32 is connected to at least one slave control unit 34. One end of the slave control unit 34 is connected to at least one master control unit 32, and the other end of the slave control unit 34 is connected to a master control unit 32 or a slave device.

[0102] In an embodiment of the present application, the bus interconnection module 30 may include multiple cascaded master control units 32 and slave control units 34, each master control unit 32 may be connected to multiple slave control units 34, and the slave control unit 34 may be connected to a master control unit 32 or a slave device to cope with application scenarios with different numbers of master devices and slave devices, and different layouts of master devices and slave devices, thereby improving the applicability of the bus interconnection module 30.

[0103] It should be noted that in Figure 5 and Figure 8 In the figure, AW is used to represent the write address channel, W is used to represent the write data channel, AR is used to represent the read address channel, R is used to represent the read data channel, and B is used to represent the write response channel.

[0104] Bus communication method

[0105] Fig.10FIG. 1 is a flow chart of a bus communication method according to an embodiment of the present application. The bus communication method can be executed by the bus interconnection module 30 in the above embodiment. Fig.10 As shown, the bus communication method comprises the following steps:

[0106] Step 1001: After receiving an address read / write request, the master control unit temporarily stores the address read / write request if the address read / write request satisfies a reverse channel deadlock condition, and sends the address read / write request to a corresponding slave control unit after determining that the address read / write request does not satisfy the reverse channel deadlock condition.

[0107] Step 1002: After receiving the address read / write request, the slave control unit sends the address read / write request.

[0108] In an embodiment of the present application, after receiving an address read / write request, the main control unit can determine whether the address read / write request satisfies the reverse channel deadlock condition. If the address read / write request satisfies the reverse channel deadlock condition, the address read / write request is temporarily stored, and after the address read / write request no longer satisfies the reverse channel deadlock condition, the address read / write request is sent to the slave control unit, which issues the address read / write request. By temporarily storing the address read / write request that may cause the reverse channel deadlock, the occurrence of the reverse channel deadlock can be avoided. After temporarily storing the address read / write request that may cause the reverse channel deadlock, subsequent address read / write requests that have no possibility of deadlock can still be transmitted normally, thereby avoiding the reverse channel deadlock while improving the bus utilization rate.

[0109] It should be noted that since the details of the bus communication method of the embodiment of the present application have been described in detail in the bus interconnection module part of the above embodiment in combination with the structural schematic diagram, the specific process can be found in the description of the above bus interconnection module embodiment, and will not be repeated here.

[0110] It should be noted that the user-related information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to sample data used to train the model, data used for analysis, stored data, displayed data, etc.) involved in the embodiments of the present application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data need to comply with relevant laws, regulations and standards of relevant countries and regions, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0111] It should be understood that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the method embodiment, since it is basically similar to the method described in the device and system embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of other embodiments.

[0112] It should be understood that the above is a description of a specific embodiment of the present specification. Other embodiments are within the scope of the claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0113] It should be understood that an element described in singular form herein or shown in the drawings as only one does not limit the number of the element to one. In addition, modules or elements described or shown as separate herein may be combined into a single module or element, and modules or elements described or shown as single herein may be split into multiple modules or elements.

[0114] It should also be understood that the terms and expressions used herein are for description only, and one or more embodiments of this specification should not be limited to these terms and expressions. The use of these terms and expressions does not mean to exclude any equivalent features of the illustrations and descriptions (or parts thereof), and it should be recognized that various modifications that may exist should also be included in the scope of the claims. Other modifications, changes and substitutions may also exist. Accordingly, the claims should be deemed to cover all such equivalents.

Claims

1. A bus interconnection module, comprising: a plurality of master control units and a plurality of slave control units; The master control unit is configured to, after receiving an address read / write request, temporarily store the address read / write request if the address read / write request satisfies a reverse channel deadlock condition, and send the address read / write request to the corresponding slave control unit after determining that the address read / write request does not satisfy the reverse channel deadlock condition; The slave control unit is used to send the address read / write request after receiving the address read / write request.

2. The bus interconnection module according to claim 1, wherein: The main control unit comprises: a first detection subunit, a second detection subunit, a first buffer zone, a first output subunit and a first arbitration subunit; The first detection subunit is used to update the detection information of the address write request into the first detection information after receiving the address write request, and detect whether the address write request meets the reverse channel deadlock condition according to the first detection information, if the address write request does not meet the reverse channel deadlock condition, send the address write request to the first output subunit, if the address write request meets the reverse channel deadlock condition, temporarily store the address write request at the end of the first buffer, the detection information of the address write request includes the identification information of the address write request and the identification information of the destination slave device of the address write request; the second detection subunit is configured to detect whether the address write request located at the first position in the first buffer satisfies the reverse channel deadlock condition according to the first detection information, and after determining that the address write request located at the first position in the first buffer does not satisfy the reverse channel deadlock condition, send the address write request located at the first position in the first buffer to the first output subunit; The first output sub-unit is used to send the received address write request to the corresponding slave control unit; The first arbitration sub-unit is used to delete the detection information of the address write request from the first detection information after receiving the response information corresponding to the address write request sent by the slave control unit, and upload the response information corresponding to the address write request.

3. The bus interconnection module according to claim 2, wherein: The main control unit further includes: a third detection subunit, a second buffer zone, a third buffer zone, and a second output subunit; The first detection subunit is used to store the identification information of the destination slave device of the address write request to the last bit of the third buffer after determining that the address write request satisfies the reverse channel deadlock condition; The third detection subunit is used for, after receiving the data to be written, if the number of data to be written in the second buffer is less than the number of identification information of the slave device in the third buffer, temporarily storing the data to be written in the last position of the second buffer, if the number of data to be written in the second buffer is equal to the number of identification information of the slave device in the third buffer, sending the data to be written to the second output subunit, and after the second output subunit sends the data to be written at the first position in the second buffer to the corresponding slave control unit, deleting the identification information of the slave device at the first position in the third buffer; The second output sub-unit is used to send the data to be written from the third detection sub-unit to the corresponding slave control unit after the first output sub-unit sends the address write request from the first detection sub-unit to the corresponding slave control unit, and to take out the data to be written at the first position in the second buffer from the second buffer and send it to the corresponding slave control unit after the first output sub-unit sends the address write request from the second detection sub-unit to the corresponding slave control unit.

4. The bus interconnection module according to claim 3, further comprising: Timing maintenance module; The timing maintenance module is used to generate timing information corresponding to the slave device, and the timing information is used to indicate the order in which the address write requests sent to the corresponding slave device are sent by the master device, and different slave devices correspond to different timing information; The slave control unit is used to send the address write request according to the timing information corresponding to the destination slave device of the address write request after receiving the address write request sent by the master control unit, so that the address write requests that can cause forward channel deadlock are sent in sequence according to the order in which they are sent.

5. The bus interconnection module according to claim 4, wherein: The slave control unit includes: a first selection subunit, a second selection subunit and a fifth buffer; The first output subunit is used for, after receiving an address write request, setting a priority identifier for the received address write request and sending it to the corresponding slave control unit if the third buffer does not include identification information of the slave device; The first selection subunit is used for, after receiving the address write request including the priority identifier, sending the address write request information, and storing the path identifier of the transmission path of the address write request in the bus interconnection module in the fifth buffer; The second selection subunit is used to receive the data to be written transmitted through the transmission path indicated by the path identifier stored in the fifth buffer, send the received data to be written, and delete the path identifier from the fifth buffer.

6. The bus interconnection module according to claim 5, wherein: The timing information includes the full queue; The timing maintenance module is used for storing the path identifier of the transmission path of the address write request in the bus interconnection module to the tail of the full queue after the master device sends an address write request whose destination slave device is the slave device corresponding to the timing information, if the address write request does not include the priority identifier; The first selection subunit is used to send an address write request transmitted through a transmission path indicated by a path identifier located at the head of the full queue, and store the path identifier in the fifth buffer.

7. The bus interconnection module according to claim 6, wherein: The timing information also includes a priority queue, and the timing maintenance module is used to perform the following operations: When multiple master devices send multiple address write requests for the destination slave device being the slave device corresponding to the timing information within one clock cycle, the waiting time is determined according to the logical length and / or physical distance between the master device and the slave device corresponding to the timing information; If the waiting time is longer than one clock cycle, and the multiple address write requests include an address write request with a priority identifier, and the time duration for the address write request with a priority identifier to be transmitted to the first selection subunit is shorter than the waiting time duration, then after the first selection subunit sends the address write request with the priority identifier, the path identifier of the transmission path of the address write request with the priority identifier in the bus interconnection module is stored in the priority queue; After the waiting period, according to the path identifiers stored in the priority queue, the address write requests among the multiple address write requests except the address write requests whose corresponding path identifiers are recorded in the priority queue are sequentially stored at the end of the full queue, and the path identifiers in the priority queue are deleted.

8. The bus interconnection module according to claim 1, wherein: The main control unit comprises: a fourth detection subunit, a fifth detection subunit, a fourth buffer zone, a third output subunit and a second arbitration subunit; The fourth detection subunit is used to update the detection information of the address read request into the second detection information after receiving the address read request, and detect whether the address read request meets the reverse channel deadlock condition according to the second detection information, if the address read request does not meet the reverse channel deadlock condition, send the address read request to the third output subunit, if the address read request meets the reverse channel deadlock condition, temporarily store the address read request at the end of the fourth buffer, the detection information of the address read request includes the identification information of the address read request and the identification information of the destination slave device of the address read request; the fifth detection subunit is configured to detect whether the first address read request in the fourth buffer satisfies the reverse channel deadlock condition according to the second detection information, and after determining that the first address read request in the fourth buffer does not satisfy the reverse channel deadlock condition, send the first address read request in the fourth buffer to the third output subunit; The third output subunit is used to send the received address read request to the corresponding slave control unit; The second arbitration sub-unit is used to delete the detection information of the address read request from the second detection information after receiving the data to be read corresponding to the address read request, and upload the data to be read corresponding to the address read request.

9. The bus interconnection module according to claim 8, wherein: The slave control unit comprises: The third arbitration sub-unit is used for sending the address read request after receiving the address read request sent by the main control unit, and sending the received to-be-read data corresponding to the address read request to the second arbitration sub-unit.

10. The bus interconnection module according to any one of claims 1 to 9, wherein: One end of the master control unit is connected to the master device or one of the slave control units, and the other end of the master control unit is connected to at least one of the slave control units; One end of the slave control unit is connected to at least one of the master control units, and the other end of the slave control unit is connected to one of the master control units or a slave device.

11. A computing device comprising: A plurality of master devices, a plurality of slave devices and a bus interconnection module according to any one of claims 1 to 9; The master device is used to send an address read and write request to the slave device through the bus interconnection module; The slave device is used to send the stored data to be read to the master device through the bus interconnection module in response to the address read / write request, or to receive the data to be written sent by the master device through the bus interconnection module.

12. A system on chip, comprising: A plurality of master devices and a bus interconnection module according to any one of claims 1 to 9; The master device is used to send an address read and write request to a slave device through the bus interconnection module, and the slave device is included in the system on chip or connected to the system on chip through an I / O interface on the system on chip; The slave device is used to send the stored data to be read to the master device through the bus interconnection module in response to the address read / write request, or to receive the data to be written sent by the master device through the bus interconnection module.

13. The system on chip according to claim 12, wherein: The master device includes a processing unit, and the slave device includes an I / O device.

14. A bus communication method, comprising: After receiving the address read / write request, the master control unit temporarily stores the address read / write request if the address read / write request meets the reverse channel deadlock condition, and sends the address read / write request to the corresponding slave control unit after determining that the address read / write request does not meet the reverse channel deadlock condition; After receiving the address read / write request, the slave control unit sends the address read / write request.

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