Mapping method, device and equipment for wafer back defect detection and storage medium

Abstract

The invention discloses a mapping method and device for wafer back defect detection, equipment and a storage medium, and relates to the field of AOI image detection.The mapping method comprises the steps that wafer front face alignment information is obtained, a wafer front face image is collected, and a front face coordinate system is established according to the recognized wafer front face circle center and a groove; overturning the wafer mirror image, determining back standard alignment information of the wafer based on the mirror image relationship between the front coordinate system and the back coordinate system of the wafer, and performing alignment; and acquiring a wafer back image, performing defect identification, determining back coordinate information of back defect points, and determining front mapping coordinates of the back defect points mapped on the front according to the mapping relation of the back coordinate system and the front coordinate system. According to the scheme, defects on the back of the wafer can be detected and mapped to the front chip, rapid defect detection is achieved, and compared with a method that two images are directly shot and then fused and matched, the detection efficiency is higher.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of AOI image detection, and in particular to a mapping method, device, equipment and storage medium for wafer back side defect detection. Background Art

[0002] The wafer processing technology is complex and closely linked, the processing and production costs are high, and the quality requirements for each process are higher. In actual production, every step of the process from designing the wafer substrate to the final etching is required to be quality tested, so that quality problems of wafer products can be discovered in time to make process adjustments or scrap problematic wafers to stop losses in time. In actual production, wafer inspection not only detects whether there are defects on the upper surface (front) of the wafer, but also needs to detect whether there are defects on the back of the wafer. Defects on the back of the wafer may also cause the finished chip to be scrapped.

[0003] In related technologies, defect detection on the back of wafers is generally performed manually. Manual detection is subjective and cannot be standardized, which results in low accuracy or precision of wafer detection. Some production processes are detected by traditional mechanical equipment, which generally uses laser scanning to collect images or collects black and white images of the back of the wafer for defect identification. The accuracy of this detection method can meet the requirements, but laser scanning and photo recognition will seriously reduce the efficiency of production line detection. Summary of the invention

[0004] The embodiments of the present application provide a mapping method, device, equipment and storage medium for wafer back side defect detection, which solve the problem of insufficient accuracy of the alignment step in the wafer defect detection process and the impact on detection efficiency.

[0005] On the one hand, the present application provides a mapping method for wafer backside defect detection, the method comprising:

[0006] Obtaining wafer front alignment information and collecting a corresponding wafer front image, and establishing a front coordinate system according to the wafer front center and groove identified in the front image;

[0007] After the wafer is flipped over, standard alignment information of the back side of the wafer is determined based on the mirror relationship between the front side coordinate system and the back side coordinate system of the wafer, and the back side of the wafer is aligned according to the standard alignment information of the back side;

[0008] Obtain the back side image of the wafer after back side alignment and perform defect identification, determine the back side coordinate information of the defect point on the back side of the wafer, and determine the front side mapping coordinates of the back side defect point mapped on the front side of the wafer based on the mapping relationship between the back side coordinate system and the front side coordinate system.

[0009] Specifically, the establishing of a front coordinate system according to the wafer front center and the groove identified in the front image includes:

[0010] Based on one-dimensional coordinate axis of the line connecting the center of the front side of the wafer and the groove, the center of the front side is used as the origin of the coordinate system, and another-dimensional coordinate axis is established with the line connecting the center of the front side and the groove to establish the front coordinate system;

[0011] Based on the positional relationship of the front coordinate system relative to the alignment mechanism, a mapping relationship between the front coordinate system and the front alignment information is established.

[0012] Specifically, there are several array-distributed chip particles distributed on the front side of the wafer. After the front coordinate system is established according to the center of the wafer front circle and the groove, the front coordinate information of all chip particles on the front side of the wafer is determined, and a mapping relationship with the front coordinate system is established according to the chip particle number.

[0013] Specifically, the step of obtaining the wafer front alignment information and collecting the corresponding wafer front image includes:

[0014] Place the wafer with the front side facing upward into the alignment mechanism for rotation adjustment, and detect and determine the position of the groove on the wafer;

[0015] Determining the relative position relationship between the groove and the reference alignment member, and determining the front alignment information based on the relative position relationship;

[0016] The front side image of the wafer corresponding to the current front side alignment information is captured by an image acquisition device.

[0017] Specifically, the method of determining the back side standard alignment information of the wafer based on the mirror relationship between the front side coordinate system and the back side coordinate system of the wafer includes:

[0018] Determine the target position of the groove in the back side state of the wafer based on the image acquisition device; at the target position, the coordinate axis direction of the back side coordinate system is parallel to the edge corresponding to the back side image of the wafer;

[0019] Based on the wafer back coordinate system at the target position and the mapping relationship with the front alignment information, the relative position change between the groove and the reference alignment part when the wafer is adjusted to the target position is calculated and determined as the back standard alignment information.

[0020] Specifically, after determining the front mapping coordinates of the back defect point mapped on the front side of the wafer, the method further includes:

[0021] Determine a mapping relationship between the back defect point and the chip particle array according to the front mapping coordinates of the back defect point mapped to the front side of the wafer;

[0022] When the back defect point is mapped to the coordinate range of the chip particle, the corresponding chip particle is determined as a defective chip, and the number information of the defective chip is determined.

[0023] Specifically, according to the groove position and design information of the wafer, the layout information of each wafer particle in the wafer particle array is determined;

[0024] Determine the coordinate range of the back defect point mapped to the defective chip and the layout information of the defective chip, and determine the orientation information of the defective chip where the defect point is located.

[0025] On the other hand, the present application provides a mapping device for wafer backside defect detection, the device comprising:

[0026] An acquisition module is used to acquire wafer front alignment information and collect a corresponding wafer front image, and establish a front coordinate system according to the wafer front center and groove identified in the front image;

[0027] An alignment module is used to determine the back side standard alignment information of the wafer based on the mirror relationship between the front side coordinate system and the back side coordinate system of the wafer after flipping the wafer, and align the back side of the wafer according to the back side standard alignment information;

[0028] The mapping module is used to obtain the back side image of the wafer after back side alignment and perform defect identification, determine the back side coordinate information of the defect point on the back side of the wafer, and determine the front side mapping coordinates of the back side defect point mapped on the front side of the wafer based on the mapping relationship between the back side coordinate system and the front side coordinate system.

[0029] On the other hand, the present application provides a computer device, comprising a processor and a memory, wherein the memory stores at least one instruction, at least one program, a code set or an instruction set, and the at least one instruction, the at least one program, the code set or the instruction set are loaded and executed by the processor to implement the mapping method for wafer back side defect detection described in the above aspects.

[0030] On the other hand, the present application provides a computer-readable storage medium, wherein the readable storage medium stores at least one instruction, at least one program, a code set or an instruction set, and the at least one instruction, the at least one program, the code set or the instruction set is loaded and executed by a processor to implement the mapping method for wafer back side defect detection described in the above aspects.

[0031] The beneficial effects brought about by the technical solution provided in the embodiment of the present application include at least: optimizing the wafer flipping alignment process from the algorithm level, establishing the front and back coordinate systems according to the center of the wafer and the notch position, and calculating the back standard alignment information according to the mirror relationship between the front and back coordinate systems and the front alignment information determined by the front state of the wafer, so as to quickly adjust the back wafer to the target position and take a back image. In the subsequent process, the defects identified in the back image are directly mapped to the chip particles on the front, and the defective chips are screened out to achieve the purpose of rapid defect detection. Compared with the method of directly taking two images and then fusing and matching them, this solution has higher detection efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 It is a schematic diagram of the front and back structures of a wafer provided in an embodiment of the present application;

[0033] Figure 2 It is a flow chart of a mapping method for wafer backside defect detection provided by an embodiment of the present application;

[0034] Figure 3 A possible alignment control schematic diagram is shown;

[0035] Figure 4 It is a schematic diagram of the state of collecting front and back wafer images in a possible form;

[0036] Figure 5 A schematic diagram of a possible chip particle layout structure is shown;

[0037] Figure 6 A structural block diagram of a mapping device for wafer backside defect detection provided by an embodiment of the present application is shown;

[0038] Figure 7 A structural block diagram of a computer device provided by an exemplary embodiment of the present application is shown. DETAILED DESCRIPTION

[0039] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0040] The term "multiple" as used herein refers to two or more than two. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the related objects are in an "or" relationship.

[0041] Wafer backside defect detection is an operational process that first determines all chip particles on the front side of the wafer, and then performs defect detection on the back side of the wafer. Regardless of whether the back side of the wafer has a pattern or a smooth surface, when the defects that appear are sufficient to affect the normal function of the chip particles on the front side or affect related parameters and processes, it is necessary to perform processing procedures such as scrapping or damage assessment detection. The chip particles on the front side of the wafer are usually in an array form, and when defects appear on the back side of the wafer, they need to be mapped to the front side of the wafer based on the defect size and coverage, and determine the area on the front side where the target defect is mapped. See Figure 1 As shown, for the convenience of alignment and detection, a notch groove for alignment is opened at the edge of the wafer. Assuming that the first crack defect contained in the back of the wafer is small, after mapping on the front of the wafer, it happens to be located in the gap between the array chip particles, and this crack defect does not affect any chip particles. The second crack defect is longer. After mapping on the front of the wafer, the crack length covers the ID 7 and ID 11 chip particles, which requires marking these two chip particles, such as scrapping the particles, or separately performing subsequent performance testing and repair processes. Figure 1 The back of the wafer in the middle is smooth, and the dotted chip particle array is displayed for the convenience of showing the mapping relationship. This process requires the wafer to be clamped to the alignment mechanism by a robotic arm, and the front and back images of the wafer are taken by an image acquisition device respectively, and then the images acquired successively are used for defect detection.

[0042] Figure 2 : is a flowchart of a mapping method for wafer backside defect detection provided by an embodiment of the present application, comprising the following steps:

[0043] S1, obtaining wafer front alignment information and collecting the corresponding wafer front image, and establishing a front coordinate system according to the wafer front center and groove identified in the front image;

[0044] In the present application, the wafer alignment is completed by auxiliary devices, such as installing a turntable on the machine. After the wafer is placed on the turntable by a robotic arm, the rotation position is identified by an alignment system or other optical detection system. Figure 3 A possible alignment control schematic diagram is shown, where the wafer 20 is placed on the turntable 10 by a robotic arm, and the turntable 20 can control the notch to rotate to a suitable position according to demand. The alignment mechanism 30 or alignment system is located at a certain position of the turntable 10, which can be on the side or above the wafer. Its function is to detect the notch of the wafer and determine the rotation state of the wafer in turn. The image acquisition device or optical acquisition system can be located directly above the turntable 10 or at other locations to capture images of the front and back of the wafer.

[0045] The front alignment information of the wafer is information used to establish a positional relationship with a reference object. The alignment mechanism in the embodiment of the present application is relatively fixed on the machine platform, so the alignment information of the front wafer can be generated or determined based on the alignment mechanism or other fixed objects as reference objects. The front image of the wafer is collected based on the target alignment information, that is, the image in this position state.

[0046] After acquiring the front image, the front coordinate system can be established. The notch in this application is set to facilitate the establishment of the coordinate system and determine the position state of the wafer. The front coordinate system is set to locate the coordinate range of the chip particles on the front of the wafer. In some embodiments, a coordinate system can be established based on the line between the center of the front circle of the wafer and the notch, such as a rectangular coordinate system or a polar coordinate system. Figure 3 The front coordinate system is established in a rectangular coordinate system. After the front coordinate system is established, the position of each chip particle can be calibrated, and the coordinate information and number information can be fed back when the chip defect is determined. After the front coordinate system is determined, the mapping relationship with the front alignment information can be completed, that is, the position relationship between the wafer (notch) position and the reference object can be established, such as the rotation angle mapping relationship and direction mapping relationship formed by the notch relative to the reference object.

[0047] S2, after flipping the wafer, determining the back side standard alignment information of the wafer based on the mirror relationship between the front side coordinate system and the back side coordinate system of the wafer, and aligning the back side of the wafer according to the back side standard alignment information;

[0048] In this application, the alignment of the back side is not strictly the same as that of the front side, because it is for back side defect detection, and the image captured on the back side is the focus of image defect detection, so the direction of the image needs to be determined when flipping to the back side facing up, in order to facilitate manual reading and re-inspection and other operations. In particular, when the specified notch orientation position is different after two flips, the notch orientation needs to be adjusted to the target position, so it is necessary to determine the mapping relationship between the back side coordinate system and the front side alignment information based on the target position, that is, the wafer position deviation in the positive and negative directions, and determine the standard alignment information of the back side of the wafer based on the position deviation.

[0049] After capturing the front image, the robotic arm can be controlled to grab the wafer and flip it in a mirror image so that the back side is facing up. Only the front and back sides change before and after the mirror image flip, and the relative rotation angle and position and other parameters of the wafer will not change. Because the flipped wafer needs to be adjusted to the most ideal state before the back image can be acquired through the image acquisition device, the first task after flipping is to perform alignment to ensure that the back image can be acquired only after the alignment is completed. Because the coordinate axes established between the back and front sides are in a mirror image relationship, that is, the back side is also a coordinate axis established by the line connecting the center of the circle and the groove. The ideal state refers to the need to rotate the wafer with the back side facing up to a specific state (or angle), which is determined by the machine layout and the posture of the image acquisition device. As shown in the attached figure Figure 1 The ideal state presented in the figure is: the position state of the wafer with the notch facing upward in the field of view of the image acquisition device is taken as the standard ideal state.

[0050] Because the back coordinate system and the front coordinate system are in a mirror relationship, after the mirror is reversed, it is only necessary to determine the back standard alignment information based on the mapping relationship between the mirror relationship and the front coordinate system and the front alignment information, that is, the posture adjustment amount to adjust the wafer to the ideal state. Then control the turntable to complete the wafer back alignment operation.

[0051] S3, obtaining the back side image of the wafer after back side alignment and performing defect recognition, determining the back side coordinate information of the defect point on the back side of the wafer, and determining the front side mapping coordinates of the back side defect point mapped on the front side of the wafer according to the mapping relationship between the back side coordinate system and the front side coordinate system.

[0052] The main purpose of defect detection of the back image is to identify defects such as cracks, bulges, stains, etc. on the back. After identifying the defect points on the back, the coordinate information and coverage of each marked defect point are determined based on the back coordinate system. Then, based on the mapping relationship between the back coordinate system and the front coordinate system, the front mapping coordinates of the back defect points mapped on the front of the wafer can be determined to complete the mapping detection of the defect points.

[0053] In summary, the present application optimizes the wafer flipping and alignment process from the algorithm level, establishes the front and back coordinate systems according to the center of the wafer and the notch position, and calculates the back standard alignment information according to the mirror relationship between the front and back coordinate systems and the front alignment information determined by the front state of the wafer, so as to quickly adjust the back wafer to the target position and capture the back image. In the subsequent process, the defects identified in the back captured image are directly mapped to the chip particles on the front, and the defective chips are screened out to achieve the purpose of rapid detection. Compared with the method of directly taking two images and then fusing and matching them, this solution has higher detection efficiency.

[0054] In some embodiments, the alignment mechanism can be designed as a laser scanning component, and the notch of the wafer can be identified and detected by a laser scanning head. When the notch of the wafer is rotated to the position of the laser scanning head through a turntable, the rotation position of the wafer can be detected.

[0055] Because it takes time for the turntable to adjust the wafer rotation alignment, assuming that the front alignment information is a fixed value, each wafer needs to be adjusted to the target position according to the fixed front alignment information before the coordinate system is established. Figure 1 The notch in the middle is facing upwards, and this front alignment may affect the lengthening of the entire wafer inspection cycle. In some embodiments, the verticality of the front alignment information may not be limited. It is only necessary to place the wafer on the turntable and perform a simple initial calibration, and then determine the front alignment information of the wafer through the alignment mechanism, that is, map and bind each wafer to the front alignment information, so that the front image acquisition of each wafer can save one or more machine beats.

[0056] Figure 4 The figure is a schematic diagram of the state of collecting front and back wafer images in a possible form. The notch when the front side of the wafer faces upward is randomly determined. Assuming that the reference alignment parts on the alignment mechanism or other reference alignment parts with relatively fixed positional relationships are used as references, the process of obtaining the front alignment information and collecting the front image of the wafer may include the following steps:

[0057] A. Place the wafer with the front side facing upward into the alignment mechanism for rotation adjustment, and detect and determine the position of the groove on the wafer;

[0058] At this time, the groove position can be determined by a laser scanning head or other optical equipment, and then the front coordinate system can be determined. After the front coordinate system is determined, the front alignment information is also determined.

[0059] B, determining the relative position relationship between the groove and the reference alignment member, and determining the front alignment information based on the relative position relationship;

[0060] The relative position relationship is determined by the fixed position of the equipment on the machine, such as Figure 4 The front alignment information in the can be represented by the distance between the reference alignment part (point) on the alignment mechanism 30 and the line connecting the center of the wafer and the notch, and the angle a formed by the connecting line. In this way, for any wafer, as long as it is placed on the turntable and calibrated, the unique front alignment information can be obtained and the mapping relationship can be established.

[0061] Of course, this embodiment is described by taking a rectangular coordinate system as an example, and one of the coordinate axes (y axis) is established by the line connecting the center of the front circle and the groove, and the other coordinate axis (x axis) is established by the line connecting the vertical center and the groove. In some other embodiments, a polar coordinate system can also be used. When the front coordinate system is a polar coordinate system, the polar axis is established by the line connecting the center of the front circle and the groove, and the coordinates are determined by the distance between the wafer and the center of the front circle and the angle formed with the polar axis.

[0062] C. There are array-distributed chip particles on the front side of the wafer. After the front side coordinate system is established, the chip coordinates of each chip particle relative to the front side coordinate system can be determined, and a mapping relationship with the front side coordinate system can be established according to the chip number;

[0063] D. Place the wafer with its back side facing upward into the alignment mechanism for rotation adjustment, and detect and determine the groove position of the wafer;

[0064] E, determining the relative position relationship between the groove and the reference alignment member, and determining the front alignment information based on the relative position relationship;

[0065] F. Use an image acquisition device to capture the front side image of the wafer corresponding to the current front side alignment information.

[0066] After the front mapping relationship is determined, the robotic arm is controlled to flip the wafer mirror image so that the back is facing up. In order to prevent mechanical errors, the position of the notch can be determined after preliminary calibration of the wafer through a turntable. The notch position at this time corresponds to the position of the notch before flipping. The notch position at this time is determined to ensure the uniformity of the position before and after flipping for subsequent alignment operations.

[0067] Because the front and back coordinate systems are mirror images, only the back standard alignment information needs to be calculated, and the subsequent posture adjustment data is calculated based on the back standard alignment information. For the turntable, the rotation angle of the wafer is calculated. In some possible implementations, the process of generating the back standard alignment information of the wafer may include the following steps:

[0068] a. Determine the target position of the notch on the back side of the wafer based on the image acquisition device;

[0069] The target position in this application is the ideal position presented when capturing the back side image of the wafer. At this target position, the coordinate axis direction of the back side coordinate system of the notch is parallel to the edge corresponding to the back side image of the wafer. Figure 4 In the middle and back side images, the notch of the wafer is facing up, which makes it easier for manual inspection later.

[0070] b. Based on the back coordinate system of the wafer at the target position and the mapping relationship with the front alignment information, the relative position change between the groove and the reference alignment member when the wafer is adjusted to the target position is calculated, and the relative position change between the groove and the reference alignment member is determined as the back standard alignment information;

[0071] This process is calculated based on the ideal target position, i.e. Figure 4 The positional relationship between the center of the wafer and the notch relative to the reference alignment member (point) on the alignment mechanism 30. Figure 4 The distance between the center reference alignment part (point) and the line connecting the center of the wafer and the notch, as well as the angle a formed by the line are determined, and alignment adjustment can be performed based on this. As long as the front alignment information of the wafer is determined in the previous stage, the mapping relationship between the back coordinate system and the front alignment information can also be determined. Specifically, the difference between the two angles and the change in the length of the two variables can be calculated based on the mapping relationship, and the turntable movement can be controlled according to the change value to move the wafer to the target position.

[0072] Further, after determining the front mapping coordinates of the back defect point mapped on the front side of the wafer, the following steps may also be included:

[0073] c. Determine the mapping relationship between the back defect point and the chip particle array according to the front mapping coordinates of the back defect point mapped to the front side of the wafer;

[0074] For example Figure 4 The defect point mapping relationship in the chip can be obtained by mapping the two defect cracks to the front side, and then the mapping relationship between them and the chip particle array can be obtained.

[0075] d. When the back defect point is mapped to the coordinate range of the chip particle, the corresponding chip particle is determined as a defective chip, and the number information of the defective chip is determined;

[0076] Likewise Figure 4 Taking the mapping relationship in the figure as an example, the defective crack in the upper part happens to be between all chip particles and does not interfere with any chip particles; while the defective crack path in the lower part extends into the coordinate range of at least two chip particles, so the two interfering chip particles are determined as defective chips. Assuming that they are arranged in the direction of the grooves, #7 and #11 are determined as defective chips.

[0077] In some other embodiments, when the chip particle size is large and the length of the defect crack mapped within the chip particle coordinate range is small, the defect does not necessarily affect the chip. In particular, in the layout of some chips, there are obvious dense and sparse areas of components. General defect stripes will not have any effect on the chip. In some chip stacking processes, for defects such as dirt and scratches that do not affect the function, the defect can be directly covered after the stacking process, and will not affect the sale and function of the chip in appearance, so it does not need to be scrapped. To this end, after determining the mapping relationship between the back defect point and the chip particle array, the scheme can further include the following steps:

[0078] 1) When the back defect point is mapped to the coordinate range of the chip particle, the corresponding chip particle is determined as a candidate defective chip, and the number information of the candidate defective chip is determined;

[0079] 2) Determine the layout information of each wafer particle in the wafer particle array according to the groove position and design information of the wafer;

[0080] Figure 5 A schematic diagram of a possible chip particle layout structure is shown. Because the chip particles contain integrated logic circuits and power tubes, and the chips in the array structure are completely consistent in structure, for example, the notch direction is set as the positive direction. On this basis, all chips are divided into the first area ① and the second area ② in layout. Therefore, after flipping and identifying the notch and establishing the back coordinate system, the layout information of the chip can be determined, and then the coordinate range of each partition can be determined according to the back coordinate system.

[0081] 3) Determine the coordinate range of the defect point on the back side mapped to the defective chip and the layout information of the defective chip, and determine the position information of the defective chip where the defect point is located.

[0082] Assuming that the first area ① of the chip particles is a dense area or a non-stacked area, and the second area ② is a sparse area or a stacked area, then it is necessary to determine whether the back defect point that causes interference falls into the first area of ​​the candidate defective chip, indicating that it will affect the chip and it needs to be marked as a defective chip. When the back defect point does not fall into the first area, it will not have any impact on the chip and will not be marked.

[0083] Through the above solution, all wafers can be quickly inspected on the back side to determine the mapping relationship between back side defects and front side wafers. If defective chips are found, corresponding measures can be taken to improve the productivity of the production line.

[0084] Figure 6 The structural block diagram of the mapping device for wafer backside defect detection provided by an embodiment of the present application is shown, and the device includes:

[0085] An acquisition module 610 is used to acquire wafer front alignment information and collect a corresponding wafer front image, and establish a front coordinate system according to the wafer front center and groove identified in the front image;

[0086] The alignment module 620 is used to determine the back side standard alignment information of the wafer based on the mirror relationship between the front side coordinate system and the back side coordinate system of the wafer after flipping the wafer, and align the back side of the wafer according to the back side standard alignment information;

[0087] The mapping module 630 is used to obtain the back side image of the wafer after back side alignment and perform defect identification, determine the back side coordinate information of the defect point on the back side of the wafer, and determine the front side mapping coordinates of the back side defect point mapped on the front side of the wafer based on the mapping relationship between the back side coordinate system and the front side coordinate system.

[0088] Optionally, the acquisition module 610 is further configured to:

[0089] Based on one-dimensional coordinate axis of the line connecting the center of the front side of the wafer and the groove, the center of the front side is used as the origin of the coordinate system, and another-dimensional coordinate axis is established with the line connecting the center of the front side and the groove to establish the front coordinate system;

[0090] Based on the positional relationship of the front coordinate system relative to the alignment mechanism, a mapping relationship between the front coordinate system and the front alignment information is established.

[0091] Optionally, the acquisition module 610 is further configured to:

[0092] There are several array-distributed chip particles on the front of the wafer. After establishing the front coordinate system according to the center of the wafer front circle and the groove, the front coordinate information of all chip particles on the front of the wafer is determined, and the mapping relationship with the front coordinate system is established according to the chip particle number.

[0093] Optionally, the acquisition module 610 is further configured to:

[0094] Place the wafer with the front side facing upward into the alignment mechanism for rotation adjustment, and detect and determine the position of the groove on the wafer;

[0095] Determining the relative position relationship between the groove and the reference alignment member, and determining the front alignment information based on the relative position relationship;

[0096] The front side image of the wafer corresponding to the current front side alignment information is captured by an image acquisition device.

[0097] Optionally, the alignment module 620 is further used for:

[0098] Determine the target position of the groove in the back side state of the wafer based on the image acquisition device; at the target position, the coordinate axis direction of the back side coordinate system is parallel to the edge corresponding to the back side image of the wafer;

[0099] Based on the wafer back coordinate system at the target position and the mapping relationship with the front alignment information, the relative position change between the groove and the reference alignment part when the wafer is adjusted to the target position is calculated and determined as the back standard alignment information.

[0100] The device also includes a first determining module, configured to:

[0101] Determine a mapping relationship between the back defect point and the chip particle array according to the front mapping coordinates of the back defect point mapped to the front side of the wafer;

[0102] When the back defect point is mapped to the coordinate range of the chip particle, the corresponding chip particle is determined as a defective chip, and the number information of the defective chip is determined.

[0103] The device also includes a first determining module, configured to:

[0104] Determine the layout information of each wafer particle in the wafer particle array according to the groove position and design information of the wafer;

[0105] Determine the coordinate range of the back defect point mapped to the defective chip and the layout information of the defective chip, and determine the orientation information of the defective chip where the defect point is located.

[0106] The mapping device for wafer back side defect detection provided in the embodiment of the present application can be applied to the mapping method for wafer back side defect detection provided in the above embodiment. For relevant details, refer to the above method embodiment. The implementation principle and technical effect are similar and will not be repeated here.

[0107] It should be noted that the mapping device for wafer back side defect detection provided in the embodiment of the present application is only illustrated by the division of the above-mentioned functional modules / functional units. In actual applications, the above-mentioned functions can be assigned to different functional modules / functional units as needed, that is, the internal structure of the mapping device for wafer back side defect detection is divided into different functional modules / functional units to complete all or part of the functions described above. In addition, the implementation method of the mapping method for wafer back side defect detection provided in the above-mentioned method embodiment and the implementation method of the mapping device for wafer back side defect detection provided in this embodiment belong to the same concept. The specific implementation process of the mapping device for wafer back side defect detection provided in this embodiment is detailed in the above-mentioned method embodiment, which will not be repeated here.

[0108] Figure 7The block diagram of a computer device provided by an exemplary embodiment of the present application is shown. It is a computer device such as a desktop computer, a laptop computer, a PDA, and a cloud server. The computer device may include, but is not limited to, a processor and a memory. Among them, the processor and the memory may be connected by a bus or in other ways. Among them, the processor may be a central processing unit (CPU). The processor may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, graphics processors (GPU), embedded neural network processors (NPU) or other dedicated deep learning coprocessors, discrete gates or transistor logic devices, discrete hardware components and other chips, or a combination of the above-mentioned various chips.

[0109] The processor may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor may be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). The processor may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content that needs to be displayed on the display screen. In some embodiments, the processor may also include an AI (Artificial Intelligence) processor, which is used to process computing operations related to machine learning.

[0110] As a non-transient computer-readable storage medium, the memory can be used to store non-transient software programs, non-transient computer executable programs and modules, such as program instructions / modules corresponding to the methods in the above-mentioned embodiments of the present application. The processor executes various functional applications and data processing of the processor by running the non-transient software programs, instructions and modules stored in the memory, that is, the method in the above-mentioned method implementation is realized. The memory may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created by the processor, etc. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some embodiments, the memory may optionally include a memory remotely arranged relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network and a combination thereof.

[0111] In some embodiments, the computer device may further optionally include: a peripheral device interface and at least one peripheral device. The processor, the memory and the peripheral device interface may be connected via a bus or a signal line. Each peripheral device may be connected to the peripheral device interface via a bus, a signal line or a circuit board. Specifically, the peripheral device includes: at least one of a radio frequency circuit, a display screen and a keyboard.

[0112] The peripheral device interface can be used to connect at least one peripheral device related to I / O (Input / Output) to the processor and the memory. In some embodiments, the processor, the memory, and the peripheral device interface are integrated on the same chip or circuit board; in some other embodiments, any one or two of the processor, the memory, and the peripheral device interface can be implemented on a separate chip or circuit board, which is not limited in this embodiment.

[0113] The display screen is used to display the UI (User Interface). The UI may include graphics, text, icons, videos and any combination thereof. When the display screen is a touch screen, the display screen also has the ability to collect touch signals on the surface or above the surface of the display screen. The touch signal can be input to the processor as a control signal for processing. At this time, the display screen can also be used to provide virtual buttons and / or virtual keyboards, also known as soft buttons and / or soft keyboards. In some embodiments, the display screen can be one, arranged on the front panel of the computer device; in other embodiments, the display screen can be at least two, respectively arranged on different surfaces of the computer device or in a folding design; in other embodiments, the display screen can be a flexible display screen, arranged on a curved surface or a folding surface of the computer device. Even, the display screen can be set to a non-rectangular irregular shape, that is, a special-shaped screen. The display screen can be made of materials such as LCD (Liquid Crystal Display), OLED (Organic Light-Emitting Diode) and the like.

[0114] The power supply is used to power various components in the computer device. The power supply can be AC, DC, a disposable battery, or a rechargeable battery. When the power supply includes a rechargeable battery, the rechargeable battery can be a wired rechargeable battery or a wireless rechargeable battery. A wired rechargeable battery is a battery that is charged through a wired line, and a wireless rechargeable battery is a battery that is charged through a wireless coil. The rechargeable battery can also be used to support fast charging technology.

[0115] Those skilled in the art will appreciate that the structure shown in this embodiment does not constitute a limitation on the computer device, and may include more or fewer components than shown in the figure, or combine certain components, or adopt a different component arrangement.

[0116] The embodiment of the present application also discloses a computer-readable storage medium. Specifically, the computer-readable storage medium is used to store a computer program, and when the computer program is executed by the processor, the method in the above-mentioned method implementation is implemented. Those skilled in the art can understand that the implementation of all or part of the process in the above-mentioned implementation method of the present application can be completed by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium, and when the program is executed, it can include the process of the implementation of the above-mentioned methods. Among them, the storage medium can be a disk, an optical disk, a read-only memory (ROM), a random access memory (RAM), a flash memory (Flash Memory), a hard disk (Hard Disk Drive, abbreviated as: HDD) or a solid-state drive (SSD), etc.; the storage medium can also include a combination of the above-mentioned types of memory.

[0117] This specific embodiment is merely an explanation of the present invention and is not a limitation of the present invention. After reading this specification, those skilled in the art may make non-creative modifications to the present embodiment as needed. However, as long as they are within the scope of the claims of the present invention, they are protected by the patent law.

Claims

1. A mapping method for wafer backside defect detection, It is characterized in that The method comprises: Obtaining wafer front alignment information and collecting a corresponding wafer front image, and establishing a front coordinate system according to the wafer front circle center and the groove identified in the front image; After the wafer is flipped over, standard alignment information of the back side of the wafer is determined based on the mirror relationship between the front side coordinate system and the back side coordinate system of the wafer, and the back side of the wafer is aligned according to the standard alignment information of the back side; Obtain the back side image of the wafer after back side alignment and perform defect identification, determine the back side coordinate information of the defect point on the back side of the wafer, and determine the front side mapping coordinates of the back side defect point mapped on the front side of the wafer based on the mapping relationship between the back side coordinate system and the front side coordinate system.

2. The method according to claim 1, It is characterized in that The establishing of a front coordinate system according to the front center of the wafer and the groove identified in the front image includes: Based on one-dimensional coordinate axis of the line connecting the center of the front side of the wafer and the groove, the center of the front side is used as the origin of the coordinate system, and another-dimensional coordinate axis is established with the line connecting the center of the front side and the groove to establish the front coordinate system; Based on the positional relationship of the front coordinate system relative to the alignment mechanism, a mapping relationship between the front coordinate system and the front alignment information is established.

3. The method according to claim 2, It is characterized in that There are several array-distributed chip particles distributed on the front side of the wafer. After the front coordinate system is established according to the center of the wafer front circle and the groove, the front coordinate information of all chip particles on the front side of the wafer is determined, and a mapping relationship with the front coordinate system is established according to the chip particle number.

4. The method according to claim 2, It is characterized in that The obtaining of wafer front alignment information and collecting a corresponding wafer front image includes: Place the wafer with the front side facing upward into the alignment mechanism for rotation adjustment, and detect and determine the position of the groove on the wafer; Determining the relative position relationship between the groove and the reference alignment member, and determining the front alignment information based on the relative position relationship; The front side image of the wafer corresponding to the current front side alignment information is captured by an image acquisition device.

5. The method according to claim 4, It is characterized in that The method of determining the back side standard alignment information of the wafer based on the mirror image relationship between the front side coordinate system and the back side coordinate system of the wafer includes: Determine the target position of the groove in the back side state of the wafer based on the image acquisition device; at the target position, the coordinate axis direction of the back side coordinate system is parallel to the edge corresponding to the back side image of the wafer; Based on the wafer back coordinate system at the target position and the mapping relationship with the front alignment information, the relative position change between the groove and the reference alignment part when the wafer is adjusted to the target position is calculated and determined as the back standard alignment information.

6. The method according to claim 3, It is characterized in that After determining the front mapping coordinates of the back defect point mapped on the front side of the wafer, the method further includes: Determine a mapping relationship between the back defect point and the chip particle array according to the front mapping coordinates of the back defect point mapped to the front side of the wafer; When the back defect point is mapped to the coordinate range of the chip particle, the corresponding chip particle is determined as a defective chip, and the number information of the defective chip is determined.

7. The method according to claim 6, It is characterized in that Determine the layout information of each wafer particle in the wafer particle array according to the groove position and design information of the wafer; Determine the coordinate range of the back defect point mapped to the defective chip and the layout information of the defective chip, and determine the orientation information of the defective chip where the defect point is located.

8. A mapping device for wafer backside defect detection, It is characterized in that The device comprises: An acquisition module is used to acquire the wafer front alignment information and collect the corresponding wafer front image, and establish a front coordinate system according to the wafer front circle center and groove identified in the front image; An alignment module is used to determine the back side standard alignment information of the wafer based on the mirror relationship between the front side coordinate system and the back side coordinate system of the wafer after flipping the wafer, and align the back side of the wafer according to the back side standard alignment information; The mapping module is used to obtain the back side image of the wafer after back side alignment and perform defect identification, determine the back side coordinate information of the defect point on the back side of the wafer, and determine the front side mapping coordinates of the back side defect point mapped on the front side of the wafer based on the mapping relationship between the back side coordinate system and the front side coordinate system.

9. A computer device, It is characterized in that The computer device includes a processor and a memory, wherein the memory stores at least one instruction, at least one program, a code set or an instruction set, and the at least one instruction, the at least one program, the code set or the instruction set is loaded and executed by the processor to implement the mapping method for wafer back side defect detection as described in any one of claims 1 to 7.

10. A computer-readable storage medium, It is characterized in that The readable storage medium stores at least one instruction, at least one program, a code set or an instruction set, and the at least one instruction, the at least one program, the code set or the instruction set is loaded and executed by the processor to implement the mapping method for wafer back side defect detection as described in any one of claims 1 to 7.

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