Automatic alignment method, device and equipment for wafer defect detection and storage medium
The automatic alignment method and device establish front and back coordinate systems to align the wafer, allowing for rapid and accurate detection of backside defects by mapping them to the frontside, enhancing detection efficiency and accuracy.
Patent Information
- Application Number
- CN202411195945.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-29
- Publication Date
- 2024-12-17
AI Technical Summary
Manual detection of wafer defects on the backside is subjective and lacks accuracy, while traditional mechanical methods like laser scanning reduce production efficiency.
An automatic alignment method and device that establishes front and back coordinate systems based on the wafer center and notch position, using a mirror relationship to align the backside for efficient defect detection, mapping defects to the frontside for rapid identification.
Optimizes the wafer flipping alignment process, enabling rapid detection of backside defects by directly mapping them to the frontside, improving detection efficiency and accuracy compared to traditional methods.
Smart Images
Figure CN119152001A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present application relate to the field of AOI image detection, and in particular to an automatic alignment method, device, equipment and storage medium for wafer defect detection. Background Art
[0002] The wafer processing technology is complex and closely linked, the processing and production costs are high, and the quality requirements for each process are higher. In actual production, every step of the process from designing the wafer substrate to the final etching is required to be quality tested, so that quality problems of wafer products can be discovered in time to make process adjustments or scrap problematic wafers to stop losses in time. In actual production, wafer inspection not only detects whether there are defects on the upper surface (front) of the wafer, but also needs to detect whether there are defects on the back of the wafer. Defects on the back of the wafer may also cause the finished chip to be scrapped.
[0003] In related technologies, defect detection on the back of wafers is generally performed manually. Manual detection is subjective and cannot be standardized, which results in low accuracy or precision of wafer detection. Some production processes are detected by traditional mechanical equipment, which generally uses laser scanning to collect images or collects black and white images of the back of the wafer for defect identification. The accuracy of this detection method can meet the requirements, but laser scanning and photo recognition will seriously reduce the efficiency of production line detection. Summary of the invention
[0004] The embodiments of the present application provide an automatic alignment method, device, equipment and storage medium for wafer defect detection, which solve the problem of insufficient accuracy of the alignment step in the wafer defect detection process and the impact on detection efficiency.
[0005] In one aspect, the present application provides an automatic alignment method for wafer defect detection, the method comprising:
[0006] Acquire front alignment information of the wafer and a front captured image of the wafer corresponding to the front alignment information;
[0007] Identify the front center and the groove of the wafer according to the front collected image, determine the front coordinate system of the wafer based on the front center and the groove, and determine the mapping relationship between the front coordinate system and the front alignment information;
[0008] Based on the mirror relationship between the front coordinate system and the back coordinate system of the wafer, the back coordinate system and its mapping relationship with the front alignment information are determined, and the back standard alignment information of the wafer is generated to align the back of the wafer according to the back standard alignment information.
[0009] Specifically, determining the front coordinate system of the wafer based on the front circle center and the groove, and determining the mapping relationship between the front coordinate system and the front alignment information, includes:
[0010] A coordinate axis is established based on a line connecting the front center of the wafer and the groove, and the front coordinate system is established with the front center as the origin of the coordinate system;
[0011] Based on the positional relationship of the front coordinate system relative to the alignment mechanism, a mapping relationship with the front alignment information is established.
[0012] Specifically, when the front coordinate system is a rectangular coordinate system, one dimensional coordinate axis is established by the line connecting the center of the front circle and the groove, and another dimensional coordinate axis is established by the line connecting the vertical center of the circle and the groove;
[0013] When the front coordinate system is a polar coordinate system, the polar axis is established by the line connecting the front center and the groove, and the coordinates are determined by the distance between the wafer and the front center and the angle formed with the polar axis.
[0014] Specifically, the obtaining of the front alignment information includes:
[0015] Place the wafer with the front side facing upward into the alignment mechanism for rotation adjustment, and detect and determine the position of the groove on the wafer;
[0016] The relative position relationship between the groove and the reference alignment member is determined, and the front alignment information is determined based on the relative position relationship.
[0017] Specifically, array-distributed chip particles are arranged on the front side of the wafer; after establishing the front side coordinate system, the method further includes:
[0018] Determine the chip coordinates of each chip particle relative to the front coordinate system, and establish a mapping relationship with the front coordinate system according to the chip number;
[0019] After determining the mapping relationship between the front coordinate system and the front alignment information, the method further includes:
[0020] Place the wafer with the back side facing upward into the alignment mechanism for rotation adjustment, and detect and determine the groove position of the wafer.
[0021] Specifically, determining the mapping relationship between the back side coordinate system and the front side alignment information to generate the back side standard alignment information of the wafer includes:
[0022] Determine the target position of the groove in the back side state of the wafer based on the image acquisition device; at the target position, the coordinate axis direction of the back side coordinate system is parallel to the edge corresponding to the back side acquisition image of the wafer;
[0023] Based on the wafer backside coordinate system determined at the target position and the mapping relationship between the backside coordinate system and the front side alignment information, the relative position relationship between the groove at the target position and the reference alignment piece is calculated.
[0024] Specifically, aligning the back side of the wafer according to the back side standard alignment information includes:
[0025] The alignment mechanism calculates the amount of posture required to adjust the wafer to the target position based on the current groove position on the back of the wafer, and adjusts the alignment of the back of the wafer based on the posture amount.
[0026] On the other hand, the present application provides an automatic alignment device for wafer defect detection, the device comprising:
[0027] An acquisition module, used to acquire front alignment information of the wafer and a front captured image of the wafer corresponding to the front alignment information;
[0028] A determination module, used to identify the front center and the groove of the wafer according to the front collected image, determine the front coordinate system of the wafer based on the front center and the groove, and determine the mapping relationship between the front coordinate system and the front alignment information;
[0029] The calculation module is used to determine the back coordinate system and its mapping relationship with the front alignment information based on the mirror relationship between the front coordinate system and the back coordinate system of the wafer, generate the back standard alignment information of the wafer, and align the back of the wafer according to the back standard alignment information.
[0030] On the other hand, the present application provides a computer device, comprising a processor and a memory, wherein the memory stores at least one instruction, at least one program, a code set or an instruction set, and the at least one instruction, the at least one program, the code set or the instruction set are loaded and executed by the processor to implement the automatic alignment method for wafer defect detection described in the above aspects.
[0031] On the other hand, the present application provides a computer-readable storage medium, wherein the readable storage medium stores at least one instruction, at least one program, a code set or an instruction set, and the at least one instruction, the at least one program, the code set or the instruction set are loaded and executed by a processor to implement the automatic alignment method for wafer defect detection described in the above aspects.
[0032] The beneficial effects brought about by the technical solution provided in the embodiment of the present application include at least: optimizing the wafer flipping alignment process from the algorithm level, establishing the front and back coordinate systems according to the center of the wafer and the notch position, and calculating the back standard alignment information according to the mirror relationship between the front and back coordinate systems and the front alignment information determined by the front state of the wafer, so as to quickly adjust the back wafer to the target position and capture the back acquisition image. In the subsequent process, the defects identified in the back acquisition image are directly mapped to the chip particles on the front side, and the defective chips are screened out to achieve the purpose of rapid detection. Compared with the method of directly taking two images and then fusing and matching them, this solution has higher detection efficiency. BRIEF DESCRIPTION OF THE DRAWINGS
[0033] Figure 1 Schematic diagram of the front and back of the wafer provided in the embodiment of the present application
[0034] Figure 2 is a flow chart of an automatic alignment method for wafer defect detection provided by an embodiment of the present application;
[0035] Figure 3 A possible alignment control schematic diagram is shown;
[0036] Figure 4 It is a schematic diagram of the state of collecting front and back wafer images in a possible form;
[0037] Figure 5 A schematic structural diagram of an automatic alignment device for wafer defect detection is shown;
[0038] Figure 6 A structural block diagram of a computer device provided by an exemplary embodiment of the present application is shown. DETAILED DESCRIPTION
[0039] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.
[0040] The term "multiple" as used herein refers to two or more than two. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the related objects are in an "or" relationship.
[0041] Wafer backside defect detection is to first determine all chip particles on the front side of the wafer, and then perform defect detection on the back side of the wafer. Regardless of whether the back side of the wafer has a pattern or a smooth surface, when the defects are sufficient to affect the normal function of the chip particles on the front side or affect related parameters and processes, it is necessary to perform processing procedures such as scrapping or damage assessment detection. Because the chip particles on the front side of the wafer are usually in array form, when defects appear on the back side of the wafer, it is necessary to map them to the front side of the wafer based on the defect size and coverage, and determine the area on the front side where the target defect is mapped. See Figure 1 As shown, for the convenience of alignment and detection, a notch groove for alignment is opened at the edge of the wafer. Assuming that the first crack defect contained in the back of the wafer is small, after mapping on the front of the wafer, it happens to be located in the gap between the array chip particles, and this crack defect does not affect any chip particles. The second crack defect is longer. After mapping on the front of the wafer, the crack length covers the ID 7 and ID 11 chip particles, which requires marking these two chip particles, such as scrapping the particles, or separately performing subsequent performance testing and repair processes. Figure 1 The back of the wafer in the middle is smooth, and the dotted chip particle array is displayed for the convenience of showing the mapping relationship. This process requires the wafer to be clamped to the alignment mechanism by a robotic arm, and images of the front and back of the wafer are taken respectively, and then the images are acquired successively for defect detection to perform defect detection on the back.
[0042] Figure 2 : is a flow chart of an automatic alignment method for wafer defect detection provided by an embodiment of the present application, comprising the following steps:
[0043] S1, obtaining front alignment information of a wafer and a front captured image of the wafer corresponding to the front alignment information;
[0044] The alignment of the wafer in the present application is accomplished through auxiliary devices, such as installing a turntable on the machine. After the wafer is placed on the turntable by a robotic arm, the rotation position is identified by an alignment system or other optical detection system. Figure 3 A possible alignment control schematic diagram is shown, where the wafer 20 is placed on the turntable 10 by a robotic arm, and the turntable 20 can control the notch to rotate to a suitable position as required, and the alignment mechanism 30 or alignment system is located at a certain position of the turntable 10, which can be on the side or above the wafer, and its function is to detect the notch of the wafer and determine the rotation state of the wafer in turn. The image acquisition device or optical acquisition system can be located directly above the turntable 10 to obtain the front and back images of the wafer.
[0045] The front alignment information of the wafer is information used to establish a positional relationship with a reference object. The alignment mechanism in the embodiment of the present application is relatively fixed on the machine platform, so the alignment information of the front wafer can be generated or determined based on the alignment mechanism or other fixed objects as reference objects. The front alignment information can be determined when the front acquisition image is obtained.
[0046] S2, identifying the front center and the groove of the wafer according to the front collected image, determining the front coordinate system of the wafer based on the front center and the groove, and determining the mapping relationship between the front coordinate system and the front alignment information;
[0047] The front coordinate system is set up to locate the coordinates of each chip particle on the front wafer, and is also used for front defect detection and subsequent establishment of the back coordinate system.
[0048] In some embodiments, a coordinate system may be established based on a line between the center of the front surface of the wafer and the groove, for example, a rectangular coordinate system or a polar coordinate system. Figure 3 The front coordinate system is established in a rectangular coordinate system. After the front coordinate system is established, the position of each chip particle can be calibrated, and the coordinate information and number information can be fed back when the chip defect is determined. After the front coordinate system is determined, the mapping relationship with the front alignment information can be completed, that is, the position relationship between the wafer (notch) position and the reference object can be established, such as the rotation angle mapping relationship and direction mapping relationship formed by the notch relative to the reference object.
[0049] S3, based on the mirror relationship between the front coordinate system and the back coordinate system of the wafer, determine the back coordinate system and its mapping relationship with the front alignment information, generate the back standard alignment information of the wafer, and align the back of the wafer according to the back standard alignment information.
[0050] Because the coordinate system is established based on the line between the center of the wafer and the notch, even after flipping to the back of the wafer, the relative relationship between the center of the wafer and the notch remains certain, so the back coordinate system is also established using a similar principle, and the back coordinate system and the front coordinate system are mirror images with respect to the wafer surface.
[0051] In this application, the alignment of the back side is not strictly the same as that of the front side, because it is for back side defect detection, and the back side image is the focus of image defect detection, so the direction of the picture needs to be determined when flipping to the back side facing up, in order to facilitate manual reading and re-inspection and other operations. In particular, when the specified notch orientation position is different after two flips, the notch orientation needs to be adjusted to the target position, so it is necessary to determine the mapping relationship between the back side coordinate system and the front side alignment information according to the target position, that is, the wafer position deviation in the positive and negative directions, and determine the standard alignment information of the back side of the wafer according to the position deviation, and then the turntable can be controlled to adjust the position of the wafer. After the alignment is completed, the back side image of the wafer can be captured.
[0052] In summary, the present application optimizes the wafer flipping alignment process from the algorithm level, establishes the front and back coordinate systems according to the center of the wafer and the notch position, and calculates the back standard alignment information according to the mirror relationship between the front and back coordinate systems and the front alignment information determined by the front state of the wafer, so as to quickly adjust the back wafer to the target position and capture the back acquisition image. In the subsequent process, the defects identified in the back acquisition image are directly mapped to the chip particles on the front side, and the defective chips are screened out to achieve the purpose of rapid detection. Compared with the method of directly taking two images and then fusing and matching them, this solution has higher detection efficiency.
[0053] In some embodiments, the alignment mechanism 30 can be designed as a laser scanning component, and the notch of the wafer can be identified and detected by a laser scanning head. When the notch of the wafer is rotated to the position of the laser scanning head through a turntable, the rotation position of the wafer can be detected.
[0054] Because it takes time for the turntable to adjust the wafer rotation alignment, assuming that the front alignment information is a fixed value, each wafer needs to be adjusted to the target position according to the fixed front alignment information before the coordinate system is established. Figure 1 The notch in the middle is facing upwards. This front alignment may affect the lengthening of the entire wafer inspection cycle. In some embodiments, the verticality of the front alignment information may not be limited. It is only necessary to place the wafer on the turntable and perform a simple initial calibration, and then determine the front alignment information of the wafer through the alignment mechanism 30, that is, map and bind each wafer to the front alignment information, so that the front image acquisition of each wafer can save one or more machine beats.
[0055] Figure 4 The figure is a schematic diagram of the state of collecting front and back wafer images in a possible form. The notch when the front side of the wafer faces upward is randomly determined. Assuming that the reference alignment parts on the alignment mechanism or other reference alignment parts with relatively fixed positional relationships are used as references, the process of obtaining the front alignment information may include the following steps:
[0056] A. Place the wafer with the front side facing up into the alignment mechanism for rotation adjustment, and detect and determine the position of the groove on the wafer;
[0057] At this time, the groove position can be determined by a laser scanning head or other optical equipment, and then the front coordinate system can be determined. After the front coordinate system is determined, the front alignment information is also determined.
[0058] B. Determine the relative position relationship between the groove and the reference alignment member, and determine the front alignment information based on the relative position relationship.
[0059] The relative position relationship is determined by the fixed position of the equipment on the machine, such as Figure 4 The front alignment information in the can be represented by the distance between the reference alignment part (point) on the alignment mechanism 30 and the line connecting the center of the wafer and the notch, and the angle a formed by the connecting line. In this way, for any wafer, as long as it is placed on the turntable and calibrated, the unique front alignment information can be obtained and the mapping relationship can be established.
[0060] Of course, this embodiment is described by taking a rectangular coordinate system as an example, and one of the coordinate axes (y axis) is established by the line connecting the center of the front circle and the groove, and the other coordinate axis (x axis) is established by the line connecting the vertical center and the groove. In some other embodiments, a polar coordinate system can also be used. When the front coordinate system is a polar coordinate system, the polar axis is established by the line connecting the center of the front circle and the groove, and the coordinates are determined by the distance between the wafer and the center of the front circle and the angle formed with the polar axis.
[0061] C. There are chip particles distributed in an array on the front side of the wafer. After the front coordinate system is established, the chip coordinates of each chip particle relative to the front coordinate system can be determined, and a mapping relationship with the front coordinate system can be established according to the chip number.
[0062] D. Place the wafer with the back side facing up into the alignment mechanism for rotation adjustment, and detect and determine the groove position of the wafer.
[0063] After the front mapping relationship is determined, the robot arm is controlled to flip the wafer so that the back is facing up. In order to prevent mechanical errors, the position of the notch can be determined after preliminary calibration of the wafer through a turntable. The notch position at this time corresponds to the position of the notch before flipping. The notch position at this time is determined to ensure the uniformity of the position before and after flipping for subsequent alignment operations.
[0064] Because the front and back coordinate systems are mirror images, only the back standard alignment information needs to be calculated, and the subsequent posture adjustment data is calculated based on the back standard alignment information. For the turntable, the rotation angle of the wafer is calculated. In some possible implementations, the process of generating the back standard alignment information of the wafer may include the following steps:
[0065] a. Determine the target position of the notch on the back side of the wafer based on the image acquisition device;
[0066] The target position in this application is the ideal position presented when capturing the back side image of the wafer. At this target position, the coordinate axis direction of the back side coordinate system of the notch is parallel to the edge corresponding to the back side image of the wafer. Figure 4 In the middle and back side images, the notch of the wafer is facing up, which makes it easier for manual inspection later.
[0067] b. Based on the back coordinate system of the wafer at the target position and the mapping relationship with the front alignment information, the relative position change between the groove and the reference alignment part when the wafer is adjusted to the target position is calculated and determined as the back standard alignment information.
[0068] This process is calculated based on the ideal target position, i.e. Figure 4 The positional relationship between the center of the wafer and the notch relative to the reference alignment member (point) on the alignment mechanism 30. Figure 4 The distance between the center reference alignment part (point) and the line connecting the center of the wafer and the notch, as well as the angle a formed by the line are determined, and alignment adjustment can be performed based on this. As long as the front alignment information of the wafer is determined in the previous stage, the mapping relationship between the back coordinate system and the front alignment information can also be determined. Specifically, the difference between the two angles and the change in the length of the two variables can be calculated based on the mapping relationship, and the turntable movement can be controlled according to the change value to move the wafer to the target position.
[0069] Furthermore, the process of aligning the back side of the wafer according to the back side standard alignment information may also include the following steps:
[0070] c. Adjust the groove of the wafer to the target position according to the standard alignment information on the back side, and obtain the back side image of the wafer through an image acquisition device;
[0071] d. Perform defect detection on the back-side captured image to determine the position coordinates of the target defect in the back-side coordinate system;
[0072] e. According to the mirror relationship between the back coordinate system and the front coordinate system, the target defect is mapped to the front coordinate system to determine the defective chip in the front coordinate system.
[0073] Figure 5 A schematic diagram of the structure of an automatic alignment device for wafer defect detection provided in an embodiment of the present application is shown, and the device includes:
[0074] An acquisition module 510 is used to acquire front alignment information of a wafer and a front captured image of the wafer corresponding to the front alignment information;
[0075] A determination module 520 is used to identify the front center and the groove of the wafer according to the front collected image, determine the front coordinate system of the wafer based on the front center and the groove, and determine the mapping relationship between the front coordinate system and the front alignment information;
[0076] The calculation module 530 is used to determine the mapping relationship between the back coordinate system and the front alignment information based on the mirror relationship between the front coordinate system and the back coordinate system of the wafer, generate the back standard alignment information of the wafer, and align the back of the wafer according to the back standard alignment information.
[0077] The determination module 520 is further used to establish a coordinate axis based on the line connecting the front center of the wafer and the groove, and to establish the front coordinate system with the front center as the origin of the coordinate system;
[0078] Based on the positional relationship of the front coordinate system relative to the alignment mechanism, a mapping relationship with the front alignment information is established.
[0079] The determination module 520 is further configured to establish one dimensional coordinate axis with a line connecting the center of the circle on the front side and the groove, and establish another dimensional coordinate axis with a line connecting the center of the circle perpendicular to the groove, when the front coordinate system is a rectangular coordinate system;
[0080] When the front coordinate system is a polar coordinate system, the polar axis is established by the line connecting the front center and the groove, and the coordinates are determined by the distance between the wafer and the front center and the angle formed with the polar axis.
[0081] The acquisition module 510 is also used to place the wafer with the front side facing upward into the alignment mechanism for rotation adjustment, and detect and determine the position of the groove on the wafer;
[0082] The relative position relationship between the groove and the reference alignment member is determined, and the front alignment information is determined based on the relative position relationship.
[0083] The device further includes an operation module 540, which is used to determine the chip coordinates of each chip particle relative to the front coordinate system after the front coordinate system is established, and establish a mapping relationship with the front coordinate system according to the chip number;
[0084] After determining the mapping relationship between the front coordinate system and the front alignment information, the wafer is placed with its back side facing upward into the alignment mechanism for rotation adjustment to detect and determine the groove position of the wafer.
[0085] The calculation module 530 is further used to determine the target position of the groove in the back side state of the wafer based on the image acquisition device; at the target position, the coordinate axis direction of the back side coordinate system is parallel to the edge corresponding to the back side acquisition image of the wafer;
[0086] Based on the back coordinate system of the wafer at the target position and the mapping relationship with the front alignment information, the relative position change between the groove and the reference alignment part when the wafer is adjusted to the target position is calculated and determined as the back standard alignment information.
[0087] The device further comprises an alignment module 550, which is used to adjust the groove of the wafer to a target position according to the back standard alignment information, and obtain a back acquisition image of the wafer through an image acquisition device;
[0088] Perform defect detection on the back side captured image to determine the position coordinates of the target defect in the back side coordinate system;
[0089] According to the mirror relationship between the back coordinate system and the front coordinate system, the target defect is mapped to the front coordinate system, and the defective chip in the front coordinate system is determined.
[0090] The automatic alignment device for wafer defect detection provided in the embodiment of the present application can be applied to the automatic alignment method for wafer defect detection provided in the above embodiment. For relevant details, refer to the above method embodiment. The implementation principle and technical effect are similar and will not be repeated here.
[0091] It should be noted that the automatic alignment device for wafer defect detection provided in the embodiment of the present application is only illustrated by the division of the above-mentioned functional modules / functional units. In actual applications, the above-mentioned functions can be assigned to different functional modules / functional units as needed, that is, the internal structure of the automatic alignment device for wafer defect detection is divided into different functional modules / functional units to complete all or part of the functions described above. In addition, the implementation method of the automatic alignment method for wafer defect detection provided in the above method embodiment and the implementation method of the automatic alignment device for wafer defect detection provided in this embodiment belong to the same concept. The specific implementation process of the automatic alignment device for wafer defect detection provided in this embodiment is detailed in the above method embodiment, which will not be repeated here.
[0092] Figure 6The block diagram of a computer device provided by an exemplary embodiment of the present application is shown. It is a computer device such as a desktop computer, a laptop computer, a PDA, and a cloud server. The computer device may include, but is not limited to, a processor and a memory. Among them, the processor and the memory may be connected by a bus or in other ways. Among them, the processor may be a central processing unit (CPU). The processor may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, graphics processors (GPU), embedded neural network processors (NPU) or other dedicated deep learning coprocessors, discrete gates or transistor logic devices, discrete hardware components and other chips, or a combination of the above-mentioned various chips.
[0093] The processor may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor may be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). The processor may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content that needs to be displayed on the display screen. In some embodiments, the processor may also include an AI (Artificial Intelligence) processor, which is used to process computing operations related to machine learning.
[0094] As a non-transient computer-readable storage medium, the memory can be used to store non-transient software programs, non-transient computer executable programs and modules, such as program instructions / modules corresponding to the methods in the above-mentioned embodiments of the present application. The processor executes various functional applications and data processing of the processor by running the non-transient software programs, instructions and modules stored in the memory, that is, the method in the above-mentioned method implementation is realized. The memory may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created by the processor, etc. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some embodiments, the memory may optionally include a memory remotely arranged relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network and a combination thereof.
[0095] In some embodiments, the computer device may further optionally include: a peripheral device interface and at least one peripheral device. The processor, the memory and the peripheral device interface may be connected via a bus or a signal line. Each peripheral device may be connected to the peripheral device interface via a bus, a signal line or a circuit board. Specifically, the peripheral device includes: at least one of a radio frequency circuit, a display screen and a keyboard.
[0096] The peripheral device interface can be used to connect at least one peripheral device related to I / O (Input / Output) to the processor and the memory. In some embodiments, the processor, the memory, and the peripheral device interface are integrated on the same chip or circuit board; in some other embodiments, any one or two of the processor, the memory, and the peripheral device interface can be implemented on a separate chip or circuit board, which is not limited in this embodiment.
[0097] The display screen is used to display the UI (User Interface). The UI may include graphics, text, icons, videos and any combination thereof. When the display screen is a touch screen, the display screen also has the ability to collect touch signals on the surface or above the surface of the display screen. The touch signal can be input to the processor as a control signal for processing. At this time, the display screen can also be used to provide virtual buttons and / or virtual keyboards, also known as soft buttons and / or soft keyboards. In some embodiments, the display screen can be one, arranged on the front panel of the computer device; in other embodiments, the display screen can be at least two, respectively arranged on different surfaces of the computer device or in a folding design; in other embodiments, the display screen can be a flexible display screen, arranged on a curved surface or a folding surface of the computer device. Even, the display screen can be set to a non-rectangular irregular shape, that is, a special-shaped screen. The display screen can be made of materials such as LCD (Liquid Crystal Display), OLED (Organic Light-Emitting Diode) and the like.
[0098] The power supply is used to power various components in the computer device. The power supply can be AC, DC, a disposable battery, or a rechargeable battery. When the power supply includes a rechargeable battery, the rechargeable battery can be a wired rechargeable battery or a wireless rechargeable battery. A wired rechargeable battery is a battery that is charged through a wired line, and a wireless rechargeable battery is a battery that is charged through a wireless coil. The rechargeable battery can also be used to support fast charging technology.
[0099] Those skilled in the art will appreciate that the structure shown in this embodiment does not constitute a limitation on the computer device, and may include more or fewer components than shown in the figure, or combine certain components, or adopt a different component arrangement.
[0100] The embodiment of the present application also discloses a computer-readable storage medium. Specifically, the computer-readable storage medium is used to store a computer program, and when the computer program is executed by the processor, the method in the above-mentioned method implementation is implemented. Those skilled in the art can understand that the implementation of all or part of the process in the above-mentioned implementation method of the present application can be completed by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium, and when the program is executed, it can include the process of the implementation of the above-mentioned methods. Among them, the storage medium can be a disk, an optical disk, a read-only memory (ROM), a random access memory (RAM), a flash memory (Flash Memory), a hard disk (Hard Disk Drive, abbreviated as: HDD) or a solid-state drive (SSD), etc.; the storage medium can also include a combination of the above-mentioned types of memory.
[0101] This specific embodiment is merely an explanation of the present invention and is not a limitation of the present invention. After reading this specification, those skilled in the art may make non-creative modifications to the present embodiment as needed. However, as long as they are within the scope of the claims of the present invention, they are protected by the patent law.
Claims
1. An automatic alignment method for wafer defect detection, characterized in that: The method comprises: Acquire front alignment information of the wafer and a front captured image of the wafer corresponding to the front alignment information; Identify the front center and the groove of the wafer according to the front collected image, determine the front coordinate system of the wafer based on the front center and the groove, and determine the mapping relationship between the front coordinate system and the front alignment information; Based on the mirror relationship between the front coordinate system and the back coordinate system of the wafer, the back coordinate system and its mapping relationship with the front alignment information are determined, and the back standard alignment information of the wafer is generated to align the back of the wafer according to the back standard alignment information.
2. The method according to claim 1, characterized in that The determining of the front coordinate system of the wafer based on the front circle center and the groove, and determining the mapping relationship between the front coordinate system and the front alignment information, includes: A coordinate axis is established based on a line connecting the front center of the wafer and the groove, and the front coordinate system is established with the front center as the origin of the coordinate system; Based on the positional relationship of the front coordinate system relative to the alignment mechanism, a mapping relationship with the front alignment information is established.
3. The method according to claim 2, characterized in that When the front coordinate system is a rectangular coordinate system, one of the coordinate axes is established by the line connecting the center of the front circle and the groove, and the other coordinate axis is established by the line connecting the vertical center of the circle and the groove; When the front coordinate system is a polar coordinate system, the polar axis is established by the line connecting the front center and the groove, and the coordinates are determined by the distance between the wafer and the front center and the angle formed with the polar axis.
4. The method according to claim 2, characterized in that: The obtaining of front alignment information includes: Place the wafer with the front side facing upward into the alignment mechanism for rotation adjustment, and detect and determine the position of the groove on the wafer; The relative position relationship between the groove and the reference alignment member is determined, and the front alignment information is determined based on the relative position relationship.
5. The method according to claim 4, characterized in that An array of chip particles is arranged on the front side of the wafer; after establishing the front side coordinate system, the method further comprises: Determine the chip coordinates of each chip particle relative to the front coordinate system, and establish a mapping relationship with the front coordinate system according to the chip number; After determining the mapping relationship between the front coordinate system and the front alignment information, the method further includes: Place the wafer with the back side facing upward into the alignment mechanism for rotation adjustment, and detect and determine the groove position of the wafer.
6. The method according to claim 3, characterized in that The determining of the mapping relationship between the back side coordinate system and the front side alignment information to generate the back side standard alignment information of the wafer includes: Determine the target position of the groove in the back side state of the wafer based on the image acquisition device; at the target position, the coordinate axis direction of the back side coordinate system is parallel to the edge corresponding to the back side acquisition image of the wafer; Based on the back coordinate system of the wafer at the target position and the mapping relationship with the front alignment information, the relative position change between the groove and the reference alignment part when the wafer is adjusted to the target position is calculated and determined as the back standard alignment information.
7. The method according to claim 6, characterized in that After aligning the back side of the wafer according to the back side standard alignment information, the method further includes: Adjusting the groove of the wafer to a target position according to the back standard alignment information, and acquiring a back side acquisition image of the wafer through an image acquisition device; Perform defect detection on the back side captured image to determine the position coordinates of the target defect in the back side coordinate system; According to the mirror relationship between the back coordinate system and the front coordinate system, the target defect is mapped to the front coordinate system, and the defective chip in the front coordinate system is determined.
8. An automatic alignment device for wafer defect detection, characterized in that: The device comprises: An acquisition module, used to acquire front alignment information of the wafer and a front captured image of the wafer corresponding to the front alignment information; A determination module, used to identify the front center and the groove of the wafer according to the front collected image, determine the front coordinate system of the wafer based on the front center and the groove, and determine the mapping relationship between the front coordinate system and the front alignment information; The calculation module is used to determine the back coordinate system and its mapping relationship with the front alignment information based on the mirror relationship between the front coordinate system and the back coordinate system of the wafer, generate the back standard alignment information of the wafer, and align the back of the wafer according to the back standard alignment information.
9. A computer device, characterized in that: The computer device includes a processor and a memory, wherein the memory stores at least one instruction, at least one program, a code set or an instruction set, and the at least one instruction, the at least one program, the code set or the instruction set is loaded and executed by the processor to implement the automatic alignment method for wafer defect detection as described in any one of claims 1 to 7.
10. A computer-readable storage medium, characterized in that: The readable storage medium stores at least one instruction, at least one program, a code set or an instruction set, and the at least one instruction, the at least one program, the code set or the instruction set are loaded and executed by the processor to implement the automatic alignment method for wafer defect detection as described in any one of claims 1 to 7.