Manufacturing method of semiconductor structure

Abstract

The invention provides a manufacturing method of a semiconductor structure, and relates to the technical field of semiconductors, the manufacturing method of the semiconductor structure comprises the following steps: in the process of grinding the semiconductor structure by using grinding slurry, adding a porous matrix into the grinding slurry, anchoring oxide particles generated in the grinding process on the surface of the porous matrix, the porous substrate loads oxide particles to form a protective material, and the protective material protects the oxide particles from being ground and removed so as to reduce the oxidation rate of the semiconductor structure and reduce the oxide erosion defect formed on the surface of the semiconductor structure, and meanwhile, the protective material is attached to the surface of the semiconductor structure so as to improve the corrosion resistance of the semiconductor structure. The grinding rate of the grinding slurry for grinding the semiconductor structure is reduced, butterfly defects formed on the surface of the semiconductor structure due to too high grinding rate are reduced, the uniformity of the surface of the ground semiconductor structure is improved, and the quality and yield of the semiconductor structure are improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor structure. Background Art

[0002] Chemical mechanical polishing (CMP) is a planarization process that combines chemical polishing and mechanical polishing. Chemical mechanical polishing is the main means of surface planarization of semiconductor structures.

[0003] During the chemical mechanical polishing process, different materials have different polishing rates, which may form two major defects on the surface of the semiconductor structure: butterfly defects (Dishing) and oxide erosion defects (Erosion). Summary of the invention

[0004] The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of the claims.

[0005] The present disclosure provides a method for manufacturing a semiconductor structure, the method comprising the following steps:

[0006] grinding the surface of the semiconductor structure using a grinding slurry, and adding a porous matrix to the grinding slurry;

[0007] Oxide particles are generated during the grinding process. The oxide particles are loaded on the surface of the porous matrix to form a protective material. The protective material adheres to the surface of the semiconductor structure to inhibit the semiconductor structure from being oxidized and reduce the grinding rate of the semiconductor structure.

[0008] In some embodiments, the porous matrix includes zirconium phosphate.

[0009] In some embodiments, the surface of the semiconductor structure has a metal layer, and the oxide particles include metal oxide particles formed by grinding and oxidizing the metal layer.

[0010] In some embodiments, the metal oxide particles include at least one of tungsten oxide, titanium oxide, cobalt oxide, copper oxide, aluminum oxide, ruthenium oxide, rhodium oxide, tantalum oxide, antimony oxide, tin oxide, or indium oxide.

[0011] In some embodiments, the metal oxide particles are supported on the surface of the porous matrix in an amorphous state and / or a crystalline state.

[0012] In some embodiments, the porous matrix includes a mesoporous structure, and the oxide particles are supported in the mesoporous structure.

[0013] In some embodiments, the average pore size of the mesoporous structure is

[0014] In some embodiments, the specific surface area of ​​the porous matrix is ​​300 m 2 / g-450m 2 / g.

[0015] In some embodiments, the porous matrix has a porosity of 30%-50%.

[0016] In some embodiments, the porous matrix has a loading rate of the oxide particles of 5 wt % to 50 wt %.

[0017] In some embodiments, the porous matrix has a loading rate of the oxide particles of 30 wt % to 40 wt %.

[0018] In some embodiments, the amount of the porous matrix added is controlled so that the pH value of the polishing slurry is less than or equal to 4 during the polishing of the semiconductor structure.

[0019] In some embodiments, the method for manufacturing the semiconductor structure further includes:

[0020] The protective material is removed by grinding.

[0021] In some embodiments, the method for manufacturing the semiconductor structure further includes:

[0022] The protective material is treated with an organic solution.

[0023] In some embodiments, the organic solution comprises glycerol.

[0024] In the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure, a porous matrix is ​​added to the polishing slurry during the process of polishing the semiconductor structure with a polishing slurry, and oxide particles generated during the polishing process are anchored on the surface of the porous matrix. The porous matrix loads the oxide particles to form a protective material, and the protective material protects the oxide particles to prevent the oxide particles from being polished and removed, thereby reducing the oxidation rate of the semiconductor structure and reducing oxide corrosion defects formed on the surface of the semiconductor structure. At the same time, the protective material is attached to the surface of the semiconductor structure, reducing the polishing rate of the semiconductor structure polished by the polishing slurry, reducing butterfly defects formed on the surface of the semiconductor structure due to excessive polishing rate, improving the uniformity of the surface of the polished semiconductor structure, and improving the quality and yield of the semiconductor structure.

[0025] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings incorporated into the specification and constituting a part of the specification illustrate embodiments of the present disclosure and are used together with the description to explain the principles of the embodiments of the present disclosure. In these drawings, similar reference numerals are used to represent similar elements. The drawings described below are some embodiments of the present disclosure, rather than all embodiments. For those skilled in the art, other drawings can be obtained based on these drawings without paying creative work.

[0027] Figure 1 The invention is a flow chart of a method for manufacturing a semiconductor structure according to an exemplary embodiment.

[0028] Figure 2 The invention is a flow chart of a method for manufacturing a semiconductor structure according to an exemplary embodiment.

[0029] Figure 3 FIG. 4 is a schematic diagram showing an operation of grinding a semiconductor structure according to an exemplary embodiment.

[0030] Figure 4 FIG. 4 is a schematic diagram showing a porous matrix loaded with oxide particles according to an exemplary embodiment.

[0031] Figure 5 is a schematic diagram of a mesoporous structure according to an exemplary embodiment.

[0032] Figure 6 is a schematic diagram of a protective material according to an exemplary embodiment.

[0033] Figure 7 is a schematic diagram of a semiconductor structure according to an exemplary embodiment.

[0034] Figure 8 is a schematic diagram showing a portion of a metal layer being removed by grinding according to an exemplary embodiment.

[0035] Fig. 9 is a schematic diagram showing adding a porous matrix into a polishing slurry according to an exemplary embodiment.

[0036] Fig.10 is a schematic diagram showing a protective material formed on the surface of a semiconductor structure according to an exemplary embodiment.

[0037] Fig.11 is a schematic diagram showing a state after a protective material is removed according to an exemplary embodiment.

[0038] Reference numerals:

[0039] 1. Semiconductor structure; 11. Substrate; 12. Bit line; 13. Dielectric material layer; 14. Barrier layer; 2. Polishing slurry; 3. Polishing table; 4. Polishing pad; 5. Porous matrix; 51. Mesoporous structure; 6. Oxide particles; 7. Protective material; 8. Metal layer. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present disclosure. It should be noted that the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other without conflict.

[0041] Chemical mechanical polishing (CMP) is a planarization process that combines chemical polishing and mechanical polishing. Chemical mechanical polishing is the main means of surface planarization of semiconductor structures. During the chemical mechanical polishing process, different materials have different polishing rates, which may form two main defects on the surface of the semiconductor structure: butterfly defects (Dishing) and oxide erosion defects (Erosion). The defects formed on the surface of the semiconductor structure by chemical mechanical polishing directly affect the quality and yield of the semiconductor structure.

[0042] In view of this, an exemplary embodiment of the present disclosure provides a method for manufacturing a semiconductor structure. In the process of grinding the semiconductor structure with a grinding slurry, a porous matrix is ​​added to the grinding slurry. Oxide particles generated during the grinding process are anchored on the surface of the porous matrix. The porous matrix loads the oxide particles to form a protective material. The protective material protects the oxide particles to prevent the oxide particles from being ground and removed, thereby reducing the oxidation rate of the semiconductor structure and reducing oxide corrosion defects formed on the surface of the semiconductor structure. At the same time, the protective material is attached to the surface of the semiconductor structure, reducing the grinding rate of the semiconductor structure when the grinding slurry is used to grind the semiconductor structure, reducing butterfly defects formed on the surface of the semiconductor structure due to excessive grinding rate, improving the uniformity of the surface of the ground semiconductor structure, and improving the quality and yield of the semiconductor structure.

[0043] In an exemplary embodiment of the present disclosure, a method for manufacturing a semiconductor structure is provided. Figure 1 As shown, Figure 1A flow chart of a method for manufacturing a semiconductor structure provided according to an exemplary embodiment of the present disclosure is shown. The method for manufacturing a semiconductor structure of this embodiment is applied, for example, in the manufacturing process of any semiconductor structure such as a dynamic random access memory (DRAM), a static random access memory (SRAM), a flash EPROM, a ferroelectric random access memory (FRAM), a magnetic random access memory (MRAM), a phase change random access memory (PRAM), etc.

[0044] like Figure 1 As shown, an exemplary embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, the manufacturing method comprising the following steps:

[0045] Step S110: grinding the surface of the semiconductor structure with grinding slurry, and adding a porous matrix into the grinding slurry.

[0046] Step S120: Oxide particles are generated during the grinding process. The oxide particles are loaded on the surface of the porous matrix to form a protective material. The protective material adheres to the surface of the semiconductor structure to inhibit oxidation of the semiconductor structure and reduce the grinding rate of the semiconductor structure.

[0047] In step S110, refer to Figure 3 As shown, the semiconductor structure 1 may be a semiconductor substrate or a semiconductor wafer. The semiconductor structure 1 may include a semiconductor material layer, such as a dielectric layer or a metal layer, for forming a semiconductor element. The material of the semiconductor substrate may be silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); it may also be silicon on insulator (SOI), germanium on insulator (GOI); or it may also be other materials, such as III-V compounds such as gallium arsenide. Certain impurity ions may be doped into the semiconductor substrate as required, and the impurity ions may be N-type impurity ions or P-type impurity ions. The semiconductor material layer may be an amorphous carbon layer, an oxide layer, a nitride layer, a copper layer, a tungsten layer, an aluminum layer, etc., but is not limited thereto.

[0048] Reference Figure 3As shown, a polishing slurry 2 including abrasive particles is sprayed onto the surface of the semiconductor structure 1 to drive the semiconductor structure 1 to rotate (the semiconductor structure 1 can be placed on a polishing table 3, and a driving structure is used to drive the polishing table 3 to rotate so as to rotate the semiconductor structure 1), and a polishing pad 4 is used to rub the polishing slurry 2 so that the abrasive particles in the polishing slurry 2 grind the surface of the semiconductor structure 1.

[0049] Reference Figure 3 , Figure 4 As shown, during the grinding process, the porous matrix 5 is added to the grinding slurry 2, and the grinding pad 4 rubs the grinding slurry 2 to evenly disperse the porous matrix 5 on the surface of the semiconductor structure 1. In this embodiment, the porous matrix 5 itself has no catalytic effect and no oxidizing effect. The porous matrix 5 can be an inorganic matrix, or the porous matrix 5 can also be an organic matrix. The porous matrix 5 includes a pore structure, and the pore structure of the porous matrix 5 can include a microporous structure and / or a mesoporous structure and / or a macroporous structure. The pore structure increases the surface area of ​​the porous matrix 5 and can improve the loading rate of the porous matrix 5.

[0050] The present embodiment does not impose any specific restrictions on the shape and size of the porous matrix 5 . The porous matrix 5 may be nano-scale particles, and the porous matrix 5 may be in a spherical, quasi-spherical, ellipsoidal, or other shapes.

[0051] In step S120, refer to Figure 3 , Figure 4 , Figure 5 , Figure 6 As shown, during the grinding process, the semiconductor structure 1 is ground and oxidized to form oxide particles 6, the porous matrix 5 contacts the oxide particles 6, the oxide particles 6 are loaded on the surface of the porous matrix 5, the porous matrix 5 loads the oxide particles 6 to form a protective material 7, the protective material 7 aggregates on the surface of the semiconductor structure 1 and adheres to the surface of the semiconductor structure 1, the protective material 7 blocks the contact between the grinding slurry 2 and the surface of the semiconductor structure 1, reduces the grinding rate of the grinding slurry 2 on the semiconductor structure 1, thereby avoiding the grinding rate of the semiconductor structure 1 being too fast, and forming a butterfly defect on the top surface of the semiconductor structure 1. At the same time, the oxide particles 6 formed by the oxidation of the semiconductor structure 1 are loaded on the porous matrix 5 to form the protective material 7, and the protective material 7 is attached to the surface of the semiconductor structure 1, which has the effect of protecting the oxide particles 6 and preventing the oxide particles 6 from being ground and removed, and can inhibit the surface of the semiconductor structure 1 from being further oxidized, and reduce the oxide erosion defects formed on the top surface of the semiconductor structure 1 during the grinding process.

[0052] In the method for manufacturing the semiconductor structure of the present embodiment, a porous matrix is ​​added to the grinding slurry during the grinding of the semiconductor structure. The oxide particles generated during the grinding process are loaded on the surface of the porous substrate to form a protective material. The protective material is attached to the top surface of the semiconductor structure, which can protect the oxide particles from being ground away, and can also protect the top surface of the semiconductor structure, reduce the grinding rate of the semiconductor structure when the grinding slurry is used, and reduce the butterfly defects and oxide erosion defects formed on the surface of the semiconductor structure during the grinding process.

[0053] According to an exemplary embodiment, this embodiment is an explanation of the above-mentioned embodiment, referring to Figure 3 , Figure 4 , Figure 5 , Figure 6 As shown, the porous matrix 5 is an inorganic matrix, and the porous matrix 5 includes a layered solid acid structure. There are acidic sites on the surface of the porous matrix 5. After the oxide particles 6 contact the porous matrix 5, the oxide particles 6 are anchored on the acidic sites of the porous matrix 5, thereby forming a structure in which the porous matrix 5 loads the oxide particles 6 to form a protective material 7.

[0054] The porous matrix 5 may include layered phosphates, for example, the porous matrix 5 may include at least one of zirconium phosphate Zr(HPO4)2·H2O, titanium phosphate Ti(HPO4)2·2H2O, hafnium phosphate Hf(HPO4)2·H2O, tin phosphate Sn(HPO4)2·2H2O, or M(IV)(HPO4)x·nH2O, wherein M(IV) is a tetravalent metal and n>1.

[0055] The porous matrix 5 includes a mesoporous structure 51, and the oxide particles 6 are loaded in the mesoporous structure 51. The mesoporous structure 51 increases the specific surface area of ​​the porous matrix 5, so that the porous matrix 5 can load more oxide particles 6. At the same time, the oxide particles 6 are located in the mesoporous structure 51, which prevents the oxide particles 6 from being exposed to the process space, protects the oxide particles 6 from being removed by grinding, and retains more oxide particles 6 in the grinding system, thereby suppressing the oxidation rate of the semiconductor structure 1 and reducing the oxide corrosion defects formed on the surface of the semiconductor structure 1 during the grinding process.

[0056] Among them, the average pore size of the mesoporous structure 51 is For example, the average pore size of the mesoporous structure 51 can be or The average pore size of the mesoporous structure 51 is In the meantime, the oxide particles 6 formed by grinding and oxidation of the semiconductor structure 1 can smoothly enter the interior of the mesoporous structure 51 , and the oxide particles 6 are anchored on the acidic sites on the inner surface of the mesoporous structure 51 .

[0057] The specific surface area of ​​the porous matrix 5 is 300 m 2 / g-450m 2 For example, the specific surface area of ​​the porous matrix 5 can be 300 m 2 / g, 320m 2 / g, 340m 2 / g, 350m 2 / g, 370m 2 / g, 390m 2 / g, 400m 2 / g, 430m 2 / g or 450m 2 / g, etc.

[0058] The porosity of the porous matrix 5 is 30%-50%. For example, the porosity of the porous matrix 5 can be 30%, 32%, 34%, 35%, 38%, 40%, 43%, 46%, 48% or 50%. The higher the porosity of the porous matrix 5, the more oxide particles 6 the porous matrix can load, thereby protecting more oxide particles 6 from being ground away, and reducing the oxidation rate of the semiconductor structure.

[0059] In some embodiments, the loading rate of the oxide particles 6 on the porous matrix 5 is 5wt%-50wt%. For example, the loading rate of the oxide particles 6 on the porous matrix 5 is 5wt%, 10wt%, 15wt%, 20wt%, 25wt%, 30wt%, 35wt%, 40wt%, 45wt%, 50wt%. In some embodiments, the loading rate of the oxide particles 6 on the porous matrix 5 is 30wt%-40wt%. For example, the loading rate of the oxide particles 6 on the porous matrix 5 is 31wt%, 32wt%, 33wt%, 34wt%, 35wt%, 36wt%, 37wt%, 38wt%, 39wt%.

[0060] In some embodiments, the porous matrix 5 includes zirconium phosphate. Zirconium phosphate is a layered phosphate that is easy to synthesize and has excellent performance. Zirconium phosphate has a uniform and ordered mesoporous structure 51, a uniform pore size distribution of the mesoporous structure 51, a large specific surface area and pore volume, and zirconium phosphate can provide a large number of acidic sites. In this embodiment, zirconium phosphate is used as the porous matrix 5. Zirconium phosphate has good stability and will not affect the oxidation process of the material of the semiconductor structure 1. In other words, zirconium phosphate will not catalyze the oxidation of the material of the semiconductor structure 1.

[0061] According to an exemplary embodiment, this embodiment is an explanation of the above-mentioned embodiment, referring to Figure 7 The surface of the semiconductor structure 1 has a metal layer 8 , and the oxide particles 6 include metal oxide particles formed by grinding and oxidizing the metal layer 8 .

[0062] The present embodiment does not limit the material of the metal layer 8, and the material of the metal layer 8 may include any metal material commonly used in the semiconductor field, for example, the material of the metal layer 8 may include at least one of tungsten, titanium, cobalt, copper, aluminum, ruthenium, rhodium, tantalum, antimony, tin or indium. It is understandable that the surface of the semiconductor structure may include a film layer of other materials, for example, a dielectric material layer, etc.

[0063] The polishing slurry 2 may include an oxidant, a catalyst, etc. During the polishing process, the surface of the metal layer 8 contacts the polishing slurry 2, and the metal layer 8 is oxidized by the oxidant to form a metal oxide. The metal oxide is ground into metal oxide particles, and the metal oxide particles include at least one of tungsten oxide, titanium oxide, cobalt oxide, copper oxide, aluminum oxide, ruthenium oxide, rhodium oxide, tantalum oxide, antimony oxide, tin oxide or indium oxide. The metal oxide particles contact the porous matrix 5 and enter the mesoporous structure 51 of the porous matrix 5. The metal oxide is anchored on the acidic site of the porous matrix 5. The porous matrix 5 carries the metal oxide particles to form the protective material 7. The protective material 7 aggregates and agglomerates on the surface of the semiconductor structure 1 into a block. The protective material 7 adheres to the surface of the semiconductor structure. The protective material 7 blocks the contact between the polishing slurry 2, the polishing pad 4 and the surface of the semiconductor structure 1, which can reduce the polishing rate of the semiconductor structure 1, avoid over-polishing due to excessive polishing rate, and form butterfly defects on the surface of the semiconductor structure 1.

[0064] According to the principle of chemical equilibrium shift, if the reaction conditions (such as the concentration of the chemical substances participating in the reaction, pressure, temperature, etc.) are changed, the chemical equilibrium will be destroyed and move in the direction of weakening this change. For example, when other conditions remain unchanged, increasing the concentration of reactants or decreasing the concentration of products will shift the equilibrium in the direction of the forward reaction; decreasing the concentration of reactants or increasing the concentration of products will shift the equilibrium in the direction of the reverse reaction.

[0065] The protective material 7 is attached to the surface of the semiconductor structure 1, and the porous matrix 5 is loaded with metal oxide particles to prevent the metal oxide particles from being ground and removed from the surface of the semiconductor structure 1. As the grinding progresses, more and more metal oxide particles are loaded on the porous matrix 5, which increases the concentration of the metal oxide particles in the grinding system, that is, increases the concentration of the product in the grinding system, thereby inhibiting the oxidation of the metal layer 8, reducing the oxidized portion of the metal layer 8, and reducing the oxide corrosion defects formed on the surface of the semiconductor structure 1 by the oxidation of the metal layer 8, thereby improving the quality of the formed semiconductor structure.

[0066] The metal oxide particles may be loaded on the surface of the porous substrate 5 in an amorphous state and / or a crystalline state. It is understood that the state of the metal oxide particles is related to the loading rate of the metal oxide particles loaded on the porous substrate 5. Generally speaking, when the loading rate of the metal oxide particles loaded on the porous substrate 5 is low, the metal oxide particles exist in an amorphous state. As the loading rate of the porous substrate 5 increases, the state of the metal oxide particles loaded on the porous substrate 5 gradually changes to a crystalline state.

[0067] According to an exemplary embodiment, this embodiment is an explanation of the above-mentioned embodiment. In this embodiment, during the process of grinding the semiconductor structure 1, the amount of porous matrix 5 added is controlled so that the pH value of the grinding slurry 2 is less than or equal to 4 during the process of grinding the semiconductor structure 1.

[0068] During the chemical mechanical polishing process, an acidic polishing slurry 2 is usually used to polish the semiconductor structure 1. The smaller the pH value of the polishing slurry 2, the faster the polishing rate. Moreover, the closer the pH value of the polishing slurry 2 is to 4, the milder the butterfly defects and oxide corrosion defects on the surface of the polished semiconductor structure 1 are, and the smoother the surface of the semiconductor structure 1 is.

[0069] In this embodiment, the porous matrix 5 added to the polishing slurry 2 is also an acidic material. However, as the polishing process proceeds, the oxide particles 6 are loaded on the surface of the porous matrix 5 to form a protective material 7. The acidity value of the protective material 7 changes, which may cause the pH value of the polishing slurry 2 to change.

[0070] By analyzing the acidity value of the protective material, it is found that when the loading rate of the porous matrix 5 loaded with oxide particles 6 is between 5wt% and 30wt%, the acidity value of the protective material 7 increases with the increase of the loading rate; when the loading rate of the porous matrix 5 loaded with oxide particles 6 increases to 40wt%, the acidity value of the protective material 7 decreases with the increase of the loading rate. Among them, when the acidity value of the protective material 7 increases, the pH value of the polishing slurry 2 decreases, and when the acidity value of the protective material 7 decreases, the pH value of the polishing slurry 2 increases.

[0071] The oxide particles 6 are loaded on the surface of the porous matrix 5 to form the protective material 7. The main factors affecting the acidity of the protective material 7 are the P-OH groups and dispersed oxide groups on its surface. Therefore, when the loading rate is low, after the oxide particles 6 enter the mesoporous structure 51 of the porous matrix 5, the oxide particles 6 are irregular and amorphous, and the oxide particles 6 are dispersed in the mesoporous structure 51. The oxide groups in the protective material 7 increase, the acidity and strength of the acid sites of the porous matrix 5 increase, the acidity value of the protective material 7 increases, and the pH of the grinding slurry 2 decreases. As the loading rate of the porous matrix 5 increases, the oxide particles 6 aggregate to form three-dimensional oxide clusters, and some oxide particles 6 combine with P-OH groups, reducing the free P-OH groups, causing the acidity of the protective material 7 to decrease and the pH of the grinding slurry 2 to increase.

[0072] This embodiment controls the amount of porous matrix 5 added to the polishing slurry 2, controls the loading rate of oxide particles 6 on the porous matrix 5 to be around 30wt%, controls the pH value of the polishing slurry 2 to be less than or equal to 4, and reduces butterfly defects and oxide corrosion defects on the surface of the semiconductor structure 1 after polishing.

[0073] It can be understood that in some embodiments, in order to reduce the butterfly defects and oxide corrosion defects on the surface of the semiconductor structure 1 after grinding, deionized water can be added to the grinding slurry 2 during the grinding process. The pH value of the deionized water is 7. The pH value of the grinding slurry 2 is adjusted by controlling the amount of deionized water and the porous matrix 5 added so that the pH value of the grinding slurry 2 is close to 4, thereby reducing the butterfly defects and oxide corrosion defects on the surface of the semiconductor structure 1 after grinding, reducing the loss of the semiconductor structure 1 during the grinding process, and improving the surface smoothness of the semiconductor structure 1, so that the grinding process is more precise and controllable.

[0074] According to an exemplary embodiment, which is an explanation of the above embodiment, the method for manufacturing a semiconductor structure further includes the following steps: grinding and removing the protective material.

[0075] Reference Figure 3 , Figure 6 As shown, during the grinding process, the grinding pad 4 rubs the grinding slurry 2. Since the protective material 7 is a loose and porous structure, under the action of friction, the grinding pad 4 can grind away the protective material 7 attached to the surface of the semiconductor structure 1 to expose the surface of the semiconductor structure 1.

[0076] In some cases, such as when the protective material 7 and the surface of the semiconductor structure 1 are closely attached, it is difficult to remove the protective material 7 by friction with the polishing pad 4, or when the polishing process needs to be ended as soon as possible in order to shorten the processing time, an organic solution can be used to treat the protective material 7. The organic solution is sprayed on the surface of the semiconductor structure, and the protective material 7 is removed by dissolving it with the organic solvent, or the difficulty of removing the protective material 7 is reduced by the reaction between the organic solvent and the protective material 7, and then the protective material 7 is removed by cleaning or polishing, so that the protective material 7 is quickly removed from the surface of the semiconductor structure 1.

[0077] The organic solution may include glycerol. Glycerol and the porous matrix 5 are in contact to undergo a gas phase dehydration reaction to generate 3-hydroxypropionic acid aldehyde and 1-hydroxyacetone. This reaction is a double dehydration reaction, that is, the porous matrix 5 also undergoes a dehydration reaction. Then, the protective material 7 can be removed from the surface of the semiconductor structure 1 by washing the protective material 7 with deionized water.

[0078] like Figure 2 As shown, Figure 2 A flow chart of a method for manufacturing a semiconductor structure provided according to an exemplary embodiment of the present disclosure is shown. A method for manufacturing a semiconductor structure provided by an exemplary embodiment of the present disclosure is described. This embodiment is introduced by taking the process of forming a capacitor contact plug in the process of a dynamic random access memory as an example, but this embodiment is not limited to this. The semiconductor structure in this embodiment can also be other structures.

[0079] like Figure 2 As shown, a method for manufacturing a semiconductor structure provided by an exemplary embodiment of the present disclosure includes the following steps:

[0080] Step S210: providing a semiconductor structure, wherein the semiconductor structure includes a metal layer.

[0081] like Figure 7 As shown, the semiconductor structure 1 includes a substrate 11, wherein the substrate 11 is a semiconductor substrate, and the substrate 11 may also include a capacitor contact plug (not shown in the figure), and a plurality of discrete bit lines 12 are also arranged in the substrate 11, the surface of the bit line 12 is covered by a dielectric material layer 13, the surface of the dielectric material layer 13 is covered by a barrier layer 14, and the metal layer 8 is filled between adjacent dielectric material layers 13 and covers the top surface of the dielectric material layer 13. The barrier layer 14 separates the dielectric material layer 13 and the metal layer 8 to prevent the material of the metal layer 8 from diffusing into the dielectric material layer 13 and contaminating the dielectric material layer 13. Among them, the substrate 11 is a silicon crystal substrate; the material of the dielectric material layer 13 includes silicon nitride; the material of the barrier layer 14 includes metal tantalum or a tantalum compound; the material of the metal layer 8 includes metal tungsten.

[0082] Step S220: grinding the surface of the metal layer with grinding slurry, and adding a porous matrix into the grinding slurry during the grinding of the metal layer.

[0083] Reference Figure 3 , Figure 7 As shown, in the chemical mechanical polishing process, the polishing slurry 2 is selected according to the material to be polished. In this embodiment, the metal layer 8 to be polished includes tungsten metal. The polishing slurry used to polish the metal layer 8 is a homogeneous solution formed by dispersing abrasive particles, oxidants, catalysts, etc. in a solvent. The pH value of the polishing slurry 2 is about 2.1. Among them, the solvent can be water or an organic solvent. The organic solvent can be alcohols, ethers, ketones, glycols, organic acids and combinations thereof.

[0084] During grinding, the substrate 11 is placed on the grinding table 3, the grinding table 3 is driven to rotate to drive the substrate 11 to rotate, the grinding slurry 2 is sprayed onto the top surface of the metal layer 8, and the grinding pad 4 is used to rub the grinding slurry 2 to grind the top surface of the metal layer 8.

[0085] Reference Figure 8 As shown, after a portion of the metal layer 8 is removed by grinding, the top surface of the dielectric material layer 13 is exposed, and a porous matrix 5 is added to the grinding slurry 2. The porous matrix 5 in this embodiment includes zirconium phosphate Zr(HPO4)2·H2O. Zirconium phosphate is a layered phosphate that is easy to synthesize and has excellent performance. Figure 4 , Figure 5 As shown, zirconium phosphate has a uniform and ordered mesoporous structure 51, and the average pore size of the mesoporous structure 51 is The specific surface area of ​​the porous matrix 5 is 300 m 2 / g-450m 2 / g, and the porosity of the porous matrix 5 is 30%-50%.

[0086] The zirconium phosphate used in this embodiment can be a commercially available product, or can be prepared by a known method. For example, the zirconium phosphate is prepared by a hydrothermal method, and the prepared zirconium phosphate is added to the polishing slurry 2 .

[0087] Step S230: metal oxide particles are generated during the grinding process. The metal oxide particles are loaded on the surface of the porous matrix to form a protective material. The protective material adheres to the surface of the semiconductor structure to inhibit oxidation of the metal layer and reduce the grinding rate of the metal layer.

[0088] Reference Fig. 9 , Fig.10As shown, during the grinding process, the oxidant decomposes a large number of hydroxyl radicals, and part of the metal layer 8 is catalytically oxidized under the action of the oxidant and the catalyst in the grinding slurry to form loose metal oxides, namely tungsten oxide (WO3). The tungsten oxide is ground to produce tungsten oxide particles, which contact zirconium phosphate and enter the mesoporous structure 51 of zirconium phosphate (see Figure 4 or Figure 5 ), the tungsten oxide particles are anchored on the acidic sites of zirconium phosphate, and the zirconium phosphate loads the tungsten oxide particles to form a protective material 7.

[0089] The protective material 7 is aggregated on the top surface of the metal layer 8 and attached to the top surface of the metal layer 8. The protective material 7 blocks the contact between the polishing slurry 2 and the top surface of the metal layer 8, and the polishing rate of the polishing slurry 2 polishing the metal layer 8 is reduced under the action of the protective material 7, thereby reducing the depth of the butterfly defect formed on the top surface of the metal layer 8 due to over-polishing caused by the excessively fast polishing rate of the metal layer 8 at the end of the polishing.

[0090] At the same time, tungsten oxide particles are loaded in the mesoporous structure of zirconium phosphate 51 (refer to Figure 4 or Figure 5 ), zirconium phosphate protects the tungsten oxide particles to prevent the tungsten oxide particles produced by the oxidation of the metal layer 8 from being ground away during the grinding process. The concentration of tungsten oxide particles in the grinding system increases, which can reduce the oxidation rate of the metal layer 8, inhibit the further oxidation of the metal layer 8, and reduce the consumption of the metal layer 8, thereby reducing the depth of oxidation of the top surface of the metal layer 8 and the depth of oxide corrosion defects formed by the oxidation of the metal layer 8.

[0091] Step S240: Grinding and removing the protective material.

[0092] Reference Fig.10 and Fig.11 As shown, the protective material 7 is a loose and porous structure, and the protective material 7 can be removed from the surface of the metal layer 8 by grinding the grinding slurry 2 through the grinding pad 4, exposing the top surface of the metal layer 8.

[0093] It is understandable that glycerol (also known as glycerol) can also be sprayed onto the surface of the protective material 7. The glycerol used in this embodiment can be a commercially available product or can be prepared by a known method. Glycerol contacts zirconium phosphate to undergo gas phase dehydration to generate 3-hydroxypropionic acid aldehyde and 1-hydroxyacetone, and glycerol and zirconium phosphate undergo double dehydration. Then, the protective material 7 can be removed from the surface of the semiconductor structure by rinsing the protective material 7 with deionized water, exposing the top surface of the metal layer 8, and preventing the protective material 7 from remaining on the surface of the semiconductor structure.

[0094] In this embodiment, zirconium phosphate is added to the polishing slurry 2, and tungsten oxide particles generated by the oxidation of the metal layer 8 loaded with zirconium phosphate form a protective material 7. The protective material 7 protects the tungsten oxide particles and prevents the tungsten oxide particles from being ground away, thereby increasing the concentration of tungsten oxide particles in the polishing system and reducing the oxidation rate of the metal layer 8, thereby reducing oxide corrosion defects formed on the surface of the metal layer 8. The protective material 7 agglomerates on and covers the surface of the metal layer 8, so that the friction force of the polishing pad 4 rubbing the polishing slurry 2 acts on the protective material 7, thereby reducing the polishing rate of the polished metal layer 8 and avoiding butterfly defects formed on the top surface of the metal layer 8 due to excessive polishing rate.

[0095] The quality of the top surface of the semiconductor structure after grinding in this embodiment is tested. The surface uniformity NU of the semiconductor structure after grinding in this embodiment is <5%, the depth of the butterfly defect on the top surface of the metal layer 8 is 1nm-5nm, and the depth of the butterfly defect on the top surface of the dielectric material layer 13 is less than 5nm.

[0096] In some embodiments, during the polishing process, the amount of the porous matrix 5 added to the polishing slurry 2 is controlled so that the pH value of the polishing slurry 2 is less than or equal to 4 during the polishing of the semiconductor structure.

[0097] As the grinding process progresses, the tungsten oxide particles in the grinding system increase, and the loading rate of the tungsten oxide particles supported by the porous matrix 5 increases. In this embodiment, by controlling the amount of the porous matrix 5 added and the amount of deionized water added to the grinding slurry 2, the loading amount of the tungsten oxide particles supported by the porous matrix 5 is between 30wt% and 40wt%, and the pH value of the grinding slurry 2 is controlled to be less than or equal to 4. Avoid the increase of tungsten oxide particles causing the pH value of the grinding slurry 2 to change, affecting the grinding effect.

[0098] According to an exemplary embodiment, this embodiment provides a polishing slurry, in which a porous matrix is ​​added. The porous matrix is ​​an inorganic matrix, the porous matrix includes a layered solid acid structure, and there are acidic sites on the surface of the porous matrix. After the oxide particles and the porous matrix are attached, the oxide particles are anchored on the acidic sites of the porous matrix and the acidic site structure, thereby forming a structure in which the porous matrix loads the oxide particles to form a protective material.

[0099] The porous matrix may include layered phosphates, for example, the porous matrix may include at least one of zirconium phosphate Zr(HPO4)2·H2O, titanium phosphate Ti(HPO4)2·2H2O, hafnium phosphate Hf(HPO4)2·H2O, tin phosphate Sn(HPO4)2·2H2O, or M(IV)(HPO4)x·nH2O, wherein M(IV) is a tetravalent metal and n>1.

[0100] The porous matrix includes a mesoporous structure. The average pore size of the mesoporous structure is For example, the average pore size of the mesoporous structure can be or

[0101] The specific surface area of ​​the porous matrix is ​​300m2 / g-450m2 / g. For example, the specific surface area of ​​the porous matrix can be 300m 2 / g, 320m 2 / g, 340m 2 / g, 350m 2 / g, 370m 2 / g, 390m 2 / g, 400m 2 / g, 430m 2 / g or 450m 2 / g, etc.

[0102] The porosity of the porous matrix is ​​30%-50%. For example, the porosity of the porous matrix can be 30%, 32%, 34%, 35%, 38%, 40%, 43%, 46%, 48% or 50%.

[0103] In some embodiments, the porous matrix supports the oxide particles at a loading rate of 5 wt % to 50 wt %. In some embodiments, the porous matrix supports the oxide particles at a loading rate of 30 wt % to 40 wt %.

[0104] In some embodiments, the polishing slurry further includes abrasive particles, an oxidizing agent, a catalyst, and the like.

[0105] In some embodiments, the polishing slurry is a homogeneous solution formed by dispersing abrasive particles, an oxidant, a catalyst and a porous matrix into a solvent. The solvent may be water or an organic solvent. The organic solvent may be alcohols, ethers, ketones, glycols, organic acids and combinations thereof.

[0106] In some embodiments, the pH value of the polishing slurry is less than or equal to 4. For example, the pH value of the polishing slurry can be 2.1, 2.5, 3, 3.5 or 4.

[0107] The various embodiments or implementation methods in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referenced to each other.

[0108] In the description of this specification, reference to the terms "embodiment", "exemplary embodiment", "some embodiments", "illustrative embodiment", "example", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure.

[0109] In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0110] In the description of the present disclosure, it should be noted that the terms "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0111] It is to be understood that the terms "first", "second", etc. used in the present disclosure can be used to describe various structures in the present disclosure, but these structures are not limited by these terms. These terms are only used to distinguish a first structure from another structure.

[0112] In one or more of the accompanying drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of simplicity, the structure obtained after several steps can be described in one figure. Many specific details of the present disclosure, such as the structure, materials, dimensions, processing technology and technology of the device are described below to more clearly understand the present disclosure. However, as those skilled in the art will appreciate, the present disclosure may not be implemented in accordance with these specific details.

[0113] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A method for manufacturing a semiconductor structure, It is characterized in that The method for manufacturing the semiconductor structure comprises the following steps: grinding the surface of the semiconductor structure using a grinding slurry, and adding a porous matrix to the grinding slurry; Oxide particles are generated during the grinding process. The oxide particles are loaded on the surface of the porous matrix to form a protective material. The protective material adheres to the surface of the semiconductor structure to inhibit the semiconductor structure from being oxidized and reduce the grinding rate of the semiconductor structure.

2. The method for manufacturing a semiconductor structure according to claim 1, It is characterized in that The porous matrix includes zirconium phosphate.

3. The method for manufacturing a semiconductor structure according to claim 1, It is characterized in that The surface of the semiconductor structure has a metal layer, and the oxide particles include metal oxide particles formed by grinding and oxidizing the metal layer.

4. The method for manufacturing a semiconductor structure according to claim 3, It is characterized in that The metal oxide particles include at least one of tungsten oxide, titanium oxide, cobalt oxide, copper oxide, aluminum oxide, ruthenium oxide, rhodium oxide, tantalum oxide, antimony oxide, tin oxide or indium oxide.

5. The method for manufacturing a semiconductor structure according to claim 3, It is characterized in that The metal oxide particles are supported on the surface of the porous matrix in an amorphous state and / or a crystalline state.

6. The method for manufacturing a semiconductor structure according to any one of claims 1 to 5, It is characterized in that The porous matrix includes a mesoporous structure, and the oxide particles are supported in the mesoporous structure.

7. The method for manufacturing a semiconductor structure according to claim 6, It is characterized in that The average pore size of the mesoporous structure is 8. The method for manufacturing a semiconductor structure according to any one of claims 1 to 5, It is characterized in that The specific surface area of ​​the porous matrix is ​​300 m 2 / g-450m 2 / g.

9. The method for manufacturing a semiconductor structure according to any one of claims 1 to 5, It is characterized in that The porosity of the porous matrix is ​​30%-50%.

10. The method for manufacturing a semiconductor structure according to any one of claims 1 to 5, It is characterized in that The porous matrix has a loading rate of the oxide particles of 5 wt % to 50 wt %.

11. The method for manufacturing a semiconductor structure according to any one of claims 1 to 5, It is characterized in that The porous matrix has a loading rate of the oxide particles of 30 wt % to 40 wt %.

12. The method for manufacturing a semiconductor structure according to any one of claims 1 to 5, It is characterized in that The amount of the porous matrix added is controlled so that the pH value of the polishing slurry is less than or equal to 4 during the polishing of the semiconductor structure.

13. The method for manufacturing a semiconductor structure according to any one of claims 1 to 5, It is characterized in that The method for manufacturing the semiconductor structure further includes: The protective material is removed by grinding.

14. The method for manufacturing a semiconductor structure according to claim 12, It is characterized in that The method for manufacturing the semiconductor structure further includes: The protective material is treated with an organic solution.

15. The method for manufacturing a semiconductor structure according to claim 14, It is characterized in that The organic solvent includes glycerol.

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