Semiconductor structure and preparation method thereof

Abstract

The embodiment of the invention provides a semiconductor structure and a preparation method thereof. The semiconductor structure comprises a semiconductor substrate, wherein a groove is formed in the semiconductor substrate; and a first dielectric layer, a pinning layer and a second dielectric layer are sequentially arranged on the inner wall of the groove. When the semiconductor structure disclosed by the embodiment of the invention works, the second dielectric layer traps charges, and the pinning layer is arranged between the first dielectric layer and the second dielectric layer and can absorb the trapped charges, so that a local electric field at a corresponding position is reduced, hot carriers are prevented from being accumulated to the top of the first dielectric layer to generate breakdown on the semiconductor structure, and the reliability of the semiconductor structure is improved. Therefore, the semiconductor structure is prevented from being damaged by hot carrier accumulation, and the electrical performance of the semiconductor structure is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] In the isolation structure of semiconductor devices, a stacked structure of oxide-nitride-oxide is usually used to form a shallow trench isolation (STI) to balance stress and ensure the smooth progress of subsequent processes.

[0003] However, when the semiconductor device is working, the nitride will capture charges, and the captured charges will cause the hot carriers in the device to accumulate to the top of the oxide in the STI structure, that is, the shoulder of the active region, thereby affecting the electrical performance of the semiconductor device. For example, the accumulated hot carriers apply a negative voltage to the PMOS (P Metal Oxide Semiconductor), continuously reducing the threshold voltage of the PMOS, resulting in hot electron induced breakdown.

[0004] The above information disclosed in this background section is only for enhancement of understanding of the background of the present disclosure and therefore it may include information that does not constitute the relevant technology that is already known to one of ordinary skill in the art. Summary of the invention

[0005] The embodiments of the present disclosure provide a semiconductor structure and a method for preparing the same, which can prevent hot carrier accumulation from damaging the semiconductor structure and improve the electrical performance of the semiconductor structure.

[0006] The embodiment of the present disclosure provides a semiconductor structure, including: a semiconductor substrate having a groove therein; a first dielectric layer, a pinning layer, and a second dielectric layer are sequentially arranged on the inner wall of the groove.

[0007] In some embodiments of the present disclosure, the pinned layer is a stacked layer including a first sub-layer and a second sub-layer.

[0008] In some embodiments of the present disclosure, the number of the stacked layers is multiple.

[0009] In some embodiments of the present disclosure, the material of the first sublayer includes at least one of HfO2, ZrO2, SrTiO3, and TiO2, and the material of the second sublayer includes at least one of single crystal silicon, polycrystalline silicon, and amorphous silicon; or, the material of the first sublayer includes GaAs, and the material of the second sublayer includes SiO2; or, the material of the first sublayer includes transition metal chalcogenides; the material of the second sublayer includes at least one of Au, Ag, Pt, Mo, Cu, Al, W, and Ni.

[0010] In some embodiments of the present disclosure, the semiconductor substrate includes a plurality of active areas, the trench is located between adjacent active areas, and part of the pinning layer is located on the first dielectric layer at a position from 1 / 7 to 1 / 6 of the depth from the top surface of the active area to the trench, wherein the depth of the trench is the dimension from the top surface of the active area to the bottom surface of the trench in the vertical direction.

[0011] In some embodiments of the present disclosure, the semiconductor substrate includes a plurality of active areas, the trench is located between adjacent active areas, the semiconductor structure includes a transistor, the transistor is located in the active area, in the horizontal direction, the source or drain of the transistor is located on one side of the trench, and the projection of the pinning layer on the transistor along the horizontal direction at least covers the side of the source or the drain.

[0012] In some embodiments of the present disclosure, the semiconductor structure further includes a third dielectric layer located on the second dielectric layer and completely filling the trench.

[0013] In some embodiments of the present disclosure, the materials of the first dielectric layer and the third dielectric layer include at least one of silicon oxide and silicon oxynitride, respectively; and the material of the second dielectric layer includes silicon nitride.

[0014] In some embodiments of the present disclosure, the second dielectric layer covers a top surface of the pinned layer.

[0015] The embodiment of the present disclosure also provides a method for preparing a semiconductor structure, including: providing a semiconductor substrate and forming a groove on the semiconductor substrate; conformally forming a first dielectric layer on an inner wall of the groove; forming a pinning layer on at least a portion of the first dielectric layer; and forming a second dielectric layer on the inner wall of the groove formed with the pinning layer.

[0016] It can be seen from the above technical solutions that the semiconductor structure of the embodiment of the present disclosure has at least one of the following advantages and positive effects:

[0017] In the embodiment of the present disclosure, when the semiconductor structure is working, the second dielectric layer will capture charges, and a pinning layer is arranged between the first dielectric layer and the second dielectric layer. The pinning layer can absorb the captured charges, thereby reducing the local electric field at the corresponding position, preventing hot carriers from accumulating to the top of the first dielectric layer to cause breakdown of the semiconductor structure, thereby preventing hot carriers from accumulating and destroying the semiconductor structure, and improving the electrical performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and other features and advantages of the present disclosure will become more apparent by describing in detail example embodiments thereof with reference to the attached drawings.

[0019] Figure 1 A schematic diagram of a semiconductor substrate according to some embodiments of the present disclosure;

[0020] Figure 2 A schematic diagram of forming a trench on a semiconductor substrate according to some embodiments of the present disclosure;

[0021] Figure 3 A schematic diagram of forming a first dielectric layer according to some embodiments of the present disclosure;

[0022] Figure 4 A schematic diagram of forming a first sub-layer according to some embodiments of the present disclosure;

[0023] Figure 5 A schematic diagram of forming a second sub-layer according to some embodiments of the present disclosure;

[0024] Figure 6 A schematic diagram of forming a second dielectric layer according to some embodiments of the present disclosure;

[0025] Figure 7 A schematic diagram of forming a third dielectric layer according to some embodiments of the present disclosure;

[0026] Figure 8 A schematic diagram of a semiconductor structure after planarization treatment according to some embodiments of the present disclosure;

[0027] Fig. 9 A schematic diagram of a semiconductor structure including a transistor according to some embodiments of the present disclosure;

[0028] Fig.10 The present invention is a flow chart of a method for preparing a semiconductor structure according to some embodiments of the present disclosure.

[0029] Description of reference numerals:

[0030] 1. Semiconductor substrate; 11. Groove; 2. First dielectric layer; 3. Pinning layer; 31. First sublayer; 32. Second sublayer; 4. Second dielectric layer; 5. Third dielectric layer; A. Active area; X. Horizontal direction; Y. Vertical direction; d. Depth of the groove; 6. Transistor; G. Gate; S. Source; D. Drain. DETAILED DESCRIPTION

[0031] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be comprehensive and complete and will fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted.

[0032] In the following description of different exemplary embodiments of the present disclosure, reference is made to the accompanying drawings, which form a part of the present disclosure and in which different exemplary structures that can implement multiple aspects of the present disclosure are shown by way of example. It should be understood that other specific schemes of components, structures, exemplary devices, systems and steps can be used, and structural and functional modifications can be made without departing from the scope of the present disclosure. Moreover, although the terms "above", "between", "within", etc. may be used in this specification to describe different exemplary features and elements of the present disclosure, these terms are used herein only for convenience, such as according to the direction of the examples in the accompanying drawings. Nothing in this specification should be construed as requiring a specific three-dimensional direction of the structure to fall within the scope of the present disclosure. In addition, the terms "first", "second", etc. in the claims are used only as marks and are not numerical limitations on their objects.

[0033] The flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps can be decomposed, and some operations / steps can be combined or partially combined, so the actual execution order may change according to actual conditions.

[0034] In addition, in the description of the present disclosure, “plurality” means at least two, for example, two, three, etc., unless otherwise clearly and specifically defined.

[0035] As pointed out in the background technology, when the semiconductor device is working, the nitride layer captures charges, and the captured charges attract hot carriers in the device, causing the hot carriers to continuously accumulate to the shoulder of the active region, which can easily cause breakdown, thereby affecting the performance of the semiconductor device. For example, for PMOS, the accumulated hot carriers will apply a negative voltage to PMOS, continuously reducing the threshold voltage of PMOS, resulting in induced breakdown, and causing damage to PMOS.

[0036] Based on this, Figure 8 and Fig. 9 As shown, the embodiment of the present disclosure provides a semiconductor structure, which includes a semiconductor substrate 1 having a trench 11. On the inner wall of the trench 11, a first dielectric layer 2, a pinning layer 3 and a second dielectric layer 4 are sequentially arranged.

[0037] In the embodiment of the present disclosure, when the semiconductor structure is working, the second dielectric layer 4 will capture charges, and a pinning layer 3 is provided between the first dielectric layer 2 and the second dielectric layer 4. The pinning layer 3 can absorb the captured charges, thereby reducing the local electric field at the corresponding position, preventing hot carriers from accumulating to the top of the first dielectric layer 2 (active area shoulder) to cause breakdown of the semiconductor structure, thereby preventing hot carrier accumulation and damaging the semiconductor structure, and improving the electrical performance of the semiconductor structure. At the same time, a first dielectric layer 2 is provided between the pinning layer 3 and the semiconductor substrate 1, so that the pinning layer 3 will not generate Coulomb scattering on the channel region of the semiconductor substrate 1, thereby avoiding affecting the mobility of the semiconductor structure.

[0038] The semiconductor structure of the embodiment of the present disclosure is described in detail below.

[0039] In the embodiments of the present disclosure, the semiconductor structure may be a transistor, such as a PMOS or NMOS. For ease of description, some embodiments of the present disclosure take PMOS as an example, but this does not limit the semiconductor structure of the embodiments of the present disclosure.

[0040] like Figure 1 As shown, the trench 11 on the semiconductor substrate 1 may be a trench 11 where a shallow trench isolation is located, and the trench 11 may be etched on the semiconductor substrate 1 by using a wet etching process or a dry etching process.

[0041] The dry etching process may be a plasma etching process, and the etching gas used in the plasma etching process may be chlorine. By controlling the amount of the etching gas, the etching degree may be controlled. The wet etching process may use hydrofluoric acid as an etchant. By adjusting the concentration of the etchant, the etching degree may also be controlled, thereby controlling the width and depth of the groove 11.

[0042] The material of the semiconductor substrate 1 can be silicon, silicon carbide, silicon on insulator, stacked silicon on insulator, stacked silicon germanium on insulator, silicon germanium on insulator or germanium on insulator, etc. The substrate can also be implanted with certain doping particles to change electrical parameters according to design requirements. The semiconductor substrate 1 can have active areas A, and shallow trench isolation is located between the active areas A, that is, the trench 11 is located between adjacent active areas A.

[0043] like Figure 1 As shown, the width of the groove 11 can be gradually increased from the bottom end of the groove to the opening of the groove in the vertical direction Y, which is conducive to depositing a film layer on the inner wall of the groove 11 and improving the stability of the functional film layer formed inside the groove 11. The vertical direction Y can be understood as a direction perpendicular to the bottom surface of the groove 11.

[0044] like Figure 8As shown, in some embodiments, the pinning layer 3 is a stack including a first sublayer 31 and a second sublayer 32. That is, the pinning layer 3 includes at least the first sublayer 31 and the second sublayer 32. A large number of interface states will be generated at the contact surface of the first sublayer 31 and the second sublayer 32, and the charges captured in the dielectric layer can preferentially fill the interface states, that is, the pinning layer 3 can absorb the captured charges, avoid the accumulation of hot carriers, thereby reducing the change in the threshold voltage of the device and preventing the induced breakdown of hot carriers, such as the induced breakdown of hot electrons. In other words, this interface state of the pinning layer can reduce the accumulation of hot carriers, thereby avoiding the induced breakdown of hot carriers in MOS, such as P-type MOS.

[0045] like Figure 8 As shown, the stack includes a first sublayer 31 and a second sublayer 32. In some embodiments, the pinned layer 3 includes a stack. In the stack, the first sublayer 31 may be disposed on the first dielectric layer 2, and the second sublayer 32 may be disposed on the first sublayer 31, or the second sublayer 32 may be disposed on the first dielectric layer 2, and the first sublayer 31 may be disposed on the second sublayer 32. That is, the order of the first sublayer 31 and the second sublayer 32 in the stack is not fixed, so the order of the first sublayer 31 and the second sublayer 32 can be adjusted according to actual conditions.

[0046] In some embodiments, the number of stacked layers is multiple. That is, multiple first sublayers 31 and second sublayers 32 are provided between the first dielectric layer 2 and the second dielectric layer 4, so that multiple interface states can be formed, thereby more effectively absorbing the charges captured by the dielectric layer and more thoroughly avoiding the accumulation of hot carriers.

[0047] In some embodiments, the number of stacks can be 2, 3, 4, 5 or more, and the number of stacks can be set according to actual conditions. The stacking order of the first sublayer 31 and the second sublayer 32 in the multiple stacks can be the same or different, or partially the same and partially different, which is not specifically limited here and can be adjusted according to actual conditions. In some embodiments, the first sublayer 31 and the second sublayer 32 in the multiple stacks are alternately arranged, so that the most interface states can be formed, which can more effectively absorb the captured charges, reduce the electric field caused by the charges, and thus reduce the accumulation of hot carriers.

[0048] The semiconductor substrate 1 includes a plurality of active regions A, and the grooves 11 are located between adjacent active regions A. In some embodiments, a portion of the pinning layer 3 is located on the first dielectric layer 2 at a position of 1 / 7 to 1 / 6 of the depth d from the top surface of the active region A to the groove 11, wherein the depth d of the groove 11 is the dimension from the top surface of the active region A to the bottom surface of the groove 11 in the vertical direction Y. For example, the dimension of the first dielectric layer 2 in the vertical direction Y is 300 to 350 nm, specifically, in addition to the above two end values, it can also be 310 nm, 320 nm, 330 nm, 340 nm, and is not specifically limited here, and the pinning layer 3 is located at a position where the depth from the top surface of the active region A to the groove 11 is 50 nm. When the semiconductor structure is working, if there is no pinning layer 3, the generated hot electrons will generally accumulate to the top of the first dielectric layer 2, which is generally located at a position from the top surface of the active area A to 1 / 7 to 1 / 6 of the depth d of the trench 11. Therefore, the pinning layer 3 is arranged at this position, which can effectively absorb the captured charges, prevent the hot carriers from accumulating to the shoulder of the active area A, and save materials and reduce costs. Alternatively, the pinning layer 3 can be located on the entire inner surface of the first dielectric layer 2 to be able to block the hot electrons from transferring to the first dielectric layer 2 at various positions.

[0049] In some embodiments, the pinning layer 3 is only formed on the bottom of the first dielectric layer 2 .

[0050] In some embodiments, the pinning layer 3 may also be located on the sidewall of the first dielectric layer 2. Optionally, the pinning layer 3 may also be located on the entire sidewall of the first dielectric layer 2, or at any position greater than 1 / 6 of the depth d from the top surface of the active region A to the trench 11, both of which can achieve shielding of hot electrons.

[0051] As in the above-mentioned embodiment, the semiconductor substrate 1 includes a plurality of active areas A, and the trench 11 is located between adjacent active areas A. In some embodiments, the semiconductor structure further includes a transistor 6, and the transistor 6 is located in the active area A. In the horizontal direction X, the source S or the drain D of the transistor is located on one side of the trench 11, and the projection of the pinning layer 3 on the transistor 6 along the horizontal direction X at least covers the source S or the drain D.

[0052] Specifically, Fig. 9 As shown, the trench 11 is located between adjacent active regions A, and the transistor 6 is located in the active region. The transistor 6 includes a source S, a drain D, and a gate G. The source S and the drain D are located in the semiconductor substrate 1. The horizontal direction X is perpendicular to the vertical direction Y. In the horizontal direction X, the area of ​​the pinning layer 3 is greater than or equal to the area of ​​the source S or the drain D, that is, the pinning layer 3 can cover the source S or the drain D, so that hot carriers will not accumulate on the shoulder of the active region A, will not affect the source S or the drain D, and reduce damage to the transistor 6.

[0053] The materials of the first sublayer 31 and the second sublayer 32 are mutually compatible materials. In some embodiments, the material of the first sublayer 31 may be a high-K material, which may include at least one of HfO2, ZrO2, SrTiO3, and TiO2, and the material of the second sublayer 32 may be silicon, specifically, the material of the second sublayer 32 may include at least one of single crystal silicon, polycrystalline silicon, and amorphous silicon. In this way, when the high-K material contacts the silicon material, an interface state can be generated, which effectively absorbs the charges captured by the second dielectric layer 4.

[0054] In some embodiments, the material of the first sub-layer 31 may include GaAs, and the material of the second sub-layer 32 may include SiO 2 .

[0055] In some embodiments, the material of the first sublayer 31 includes a transition metal chalcogenide, with a chemical formula of MX2, wherein M may be any one of Ti, V, Ta, Mo, W, and Re, and X may be at least one of S, Se, and Te. The material of the second sublayer 32 may include at least one of Au, Ag, Pt, Mo, Cu, Al, W, and Ni.

[0056] In the above embodiment, the materials used in the first sublayer 31 and the second sublayer 32 can generate interface states when in contact with each other, effectively absorbing the charges captured by the second dielectric layer 4. At the same time, since the thickness of the first dielectric layer 2 is relatively thick, optionally, (angstroms) or more, so that the pinned layer 3 will not generate Coulomb scattering on the channel of the PMOS, thereby avoiding affecting the mobility of the PMOS.

[0057] In some embodiments, Figure 8 and Fig. 9 As shown, the semiconductor structure further includes a third dielectric layer 5 , which is located on the second dielectric layer 4 and completely fills the trench 11 .

[0058] In some embodiments, the materials of the first dielectric layer 2 and the third dielectric layer 5 may include at least one of silicon oxide, silicon nitride and silicon oxynitride, respectively. The material of the first dielectric layer 2 may be the same as that of the third dielectric layer 5, so as to avoid replacing materials during the process and simplify the process. Of course, the materials of the first dielectric layer 2 and the third dielectric layer 5 may also be different. The material of the second dielectric layer 4 may be silicon nitride. After the third dielectric layer 5 is formed, the shallow trench isolation is still an oxide-nitride-oxide structure, which can better balance the stress and ensure the smooth progress of the process.

[0059] In some embodiments, the semiconductor structure may not include the third dielectric layer 5, but the second dielectric layer 4 fills the trench 11. After the pinning layer 3 is formed, the second dielectric layer 4 may be formed on the pinning layer 3 or on the pinning layer 3 and the first dielectric layer 2 (when the pinning layer 3 is only formed on a portion of the first dielectric layer 2), so that the remaining space of the trench 11 may be filled with the second dielectric layer 4, thereby simplifying the process on the basis of having a certain balanced stress effect.

[0060] In some embodiments, the top surface of the pinned layer 3 is lower than the top surface of the semiconductor substrate 1 , and the second dielectric layer 4 covers the top surface of the pinned layer 3 .

[0061] Specifically, Figure 8 As shown, the top surfaces of the first dielectric layer 2, the pinning layer 3, and the second dielectric layer 4 are all flush with the top surface of the semiconductor substrate 1. In this embodiment, the top surface of the pinning layer 3 is lower than the top surface of the semiconductor substrate 1, and the second dielectric layer 4 covers the top surface of the pinning layer 3, and the top surface of the second dielectric layer 4 is flush with the top surface of the semiconductor substrate 1. Such an arrangement can prevent the pinning layer 3 from being exposed to the surface of the semiconductor substrate 1. Based on the material of the above-mentioned pinning layer 3, it can be known that the pinning layer 3 is conductive. For some semiconductor structures, it is not desirable for the pinning layer 3 to be exposed, because the pinning layer 3 exposed on the surface of the semiconductor substrate 1 may short-circuit with other electrical connection structures, and there is a risk of damaging the semiconductor structure. In order to avoid such a risk, the second dielectric layer 4 can be covered on the top surface of the pinning layer 3, so that the top surface of the pinning layer 3 cannot be exposed to the outside, avoiding short-circuit with other electrical connection structures.

[0062] Of course, in other embodiments, some semiconductor structures do not have the risk of short circuit between the pinning layer 3 and other electrical connection structures, and the top surface of the pinning layer 3 can be flush with the top surface of the semiconductor substrate 1, that is, the top surfaces of the first dielectric layer 2, the pinning layer 3, the second dielectric layer 4 and the third dielectric layer 5 are all flush with the top surface of the semiconductor substrate 1. In this way, a flat surface can be formed at one time using a chemical mechanical process, which simplifies the process.

[0063] To sum up, in the semiconductor structure of the embodiment of the present disclosure, when the semiconductor structure is working, the second dielectric layer 4 will capture charges, and a pinning layer 3 is arranged between the first dielectric layer 2 and the second dielectric layer 4. The pinning layer 3 can absorb the captured charges, thereby reducing the local electric field at the corresponding position, avoiding the accumulation of hot carriers to the top of the first dielectric layer 2 to cause breakdown of the semiconductor structure, thereby avoiding the accumulation of hot carriers and destroying the semiconductor structure, and improving the electrical performance of the semiconductor structure.

[0064] The present disclosure also provides a method for preparing a semiconductor structure. Figures 1 to 8, showing a schematic diagram of the structure of the semiconductor structure in each step, such as Fig.10 As shown, a schematic flow chart of a method for preparing a semiconductor structure is shown.

[0065] like Fig.10 As shown, the method for preparing the semiconductor structure of the embodiment of the present disclosure includes the following steps S101 to S104.

[0066] S101 : providing a semiconductor substrate 1 , and forming a trench 11 on the semiconductor substrate 1 .

[0067] S102 : forming a first dielectric layer 2 conformally on the inner wall of the trench 11 .

[0068] S103 : forming a pinning layer 3 on at least a portion of the first dielectric layer 2 .

[0069] S104 : forming a second dielectric layer 4 on the inner wall of the trench 11 where the pinning layer 3 is formed.

[0070] In the above method, when the semiconductor structure is working, the second dielectric layer 4 will capture charges, and a pinning layer is set between the first dielectric layer 2 and the second dielectric layer 4. The pinning layer 3 can absorb the captured charges, thereby reducing the local electric field at the corresponding position, avoiding the accumulation of hot carriers to the top of the first dielectric layer 2 to cause breakdown of the semiconductor structure, thereby avoiding the accumulation of hot carriers and destroying the semiconductor structure, and improving the electrical performance of the semiconductor structure.

[0071] The following is a detailed description of the method for preparing the semiconductor structure according to the embodiment of the present disclosure.

[0072] S101 : providing a semiconductor substrate 1 , and forming a trench 11 on the semiconductor substrate 1 .

[0073] like Figure 1 and Figure 2 As shown, a plurality of trenches 11 may be formed in the semiconductor substrate 1 . For the sake of convenience, only one trench 11 is shown in the figure. The plurality of trenches 11 are used to form shallow trench isolation. The active area A of the semiconductor substrate 1 is located between the plurality of trenches 11 .

[0074] A mask layer may be formed on the semiconductor substrate 1, the mask layer having a pattern of the grooves 11, and the pattern of the grooves 11 of the mask layer may be transferred to the semiconductor substrate 1 by an etching process to form a plurality of grooves 11. When a wet etching process is used, the depth and width of the grooves 11 may be controlled by controlling the amount and concentration of the etchant. When a dry etching process is used, the depth and width of the grooves 11 may be controlled by controlling the amount and concentration of the etching gas to obtain a groove 11 that meets the requirements.

[0075] In some embodiments, in the vertical direction Y, the width of the groove 11 gradually increases from the bottom wall of the groove 11 to the opening, wherein the width of the groove 11 refers to the distance between the two side walls of the groove 11 in the horizontal direction X shown in the figure. In the subsequent process, a deposition process will be used to form the first dielectric layer 2 on the inner wall of the groove 11. Since the width of the groove 11 gradually increases from bottom to top, the material of the first dielectric layer 2 can be uniformly deposited on the surface of the inner wall of the groove 11 without any deposition dead angle, so that the thickness of the first dielectric layer 2 is more uniform and its stability is improved.

[0076] S102 : forming a first dielectric layer 2 conformally on the inner wall of the trench 11 .

[0077] like Figure 3 As shown, the first dielectric layer 2 can be formed on the inner wall of the trench 11 and the surface of the semiconductor substrate 1 outside the trench 11 by a deposition process. Here, “conformally formed” can be understood as formed along the surface contour of the inner wall of the trench 11.

[0078] In some embodiments, the deposition process may be a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process, which may be selected based on actual conditions and is not specifically limited herein.

[0079] S103 : forming a pinning layer 3 on at least a portion of the first dielectric layer 2 .

[0080] Specifically, Figure 4 and Figure 5 As shown, forming the pinning layer 3 on at least a portion of the first dielectric layer 2 includes: forming a stack of a first sub-layer 31 and a second sub-layer 32 on at least a portion of the first dielectric layer 2 .

[0081] like Figure 5 As shown, the stack of the first sublayer 31 and the second sublayer 32 has one. The first sublayer 31 can be formed on the surface of the first dielectric layer 2 by a deposition process, and then the second sublayer 32 can be formed on the surface of the first sublayer 31. Of course, the second sublayer 32 can also be formed on the surface of the first dielectric layer 2, and then the first sublayer 31 can be formed on the surface of the second sublayer 32.

[0082] In some embodiments, the stack of the first sublayer 31 and the second sublayer 32 has a plurality of layers, for example, 2, 3, 4, 5 or more layers. For example, when there are 2 stacks, the first sublayer 31, the second sublayer 32, the first sublayer 31 and the second sublayer 32 may be sequentially formed on the first dielectric layer 2, or the second sublayer 32, the first sublayer 31, the second sublayer 32 and the first sublayer 31 may be sequentially formed. Of course, it is best that the first sublayer 31 and the second sublayer 32 appear alternately, so as to increase the number of interface states and more effectively absorb the charges captured by the dielectric layer.

[0083] In some embodiments, a pinning layer 3 may be formed on the entire surface of the first dielectric layer 2 to be able to block hot electrons from being transferred to the first dielectric layer 2 at various locations. In other embodiments, the pinning layer 3 may be deposited on the first dielectric layer 2 from the top surface of the active region A to 1 / 7 to 1 / 6 of the depth d of the groove 11. Specifically, a blocking layer may be formed on the inner surface of the first dielectric layer 2, an opening may be formed at a location where the pinning layer 3 is required to be deposited, the location is exposed, and the pinning layer 3 is formed at the location using a deposition process. Alternatively, a blocking layer may be not formed, the pinning layer 3 may be deposited on the inner surface of the first dielectric layer 2, and then the pinning layer 3 may be patterned to retain only the pinning layer 3 at the required location. In the case where the pinning layer 3 is not formed, when the semiconductor structure is working, the generated hot electrons are easily accumulated to the top of the first dielectric layer 2, that is, at a position from the top of the first dielectric layer 2 to 1 / 7 to 1 / 6 of the depth of the first dielectric layer 2. Depositing at least a portion of the pinning layer 3 at this position can effectively absorb charges, avoid hot carriers from gathering at the shoulder of the active area A, and simplify the structure.

[0084] In other embodiments, the pinning layer 3 can be formed only on the sidewalls of the first dielectric layer 2 by a deposition process, or on the first dielectric layer 2 at any position greater than 1 / 6 of the depth d from the top surface of the active area A to the trench 11, so as to shield hot electrons.

[0085] S104 : forming a second dielectric layer 4 on the inner wall of the trench 11 where the pinning layer 3 is formed.

[0086] like Figure 6 As shown, a second dielectric layer 4 can be formed on the surface of the pinned layer 3 by a deposition process. In some embodiments, the second dielectric layer 4 can be filled in the remaining space of the trench 11 formed with the pinned layer 3. That is, the second dielectric layer 4 fills the remaining space of the trench 11. In this way, the process can be simplified.

[0087] In some embodiments, Figure 6 As shown, after the second dielectric layer 4 is formed on the pinning layer 3, it does not fill up the remaining space of the groove 11, but leaves a certain amount of space. In the embodiment of the present disclosure, after the pinning layer 3 is formed, the third dielectric layer 5 is also filled in the remaining space of the groove 11 where the second dielectric layer 4 is formed. Figure 7 As shown, the third dielectric layer 5 can be formed by a deposition process. After the third dielectric layer 5 is formed, the structure of the shallow trench isolation is still an oxide-nitride-oxide structure, which can better balance the stress and ensure the smooth progress of the process.

[0088] In some embodiments, after forming the pinning layer 3 on at least a portion of the first dielectric layer 2 in S1030, the preparation method further includes: etching back the pinning layer 3 until the top surface of the pinning layer 3 is lower than the top surface of the semiconductor substrate 1. Then, forming the second dielectric layer 4 on the inner wall of the trench 11 in which the pinning layer 3 is formed in S104 includes forming the second dielectric layer 4 on the inner wall surface of the pinning layer 3 and the top surface of the pinning layer 3.

[0089] Specifically, after forming the second dielectric layer 4 or the third dielectric layer 5, the first dielectric layer 2, the pinning layer 3, the second dielectric layer 4 and the third dielectric layer 5 located on the surface of the semiconductor substrate 1 are removed, so that the isolation structure in the trench 11 is flush with the surface of the semiconductor substrate 1, so as to facilitate the implementation of the next process. The above structure can be polished by a chemical mechanical polishing process to achieve planarization.

[0090] like Figure 8 As shown, after grinding the surface of the semiconductor substrate 1, the top surface of the pinning layer 3 will be exposed. However, in some semiconductor structures, it is not desirable to expose the pinning layer 3 because the pinning layer 3 has the risk of short-circuiting with other electrical connection structures, which may damage the semiconductor structure. In order to avoid this risk, it is necessary to insulate the pinning layer 3 from the outside world. Therefore, in the present embodiment, after the pinning layer 3 is formed, the top surface of the pinning layer 3 can be etched back so that its top surface is lower than the top surface of the semiconductor substrate 1, so that when the second dielectric layer 4 is subsequently formed by a deposition process, the second dielectric layer 4 can be deposited on the top surface of the pinning layer 3, and part of the second dielectric layer 4 is located in the groove 11. When the semiconductor structure is ground so that the top surface of the isolation structure in the groove 11 is flush with the top surface of the semiconductor substrate 1, the top surface of the pinning layer 3 still covers the second dielectric layer 4, that is, the pinning layer 3 is not exposed, but is insulated from the outside world, thereby avoiding the risk of short-circuiting with the electrical connection structure, thereby avoiding damage to the semiconductor structure and improving the conductivity of the semiconductor structure.

[0091] It should be noted that the amount of back-etching on the top surface of the pinning layer 3 should not be too much. When the pinning layer 3 is covered by the second dielectric layer 4 and is insulated from the outside, the back-etching depth should be as small as possible, so as to improve the shielding effect on thermal electrons.

[0092] In summary, in the preparation method of the embodiment of the present disclosure, when the semiconductor structure is working, the second dielectric layer 4 will capture charges, and a pinning layer is set between the first dielectric layer 2 and the second dielectric layer 4. The pinning layer 3 can absorb the captured charges, thereby reducing the local electric field at the corresponding position, avoiding the accumulation of hot carriers to the top of the first dielectric layer 2 to cause breakdown of the semiconductor structure, thereby avoiding the accumulation of hot carriers and destroying the semiconductor structure, and improving the electrical performance of the semiconductor structure.

[0093] It should be understood that the present disclosure does not limit its application to the detailed structure and arrangement of the components proposed in this specification. The present disclosure can have other embodiments and can be implemented and executed in a variety of ways. The aforementioned variations and modifications fall within the scope of the present disclosure. It should be understood that the present disclosure disclosed and defined in this specification extends to all alternative combinations of two or more individual features mentioned or evident in the text and / or the drawings. All these different combinations constitute multiple alternative aspects of the present disclosure. The embodiments described in this specification illustrate the best mode known for implementing the present disclosure and will enable those skilled in the art to adopt the present disclosure.

Claims

1. A semiconductor structure, characterized in that: include: A semiconductor substrate having a trench therein; A first dielectric layer, a pinning layer and a second dielectric layer are sequentially arranged on the inner wall of the groove.

2. The semiconductor structure according to claim 1, characterized in that: The pinned layer is a stacked layer including a first sub-layer and a second sub-layer.

3. The semiconductor structure according to claim 2, characterized in that: The number of the stacked layers is multiple.

4. The semiconductor structure according to claim 2, characterized in that: The material of the first sublayer includes at least one of HfO2, ZrO2, SrTiO3, and TiO2, and the material of the second sublayer includes at least one of single crystal silicon, polycrystalline silicon, and amorphous silicon; or, The material of the first sub-layer includes GaAs, and the material of the second sub-layer includes SiO2; Or, the material of the first sublayer includes a transition metal chalcogenide; and the material of the second sublayer includes at least one of Au, Ag, Pt, Mo, Cu, Al, W and Ni.

5. The semiconductor structure according to claim 1, characterized in that: The semiconductor substrate includes a plurality of active areas, the trench is located between adjacent active areas, and part of the pinning layer is located on the first dielectric layer at a position from the top surface of the active area to 1 / 7 to 1 / 6 of the depth of the trench, wherein the depth of the trench is the dimension from the top surface of the active area to the bottom surface of the trench in the vertical direction.

6. The semiconductor structure according to claim 1, characterized in that The semiconductor substrate includes a plurality of active areas, the trench is located between adjacent active areas, the semiconductor structure includes a transistor, the transistor is located in the active area, in the horizontal direction, the source or drain of the transistor is located on one side of the trench, and the projection of the pinning layer on the transistor along the horizontal direction at least covers the side of the source or the drain.

7. The semiconductor structure according to claim 1, characterized in that: Also includes: The third dielectric layer is located on the second dielectric layer and completely fills the trench.

8. The semiconductor structure according to claim 7, characterized in that: The materials of the first dielectric layer and the third dielectric layer include at least one of silicon oxide and silicon oxynitride respectively; the material of the second dielectric layer includes silicon nitride.

9. The semiconductor structure according to any one of claims 1 to 8, characterized in that: The second dielectric layer covers a top surface of the pinned layer.

10. A method for preparing a semiconductor structure, characterized in that: include: Providing a semiconductor substrate, and forming a trench on the semiconductor substrate; Conformally forming a first dielectric layer on an inner wall of the trench; forming a pinning layer on at least a portion of the first dielectric layer; A second dielectric layer is formed on the inner wall of the trench where the pinning layer is formed.

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