Charging and discharging control method for electronic equipment

Abstract

The invention provides a charging and discharging control method for electronic equipment, and relates to the technical field of power supply circuits. The control method comprises the following steps: when a power supply is connected, the step-down circuit is switched on, the logic switching circuit is switched off, and the power supply charges the farad capacitor through the step-down circuit and the current limiting circuit; when the electric quantity of the farad capacitor reaches a preset value, the processor controls the step-down circuit to be switched off and controls the logic switch circuit to be switched on, and the power supply charges the battery through the logic switch circuit and the battery charging circuit. When a load is connected, if the voltage of the farad capacitor is within a voltage input value range required by the work of the booster circuit, the booster circuit is switched on, the farad capacitor supplies power to the load at a first voltage value after being boosted by the booster circuit, and meanwhile, the output switch circuit is switched off; when the farad capacitor discharges until the farad capacitor cannot supply power to the load with the first voltage value, the booster circuit is disconnected, the output switch circuit is connected, and the battery supplies power to the load with the second voltage value through the output switch circuit.

Description

Technical Field

[0001] The present invention relates to the technical field of power supply circuits, and in particular to a method for controlling charging and discharging of electronic equipment. Background Art

[0002] Nowadays, with the rapid development of electronic devices, users' demand for power management of electronic devices is constantly increasing. The single battery power supply mode can no longer meet the challenges of these devices in terms of battery life, fast charging and discharging, and high power output requirements. In traditional electronic device power management systems, batteries are often responsible for power supply tasks, resulting in frequent charging and discharging of batteries, thereby shortening their service life. At the same time, when electronic devices require high power output, the battery may not be able to meet the demand, which will lead to a decline in performance in the long run.

[0003] In recent years, as a new type of energy storage component, farad capacitors have gradually attracted widespread attention due to their advantages such as fast charging and discharging speed, long cycle life, and high power density. Therefore, how to achieve the complementary advantages of batteries and farad capacitors and extend the service life of batteries is an urgent problem to be solved. Summary of the invention

[0004] The present invention provides an electronic equipment charge and discharge control method and circuit, which are used to improve the defect of the electronic equipment in the prior art that the service life of the battery is shortened due to frequent charge and discharge, realize the complementary advantages of the battery and the farad capacitor, and prolong the service life of the battery.

[0005] In one aspect, the present invention provides a method for controlling charging and discharging of an electronic device, comprising:

[0006] When the power supply is connected, the step-down circuit is turned on, the logic switch circuit is turned off, and the power supply charges the farad capacitor through the step-down circuit and the current limiting circuit;

[0007] When the electric quantity of the farad capacitor reaches a preset value, the processor controls the step-down circuit to be disconnected, and controls the logic switch circuit to be turned on at the same time, and the power supply charges the battery through the logic switch circuit and the battery charging circuit;

[0008] When the load is connected, if the voltage of the farad capacitor is within the voltage input value range required for the boost circuit to work, the boost circuit is turned on, and the farad capacitor is boosted by the boost circuit to supply power to the load at the first voltage value, and at the same time, the output switch circuit is disconnected;

[0009] When the farad capacitor is discharged to the point where it cannot supply power to the load at the first voltage value, the boost circuit is disconnected, and the output switch circuit is turned on, and the battery supplies power to the load at the second voltage value through the output switch circuit;

[0010] Wherein, the first voltage value is greater than the second voltage value;

[0011] The step-down circuit includes a step-down chip, which has 5 pins, wherein pin 1 of the step-down chip is connected to the processor, pin 2 of the step-down chip is grounded, pin 4 of the step-down chip is connected to the power supply, pin 1 of the step-down chip is also connected to pin 4 of the step-down chip through a second resistor, pin 3 of the step-down chip is connected to the current limiting circuit through a first inductor, and pin 5 of the step-down chip is grounded through a fourth resistor;

[0012] The current limiting circuit includes a current limiting chip, which has 5 pins. Pin 5 of the current limiting chip is connected to pin 3 of the buck chip through a first inductor, pin 4 of the current limiting chip is connected to pin 5 of the current limiting chip, pin 2 of the current limiting chip is grounded, pin 3 of the current limiting chip is grounded through a third resistor, pin 1 of the current limiting chip is connected to the positive electrode of the farad capacitor, and the negative electrode of the farad capacitor is grounded.

[0013] According to a method for controlling charge and discharge of an electronic device provided by the present invention, the boost circuit includes a boost chip, the boost chip has 6 pins, 4 pins of the boost chip are respectively connected to 1 pin of the current limiting chip and the positive electrode of the farad capacitor, 6 pins of the boost chip are suspended, 2 pins of the boost chip are grounded, 3 pins of the boost chip are grounded through a seventh resistor, 5 pins of the boost chip are connected to the negative electrode of the rectifier diode, 1 pin of the boost chip is connected to the positive electrode of the rectifier diode, and 5 pins of the boost chip are also connected to the seventh resistor through a fifth resistor and then grounded.

[0014] According to a charge and discharge control method for an electronic device provided by the present invention, pin 1 of the buck chip is a switch pin. During the charging of the farad capacitor, pin 1 of the buck chip is at a high level, and the buck chip remains in an open and conductive state.

[0015] According to a method for controlling charge and discharge of an electronic device provided by the present invention, the processor controls pin 1 of the buck chip to be at a low level, so that the buck chip is in a closed and disconnected state.

[0016] According to a method for controlling charge and discharge of an electronic device provided by the present invention, during the charging of the farad capacitor, the processor detects the charge of the farad capacitor in real time, and when the charge of the farad capacitor reaches 90% of the full charge state, the processor controls the buck chip to shut down.

[0017] According to a method for controlling charging and discharging of an electronic device provided by the present invention, pin 4 of the current limiting chip is a switch pin. During the charging of the farad capacitor, pin 4 of the current limiting chip is a high level, and the current limiting chip remains in an open and conducting state.

[0018] According to a method for controlling charge and discharge of an electronic device provided by the present invention, the logic switch circuit includes a PMOS tube, the S pole of the PMOS tube is connected to a power supply, the G pole of the PMOS tube is connected to a processor through a twelfth resistor, the D pole of the PMOS tube is connected to a battery charging circuit, and the G pole of the PMOS tube is connected to the S pole of the PMOS tube through an eleventh resistor, so that the PMOS tube remains in a disconnected state during the charging of the farad capacitor.

[0019] According to a method for controlling charge and discharge of an electronic device provided by the present invention, a processor controls the G pole of a PMOS tube to be at a low level, so that the PMOS tube is in a conducting state.

[0020] According to a method for controlling charge and discharge of an electronic device provided by the present invention, the battery charging circuit includes a charging management chip, the charging management chip has 9 pins, pin 4 of the charging management chip is connected to the D pole of a PMOS tube, pin 8 of the charging management chip is connected to pin 4 of the charging management chip, pin 7 of the charging management chip is suspended, pin 6 of the charging management chip is grounded through a thirteenth resistor, pin 3 of the charging management chip is grounded, pin 2 of the charging management chip is grounded through a fourteenth resistor, pin 1 of the charging management chip is connected to a battery, pin 1 of the charging management chip is also connected to pin 4 of the charging management chip through a tenth resistor, and pin 1 of the charging management chip is also grounded through a fifteenth resistor, pin 9 of the charging management chip is grounded, and pin 9 of the charging management chip is also connected to pin 5 of the charging management chip through a sixth capacitor, and pin 5 of the charging management chip is also connected to a battery and an output switch circuit, respectively.

[0021] According to a charge and discharge control method for an electronic device provided by the present invention, the battery has an NTC pin, the NTC pin of the battery is connected to pin 1 of a charging management chip, the negative electrode of the battery is grounded, the positive electrode of the battery is connected to pin 5 of the charging management chip, and the positive electrode of the battery is also connected to an output switch circuit.

[0022] According to a charge and discharge control method for an electronic device provided by the present invention, the output switch circuit includes a switch chip, the switch chip has 5 pins, pin 1 of the switch chip is connected to the load, pin 2 of the switch chip is grounded, pin 3 of the switch chip is connected to pin 5 of the switch chip through a ninth resistor, pin 4 of the switch chip is connected to pin 5 of the switch chip, and pin 5 of the switch chip is respectively connected to the positive pole of the battery and pin 5 of the charging management chip.

[0023] On the other hand, the present invention also provides an electronic device charge and discharge control circuit, comprising: a power connection terminal, a processor, a load connection terminal, a farad capacitor and a battery;

[0024] The power connection terminal is connected to the farad capacitor through a step-down circuit and a current limiting circuit in sequence, and the farad capacitor is connected to the load connection terminal through a step-up circuit;

[0025] The power connection end is also connected to the battery through the logic switch circuit and the battery charging circuit in sequence, and the battery is connected to the load connection end through the output switch circuit; the processor is respectively connected to the step-down circuit, the farad capacitor, and the logic switch circuit;

[0026] The processor is connected to the step-down circuit, the farad capacitor and the logic switch circuit respectively.

[0027] According to a charge and discharge control circuit of an electronic device provided by the present invention, the step-down circuit includes a step-down chip, the step-down chip has 5 pins, pin 1 of the step-down chip is connected to the processor, pin 2 of the step-down chip is grounded, pin 4 of the step-down chip is connected to the power connection end, pin 1 of the step-down chip is also connected to pin 4 of the step-down chip through a second resistor, pin 3 of the step-down chip is connected to the current limiting circuit through a first inductor, and pin 5 of the step-down chip is grounded through a fourth resistor.

[0028] According to a charge and discharge control circuit of an electronic device provided by the present invention, the current limiting circuit includes a current limiting chip, the current limiting chip has 5 pins, pin 5 of the current limiting chip is connected to pin 3 of the step-down chip through a first inductor, pin 4 of the current limiting chip is connected to pin 5 of the current limiting chip, pin 2 of the current limiting chip is grounded, pin 3 of the current limiting chip is grounded through a third resistor, pin 1 of the current limiting chip is connected to the positive electrode of the farad capacitor, and the negative electrode of the farad capacitor is grounded.

[0029] According to an electronic device charge and discharge control circuit provided by the present invention, the boost circuit includes a boost chip, the boost chip has 6 pins, 4 pins of the boost chip are respectively connected to 1 pin of the current limiting chip and the positive electrode of the farad capacitor, 6 pins of the boost chip are suspended, 2 pins of the boost chip are grounded, 3 pins of the boost chip are grounded through a seventh resistor, 5 pins of the boost chip are connected to the negative electrode of the rectifier diode, 1 pin of the boost chip is connected to the positive electrode of the rectifier diode, and 5 pins of the boost chip are also connected to the seventh resistor through a fifth resistor and then grounded.

[0030] According to the electronic device charge and discharge control circuit provided by the present invention, the line connecting the power connection end and the step-down circuit is also grounded through a first capacitor.

[0031] According to a charge and discharge control circuit of an electronic device provided by the present invention, the logic switch circuit includes a PMOS tube, the S pole of the PMOS tube is connected to the power connection end, the G pole of the PMOS tube is connected to the processor through a twelfth resistor, the D pole of the PMOS tube is connected to the battery charging circuit, and the G pole of the PMOS tube is connected to the S pole of the PMOS tube through an eleventh resistor.

[0032] According to an electronic device charging and discharging control circuit provided by the present invention, the battery charging circuit includes a charging management chip, the charging management chip has 9 pins, pin 4 of the charging management chip is connected to the D pole of the PMOS tube, pin 8 of the charging management chip is connected to pin 4 of the charging management chip, pin 7 of the charging management chip is suspended, pin 6 of the charging management chip is grounded through a thirteenth resistor, pin 3 of the charging management chip is grounded, pin 2 of the charging management chip is grounded through a fourteenth resistor, pin 1 of the charging management chip is connected to the battery, pin 1 of the charging management chip is also connected to pin 4 of the charging management chip through a tenth resistor, and pin 1 of the charging management chip is also grounded through a fifteenth resistor, pin 9 of the charging management chip is grounded, and pin 9 of the charging management chip is also connected to pin 5 of the charging management chip through a sixth capacitor, and pin 5 of the charging management chip is also connected to the battery and the output switch circuit respectively.

[0033] According to an electronic device charge and discharge control circuit provided by the present invention, the battery is a lithium battery, the battery has an NTC pin, the NTC pin of the battery is connected to pin 1 of the charging management chip, the negative electrode of the battery is grounded, the positive electrode of the battery is connected to pin 5 of the charging management chip, and the positive electrode of the battery is also connected to the output switch circuit.

[0034] According to an electronic device charge and discharge control circuit provided by the present invention, the output switch circuit includes a switch chip, the switch chip U5 has 5 pins, pin 1 of the switch chip is connected to the load connection end, pin 2 of the switch chip is grounded, pin 3 of the switch chip is connected to pin 5 of the switch chip through a ninth resistor, pin 4 of the switch chip is connected to pin 5 of the switch chip, and pin 5 of the switch chip is respectively connected to the positive pole of the battery and pin 5 of the charging management chip.

[0035] The electronic device charge and discharge control method and circuit provided by the present invention, during the charging process, when the external power supply is connected, the step-down circuit starts to work, and the step-down circuit reduces the voltage of the external power supply to a level suitable for charging the farad capacitor, while the logic switch circuit remains disconnected to ensure that the power supply only charges the farad capacitor through the step-down circuit and the current limiting circuit, and the current limiting circuit prevents excessive current from damaging the circuit. At this time, the farad capacitor begins to store electricity, and when its electricity reaches a preset value, the processor turns off the step-down circuit, and the power supply stops charging the farad capacitor. At the same time, the processor controls the logic switch circuit to be turned on, and the power supply directly charges the battery through the logic switch circuit and the battery charging circuit.

[0036] During the discharge process, when the load is connected, if the voltage of the farad capacitor is still within the range in which the boost circuit can work effectively, the boost circuit starts to work, and the boost circuit increases the voltage of the farad capacitor to the first voltage value, and uses this voltage to power the load. At the same time, the output switch circuit remains disconnected, so that the battery is in a non-working state and does not participate in the power supply of the circuit. As the farad capacitor continues to discharge, when its voltage drops to a level that is insufficient to maintain the first voltage value for power supply, the boost circuit automatically disconnects, the output switch circuit is turned on, and the battery begins to power the load at a second voltage value (lower than the first voltage value) through the output switch circuit.

[0037] In summary, the technical solution provided by the present invention has the following beneficial effects:

[0038] 1. By setting the circuit logic, the farad capacitor can be charged and discharged first, reducing the frequent charging and discharging of the battery and extending the battery life;

[0039] 2. When the farad capacitor supplies power to the load, the battery is in a non-working state and does not participate in the power supply of the circuit, thus avoiding battery heating and battery aging;

[0040] 3. When the Farad capacitor is low on power, the circuit can seamlessly switch to battery power to ensure continuous and stable operation of the load equipment. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0042] Figure 1 It is an electrical block diagram of the electronic device charge and discharge control circuit provided by the present invention;

[0043] Figure 2 It is the circuit diagram of the power supply connection terminal, the farad capacitor and the load connection terminal;

[0044] Figure 3 It is a circuit diagram of the power supply connection terminal, battery and load connection terminal. DETAILED DESCRIPTION

[0045] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0046] Combine the following Figure 1-Figure 3 The present invention describes a method and circuit for controlling the charge and discharge of an electronic device. The electronic device of the present invention is a handheld mobile device such as a barcode scanner, a PDA, a handheld terminal, a mobile phone, etc., which is equipped with a corresponding power adapter. When the electronic device is connected to the power adapter, the internal circuit enters the charging state. When the electronic device is working (i.e., when the load is connected), the internal circuit enters the discharging state. The electronic device can be charged and discharged at the same time, or it can be charged or discharged separately.

[0047] In one aspect, the present invention provides a method for controlling charging and discharging of an electronic device, comprising:

[0048] When the power supply is connected, the step-down circuit is turned on, the logic switch circuit is turned off, and the power supply charges the farad capacitor through the step-down circuit and the current limiting circuit;

[0049] When the electric quantity of the farad capacitor C4 reaches a preset value, the processor controls the step-down circuit to be disconnected, and controls the logic switch circuit to be turned on at the same time, and the power supply charges the battery through the logic switch circuit and the battery charging circuit;

[0050] When the load is connected, if the voltage of the farad capacitor C4 is within the voltage input value range required for the boost circuit to work, the boost circuit is turned on, and the farad capacitor C4 supplies power to the load at the first voltage value after being boosted by the boost circuit, and at the same time, the output switch circuit is disconnected;

[0051] When the farad capacitor C4 is discharged to the point where it cannot supply power to the load at the first voltage value, the boost circuit is disconnected and the output switch circuit is turned on, and the battery supplies power to the load at the second voltage value through the output switch circuit.

[0052] That is to say, in the present application, the electronic device has two energy storage elements, namely, a farad capacitor C4 and a battery; when the power source is connected for charging, the farad capacitor C4 will be charged first, and when the farad capacitor C4 is charged to a preset level, the farad capacitor C4 will be stopped from being charged, and the battery will be charged instead;

[0053] During discharge, if there is a certain amount of electricity in the farad capacitor C4, the farad capacitor C4 is used first to power the load. When the electricity in the farad capacitor C4 decreases to a certain level and the boost circuit cannot work, the output voltage of the boost circuit can be considered to be zero, and then the battery is used to power the load.

[0054] Since the farad capacitor C4 and the battery are respectively connected to the load, the circuit is configured so that whichever power supply line has a higher voltage will be used first to supply power to the load. In the present application, the farad capacitor corresponds to a first voltage value after boosting, and the battery corresponds to a second voltage value. Therefore, by setting the first voltage value to be greater than the second voltage value, it is possible to ensure that the farad capacitor is used first for power supply. That is to say, when the amount of electricity in the farad capacitor can maintain the operation of the boost circuit, the boost circuit can output a voltage of the first voltage value. If the first voltage value is higher than the second voltage value, the first voltage value will be used first for power supply until the first voltage value disappears.

[0055] The buck circuit includes a buck chip U1, which has 5 pins, namely, pin 1 (EN), pin 2 (GND), pin 3 (LX), pin 4 (VIN), and pin 5 (FB). Pin 1 of the buck chip U1 is connected to the processor, pin 2 of the buck chip U1 is grounded, pin 4 of the buck chip U1 is connected to the power supply, pin 1 of the buck chip U1 is also connected to pin 4 of the buck chip U1 through a second resistor R2, pin 3 of the buck chip U1 is connected to the current limiting circuit through a first inductor L1, and pin 5 of the buck chip U1 is grounded through a fourth resistor R4; the input power supply voltage can be stepped down by the buck circuit to become a suitable charging voltage;

[0056] The current limiting circuit includes a current limiting chip U2, which has 5 pins, namely, pin 1 (VOUT), pin 2 (GND), pin 3 (ILIM), pin 4 (EN), and pin 5 (VIN). Pin 5 of the current limiting chip U2 is connected to pin 3 of the buck chip U1 through the first inductor L1, pin 4 of the current limiting chip U2 is connected to pin 5 of the current limiting chip U2, pin 2 of the current limiting chip U2 is grounded, pin 3 of the current limiting chip U2 is grounded through the third resistor R3, pin 1 of the current limiting chip U2 is connected to the positive electrode of the farad capacitor C4, and the negative electrode of the farad capacitor C4 is grounded; the farad capacitor C4 is a single capacitor with a rated voltage of 2.7V; the current limiting circuit limits the current in the circuit to prevent excessive current from damaging the circuit;

[0057] The boost circuit includes a boost chip U3, which has 6 pins, namely, pin 1 (SW), pin 2 (GND), pin 3 (FB), pin 4 (EN), pin 5 (VS), and pin 6 (NC). Pin 4 of the boost chip U3 is connected to pin 1 of the current limiting chip U1 and the positive electrode of the farad capacitor C4, respectively, and pin 6 of the boost chip U3 is suspended, pin 2 of the boost core U3 is grounded, pin 3 of the boost chip U3 is grounded through the seventh resistor R7, pin 5 of the boost chip U3 is connected to the negative electrode of the rectifier diode D1, pin 1 of the boost chip U3 is connected to the positive electrode of the rectifier diode D1, and pin 5 of the boost chip U3 is also connected to the seventh resistor R7 through the fifth resistor R5 and then grounded. Through the boost circuit, the output voltage of the farad capacitor C4 can be boosted to a set first voltage value, and then the load is powered with the first voltage value.

[0058] Among them, the pin 1 of the buck chip U1 is a switch pin. During the charging of the farad capacitor C4, the pin 1 of the buck chip U1 is at a high level, and the buck chip U1 remains in an open and conducting state;

[0059] The processor controls the pin 1 of the buck chip U1 to be at a low level, so that the buck chip U1 is turned off and disconnected;

[0060] During the charging of the farad capacitor C4, the processor will detect the power of the farad capacitor C4 in real time. When the power of the farad capacitor C4 reaches 90% of the full charge state, the processor controls the buck chip U1 to turn off.

[0061] Furthermore, in terms of circuit design, the line connecting the first inductor L1 and the current limiting chip U2 is connected to the second capacitor C2 and the first end of the first resistor R1 in sequence, and the second ends of the second capacitor C2 and the first resistor R1 are respectively connected to the 5th pin of the step-down chip U1;

[0062] The line connecting the power supply and the step-down circuit is also grounded via a first capacitor C1.

[0063] Among them, the 4th pin of the current limiting chip U2 is a switch pin. During the charging of the farad capacitor C4, the 4th pin of the current limiting chip U2 is a high level, and the current limiting chip U2 remains in an open and conducting state.

[0064] Furthermore, in circuit design, pin 1 of the current limiting chip U2 is also connected to the load through the second inductor L2 and the rectifier diode D1 in sequence, the second inductor L2 is connected to the positive electrode of the rectifier diode D1, and the negative electrode of the rectifier diode D1 is connected to the load;

[0065] The positive electrode of the farad capacitor C4 is connected to the boost circuit and is also grounded via a sixth resistor R6 and an eighth resistor R8 connected in series;

[0066] The line connecting the sixth resistor R6 and the eighth resistor R8 is also connected to the processor.

[0067] Among them, the 4th pin of the boost chip U3 is the switch pin. When the farad capacitor C4 supplies power to the load, the 4th pin of the boost chip U3 is at a high level, and the boost chip U3 remains in an open and conductive state. If the battery supplies power to the load, the boost chip U3 is in a closed and disconnected state, and the coordination of the rectifier diode D1 and the boost chip U3 can effectively prevent backflow.

[0068] During the charging of the farad capacitor C4, the current flows in the following direction: power supply - pin 4 of the buck chip U1 - pin 3 of the buck chip U1 - first inductor L1 - pin 5 of the current limiting chip U2 - pin 1 of the current limiting chip U2 - positive electrode of the farad capacitor C4;

[0069] During the discharge of the farad capacitor C4, the current flows in the following direction: the positive electrode of the farad capacitor C4 - the second inductor L2 - the rectifier diode D1 - the load.

[0070] The logic switch circuit includes a PMOS tube Q1, the S pole of the PMOS tube Q1 is connected to the power supply, the G pole of the PMOS tube Q1 is connected to the processor through a twelfth resistor R12, the D pole of the PMOS tube Q1 is connected to the battery charging circuit, and the G pole of the PMOS tube Q1 is connected to the S pole of the PMOS tube Q1 through an eleventh resistor R11, so that the PMOS tube Q1 is kept in a disconnected state during the charging of the farad capacitor C4;

[0071] When the power supply is just connected, the 1st pin of the buck chip U1 is at a high level, and the buck chip U1 is in an open and conducting state by default. At the same time, the G pin of the PMOS tube Q1 is at a high level, and the PMOS tube Q1 is in a disconnected (or cut-off) state by default; the processor detects the power of the farad capacitor C4 in real time. If the power of the farad capacitor C4 is less than 90%, the states of the above two pins are not changed, so that the power supply gives priority to charging the farad capacitor C4;

[0072] When the power of the Farad capacitor C4 reaches 90% of the full charge state, the processor controls the buck chip U1 to turn off. At the same time, the processor controls the G pole of the PMOS tube Q1 to a low level, so that the PMOS tube Q1 is turned on, and then switches to charging the battery.

[0073] Furthermore, in circuit design, the G pole of the PMOS tube Q1 is also connected to the S pole of the PMOS tube Q1 through the seventh capacitor C7, and the D pole of the PMOS tube Q1 is also grounded through the fifth capacitor C5;

[0074] The line connecting the power supply and the logic switch circuit is also grounded through a seventeenth resistor R17 and a sixteenth resistor R16 connected in series;

[0075] The line connecting the sixteenth resistor R16 and the seventeenth resistor R17 is also connected to the processor.

[0076] The battery charging circuit includes a charging management chip U4. The charging management chip U4 has 9 pins, namely pin 1 (TEMP), pin 2 (PROG), pin 3 (GND), pin 4 (VCC), pin 5 (BAT), pin 6 (STDBY#), pin 7 (CHRG#), pin 8 (CE), and pin 9 (EP). Pin 4 of the charging management chip U4 is connected to the D pole of the PMOS tube Q1, pin 8 of the charging management chip U4 is connected to pin 4 of the charging management chip U4, pin 7 of the charging management chip U4 is suspended, pin 6 of the charging management chip U4 is grounded through the thirteenth resistor R13, pin 3 of the charging management chip U4 is grounded, pin 2 of the charging management chip U4 is grounded through the fourteenth resistor R14, pin 1 of the charging management chip U4 is connected to the battery, pin 1 of the charging management chip U4 is also connected to pin 4 of the charging management chip U4 through the tenth resistor R10, and pin 1 of the charging management chip U4 is also grounded through the fifteenth resistor R15, pin 9 of the charging management chip U4 is grounded, and pin 9 of the charging management chip U4 is also connected to pin 5 of the charging management chip U4 through the sixth capacitor C6, and pin 5 of the charging management chip U4 is also connected to the battery and the output switch circuit respectively.

[0077] The battery is a lithium battery, the quantity is one, and the rated output voltage is 4.2 V. The battery has an NTC pin, the NTC pin of the battery is connected to pin 1 of the charging management chip U4, the negative electrode of the battery is grounded, the positive electrode of the battery is connected to pin 5 of the charging management chip U4, and the positive electrode of the battery is also connected to the output switch circuit.

[0078] The output switch circuit includes a switch chip U5, which has 5 pins, namely, pin 1 (VOUT), pin 2 (GND), pin 3 (nFAULT), pin 4 (EN), and pin 5 (VIN). Pin 1 of the switch chip U5 is connected to the load, pin 2 of the switch chip U5 is grounded, pin 3 of the switch chip U5 is connected to pin 5 of the switch chip U5 through a ninth resistor R9, pin 4 of the switch chip U5 is connected to pin 5 of the switch chip U5, and pin 5 of the switch chip U5 is respectively connected to the positive electrode of the battery and pin 5 of the charging management chip U4.

[0079] Among them, pin 4 of the switch chip U5 is the switch pin. During battery discharge, pin 4 of the switch chip U5 is at a high level, so that the switch chip U5 is in an open and conductive state; if the farad capacitor C4 supplies power to the load, the switch chip U5 is in a closed and disconnected state, which plays a role in preventing backflow.

[0080] Furthermore, in circuit design, the line connecting the load and the switch chip U5 is grounded via a ninth capacitor C9.

[0081] During battery charging, the current flows from: power supply -- PMOS tube Q1 -- pin 4 of charging management chip U4 -- pin 5 of charging management chip U4 -- positive electrode of the battery;

[0082] During battery discharge, the current flows from the positive electrode of the battery to the pin 5 of the switch chip U5 to the pin 1 of the switch chip U5 to the load.

[0083] In this embodiment, in order to adapt to the corresponding electronic equipment, it can be set that: the input voltage of the power supply is 5V, and after the step-down circuit, the voltage becomes 2.7V, and the rated voltage of the farad capacitor C4 is also 2.7V, so that the farad capacitor C4 is charged with a charging voltage of 2.7V;

[0084] The boost chip U3 is configured to work at an input voltage of 0.8-5V, and output a constant voltage of 5V after boosting; therefore, it can be concluded that the first voltage value is 5V; when the farad capacitor C4 is discharged until its voltage drops below 0.8V, the boost chip U3 will no longer work;

[0085] The rated voltage of the battery is set to 4.2V, that is, the second voltage value is 4.2V;

[0086] The supply voltage value of the load can be configured between 3.0-5.5V, that is, the load can work normally within this voltage value range.

[0087] Of course, the above numerical settings are not limited and can be set according to actual application products and needs.

[0088] The electronic device charge and discharge control circuit provided by the present invention is described below. The electronic device charge and discharge control circuit described below and the electronic device charge and discharge control method described above can be referred to each other.

[0089] On the other hand, the present invention provides an electronic device charge and discharge control circuit, comprising: a power connection terminal, a processor, a load connection terminal, a farad capacitor C4 and a battery;

[0090] The power connection end is connected to the farad capacitor C4 through the step-down circuit and the current limiting circuit in sequence, and the farad capacitor C4 is connected to the load connection end through the step-up circuit;

[0091] The power connection terminal is also connected to the battery through the logic switch circuit and the battery charging circuit in sequence, and the battery is connected to the load connection terminal through the output switch circuit;

[0092] The processor is connected to the step-down circuit, the farad capacitor C4, and the logic switch circuit respectively.

[0093] As the names suggest, the power connection terminal is used to connect to a power source, and the load connection terminal is used to connect to a load.

[0094] Specifically, the buck circuit includes a buck chip U1, and the model of the buck chip U1 is: ETA3409S2F. The buck chip U1 has 5 pins, namely pin 1 (EN), pin 2 (GND), pin 3 (LX), pin 4 (VIN), and pin 5 (FB). Pin 1 of the buck chip U1 is connected to the processor, pin 2 of the buck chip U1 is grounded, pin 4 of the buck chip U1 is connected to the power connection terminal, pin 1 of the buck chip U1 is also connected to pin 4 of the buck chip U1 through a second resistor R2, pin 3 of the buck chip U1 is connected to the current limiting circuit through a first inductor L1, and pin 5 of the buck chip U1 is grounded through a fourth resistor R4;

[0095] The current limiting circuit includes a current limiting chip U2, and the model of the current limiting chip U2 is: SGM2590. The current limiting chip U2 has 5 pins, namely pin 1 (VOUT), pin 2 (GND), pin 3 (ILIM), pin 4 (EN), and pin 5 (VIN). Pin 5 of the current limiting chip U2 is connected to pin 3 of the buck chip U1 through the first inductor L1, pin 4 of the current limiting chip U2 is connected to pin 5 of the current limiting chip U2, pin 2 of the current limiting chip U2 is grounded, pin 3 of the current limiting chip U2 is grounded through the third resistor R3, pin 1 of the current limiting chip U2 is connected to the positive electrode of the farad capacitor C4, and the negative electrode of the farad capacitor C4 is grounded.

[0096] The boost circuit includes a boost chip U3, and the model of the boost chip U3 is: SGM6623YN6G / TR. The boost chip U3 has 6 pins, namely, pin 1 (SW), pin 2 (GND), pin 3 (FB), pin 4 (EN), pin 5 (VS), and pin 6 (NC). Pin 4 of the boost chip U3 is respectively connected to pin 1 of the current limiting chip U2 and the positive electrode of the farad capacitor C4, pin 6 of the boost chip U3 is suspended, pin 2 of the boost chip U3 is grounded, pin 3 of the boost chip U3 is grounded through the seventh resistor R7, pin 5 of the boost chip U3 is connected to the negative electrode of the rectifier diode D1, pin 1 of the boost chip U3 is connected to the positive electrode of the rectifier diode D1, and pin 5 of the boost chip U3 is also connected to the seventh resistor R7 through the fifth resistor R5 and then grounded.

[0097] Furthermore, the line connecting the first inductor L1 and the current limiting chip U2 is connected with the second capacitor C2 and the first end of the first resistor R1 in sequence, and the second ends of the second capacitor C2 and the first resistor R1 are respectively connected to the 5th pin of the step-down chip U1;

[0098] The line connecting the power supply connection end and the step-down circuit is also grounded via a first capacitor C1;

[0099] Pin 1 of the current limiting chip U2 is also connected to the load connection terminal through the second inductor L2 and the rectifier diode D1 in sequence. The second inductor L2 is connected to the positive electrode of the rectifier diode D1, and the negative electrode of the rectifier diode D1 is connected to the load connection terminal.

[0100] The positive electrode of the farad capacitor C4 is connected to the boost circuit and is also grounded via a sixth resistor R6 and an eighth resistor R8 connected in series;

[0101] The line connecting the sixth resistor R6 and the eighth resistor R8 is also connected to the processor.

[0102] The logic switch circuit includes a PMOS tube Q1, the S pole of the PMOS tube Q1 is connected to the power connection end, the G pole of the PMOS tube Q1 is connected to the processor through the twelfth resistor R12, the D pole of the PMOS tube Q1 is connected to the battery charging circuit, and the G pole of the PMOS tube Q1 is connected to the S pole of the PMOS tube Q1 through the eleventh resistor R11.

[0103] Furthermore, the G pole of the PMOS tube Q1 is also connected to the S pole of the PMOS tube Q1 through the seventh capacitor C7, and the D pole of the PMOS tube Q1 is also grounded through the fifth capacitor C5;

[0104] The line connecting the power supply connection end and the logic switch circuit is also grounded through a seventeenth resistor R17 and a sixteenth resistor R16 connected in series;

[0105] The line connecting the sixteenth resistor R16 and the seventeenth resistor R17 is also connected to the processor.

[0106] The battery charging circuit includes a charging management chip U4, and the model of the charging management chip U4 is: TP4056. The charging management chip U4 has 9 pins, namely pin 1 (TEMP), pin 2 (PROG), pin 3 (GND), pin 4 (VCC), pin 5 (BAT), pin 6 (STDBY#), pin 7 (CHRG#), pin 8 (CE), and pin 9 (EP). Pin 4 of the charging management chip U4 is connected to the D pole of the PMOS tube Q1, pin 8 of the charging management chip U4 is connected to pin 4 of the charging management chip U4, pin 7 of the charging management chip U4 is suspended, pin 6 of the charging management chip U4 is grounded through the thirteenth resistor R13, pin 3 of the charging management chip U4 is grounded, pin 2 of the charging management chip U4 is grounded through the fourteenth resistor R14, pin 1 of the charging management chip U4 is connected to the battery, pin 1 of the charging management chip U4 is also connected to pin 4 of the charging management chip U4 through the tenth resistor R10, and pin 1 of the charging management chip U4 is also grounded through the fifteenth resistor R15, pin 9 of the charging management chip U4 is grounded, and pin 9 of the charging management chip U4 is also connected to pin 5 of the charging management chip U4 through the sixth capacitor C6, and pin 5 of the charging management chip U4 is also connected to the battery and the output switch circuit respectively.

[0107] The battery is a lithium battery, the quantity is one, and the rated output voltage is 4.2 V. The battery has an NTC pin, the NTC pin of the battery is connected to pin 1 of the charging management chip U4, the negative electrode of the battery is grounded, the positive electrode of the battery is connected to pin 5 of the charging management chip U4, and the positive electrode of the battery is also connected to the output switch circuit.

[0108] The output switch circuit includes a switch chip U5, and the model of the switch chip U5 is: SGM2594CXN5. The switch chip U5 has 5 pins, namely pin 1 (VOUT), pin 2 (GND), pin 3 (nFAULT), pin 4 (EN), and pin 5 (VIN). Pin 1 of the switch chip U5 is connected to the load connection terminal, pin 2 of the switch chip U5 is grounded, pin 3 of the switch chip U5 is connected to pin 5 of the switch chip U5 through the ninth resistor R9, pin 4 of the switch chip U5 is connected to pin 5 of the switch chip U5, and pin 5 of the switch chip U5 is respectively connected to the positive electrode of the battery and pin 5 of the charging management chip U4.

[0109] Furthermore, the line connecting the load connection terminal and the switch chip U5 is grounded via a ninth capacitor C9.

[0110] The electronic device charge and discharge control circuit of the present invention is used to execute the electronic device charge and discharge control method described above, so the operation logic of the circuit is not described in detail here.

[0111] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for controlling charging and discharging of an electronic device, characterized in that: include: When the power supply is connected, the step-down circuit is turned on, the logic switch circuit is turned off, and the power supply charges the farad capacitor through the step-down circuit and the current limiting circuit; When the electric quantity of the farad capacitor reaches a preset value, the processor controls the step-down circuit to be disconnected, and controls the logic switch circuit to be turned on at the same time, and the power supply charges the battery through the logic switch circuit and the battery charging circuit; When the load is connected, if the voltage of the farad capacitor is within the voltage input value range required for the boost circuit to work, the boost circuit is turned on, and the farad capacitor is boosted by the boost circuit to supply power to the load at the first voltage value, and at the same time, the output switch circuit is disconnected; When the farad capacitor is discharged to the point where it cannot supply power to the load at the first voltage value, the boost circuit is disconnected, and the output switch circuit is turned on, and the battery supplies power to the load at the second voltage value through the output switch circuit; Wherein, the first voltage value is greater than the second voltage value; The step-down circuit includes a step-down chip, which has 5 pins, wherein pin 1 of the step-down chip is connected to the processor, pin 2 of the step-down chip is grounded, pin 4 of the step-down chip is connected to the power supply, pin 1 of the step-down chip is also connected to pin 4 of the step-down chip through a second resistor, pin 3 of the step-down chip is connected to the current limiting circuit through a first inductor, and pin 5 of the step-down chip is grounded through a fourth resistor; The current limiting circuit includes a current limiting chip, which has 5 pins. Pin 5 of the current limiting chip is connected to pin 3 of the buck chip through a first inductor, pin 4 of the current limiting chip is connected to pin 5 of the current limiting chip, pin 2 of the current limiting chip is grounded, pin 3 of the current limiting chip is grounded through a third resistor, pin 1 of the current limiting chip is connected to the positive electrode of the farad capacitor, and the negative electrode of the farad capacitor is grounded.

2. The electronic device charge and discharge control method according to claim 1, characterized in that: The boost circuit includes a boost chip, which has 6 pins. Pin 4 of the boost chip is respectively connected to pin 1 of the current limiting chip and the positive electrode of the farad capacitor, pin 6 of the boost chip is suspended, pin 2 of the boost chip is grounded, pin 3 of the boost chip is grounded through a seventh resistor, pin 5 of the boost chip is connected to the negative electrode of the rectifier diode, pin 1 of the boost chip is connected to the positive electrode of the rectifier diode, and pin 5 of the boost chip is also connected to the seventh resistor through a fifth resistor and then grounded.

3. The electronic device charge and discharge control method according to claim 1, characterized in that: Pin 1 of the buck chip is a switch pin. During the charging of the farad capacitor, pin 1 of the buck chip is at a high level, and the buck chip remains in an open and conducting state.

4. The electronic device charge and discharge control method according to claim 3, characterized in that: The processor controls pin 1 of the buck chip to be at a low level, so that the buck chip is turned off and disconnected.

5. The electronic device charge and discharge control method according to claim 4, characterized in that: During the charging of the farad capacitor, the processor will detect the power of the farad capacitor in real time. When the power of the farad capacitor reaches 90% of the full charge state, the processor controls the buck chip to turn off.

6. The electronic device charge and discharge control method according to claim 1, characterized in that: Pin 4 of the current limiting chip is a switch pin. During the charging of the farad capacitor, pin 4 of the current limiting chip is at a high level, and the current limiting chip remains in an open and conducting state.

7. The electronic device charge and discharge control method according to claim 1, characterized in that: The logic switch circuit includes a PMOS tube, the S pole of the PMOS tube is connected to the power supply, the G pole of the PMOS tube is connected to the processor through a twelfth resistor, the D pole of the PMOS tube is connected to the battery charging circuit, and the G pole of the PMOS tube is connected to the S pole of the PMOS tube through an eleventh resistor, so that the PMOS tube remains in a disconnected state during the charging of the farad capacitor.

8. The electronic device charge and discharge control method according to claim 7, characterized in that: The processor controls the G pole of the PMOS tube to a low level, so that the PMOS tube is in a conducting state.

9. The electronic device charge and discharge control method according to claim 7, characterized in that: The battery charging circuit includes a charging management chip, which has 9 pins. Pin 4 of the charging management chip is connected to the D pole of the PMOS tube, pin 8 of the charging management chip is connected to pin 4 of the charging management chip, pin 7 of the charging management chip is suspended, pin 6 of the charging management chip is grounded through a thirteenth resistor, pin 3 of the charging management chip is grounded, pin 2 of the charging management chip is grounded through a fourteenth resistor, pin 1 of the charging management chip is connected to the battery, pin 1 of the charging management chip is also connected to pin 4 of the charging management chip through a tenth resistor, and pin 1 of the charging management chip is also grounded through a fifteenth resistor, pin 9 of the charging management chip is grounded, and pin 9 of the charging management chip is also connected to pin 5 of the charging management chip through a sixth capacitor, and pin 5 of the charging management chip is also connected to the battery and the output switch circuit respectively.

10. The electronic device charge and discharge control method according to claim 9, characterized in that: The battery has an NTC pin, the NTC pin of the battery is connected to pin 1 of the charging management chip, the negative electrode of the battery is grounded, the positive electrode of the battery is connected to pin 5 of the charging management chip, and the positive electrode of the battery is also connected to the output switch circuit.

11. The electronic device charge and discharge control method according to claim 10, characterized in that: The output switch circuit includes a switch chip, which has 5 pins. Pin 1 of the switch chip is connected to the load, pin 2 of the switch chip is grounded, pin 3 of the switch chip is connected to pin 5 of the switch chip through a ninth resistor, pin 4 of the switch chip is connected to pin 5 of the switch chip, and pin 5 of the switch chip is respectively connected to the positive pole of the battery and pin 5 of the charging management chip.

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