Time-domain ping-pong quantization ultra-high-speed analog-to-digital

Abstract

The invention relates to a time domain ping-pong type quantization ultra-high-speed analog-to-digital converter which comprises a sampling switch, a voltage time conversion module, a first ping-pong channel, a second ping-pong channel, a time residual error generator, an asynchronous pipeline successive approximation time-to-digital converter, an encoder and a code value combination unit. The sampling switch is used for sampling an input signal; the voltage-time conversion module is used for performing voltage-time signal conversion on the sampling signal; the first ping-pong channel and the second ping-pong channel are used for quantizing differential time signals in different sampling periods; the time residual error generator is used for generating a time residual error signal; the asynchronous pipeline successive approximation time-to-digital converter is used for quantizing the residual time difference; the encoder is used for carrying out code value conversion; the code value combining unit is used for combining the first quantized code value and the second quantized code value. According to the converter, the circuit area is greatly reduced on the basis of realizing the sampling speed of the two channels, and the clock skew and jitter of the clock signal do not influence the circuit performance.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a time domain ping-pong quantized ultra-high-speed analog-to-digital converter. Background Art

[0002] The development of the Internet of Things has led to a growing demand for high-speed data transmission and acquisition. Wired transmission and high-performance instrument systems require ultra-high-speed medium-resolution analog-to-digital converters. With the gradual development of integrated circuit technology, transistor size and power supply voltage continue to decrease, and the design difficulty of traditional voltage domain analog-to-digital converters (ADCs) has gradually increased. Currently, time interleaving technology (TI) is often used to implement ultra-high-speed analog-to-digital converters. However, due to the limitation of single-channel conversion speed, a large number of channels often need to be interleaved to achieve ultra-high sampling rates, which greatly increases the chip area and power consumption, and makes the chip performance extremely susceptible to clock skew and channel mismatch. Since time domain ADC can achieve ultra-high conversion rates for a single channel, it has become a research hotspot in academia and industry.

[0003] But single-channel ultra-high-speed time domain ADC also faces some problems.

[0004] Prior art 1 implements a successive approximation time-to-digital converter (SA TDC) based on loop expansion, achieving a single-channel sampling rate of 10 GS / s. However, due to the accumulation of jitter noise in the SA TDC delay chain, the noise performance of the system is poor.

[0005] The second prior art realizes a two-step data converter that uses a flash time-to-digital converter (Flash TDC) for high-bit quantization and a SA TDC for low-bit quantization. Compared with the first prior art, it realizes lower jitter noise. However, it is limited by the quantization speed of the first-stage Flash TDC and the speed of the inter-stage time residual generator, and its single-channel sampling speed is relatively low. In order to increase the sampling speed, the second prior art uses two-channel interleaving at the same time and adds another channel, that is, adds another voltage-to-time data converter, a Flash TDC, a time residual generator, and a delay pipeline successive approximation time digital converter.

[0006] However, the speed-up method of the second prior art causes the circuit area to be directly doubled, and there will be a clock skew between the sampling clocks of the two channels, which will bring additional nonlinearity. Summary of the invention

[0007] In order to solve the above problems existing in the prior art, the present invention provides a time domain ping-pong quantized ultra-high-speed analog-to-digital converter. The technical problem to be solved by the present invention is achieved by the following technical solutions:

[0008] The embodiment of the present invention provides a time domain ping-pong quantization ultra-high-speed analog-to-digital converter, comprising: a sampling switch, a voltage-time conversion module, a first ping-pong channel, a second ping-pong channel, a time residual generator, an asynchronous pipeline successive approximation time-to-digital converter, an encoder and a code value combination unit, wherein:

[0009] The sampling switch is used to sample the input signal to obtain a sampled signal;

[0010] The voltage-time conversion module is used to convert the sampling signal into a voltage-time signal to obtain a differential time signal;

[0011] The first ping-pong channel is used to quantize the differential time signal under the control of a first clock signal within a first sampling period to obtain a first quantization code value;

[0012] The second ping-pong channel is used to quantize the differential time signal under the control of a second clock signal in a second sampling period to obtain a second quantization code value; the first sampling period is different from the second sampling period;

[0013] The time residual generator is used to generate a time residual signal according to the first quantization code value or the second quantization code value;

[0014] The asynchronous pipeline successive approximation time-to-digital converter is used to complete the quantization of the residual time difference according to the time residual difference signal and output a first quantization code value;

[0015] The encoder is used for converting the first quantization code value or the second quantization code value to obtain a second quantization code value;

[0016] The code value combining unit is used to combine the first quantization code value and the second quantization code value to obtain a quantization result.

[0017] In one embodiment of the present invention, the first ping-pong channel includes a first selection switch and a first time-to-digital converter, wherein:

[0018] The input end of the first selection switch is connected to the output end of the voltage-to-time converter and inputs the first clock signal, and the output end is connected to the input end of the first time-to-digital converter; the output end of the first time-to-digital converter is connected to the input end of the time residual generator and the input end of the encoder.

[0019] In one embodiment of the present invention, the first time-to-digital converter comprises a flash time-to-digital converter, a vernier time-to-digital converter, or an interpolation-based flash time-to-digital converter.

[0020] In one embodiment of the present invention, the second ping-pong channel comprises a second selection switch and a second time-to-digital converter, wherein:

[0021] The input end of the second selection switch is connected to the output end of the voltage-to-time converter and inputs the second clock signal, and the output end is connected to the input end of the second time-to-digital converter; the output end of the second time-to-digital converter is connected to the input end of the time residual generator and the input end of the encoder.

[0022] In one embodiment of the present invention, the second time-to-digital converter comprises a flash time-to-digital converter, a vernier time-to-digital converter, or an interpolation-based flash time-to-digital converter.

[0023] In one embodiment of the present invention, the asynchronous pipelined successive approximation time-to-digital converter is formed by sequentially connecting a number of single-stage structures with the same structure.

[0024] In one embodiment of the present invention, each stage of the single-stage structure includes: a time comparator, a first delay unit, a first inverter, a second inverter, a first MOS tube, a second MOS tube, a first load capacitor, a second load capacitor, a second delay unit, a third inverter, a fourth inverter, a third MOS tube, a fourth MOS tube, a third load capacitor and a fourth load capacitor, wherein:

[0025] The positive phase input end of the time comparator is connected to the input end of the first delay unit and serves as the first input end of the single-stage structure to input the first time pulse signal, the negative phase input end is connected to the input end of the second delay unit and serves as the second input end of the single-stage structure to input the second time pulse signal, the first output end is connected to the gate of the first MOS tube and the gate of the fourth MOS tube, and the second output end is connected to the gate of the third MOS tube and the gate of the second MOS tube;

[0026] The output end of the first delay unit is connected to the input end of the first inverter; the output end of the first inverter is connected to the input end of the second inverter, the drain of the first MOS tube, and the drain of the second MOS tube; the source of the first MOS tube is connected to the first end of the first load capacitor, and the second end of the first load capacitor is grounded; the source of the second MOS tube is connected to the second end of the second load capacitor, and the second end of the second load capacitor is grounded; the output end of the second inverter outputs a third time pulse signal and is connected to the first input end of the lower single-stage structure;

[0027] The output end of the second delay unit is connected to the input end of the third inverter; the output end of the third inverter is connected to the input end of the fourth inverter, the drain of the third MOS tube, and the drain of the fourth MOS tube; the source of the third MOS tube is connected to the first end of the third load capacitor, and the second end of the third load capacitor is grounded; the source of the fourth MOS tube is connected to the second end of the fourth load capacitor, and the second end of the fourth load capacitor is grounded; the output end of the fourth inverter outputs a fourth time pulse signal and is connected to the second input end of the lower single-stage structure;

[0028] The capacitance value of the first load capacitor is greater than the capacitance value of the second load capacitor;

[0029] The capacitance value of the third load capacitor is greater than the capacitance value of the fourth load capacitor.

[0030] In one embodiment of the present invention, the voltage-to-time conversion module includes a first voltage-to-time converter, wherein the input end of the first voltage-to-time converter is the output end of the sampling switch, and the output end is connected to the input end of the first ping-pong channel and the input end of the second ping-pong channel.

[0031] In one embodiment of the present invention, the voltage-to-time conversion module includes a first voltage-to-time converter and a second voltage-to-time converter, wherein:

[0032] The input end of the first voltage-to-time converter is connected to the output end of the sampling switch, and the output end is connected to the input end of the first ping-pong channel;

[0033] The input end of the second voltage-to-time converter is connected to the output end of the sampling switch, and the output end is connected to the input end of the second ping-pong channel.

[0034] In one embodiment of the present invention, a capacitor is further included, wherein one end of the capacitor is connected to the output end of the sampling switch, and the other end is grounded.

[0035] Compared with the prior art, the present invention has the following beneficial effects:

[0036] 1. The analog-to-digital converter of the present invention is based on the time domain ping-pong quantization technology, and adopts the first ping-pong channel and the second ping-pong channel to quantize the differential time signal. On the basis of the single-channel circuit, one ping-pong channel is added, and the circuit area is greatly reduced on the basis of achieving the sampling speed of two channels. The first clock signal and the second clock signal are only used to select the first ping-pong channel and the second ping-pong channel, and are not used for front-end sampling. Therefore, the clock skew and jitter of the first clock signal and the second clock signal will not affect the circuit performance.

[0037] 2. In the asynchronous pipeline successive approximation time-to-digital converter of the present invention, the single-stage structure uses the first load capacitor, the second load capacitor, the third load capacitor and the fourth load capacitor as selective delay units to generate a reference delay value. The capacitance value of the load capacitor unit is less affected by changes in process, power supply voltage and temperature, so that the single-stage structure has stronger stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 A schematic diagram of the structure of a time domain ping-pong quantized ultra-high-speed analog-to-digital converter provided by an embodiment of the present invention;

[0039] Figure 2 A timing diagram of a time domain ping-pong quantized ultra-high-speed analog-to-digital converter provided by an embodiment of the present invention;

[0040] Figure 3 A schematic diagram of a single-stage structure of an asynchronous pipeline successive approximation time-to-digital converter provided by an embodiment of the present invention;

[0041] Figure 4 A schematic diagram of the structure of another time-domain ping-pong quantized ultra-high-speed analog-to-digital converter provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0042] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0043] Embodiment 1

[0044] See also Figure 1 and Figure 2 , Figure 1 A schematic diagram of the structure of a time domain ping-pong quantized ultra-high-speed analog-to-digital converter provided by an embodiment of the present invention. Figure 2 A timing diagram of a time-domain ping-pong quantized ultra-high-speed analog-to-digital converter provided by an embodiment of the present invention.

[0045] The time domain ping-pong quantized ultra-high-speed analog-to-digital converter of this embodiment includes a sampling switch 1, a voltage-time conversion module 2, a first ping-pong channel 3, a second ping-pong channel 4, a time residual generator 5, an asynchronous pipeline successive approximation time digital converter 6, an encoder 7 and a code value combination unit 8. The sampling switch 1 is used to sample an input signal to obtain a sampling signal. The voltage-time conversion module 2 is used to convert the sampling signal into a voltage-time signal to obtain a differential time signal. The first ping-pong channel 3 is used to quantize the differential time signal under the control of a first clock signal in a first sampling period to obtain a first quantization code value. The second ping-pong channel 4 is used to quantize the differential time signal under the control of a second clock signal in a second sampling period to obtain a second quantization code value; the first sampling period is different from the second sampling period. The time residual generator 5 is used to generate a time residual signal according to the first quantization code value or the second quantization code value. The asynchronous pipeline successive approximation time digital converter 6 is used to complete the quantization of the remaining time difference according to the time residual signal and output a first quantization code value. The encoder 7 is used to convert the first quantization code value or the second quantization code value to obtain a second quantization code value. The code value combination unit 8 is used to combine the first quantization code value and the second quantization code value to obtain a quantization result Dout.

[0046] Specifically, the sampling switch 1 controlled by the clock signal CLKS samples the input voltage signal Vin to obtain a sampling signal, which is a differential voltage.

[0047] After sampling is completed, the clock signal CLKT controls the voltage-time conversion module 2 to convert the input differential voltage into a voltage-time signal, and outputs a set of differential time signals.

[0048] The first ping-pong channel 3 and the second ping-pong channel 4 quantize the input differential time signal under the control of different clock signals in different sampling periods, and output the quantized code value of the time signal, and the code value is in the form of a thermometer code. It can be understood that in the first sampling period, the first ping-pong channel 3 quantizes the differential time signal converted by the voltage-time conversion module 2 under the control of the first clock signal; when the voltage-time conversion module 2 completes the conversion, the circuit starts sampling in the second sampling period; in the second sampling period, the second ping-pong channel 4 quantizes the differential time signal converted by the voltage-time conversion module 2 under the control of the second clock signal, such as Figure 2 As shown, Figure 2 The middle channel 1 refers to the first ping-pong channel 3 , and the channel 2 refers to the second ping-pong channel 4 .

[0049] The time residual generator 5 generates a time residual signal according to the quantization result of the first ping-pong channel 3 or the second ping-pong channel 4. Its input signal is the thermometer code output by the first ping-pong channel 3 or the second ping-pong channel 4 and the clock signal CLKR, and its output is the time residual signal.

[0050] After the time difference is generated, it is passed to the next-stage asynchronous pipeline successive approximation time digital converter 6 for conversion. The asynchronous pipeline successive approximation time digital converter 6 completes the quantization of the remaining time difference, and the input is the time difference signal, and the output is the first quantization code value of the low bit, and the code value form is binary code. In addition, the asynchronous pipeline successive approximation time digital converter 6 generates an asynchronous clock according to the time signal, and the asynchronous clock is used to sample the output result of the thermometer code encoder 7 and the quantization result of the asynchronous pipeline successive approximation time digital converter 6.

[0051] The encoder 7 is used to convert the thermometer code output by the first ping-pong channel 3 or the second ping-pong channel 4 into a binary code to obtain a high-order second quantization code value.

[0052] The code value combination unit 8 is used to combine and output the high-order second quantization code value and the low-order first quantization code value, so as to realize the storage and output of multi-stage pipeline quantization results.

[0053] The analog-to-digital converter of this embodiment is based on the time-domain ping-pong quantization technology, and uses the first ping-pong channel and the second ping-pong channel to quantize the differential time signal. On the basis of the single-channel circuit, one ping-pong channel is added, and the circuit area is greatly reduced on the basis of achieving the sampling speed of two channels. The first clock signal and the second clock signal are only used to select the first ping-pong channel and the second ping-pong channel, and are not used for front-end sampling. Therefore, the clock skew and jitter of the first clock signal and the second clock signal will not affect the circuit performance.

[0054] Furthermore, the time-domain ping-pong quantized ultra-high-speed analog-to-digital converter further includes a capacitor C, one end of which is connected to the output end of the sampling switch 1 , and the other end of which is grounded.

[0055] In a specific embodiment, the first ping-pong channel 3 includes a first selection switch 31 and a first time-to-digital converter 32, wherein the input end of the first selection switch 31 is connected to the output end of the voltage-to-time converter 2 and inputs the first clock signal CLKS1, and the output end is connected to the input end of the first time-to-digital converter 32; the output end of the first time-to-digital converter 32 is connected to the input end of the time residual generator 5 and the input end of the encoder 7.

[0056] The second ping-pong channel 4 includes a second selection switch 41 and a second time digital converter 42, wherein the input end of the second selection switch 41 is connected to the output end of the voltage-to-time converter 2 and inputs the second clock signal CLKS2, and the output end is connected to the input end of the second time digital converter 42; the output end of the second time digital converter 42 is connected to the input end of the time residual generator 5 and the input end of the encoder 7.

[0057] The first time-to-digital converter 32 and the second time-to-digital converter 42 each include a flash time-to-digital converter Flash TDC, a vernier time-to-digital converter, or an interpolation-based flash time-to-digital converter.

[0058] Specifically, when the first clock signal CLKS1 is at a high level, the first selection switch 31 is turned on, and the first time digital converter 32 receives the differential time signal and starts quantization. When the voltage-time conversion module 2 completes the conversion, the circuit can start sampling in the next cycle without waiting for the first time digital converter 32 to complete quantization and generate a time residual. When sampling and the voltage-time conversion module 2 are converted in the next cycle, the second selection switch 41 is turned on, and the second time digital converter 42 receives the differential time signal and starts quantization.

[0059] In this embodiment, two Flash TDCs are used to perform ping-pong operation and the remaining circuit modules are multiplexed, so that only the circuit area of ​​one Flash TDC is added to the single-channel circuit, thereby achieving the speed-up effect of two channels compared with the prior art, greatly reducing the circuit area. In addition, since the first clock signal CLKS1 and the second clock signal CLKS2 are not directly used as front-end sampling signals, but only control the selection of Flash TDC operation, their clock skew will not cause nonlinearity.

[0060] See also Figure 3 , Figure 3 A schematic diagram of a single-stage structure of an asynchronous pipeline successive approximation time-to-digital converter provided by an embodiment of the present invention.

[0061] The asynchronous pipeline SAR TDC 6 is formed by connecting a plurality of single-stage structures 60 with the same structure in sequence.

[0062] Each single-stage structure 60 includes: a time comparator A, a first delay unit Delay1, a first inverter I1, a second inverter I2, a first MOS tube M1, a second MOS tube M2, a first load capacitor C L1 , the second load capacitance C S1 , the second delay unit Delay2, the third inverter I3, the fourth inverter I4, the third MOS tube M3, the fourth MOS tube M4, the third load capacitor CL2 and the fourth load capacitor C S2 .

[0063] The positive input terminal of the time comparator A is connected to the input terminal of the first delay unit Delay1 and serves as the first input terminal of the single-stage structure to input the first time pulse signal, the negative input terminal is connected to the input terminal of the second delay unit Delay2 and serves as the second input terminal of the single-stage structure to input the second time pulse signal, the first output terminal is connected to the gate of the first MOS tube M1 and the gate of the fourth MOS tube M4, and the second output terminal is connected to the gate of the third MOS tube M3 and the gate of the second MOS tube M2. The output terminal of the first delay unit Delay1 is connected to the input terminal of the first inverter I1; the output terminal of the first inverter I1 is connected to the input terminal of the second inverter I2, the drain of the first MOS tube M1, and the drain of the second MOS tube M2; the source of the first MOS tube M1 is connected to the first load capacitor C L1 The first end of the first load capacitor C L1 The second end of the second MOS tube M2 is connected to the second load capacitor C S1 The second end of the second load capacitor C S1 The second end of the second inverter I2 is grounded; the output end of the second inverter I2 outputs a third time pulse signal and is connected to the first input end of the lower single-stage structure. The output end of the second delay unit Delay2 is connected to the input end of the third inverter I3; the output end of the third inverter I3 is connected to the input end of the fourth inverter I4, the drain of the third MOS tube M3, and the drain of the fourth MOS tube M4; the source of the third MOS tube M3 is connected to the third load capacitor C L2 The first end of the third load capacitor C L2 The second end of the fourth MOS tube M4 is connected to the ground; the source of the fourth MOS tube M4 is connected to the fourth load capacitor C S2 The second end of the fourth load capacitor C S2 The second end of the first load capacitor C is grounded; the output end of the fourth inverter I4 outputs a fourth time pulse signal and is connected to the second input end of the lower single-stage structure. L1 The capacitance value is greater than the second load capacitance C S1 The capacitance value of the third load capacitor C L2 The capacitance value is greater than the fourth load capacitance C S2 Capacitance value.

[0064] For the Nth single-stage structure of the asynchronous pipelined successive approximation time-to-digital converter 6, the input signal is two time pulse signals Tp <n>With Tn <n>The time comparator A compares the input time difference according to the order of the rising edge of the input signal, obtains the comparison result, and controls the conduction of the load capacitor switch according to the result. Different delay times are generated by the selected load capacitor size. <n>For example, when the rising edge of comes first, OP outputs high level and ON outputs low level. OP and ON control the large load capacitor C at the P end. L1 , the small load capacitance C at the N end S2 Turn on, so that the load of the P-side inverter I1 is larger, the path delay is longer, the load of the N-side inverter I3 is smaller, the path delay is shorter, and the first Tp <n>The signal delay is greater, and the later arriving Tn <n>Less signal delay, shortening Tp <n>With Tn <n>The delay value of the delay unit Delay1 and Delay2 must be greater than the comparison time of the time comparator A. <n>Arrives at the first inverter I1, Tn <n>Before reaching the third inverter I3, the time comparator A has compared the result, resulting in a path delay. Similarly, when OP outputs a low level and ON outputs a high level, the small load capacitor C at the P end S1 , the large load capacitance C at the N end L2 Turn on.

[0065] The size of the reference delay of the SA TDC of the prior art solution is determined by the size of the discharge transistor current. Since the size of the discharge current of the transistor is greatly affected by PVT fluctuations, the reference delay value is also sensitive to PVT changes. Compared with the discharge transistor structure used in the prior art, the single-stage structure of this embodiment uses the first load capacitor, the second load capacitor, the third load capacitor and the fourth load capacitor as selective delay units to generate the reference delay value. The capacitance value of the capacitor is less affected by changes in the process, power supply voltage and temperature, so that the single-stage structure has stronger stability.

[0066] In a specific embodiment, the voltage-time conversion module 2 includes a first voltage-time converter VTC, wherein the input end of the first voltage-time converter VTC is connected to the output end of the sampling switch 1, and the output end is connected to the input end of the first ping-pong channel 3 and the input end of the second ping-pong channel 4. Figure 1 Specifically, after sampling is completed, the clock signal CLKT controls the first voltage-to-time converter VTC to convert the input differential voltage into a voltage-to-time signal, and outputs a set of differential time signals.

[0067] In another specific embodiment, the voltage-time conversion module 2 includes two voltage-time converters, namely a first voltage-time converter VTC1 and a second voltage-time converter VTC2. The input end of the first voltage-time converter VTC1 is connected to the output end of the sampling switch 1, and the output end is connected to the input end of the first ping-pong channel 3; the input end of the second voltage-time converter VTC2 is connected to the output end of the sampling switch 1, and the output end is connected to the input end of the second ping-pong channel 4. Figure 4 As shown, Figure 4 A schematic diagram of the structure of another time-domain ping-pong quantized ultra-high-speed analog-to-digital converter provided by an embodiment of the present invention.

[0068] Specifically, in the first sampling period, the clock signal CLKT1 controls the first voltage-to-time converter VTC1 to convert the input differential voltage into a voltage-to-time signal and output a set of differential time signals. In the second sampling period, the clock signal CLKT2 controls the second voltage-to-time converter VTC2 to convert the input differential voltage into a voltage-to-time signal and output a set of differential time signals.

[0069] This embodiment uses two voltage-to-time converters to achieve the sampling speed of two channels, thereby achieving the effect of increasing the speed.

[0070] In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise clearly and specifically defined.

[0071] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification.

[0072] Although the present application is described herein in conjunction with various embodiments, in the process of implementing the claimed application, those skilled in the art may understand and implement other variations of the disclosed embodiments by viewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "one" or "an" does not exclude multiple situations. A single processor or other unit may implement several functions listed in a claim. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0073] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.< / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A time domain ping-pong quantized ultra-high-speed analog-to-digital converter, It is characterized in that include: A sampling switch, a voltage-time conversion module, a first ping-pong channel, a second ping-pong channel, a time residual generator, an asynchronous pipeline successive approximation time-to-digital converter, an encoder and a code value combination unit, wherein: The sampling switch is used to sample the input signal to obtain a sampled signal; The voltage-time conversion module is used to convert the sampling signal into a voltage-time signal to obtain a differential time signal; The first ping-pong channel is used to quantize the differential time signal under the control of a first clock signal within a first sampling period to obtain a first quantization code value; The second ping-pong channel is used to quantize the differential time signal under the control of a second clock signal in a second sampling period to obtain a second quantization code value; the first sampling period is different from the second sampling period; The time residual generator is used to generate a time residual signal according to the first quantization code value or the second quantization code value; The asynchronous pipeline successive approximation time-to-digital converter is used to complete the quantization of the residual time difference according to the time residual difference signal and output a first quantization code value; The encoder is used for converting the first quantization code value or the second quantization code value to obtain a second quantization code value; The code value combining unit is used to combine the first quantization code value and the second quantization code value to obtain a quantization result.

2. The time domain ping-pong quantized ultra-high speed analog-to-digital converter according to claim 1, It is characterized in that The first ping-pong channel includes a first selection switch and a first time-to-digital converter, wherein: The input end of the first selection switch is connected to the output end of the voltage-to-time converter and inputs the first clock signal, and the output end is connected to the input end of the first time-to-digital converter; the output end of the first time-to-digital converter is connected to the input end of the time residual generator and the input end of the encoder.

3. The time domain ping-pong quantized ultra-high speed analog-to-digital converter according to claim 2, It is characterized in that The first time-to-digital converter includes a flash time-to-digital converter, a vernier time-to-digital converter, or an interpolation-based flash time-to-digital converter.

4. The time domain ping-pong quantized ultra-high speed analog-to-digital converter according to claim 1, It is characterized in that The second ping-pong channel includes a second selection switch and a second time-to-digital converter, wherein: The input end of the second selection switch is connected to the output end of the voltage-to-time converter and inputs the second clock signal, and the output end is connected to the input end of the second time-to-digital converter; the output end of the second time-to-digital converter is connected to the input end of the time residual generator and the input end of the encoder.

5. The time domain ping-pong quantized ultra-high speed analog-to-digital converter according to claim 4, It is characterized in that The second time-to-digital converter includes a flash time-to-digital converter, a vernier time-to-digital converter, or an interpolation-based flash time-to-digital converter.

6. The time domain ping-pong quantized ultra-high speed analog-to-digital converter according to claim 1, It is characterized in that The asynchronous pipeline successive approximation time-to-digital converter is formed by connecting a number of single-stage structures with the same structure in sequence.

7. The time domain ping-pong quantized ultra-high speed analog-to-digital converter according to claim 6, It is characterized in that Each single-stage structure includes: a time comparator, a first delay unit, a first inverter, a second inverter, a first MOS tube, a second MOS tube, a first load capacitor, a second load capacitor, a second delay unit, a third inverter, a fourth inverter, a third MOS tube, a fourth MOS tube, a third load capacitor and a fourth load capacitor, wherein: The positive phase input end of the time comparator is connected to the input end of the first delay unit and serves as the first input end of the single-stage structure to input the first time pulse signal, the negative phase input end is connected to the input end of the second delay unit and serves as the second input end of the single-stage structure to input the second time pulse signal, the first output end is connected to the gate of the first MOS tube and the gate of the fourth MOS tube, and the second output end is connected to the gate of the third MOS tube and the gate of the second MOS tube; The output end of the first delay unit is connected to the input end of the first inverter; the output end of the first inverter is connected to the input end of the second inverter, the drain of the first MOS tube, and the drain of the second MOS tube; the source of the first MOS tube is connected to the first end of the first load capacitor, and the second end of the first load capacitor is grounded; the source of the second MOS tube is connected to the second end of the second load capacitor, and the second end of the second load capacitor is grounded; the output end of the second inverter outputs a third time pulse signal and is connected to the first input end of the lower single-stage structure; The output end of the second delay unit is connected to the input end of the third inverter; the output end of the third inverter is connected to the input end of the fourth inverter, the drain of the third MOS tube, and the drain of the fourth MOS tube; the source of the third MOS tube is connected to the first end of the third load capacitor, and the second end of the third load capacitor is grounded; the source of the fourth MOS tube is connected to the second end of the fourth load capacitor, and the second end of the fourth load capacitor is grounded; the output end of the fourth inverter outputs a fourth time pulse signal and is connected to the second input end of the lower single-stage structure; The capacitance value of the first load capacitor is greater than the capacitance value of the second load capacitor; The capacitance value of the third load capacitor is greater than the capacitance value of the fourth load capacitor.

8. The time domain ping-pong quantized ultra-high speed analog-to-digital converter according to claim 1, It is characterized in that The voltage-to-time conversion module comprises a first voltage-to-time converter, wherein an input end of the first voltage-to-time converter is an output end of the sampling switch, and an output end of the first voltage-to-time converter is connected to an input end of the first ping-pong channel and an input end of a second ping-pong channel.

9. The time domain ping-pong quantized ultra-high speed analog-to-digital converter according to claim 1, It is characterized in that The voltage-time conversion module includes a first voltage-time converter and a second voltage-time converter, wherein: The input end of the first voltage-to-time converter is connected to the output end of the sampling switch, and the output end is connected to the input end of the first ping-pong channel; The input end of the second voltage-to-time converter is connected to the output end of the sampling switch, and the output end is connected to the input end of the second ping-pong channel.

10. The time domain ping-pong quantized ultra-high-speed analog-to-digital converter according to claim 1, It is characterized in that It also includes a capacitor, wherein one end of the capacitor is connected to the output end of the sampling switch, and the other end is grounded.

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