Semiconductor structure and preparation method thereof

Abstract

The embodiment of the invention relates to a semiconductor structure and a preparation method thereof. The semiconductor structure comprises a substrate; the first stacking structures are located on the substrate, the first stacking structures are arranged at intervals in the first direction, each first stacking structure comprises a bit line and a first semiconductor layer which are sequentially stacked in the vertical direction, and the bit lines make electrical contact with the first semiconductor layers; the supporting layer is located on the substrate and at least makes contact with part of the side wall of the first semiconductor layer. The embodiment of the invention provides a semiconductor structure which is beneficial to improving the electrical performance of the semiconductor structure.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] As the integration density of semiconductor memories develops toward a higher direction, higher requirements are placed on the structure size of semiconductor memory arrays.

[0003] Semiconductor memory usually includes a transistor, the drain of the transistor is connected to the bit line, the source of the transistor is connected to the capacitor, and the word line of the semiconductor memory can control the opening or closing of the channel region of the transistor, and then read the data information stored in the capacitor through the bit line, or write the data information into the capacitor for storage through the bit line. As the size of transistors decreases, in order to ensure the better electrical performance of semiconductor memory, the requirements for the process of preparing transistors, bit lines, word lines, etc. are getting higher and higher.

[0004] However, the electrical performance of current semiconductor memories still needs to be further improved. Summary of the invention

[0005] The embodiments of the present disclosure provide a semiconductor structure and a method for preparing the same, which are at least beneficial to improving the electrical performance of the semiconductor structure.

[0006] An embodiment of the present disclosure provides a semiconductor structure, including: a substrate; a plurality of first stacked structures located on the substrate, the first stacked structures being arranged at intervals along a first direction, the first stacked structures comprising bit lines and a first semiconductor layer stacked in sequence along a vertical direction, the bit lines being electrically in contact with the first semiconductor layer; a supporting layer, located on the substrate, in contact with at least a portion of the side walls of the first semiconductor layer.

[0007] In some embodiments, the semiconductor structure also includes: a second stacking structure located on the first stacking structure, each of the first stacking structures includes a plurality of second stacking structures arranged at intervals along the second direction, the second stacking structure includes a second semiconductor layer and a third semiconductor layer stacked in sequence along a vertical direction, the size of the first semiconductor layer in the first direction is larger than the size of the third semiconductor layer in the first direction, the second semiconductor layer includes a first sublayer, a second sublayer and a third sublayer, the size of the second sublayer along the second direction is smaller than the sizes of the first sublayer and the third sublayer along the second direction; the semiconductor structure also includes: a word line, the word line extends along the first direction, and the word line surrounds the side wall of the second sublayer of each of the plurality of second stacking structures arranged at intervals along the first direction, the size of the word line in the second direction is smaller than or equal to the size of the second stacking structure in the second direction.

[0008] In some embodiments, the first semiconductor layer and the bit line both extend along the second direction, the projections of the first semiconductor layer and the bit line on the substrate overlap, the first stacking structure includes a first segment and a second segment adjacent to each other in sequence along the second direction, the first segment contacts the second semiconductor layer, the second segment is adjacent to the first segments arranged at intervals along the second direction, the size of the first segment in the first direction is larger than the size of the second segment in the first direction; the supporting layer contacts two opposite side walls of the second segment, and contacts a portion of the side wall of the first segment adjacent to the second segment, and the supporting layer is also located between the second stacking structures arranged along the second direction.

[0009] In some embodiments, the support layer includes a first support layer, a second support layer, and a third support layer stacked in sequence along a vertical direction, the material of the second support layer is different from the material of the first support layer and the third support layer, the upper surface of the first support layer is flush with the upper surface of the first stacking structure, and the upper surface of the second support layer is flush with the upper surface of the first sublayer.

[0010] Correspondingly, an embodiment of the present disclosure also provides a method for preparing a semiconductor structure, comprising: providing a substrate; forming a plurality of initial first stacking structures arranged at intervals along a first direction on the substrate, the initial first stacking structure comprising a sacrificial layer and a first semiconductor layer stacked in sequence along a vertical direction; forming a supporting layer on the substrate, the supporting layer being located on a portion of the side walls of the initial first stacking structure and at least in contact with the first semiconductor layer; removing the sacrificial layer to form a first groove, the first groove exposing the bottom surface of the first semiconductor layer; forming a plurality of bit lines arranged at intervals along the first direction, a bit line filling a first groove, and the bit line being in electrical contact with the first semiconductor layer.

[0011] In some embodiments, it also includes: forming a second stacking structure arranged in an array on the surface of the initial first stacking structure, the second stacking structure arranged in an array is arranged at intervals along the first direction and the second direction, the second stacking structure includes a second semiconductor layer and a third semiconductor layer stacked in sequence along a vertical direction, and the second semiconductor layer is electrically in contact with the first semiconductor layer; forming a word line, the word line extends along the first direction, and the word line surrounds the side wall of each of the multiple second semiconductor layers arranged at intervals along the first direction.

[0012] In some embodiments, the method for forming the initial first stacking structure includes: forming an initial sacrificial layer and an initial first semiconductor layer stacked in sequence along a direction away from the substrate on the substrate; etching the initial sacrificial layer and the initial first semiconductor layer to form a plurality of sacrificial layers arranged at intervals along the first direction and a plurality of first semiconductor layers arranged at intervals along the first direction, one of the first semiconductor layers is located on the top surface of one of the sacrificial layers to form the initial first stacking structure, and each of the first semiconductor layers and each of the sacrificial layers extends along the second direction.

[0013] In some embodiments, it also includes: forming a second stacking structure arranged in an array on the surface of the initial first semiconductor layer, and the method for forming the second stacking structure includes: forming an isolation layer on the top surface of the initial first semiconductor layer; etching the isolation layer to form a plurality of first through holes arranged in an array in the isolation layer, the plurality of first through holes are arranged at intervals along the first direction and the second direction, and the first through holes expose a portion of the top surface of the initial first semiconductor layer; forming a second semiconductor layer filled in a portion of the first through holes, the second semiconductor layer is located on the top surface of the initial first semiconductor layer; forming a third semiconductor layer, the third semiconductor layer is located on the top surface of the second semiconductor layer, and together with the second semiconductor layer constitute the second stacking structure.

[0014] In some embodiments, a plurality of second stacking structures arranged at intervals along the second direction are arranged in a row, and a method for forming the initial first stacking structure includes: etching a portion of the isolation layer and a portion of the initial first stacking structure located between two adjacent columns of the second stacking structures until the substrate is exposed to form a first groove and a plurality of the initial first stacking structures isolated by the first groove, wherein the first groove extends along the second direction, and a size of the second stacking structure in the first direction is smaller than a size of the initial first stacking structure in the first direction.

[0015] In some embodiments, the second stacking structures arranged at intervals along the first direction are arranged in a row, and the isolation layer located between two adjacent rows of the second stacking structures includes a first portion and a second portion arranged alternately along the first direction, the second portion is opposite to the second stacking structure, and the size of the second portion in the first direction is less than or equal to the size of the second stacking structure in the first direction, and the method for forming the support layer includes: etching the first portion until a portion of the surface of the initial first stacking structure is exposed; etching the exposed initial first stacking structure until a portion of the substrate surface is exposed to form a second through hole; the remaining initial first stacking structure forms a first area and a second area adjacent to each other in sequence along the second direction, wherein the second area is opposite to the gap between two adjacent second stacking structures along the second direction, the first area is opposite to the second stacking structure, and the size of the first area in the first direction is greater than the size of the second area in the first direction; forming the support layer filled in the second through hole, the support layer is in contact with two opposite side walls of the second area, and in contact with a portion of the side wall of the first area adjacent to the second area.

[0016] In some embodiments, the isolation layer includes: a first sub-isolation layer, a first dielectric layer, and a second sub-isolation layer stacked in sequence along a direction perpendicular to the surface of the substrate, the first dielectric layer, the first sub-isolation layer, and the second sub-isolation layer all surround the second semiconductor layer, and the material of the first dielectric layer is different from the materials of the first sub-isolation layer and the second sub-isolation layer; etching the isolation layer to form a plurality of first through holes arranged in an array in the isolation layer, including: etching the isolation layer to form a plurality of initial first through holes arranged in an array in the isolation layer; etching the first sub-isolation layer and the second sub-isolation layer laterally along the initial first through holes to form a first through hole, the aperture of the first through hole corresponding to the first sub-isolation layer and the second sub-isolation layer is larger than the aperture of the first through hole corresponding to the first dielectric layer; after forming the bit line, it also includes: removing the first dielectric layer to expose a portion of the side wall of the second semiconductor layer; forming a word line, the word line extending along the first direction, and the word line surrounds the side wall of each of the plurality of second semiconductor layers arranged at intervals along the first direction.

[0017] In some embodiments, the method for forming the support layer filled in the second through hole includes: filling the first support layer, the second support layer and the third support layer in sequence in the second through hole, the material of the second support layer is different from the materials of the first support layer and the third support layer, the upper surface of the first support layer is flush with the upper surface of the initial first stacking structure, and the upper surface of the second support layer is in contact with the lower surface of the first dielectric layer.

[0018] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0019] In the technical solution of the semiconductor structure provided by the embodiment of the present disclosure, a plurality of first stacked structures are provided on the substrate, and the first stacked structure includes a bit line and a first semiconductor layer stacked in sequence in a vertical direction, and the first semiconductor layer can be used to form a transistor, and the bit line is in electrical contact with the first semiconductor layer. The bit line is located on the surface of the substrate, so that in the actual step of preparing the semiconductor structure, the bit line can be formed on the surface of the substrate, and compared with forming a buried bit line, a larger space can be provided for the preparation process of forming the bit line, the reliability of the process of forming the bit line is improved, and the formed bit line is ensured to have a good morphology.

[0020] In the actual preparation process steps of forming the bit line on the surface of the substrate, the support layer plays a supporting role for the first semiconductor layer, preventing the first semiconductor layer from collapsing and causing process damage to the bit line on the substrate, ensuring that the formed bit line has a continuous morphology, thereby improving the electrical performance of the formed semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings, and these exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise specified, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0022] Figure 1 A schematic diagram of a three-dimensional structure of a semiconductor structure provided by an embodiment of the present disclosure;

[0023] Figure 2 A schematic diagram of a top view of a semiconductor structure provided by an embodiment of the present disclosure;

[0024] Figure 3 A schematic diagram of a three-dimensional structure of another semiconductor structure provided by an embodiment of the present disclosure;

[0025] Figure 4 A schematic diagram of a top view of another semiconductor structure provided by an embodiment of the present disclosure;

[0026] Figure 5 A schematic cross-sectional structure diagram of a semiconductor structure provided by an embodiment of the present disclosure;

[0027] Figure 6A schematic diagram of a three-dimensional structure of another semiconductor structure provided by an embodiment of the present disclosure;

[0028] Figures 7 to 33 A schematic structural diagram corresponding to each step in a method for preparing a semiconductor structure provided in another embodiment of the present disclosure. DETAILED DESCRIPTION

[0029] As can be seen from the background technology, the yield of semiconductor structures currently needs to be further improved.

[0030] Analysis has found that one of the reasons why the yield of the current semiconductor structure needs to be further improved is that, at present, the semiconductor structure generally includes a substrate and a semiconductor layer located on the substrate. The semiconductor layer is used to form a transistor. As the integration of transistors becomes higher and higher, the number of semiconductor layers also increases. In the process of preparing the bit line, it is necessary to dope the substrate from the gap between adjacent semiconductor layers to convert the substrate directly opposite to the semiconductor layer into a bit line with conductive ability, forming a buried bit line. However, as the size of the semiconductor structure decreases, the gap between adjacent semiconductor layers has a large aspect ratio, making it difficult to control the doping accuracy of the substrate, and the problem of uneven doping is prone to occur, making the formed buried bit line discontinuous and poor in morphology, which in turn leads to poor electrical performance of the bit line, which is not conducive to improving the electrical performance of the semiconductor structure.

[0031] The embodiments of the present disclosure provide a semiconductor structure in which a bit line is located on the surface of a substrate, so that in the actual step of preparing the semiconductor structure, the bit line can be formed on the surface of the substrate. Compared with forming a buried bit line, a larger space can be provided for the preparation process of forming the bit line, the reliability of the process of forming the bit line is improved, and it is ensured that the formed bit line has a good morphology, thereby improving the electrical performance of the formed semiconductor structure.

[0032] The following will describe the various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present disclosure, many technical details are provided in order to enable the reader to better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can be implemented.

[0033] Figure 1 A schematic diagram of the three-dimensional structure of a semiconductor structure provided by an embodiment of the present disclosure.

[0034] refer to Figure 1, the semiconductor structure includes: a substrate 101. The semiconductor structure also includes: a plurality of first stacked structures 1 located on the substrate 101, the first stacked structures 1 are arranged at intervals along the first direction X, the first stacked structures 1 include bit lines 103 and first semiconductor layers 102 stacked in sequence along the vertical direction, and the bit lines 103 are in electrical contact with the first semiconductor layer 102. The semiconductor structure also includes: a support layer 104, located on the substrate 101, and in contact with at least part of the sidewall of the first semiconductor layer 102. The vertical direction is a direction perpendicular to the plane where the substrate 101 is located.

[0035] In some embodiments, the semiconductor structure can be used to form any one of a DRAM (Dynamic Random Access Memory) memory, a SRAM (Static Random-Access Memory) memory, or a SDRAM (Synchronous Dynamic Random-Access Memory) memory.

[0036] In some embodiments, the material of the substrate 101 is a semiconductor material. In some embodiments, the material of the substrate 101 is silicon. In some embodiments, the substrate 101 may also be germanium, germanium silicon, or silicon on insulator.

[0037] In some embodiments, the first semiconductor layer 102 may be used to form a source of a transistor. The first semiconductor layer 102 is in electrical contact with the bit line 103 to receive data information transmitted via the bit line 103 .

[0038] In some embodiments, the first semiconductor layer 102 is doped with doping ions, and the type of the doping ions may be either P-type or N-type. In a specific example, the P-type doping ions may include: any one of boron ions, aluminum ions, gallium ions, or indium ions, and the N-type doping ions may include: any one of phosphorus ions, bismuth ions, antimony ions, or arsenic ions.

[0039] In some embodiments, the material of the first semiconductor layer 102 is silicon. In some embodiments, the first semiconductor layer 102 may also be germanium, germanium silicon, or silicon on insulator.

[0040] The plurality of first stacked structures 1 are arranged at intervals along the first direction X, so that each first semiconductor layer 102 in the plurality of first stacked structures 1 is also arranged at intervals along the first direction X. Each semiconductor layer is used to form a source of at least one transistor, so that a plurality of transistors can be formed on the surface of the substrate 101 .

[0041] The bit line 103 is located on the surface of the substrate 101, so that in the actual step of preparing the semiconductor structure, the bit line 103 can be formed on the surface of the substrate 101. Compared with forming a buried bit line 103, a larger space can be provided for the preparation process of forming the bit line 103, thereby improving the reliability of the process of forming the bit line 103 and ensuring that the formed bit line 103 has a good morphology.

[0042] The support layer 104 plays a supporting role. The support layer 104 is in contact with at least part of the side wall of the first semiconductor layer 102. In the actual preparation process step of forming the bit line 103 on the surface of the substrate 101, it is used to support the first semiconductor layer 102 to prevent the first semiconductor layer 102 from collapsing and causing process damage to the bit line 103 on the substrate 101, thereby ensuring that the formed bit line 103 has a continuous and uniform morphology, thereby ensuring better electrical performance of the semiconductor structure.

[0043] Figure 3 A schematic diagram of a three-dimensional structure of another semiconductor structure provided by an embodiment of the present disclosure, Figure 4 for Figure 3 The top view of the structure is shown in Fig. Figure 5 for Figure 4 Schematic diagram of the cross-sectional structure along the aa' direction.

[0044] refer to Figures 3 to 5 In some embodiments, the semiconductor structure further includes: a second stack structure 2 located on the first stack structure 1, each first stack structure 1 includes a plurality of second stack structures 2 arranged at intervals along the second direction Y, the second stack structure 2 includes a second semiconductor layer 105 and a third semiconductor layer 106 stacked in sequence along a vertical direction, the size of the first semiconductor layer 102 in the first direction X is greater than the size of the third semiconductor layer 106 in the first direction X, the second semiconductor layer 105 includes a first sublayer 111, a second sublayer 112 and a third sublayer 113, the size of the second sublayer 112 in the second direction Y is smaller than the sizes of the first sublayer 111 and the third sublayer 113 in the second direction Y; the semiconductor structure further includes: a word line 107, the word line 107 extends along the first direction X, and the word line 107 surrounds the side wall of the second sublayer 112 of each second semiconductor layer 105 in the plurality of second stack structures 2 arranged at intervals along the first direction X, and the size of the word line 107 in the second direction Y is less than or equal to the size of the second stack structure 2 in the second direction Y.

[0045] The second semiconductor layer 105, the third semiconductor layer 106 and the first semiconductor layer 102 are used to form a transistor. In some embodiments, the second semiconductor layer 105 is used to form a channel of the transistor, the third semiconductor layer 106 is used to form a drain region of the transistor, and the first semiconductor layer 102 is used to form a source region of the transistor.

[0046] In some embodiments, the doping ion type of the first semiconductor layer 102 is the same as the doping ion type of the third semiconductor layer 106 , and the doping ion type of the first semiconductor layer 102 is different from the doping ion type of the second semiconductor layer 105 to form a junction transistor.

[0047] In a specific example, the doping ion types of the first semiconductor layer 102 and the third semiconductor layer 106 can be P-type, the doping ion type of the first semiconductor layer 102 can be N-type, and the doping ion concentration of the second semiconductor layer 105 is less than the doping ion concentration of the first semiconductor layer 102, and the doping ion concentration of the second semiconductor layer 105 is less than the doping ion concentration of the third semiconductor layer 106.

[0048] In another specific example, the doping ion types of the first semiconductor layer 102 and the third semiconductor layer 106 can be N-type, the doping ion type of the first semiconductor layer 102 can be P-type, and the doping ion concentration of the second semiconductor layer 105 is less than the doping ion concentration of the first semiconductor layer 102, and the doping ion concentration of the second semiconductor layer 105 is less than the doping ion concentration of the third semiconductor layer 106.

[0049] In some embodiments, the doping ion types of the first semiconductor layer 102, the second semiconductor layer 105, and the third semiconductor layer 106 can be the same to form a junctionless transistor, and the doping ion concentration of the second semiconductor layer 105 is less than the doping ion concentration of the first semiconductor layer 102, and the doping ion concentration of the second semiconductor layer 105 is less than the doping ion concentration of the third semiconductor layer 106.

[0050] In some embodiments, the material of the second semiconductor layer 105 is any one of silicon, germanium, silicon germanium, or silicon on insulator. In some embodiments, the material of the third semiconductor layer 106 is any one of silicon, germanium, silicon germanium, or silicon on insulator.

[0051] Each first stacking structure 1 includes a plurality of second stacking structures 2 arranged at intervals along a second direction Y. Each first stacking structure 1 and a second stacking structure 2 located thereon constitute a transistor. That is, the first stacking structure 1 and the plurality of second stacking structures 2 arranged at intervals on the first stacking structure 1 can constitute a plurality of transistors.

[0052] The width of the first semiconductor layer 102 in the first direction X is greater than the width of the third semiconductor layer 106 in the first direction X, so that the size of the third semiconductor layer 106 in the first direction X is smaller, and the volume occupied by the third semiconductor layer 106 is smaller, thereby reducing the size of the semiconductor structure.

[0053] In some embodiments, the width dimension of the first semiconductor layer 102 in the first direction X may also be greater than the width dimension of the second semiconductor layer 105 in the first direction X, so that the volume occupied by the second semiconductor layer 105 in the first direction X is small, which can reduce the volume occupied by the second semiconductor layer 105 and further reduce the size of the semiconductor structure. In addition, the width dimension of the first semiconductor layer 102 in the first direction X is set to be larger, which can avoid the problem that the contact area between the first semiconductor layer 102 and the second semiconductor layer 105 is reduced due to the process reasons in the actual step of forming the stack of the first semiconductor layer 102 and the second semiconductor layer 105, which makes the first semiconductor layer 102 and the second semiconductor layer 105 staggered. The width dimension of the first semiconductor layer 102 in the first direction X is greater than the width dimension of the second semiconductor layer 105 in the first direction X, so that the alignment accuracy between the first semiconductor layer 102 and the second semiconductor layer 105 is high, thereby ensuring that there is a large contact area between the first semiconductor layer 102 and the second semiconductor layer 105, which is conducive to the transmission of carriers.

[0054] In the embodiment of the present disclosure, the second semiconductor layer 105 is divided into a first sublayer 111, a second sublayer 112 and a third sublayer 113 according to the different width dimensions of different parts of the second semiconductor layer 105. In fact, the first sublayer 111, the second sublayer 112 and the third sublayer 113 are an integrated structure.

[0055] The width dimension of the second sub-layer 112 along the second direction Y is smaller than the width dimension of the first sub-layer 111 along the second direction Y, and the width dimension of the second sub-layer 112 along the second direction Y is smaller than the width dimension of the third sub-layer 113 along the second direction Y. In this way, the second sub-layer 112 is concave in the second direction Y compared with the first sub-layer 111 and the third sub-layer 113, exposing a portion of the top surface of the first sub-layer 111 facing the second sub-layer 112, and exposing a portion of the bottom surface of the third sub-layer 113 facing the second sub-layer 112. In this way, the word line 107 surrounding the side wall of the second sub-layer 112 can also contact the exposed top surface of the first sub-layer 111, and the exposed portion of the bottom surface of the third sub-layer 113 facing the second sub-layer 112, thereby increasing the contact area between the word line 107 and the second semiconductor layer 105, increasing the channel length of the transistor, and improving the control capability of the word line 107 over the transistor.

[0056] In some embodiments, the width dimension of the second sub-layer 112 along the first direction X is also smaller than the width dimension of the first sub-layer 111 along the first direction X, and the width dimension of the second sub-layer 112 along the first direction X is also smaller than the width dimension of the third sub-layer 113 along the first direction X, so that the second sub-layer 112 is concave compared to the first sub-layer 111 and the third sub-layer 113 in the first direction X. In other words, the orthographic projection of the second sub-layer 112 on the surface of the substrate 101 is located within the orthographic projection of the first sub-layer 111 on the surface of the substrate 101, and the orthographic projection of the second sub-layer 112 on the surface of the substrate 101 is located within the orthographic projection of the third sub-layer 113 on the surface of the substrate 101. In this way, more of the first sublayer 111 is exposed toward the top surface of the second sublayer 112, and more of the third sublayer 113 is exposed toward the bottom surface of the second sublayer 112, so that the contact area between the word line 107 and the second semiconductor layer 105 is further increased, and the channel length of the transistor is further increased, which is beneficial to further improve the control ability of the word line 107 over the transistor.

[0057] The width of the second sub-layer 112 along the second direction Y is smaller than the width of the first sub-layer 111 along the second direction Y, and the width of the second sub-layer 112 along the second direction Y is smaller than the width of the third sub-layer 113 along the second direction Y, so that the sidewalls of the second sub-layer 112 are recessed compared to the first sub-layer 111 and the third sub-layer 113 in the second direction Y. The word line 107 surrounds the sidewall of the second sub-layer 112, which is equivalent to the word line 107 being embedded in a portion of the sidewall of the second semiconductor layer 105, and the width of the word line 107 in the second direction Y is smaller than or equal to the width of the third sub-layer 113 in the second direction Y, and smaller than or equal to the width of the first sub-layer 111 in the second direction Y.

[0058] Specifically, in some embodiments, the width of the word line 107 in the second direction Y is smaller than the width of the third sub-layer 113 in the second direction Y, and the width of the word line 107 in the second direction Y is smaller than the width of the first sub-layer 111 in the second direction Y. In other embodiments, the width of the word line 107 in the second direction Y may also be equal to the width of the third sub-layer 113 in the second direction Y, and the width of the word line 107 in the second direction Y is equal to the width of the first sub-layer 111 in the second direction Y.

[0059] In some embodiments, the material of the word line 107 may be a conductive material, for example, a metal material, including but not limited to at least one of titanium, tantalum, ruthenium, molybdenum, aluminum, tungsten, silver or copper.

[0060] Figure 2 for Figure 1 Schematic diagram of the cross-sectional structure along the AA' direction.

[0061] refer to Figure 1 as well as Figure 2 In some embodiments, the first semiconductor layer 102 and the bit line 103 both extend along the second direction Y, and the projections of the first semiconductor layer 102 and the bit line 103 on the substrate 101 overlap. The first stacked structure 1 includes a first segment 10 and a second segment 11 adjacent to each other in sequence along the second direction Y, the first segment 10 contacts the second semiconductor layer 105, the second segment 11 is adjacent to the first segments 10 arranged at intervals along the second direction Y, and the size of the first segment 10 in the first direction X is greater than the size of the second segment 11 in the first direction X; the support layer 104 contacts the two opposite side walls of the second segment 11, and contacts the partial side walls of the first segment 10 adjacent to the second segment 11, and the support layer 104 is also located between the second stacked structures 2 arranged along the second direction Y.

[0062] The orthographic projections of the first semiconductor layer 102 and the bit line 103 on the substrate 101 overlap, so that the contact area between the first semiconductor layer 102 and the bit line 103 is larger, which is beneficial to enhance the signal transmission capability of the bit line 103 to the first semiconductor layer 102 .

[0063] The first segment 10 is directly opposite to the second semiconductor layer 105 in the vertical direction, and the second segment 11 is directly opposite to the gap between the second semiconductor layers 105 adjacent to each other along the second direction Y in the vertical direction. The size of the first segment 10 in the first direction X is larger than the size of the second segment 11 in the first direction X, so that the contact area between the first semiconductor layer 102 and the second semiconductor layer 105 is larger, which is conducive to increasing the number of carriers transferred from the first semiconductor layer 102 to the second semiconductor layer 105.

[0064] The width of the first segment 10 in the first direction X is set to be greater than the width of the second segment 11 in the first direction X, that is, the width of the second segment 11 in the first direction X is smaller, so that in the adjacent bit lines 103 in the second direction Y, the distance between the two second segments 11 is larger, which can improve the problem of large parasitic capacitance between adjacent bit lines 103 due to the small distance between adjacent bit lines 103, avoid the problem of interference to the signal transmitted in the bit line 103 due to the excessive parasitic capacitance, and ensure the reliability of the signal transmitted in the bit line 103.

[0065] The support layer 104 contacts the two opposite side walls of the second section 11 in the second direction Y, and is located between the second stacked structures 2 arranged along the second direction Y. It can not only isolate the two adjacent bit lines 103 along the second direction Y, but also support the bit lines 103.

[0066] refer to Figure 3In some embodiments, the support layer 104 includes a first support layer 121, a second support layer 122, and a third support layer 123 stacked in sequence along a vertical direction, the material of the second support layer 122 is different from the materials of the first support layer 121 and the third support layer 123, the upper surface of the first support layer 121 is flush with the upper surface of the first stacking structure 1, and the upper surface of the second support layer 122 is flush with the upper surface of the first sublayer 111.

[0067] The upper surface of the first supporting layer 121 refers to the surface of the first supporting layer 121 away from the substrate 101, and the upper surface of the second supporting layer 122 refers to the surface of the second supporting layer 122 away from the substrate 101. The upper surface of the first stacked structure 1 refers to the surface of the first semiconductor layer 102 away from the substrate 101, and the upper surface of the first sublayer 111 refers to the surface of the first sublayer 111 away from the substrate 101.

[0068] In some embodiments, the material of the first support layer 121 may be silicon nitride material, the material of the second support layer 122 may be silicon oxide material, and the material of the third support layer 123 may be silicon nitride material. In this way, the hardness of the formed support layer 104 can be improved and the supporting capacity of the support layer 104 can be improved.

[0069] refer to Figure 3 In some embodiments, the semiconductor structure further includes: an isolation structure 109, the isolation structure 109 covers the surface of the word line 107, and the isolation structure 109 is also located between adjacent second stacked structures 2 to isolate the adjacent second stacked structures 2. The top surface of the isolation structure 109 is flush with the top surface of the second stacked structure 2, exposing the top surface of the third semiconductor layer 106.

[0070] refer to Figure 6 In some embodiments, a capacitor structure 108 is further included. The capacitor structure 108 is located on a surface of the third semiconductor layer 106 away from the substrate 101 and is in electrical contact with the third semiconductor layer 106 .

[0071] In the semiconductor structure provided by the above embodiment, the bit line 103 is located on the surface of the substrate 101, so that in the actual step of preparing the semiconductor structure, the bit line 103 can be formed on the surface of the substrate 101. Compared with forming a buried bit line 103, a larger space can be provided for the preparation process of forming the bit line 103, the reliability of the process of forming the bit line 103 is improved, and it is ensured that the formed bit line 103 has a good morphology, thereby improving the electrical performance of the formed semiconductor structure.

[0072] Correspondingly, an embodiment of the present disclosure also provides a method for preparing a semiconductor structure, which can be used to prepare the semiconductor structure provided by the above embodiment. The semiconductor structure provided by an embodiment of the present disclosure will be described in detail below in conjunction with the accompanying drawings.

[0073] The method for preparing a semiconductor structure comprises:

[0074] refer to Figures 7 to 18 A substrate 101 is provided, and a plurality of initial first stacked structures 3 arranged at intervals along a first direction X are formed on the substrate 101. The initial first stacked structure 3 includes a sacrificial layer 110 and a first semiconductor layer 102 stacked in sequence along a vertical direction. The location of the sacrificial layer 110 is subsequently removed to fill the bit line 103, that is, the sacrificial layer 110 plays a placeholder role.

[0075] In some embodiments, the material of the substrate 101 is a semiconductor material. In some embodiments, the material of the substrate 101 is silicon. In some embodiments, the substrate 101 may also be germanium, germanium silicon, or silicon on insulator.

[0076] In some embodiments, the method of forming the initial first stacking structure 3 includes:

[0077] refer to Figure 7 , an initial sacrificial layer 31 and an initial first semiconductor layer 32 are formed on the substrate 101 and are stacked in sequence in a direction away from the substrate 101 .

[0078] In some embodiments, an epitaxial process may be used to sequentially form a stacked initial sacrificial layer 31 and an initial first semiconductor layer 32 on a substrate 101. The substrate 101 may be a silicon substrate 101, the material of the initial first semiconductor layer 32 may be the same as the material of the substrate 101, and the material of the initial sacrificial layer 31 may be silicon germanium. When the substrate 101 is subjected to an epitaxial process to form silicon germanium, since both the substrate 101 and the initial sacrificial layer 31 contain silicon elements, the lattice constants of the substrate 101 and the initial sacrificial layer 31 match, so that silicon germanium can be more easily grown using the silicon in the substrate 101, and the formed initial sacrificial layer 31 and the initial first semiconductor layer 32 have high film quality and clear boundaries.

[0079] In the embodiment of the present disclosure, a sacrificial layer 110 is first formed, and then the first semiconductor layer 102 is formed. The sacrificial layer 110 is used as a placeholder layer. After the sacrificial layer 110 is subsequently removed and the bit line 103 is filled, the bit line 103 can be in electrical contact with the first semiconductor layer 102. Compared with directly forming the bit line 103 on the substrate 101 and then directly forming the first semiconductor layer 102 on the bit line 103, the use of an epitaxial process to first form the initial sacrificial layer 31 and then form the initial first semiconductor layer 32 can greatly improve the film quality of the formed first semiconductor layer 102, which is conducive to ensuring that the formed semiconductor structure has a high yield.

[0080] refer to Figures 8 to 17In some embodiments, after forming the initial first stacking structure 3, the method for preparing the semiconductor structure further includes:

[0081] A second stacking structure 2 arranged in an array is formed on the surface of the initial first stacking structure 3. The second stacking structure 2 arranged in an array is arranged at intervals along the first direction X and the second direction Y. The second stacking structure 2 includes a second semiconductor layer 105 and a third semiconductor layer 106 stacked in sequence along a vertical direction. The second semiconductor layer 105 is in electrical contact with the first semiconductor layer 102.

[0082] The second semiconductor layer 105, the third semiconductor layer 106 and the first semiconductor layer 102 are used to form a transistor. In some embodiments, the second semiconductor layer 105 is used to form a channel of the transistor, the third semiconductor layer 106 is used to form a drain region of the transistor, and the first semiconductor layer 102 is used to form a source region of the transistor.

[0083] In some embodiments, the doping ion type of the first semiconductor layer 102 is the same as the doping ion type of the third semiconductor layer 106 , and the doping ion type of the first semiconductor layer 102 is different from the doping ion type of the second semiconductor layer 105 .

[0084] In some embodiments, the first semiconductor layer 102 may be doped after forming the first stacked structure 1. In some embodiments, the second semiconductor layer 105 and the third semiconductor layer 106 may be doped after forming the second stacked structure 2. In some embodiments, the initial first stacked structure 3 may also be doped before forming the first stacked structure 1 to form the first semiconductor layer 102.

[0085] In some embodiments, a method of forming the second stacked structure 2 includes:

[0086] refer to Figure 8 , an isolation layer 20 is formed on the top surface of the initial first semiconductor layer 32. In some embodiments, the isolation layer 20 can be formed on the top surface of the initial first semiconductor layer 32 by a deposition process, for example, an atomic layer deposition process or a chemical vapor deposition process can be used. The formed isolation layer 20 covers the entire surface of the initial first semiconductor layer 32.

[0087] refer to Figures 9 to 13 , etching the isolation layer 20 to form a plurality of first through holes 15 arranged in an array in the isolation layer 20 , wherein the plurality of first through holes 15 are arranged at intervals along the first direction X and the second direction Y, and the first through holes 15 expose a portion of the top surface of the initial first semiconductor layer 32 .

[0088] In some embodiments, a method of forming the first through hole 15 may include:

[0089] The top surface of the isolation layer 20 is patterned to define the shape and position of the first through hole 15. In some embodiments, the method for patterning the isolation layer 20 may include: first, forming a first mask layer on the top surface of the isolation layer 20. In some embodiments, the first mask layer may be formed on the top surface of the isolation layer 20 by a deposition process. In some embodiments, the material of the first mask layer may be a spin-coated hard mask. Next, the first mask layer may be patterned by using either a SADP (Self-aligned Double Patterning) process or a SAQP (Self-Aligned Quadruple Patterning) process to form a first opening in the first mask layer. The first opening exposes the top surface of the isolation layer 20, and the shape of the first opening is the same as the opening shape of the first through hole 15 formed subsequently. An etching process may be performed on the isolation layer 20 along the first opening. In some embodiments, the isolation layer 20 may be etched by using either a dry etching process or a wet etching process until the top surface of the initial first semiconductor layer 32 is exposed to form the first through hole 15.

[0090] In some embodiments, the material of the isolation layer 20 may be an integrated structure, that is, the isolation layer 20 is made of the same material. In a direction away from the initial first semiconductor layer 32 , the width of the first through hole 15 remains unchanged.

[0091] In some embodiments, the isolation layer 20 may also include: a first sub-isolation layer 21, a first dielectric layer 22 and a second sub-isolation layer 23 stacked in sequence along a direction perpendicular to the surface of the substrate 101, the first dielectric layer 22, the first sub-isolation layer 21 and the second sub-isolation layer 23 all surround the second semiconductor layer 105, and the material of the first dielectric layer 22 is different from the material of the first sub-isolation layer 21 and the second sub-isolation layer 23.

[0092] In this way, the etching selectivity between the first dielectric layer 22 and the first sub-isolation layer 21, and the etching selectivity between the first dielectric layer 22 and the second sub-isolation layer 23 can be used to remove only the first dielectric layer 22, exposing part of the sidewall of the second semiconductor layer 105, while the first sub-isolation layer 21 and the second sub-isolation layer 23 will not be removed, thereby protecting the remaining sidewalls of the second semiconductor layer 105 and the third semiconductor layer 106. The word line 107 formed subsequently only surrounds the exposed sidewall of the second semiconductor layer 105, avoiding the formation of the word line 107 on the sidewall of the third semiconductor layer 106. In other words, the formed word line 107 is only in electrical contact with the channel region, but not in electrical contact with the drain region.

[0093] refer to Figures 9 to 11 , Fig.10 for Fig. 9The top view of the structure is shown in Fig. Fig.11 for Fig.10 A schematic diagram of a cross-sectional structure in the aa' direction, in some embodiments, the isolation layer 20 includes a first sub-isolation layer 21, a first dielectric layer 22 and a second sub-isolation layer 23, and the isolation layer 20 is etched to form a plurality of first through holes 15 arranged in an array in the isolation layer 20, including:

[0094] The isolation layer 20 is etched to form a plurality of initial first through holes 14 arranged in an array in the isolation layer 20. In some embodiments, the step of forming the initial first through holes 14 may include: etching the first sub-isolation layer 21 along the first opening until the top surface of the first dielectric layer 22 is exposed; continuing to perform an etching process on the first dielectric layer 22 until the top surface of the second sub-isolation layer 23 is exposed; continuing to etch the second sub-isolation layer 23 until the initial first semiconductor layer 32 is exposed to form the initial first through holes 14.

[0095] In the direction away from the top surface of the initial first semiconductor layer 32, the initial first through hole 14 has a constant width in the first direction X and a constant width in the second direction Y. That is, the initial first through hole 14 has a uniform width in the vertical direction.

[0096] After forming the initial first through hole 14, the first sub-isolation layer 21 and the second sub-isolation layer 23 are laterally etched along the initial first through hole 14 to form a first through hole 15, wherein the aperture of the first through hole 15 corresponding to the first sub-isolation layer 21 and the second sub-isolation layer 23 is larger than the aperture of the first through hole 15 corresponding to the first dielectric layer 22.

[0097] That is, the sidewall of the first sub-isolation layer 21 and the second sub-isolation layer 23 are isolated and etched along the initial first through hole 14. In this way, in the formed first through hole 15, the aperture of the first through hole 15 corresponding to the first sub-isolation layer 21 and the aperture of the first through hole 15 corresponding to the second sub-isolation layer 23 are both larger than the aperture of the first through hole 15 corresponding to the first dielectric layer 22. In the second semiconductor layer 105 subsequently formed in the first through hole 15, the width dimension of the second semiconductor layer 105 directly facing the first sub-isolation layer 21 in the vertical direction is larger than the width dimension of the second semiconductor layer 105 directly facing the first dielectric layer 22 in the vertical direction, and the width dimension of the second semiconductor layer 105 directly facing the second sub-isolation layer 23 in the vertical direction is larger than the width dimension of the second semiconductor layer 105 directly facing the first dielectric layer 22. Subsequently, after removing the first dielectric layer 22 , the word line 107 formed at the original position of the first dielectric layer 22 can be embedded in the second semiconductor layer 105 , increasing the contact area between the word line 107 and the second semiconductor layer 105 , thereby increasing the length of the channel and improving the control capability of the word line 107 over the channel.

[0098] In some embodiments, the material of the first sub-isolation layer 21 is the same as that of the second sub-isolation layer 23 , for example, silicon oxide or silicon oxynitride, and the material of the first dielectric layer 22 may be silicon nitride.

[0099] refer to Figures 14 to 17 After forming the first through hole 15, a second semiconductor layer 105 is formed to fill part of the first through hole 15, and the second semiconductor layer 105 is located on the top surface of the initial first semiconductor layer 32; a third semiconductor layer 106 is formed, and the third semiconductor layer 106 is located on the top surface of the second semiconductor layer 105, and together with the second semiconductor layers constitute a second stacking structure 2.

[0100] refer to Figure 14 to Figure 15 , forming a second semiconductor layer 105 in part of the first through hole 15; referring to Figure 16 to Figure 17 A third semiconductor layer 106 is formed in the remaining first through holes 15 , the third semiconductor layer 106 is in electrical contact with the second semiconductor layer 105 , and a top surface of the third semiconductor layer 106 is flush with the top of the opening of the first through hole 15 .

[0101] It can be understood that, since the second semiconductor layer 105 and the third semiconductor layer 106 are filled and formed in the first through hole 15, the side walls of the formed second semiconductor layer 105 and the third semiconductor layer 106 are covered by the isolation layer 20. In order to perform a doping process on the second semiconductor layer 105 and the third semiconductor layer 106 respectively to form a channel region and a drain region respectively, in some embodiments, after the second semiconductor layer 105 is formed in the first through hole 15, the second semiconductor layer 105 is doped to form a channel region. Then, the third semiconductor layer 106 is formed on the top surface of the second semiconductor layer 105, and then the third semiconductor layer 106 is doped to form a drain region. In some embodiments, the doping process can be an ion implantation process.

[0102] In some embodiments, the second semiconductor layer 105 and the third semiconductor layer 106 may be formed by using either a deposition process or an epitaxial process.

[0103] After forming the second semiconductor layer 105 and the third semiconductor layer 106, the initial sacrificial layer 31 and the initial first semiconductor layer 32 are etched to form a plurality of sacrificial layers 110 arranged at intervals along the first direction X and a plurality of first semiconductor layers 102 arranged at intervals along the first direction X, wherein a first semiconductor layer 102 is located on the top surface of a sacrificial layer 110 to form an initial first stacked structure 3, and each first semiconductor layer 102 and each sacrificial layer 110 extend along the second direction Y.

[0104] refer to Fig.18In some embodiments, a plurality of second stacking structures 2 arranged at intervals along the second direction Y are arranged in a row, and a method for forming an initial first stacking structure 3 includes: etching a portion of the isolation layer 20 and a portion of the initial first stacking structure 3 located between two adjacent columns of the second stacking structures 2 until the substrate 101 is exposed to form a first groove 40 and a plurality of initial first stacking structures 3 isolated by the first groove 40, wherein the first groove 40 extends along the second direction Y, and a size of the second stacking structure 2 in the first direction X is smaller than a size of the initial first stacking structure 3 in the first direction X.

[0105] In some embodiments, the exposed substrate 101 is further etched to etch a portion of the thickness of the substrate 101 to form a first groove 40 . This can increase the gap between adjacent first stacking structures 1 and better avoid the risk of short circuit between adjacent first stacking structures 1 .

[0106] In some embodiments, a method for etching a portion of the isolation layer 20 located between two adjacent columns of second stacked structures 2 includes: forming a second mask layer on the top surface of the isolation layer 20 and the top surface of the third semiconductor layer 106; performing a patterning process on the second mask layer, for example, the second mask layer can be patterned by using either a SADP process or a SAQP process to form a second opening in the second mask layer, the second opening exposing the top surface of the isolation layer 20, and the second opening is used to define the opening shape of a first groove 40 formed subsequently; etching the isolation layer 20 along the second opening until the initial first semiconductor layer 32 is exposed, continuing to etch the exposed initial first semiconductor layer 32 until the initial sacrificial layer 31 is exposed, continuing to etch the initial sacrificial layer 31 until the substrate 101 is exposed, and continuing to etch the exposed substrate 101 to etch a partial thickness of the substrate 101 to form a first groove 40.

[0107] refer to Figures 19 to 21 , Fig. 20 for Fig.19 A top view of the structure. Fig.21 for Fig. 20 , in some embodiments, after forming the first trench 40, a trench isolation structure 120 is filled in the first trench 40, the trench isolation structure 120 fills the first trench 40, contacts the sidewall of the formed first semiconductor layer 102, and contacts the sidewall of the formed sacrificial layer 110. The formed trench isolation structure 120 is flush with the top surface of the third semiconductor layer 106.

[0108] In some embodiments, in the step of etching a portion of the isolation layer 20 between two adjacent columns of the second stacked structures 2, the isolation layer 20 located on the sidewalls of the second stacked structures 2 is retained, so that the isolation layer 20 located on the sidewalls of the second stacked structures 2 can protect the second stacked structures 2 and prevent the etching process from causing process damage to the second stacked structures 2. The formed trench isolation structure 120 covers the isolation layer 20 located on the sidewalls of the second stacked structures 2.

[0109] Since part of the isolation layer 20 on the side wall of the second stacking structure 2 is retained, the initial first stacking structure 1 facing the partial isolation layer 20 in the vertical direction is not etched. Therefore, the width dimension of the formed initial first stacking structure 3 in the first direction X is greater than the width dimension of the second stacking structure 2 in the first direction X.

[0110] In some embodiments, the trench isolation structure 120 may be formed by a deposition process, such as an atomic layer deposition process. In some embodiments, the material of the trench isolation structure 120 may be at least one of silicon oxide or silicon oxynitride.

[0111] refer to Figure 22 to Figure 25 ,in, Fig.24 for Fig.23 A top view of the structure. Fig.25 for Fig.24 Schematic diagram of the cross-sectional structure along the bb' direction. The method for preparing the semiconductor structure also includes: forming a support layer 104 on the substrate 101, the support layer 104 is located on a part of the side wall of the initial first stacked structure 3, and at least contacts the first semiconductor layer 102; removing the sacrificial layer 110 to form a first groove, and the first groove exposes the bottom surface of the first semiconductor layer 102. The support layer 104 is used to support the first semiconductor layer 102 in the step of removing the sacrificial layer 110, to prevent the first semiconductor layer 102 from collapsing and causing process damage to the bit line 103 on the substrate 101, to ensure that the formed bit line 103 has a continuous morphology, and to improve the electrical performance of the formed semiconductor structure.

[0112] In some embodiments, the support layer 104 is also in contact with the side wall of the sacrificial layer 110. After removing the sacrificial layer 110, the first groove exposes the side wall of the support layer 104. The bit line 103 subsequently formed in the first groove is in contact with the side wall of the support layer 104. The support layer 104 can play a role in limiting the morphology of the formed bit line 103.

[0113] refer to Fig. 20In some embodiments, the second stacked structures 2 arranged at intervals along the first direction X are arranged in a row, and the isolation layer 20 located between two adjacent rows of second stacked structures 2 includes first portions 51 and second portions 52 arranged alternately along the first direction X, the second portions 52 are directly opposite to the second stacked structures 2 along the second direction Y, and the size of the second portions 52 in the first direction X is less than or equal to the size of the second stacked structures 2 in the first direction X. The method for forming the support layer 104 includes:

[0114] refer to Fig. 22 , the first portion 51 is etched until a portion of the surface of the initial first stacked structure 3 is exposed. In some embodiments, during the step of etching the first portion 51, the trench isolation structure 120 between two adjacent rows of second stacked structures 2 is also etched to expose a portion of the top surface of the initial first stacked structure 3.

[0115] The exposed initial first stacking structure 3 is etched until a portion of the surface of the substrate 101 is exposed, thereby forming a second through hole 16. The second through hole 16 exposes the sidewall of the second portion 52, the sidewall of the initial first stacking structure 3, and the surface of the substrate 101. The remaining initial first stacking structure 3 forms a first region and a second region that are adjacent in sequence along the second direction Y, wherein the second region is directly opposite to the gap between two second stacking structures 2 adjacent along the second direction Y in the vertical direction, the first region is directly opposite to the second stacking structure 2 in the vertical direction, and the size of the first region in the first direction X is greater than the size of the second region in the first direction X.

[0116] In some embodiments, a method for etching the exposed initial first stacking structure 3 until a portion of the surface of the substrate 101 is exposed may include: forming a third mask layer on the top surfaces of the isolation layer 20 and the trench isolation structure 120; patterning the third mask layer using either the SADP process or the SAQP process to form a third opening in the third mask layer, wherein the third opening exposes a portion of the top surface of the isolation layer 20 and a portion of the top surface of the trench isolation structure 120 to define the opening shape of the second through hole 16; etching the isolation layer 20 and the trench isolation structure 120 along the third opening until a portion of the top surface of the initial first stacking structure 3 is exposed; and continuing to etch the initial first stacking structure 3 until the substrate 101 is exposed.

[0117] It can be understood that the size of the second portion 52 in the first direction X is less than or equal to the size of the second stacking structure 2 in the first direction X. In some embodiments, the width of the second portion 52 in the first direction X is equal to the width of the second stacking structure 2 in the first direction X. Then the side wall of the first portion 51 facing the second portion 52 is flush with the side wall of the second stacking structure 2. Since the width of the second stacking structure 2 in the first direction X is less than the width of the initial first stacking structure 3 in the first direction X, after etching the first portion 51, a portion of the top surface of the initial first stacking structure 3 is exposed. The exposed initial first stacking structure 3 is etched so that the width of the initial first stacking structure 3 facing the first portion 51 in the first direction X in the first direction X is less than the width of the remaining portion of the initial first stacking structure 3 in the first direction X.

[0118] In some embodiments, the width dimension of the second portion 52 in the first direction X is smaller than the width dimension of the second stacking structure 2 in the first direction X. After etching the first portion 51, a portion of the top surface of the initial first stacking structure 3 is also exposed, so that after etching the exposed initial first stacking structure 3, the width dimension of the initial first stacking structure 3 directly facing the first portion 51 along the first direction X in the first direction X is smaller than the width dimension of the remaining portion of the initial first stacking structure 3 in the first direction X. Among them, the initial first stacking structure 3 directly facing the first portion 51 along the first direction X is the second region, and the remaining portion of the initial first stacking structure 3 is the first region.

[0119] refer to Figure 23 to Figure 25 , forming a support layer 104 filled in the second through hole 16, the support layer 104 contacts the two opposite side walls of the second region, and contacts the part of the side wall of the first region adjacent to the second region. The second through hole 16 exposes the side wall of the first semiconductor layer 102 and the side wall of the sacrificial layer 110, so the support layer 104 formed in the second through hole 16 contacts the side wall of the first semiconductor layer 102 and the side wall of the sacrificial layer 110. Since the width dimension of the second region along the first direction X is smaller than the width dimension of the first region along the first direction X, the side wall of part of the first region is not connected to the second region, and is thus exposed to the outside. The formed support layer 104 also covers the side wall of the part of the first region exposed to the outside.

[0120] In some embodiments, the method of forming the support layer 104 filled in the second through hole 16 includes: sequentially filling the first support layer 121, the second support layer 122 and the third support layer 123 in the second through hole 16, the material of the second support layer 122 is different from the materials of the first support layer 121 and the third support layer 123, the upper surface of the first support layer 121 is flush with the upper surface of the initial first stacked structure 3, and the upper surface of the second support layer 122 is in contact with the lower surface of the first dielectric layer 22. It can be understood that the isolation layer 20 includes a first sub-isolation layer 21, a first dielectric layer 22 and a second sub-isolation layer 23, the material of the first sub-isolation layer 21 is different from the material of the first dielectric layer 22, and the material of the second sub-isolation layer 23 is different from the material of the first dielectric layer 22. That is, the material of the second portion 52 includes the material of the first sub-isolation layer 21, the material of the first dielectric layer 22 and the material of the second sub-isolation layer 23. The support layer 104 filled in the second through hole 16 is also in contact with the side wall of the second portion 52 , that is, the support layer 104 is also in contact with the first sub-isolation layer 21 , the first dielectric layer 22 and the second sub-isolation layer 23 .

[0121] The upper surface of the first supporting layer 121 is set flush with the upper surface of the first stacking structure 1, and the upper surface of the second supporting layer 122 is in contact with the lower surface of the first dielectric layer 22. In other words, the first supporting layer 121 is directly opposite to the initial first stacking structure 3 along the first direction X, the second supporting layer 122 is directly opposite to the first sub-isolating layer 21 along the first direction X, and the third supporting layer 123 is directly opposite to the first dielectric layer 22 and the second sub-isolating layer 23 along the first direction X.

[0122] In some embodiments, the material of the second support layer 122 may be the same as that of the first sub-isolation layer 21, so that the bonding degree between the second support layer 122 and the first sub-isolation layer 21 is high, and the stability of the support layer 104 is improved. In a specific example, the material of the first support layer 121 may be silicon nitride, the material of the second support layer 122 may be silicon oxide, and the material of the third support layer 123 may be silicon nitride. The material of the first sub-isolation layer 21 may be silicon oxide, the material of the first dielectric layer 22 may be silicon nitride, and the material of the second sub-isolation layer 23 may be silicon oxide.

[0123] Fig.28 Fig. 27 Schematic diagram of the cross-sectional structure along the cc' direction, Fig.29 for Fig. 27 Schematic diagram of the cross-sectional structure along the dd' direction.

[0124] refer to Figure 27 to Figure 29After forming the support layer 104, the sacrificial layer 110 is removed, and a first groove 17 is formed at the location of the sacrificial layer 110. The first groove 17 exposes the bottom surface of the first semiconductor layer 102 facing the substrate 101 and the sidewall of the support layer 104. The first groove 17 extends along the second direction Y. In some embodiments, the sacrificial layer 110 can be removed by either a wet etching process or a dry etching process.

[0125] refer to Fig.26 Before removing the sacrificial layer 110, the trench isolation structure 120 between the second stacked structures 2 adjacent to each other along the first direction X can be removed, the trench isolation structure 120 between the adjacent sacrificial layers 110 can be removed, and the trench isolation structure 120 between the adjacent first semiconductor layers 102 can be removed to expose the sidewalls of the sacrificial layer 110. The sidewalls of the sacrificial layer 110 are then etched to remove the sacrificial layer 110 by utilizing the etching selectivity between the sacrificial layer 110 and the first semiconductor layer 102 to form a first groove 17.

[0126] Fig.31 for Fig.30 Schematic diagram of the cross-sectional structure along the cc' direction, Fig.32 for Fig.30 Schematic diagram of the cross-sectional structure along the dd' direction.

[0127] refer to Figure 30 to Figure 32 , forming a plurality of bit lines 103 arranged at intervals along the first direction X, wherein each bit line 103 fills a first groove 17, and the bit line 103 is in electrical contact with the first semiconductor layer 102. In some embodiments, a deposition process may be used in each first groove 17. In some embodiments, the material of the bit line 103 may be metal, and thus there is no need to dope the substrate 101 that is directly opposite to the first semiconductor layer 102 in the vertical direction to convert part of the substrate 101 into a conductive bit line 103. Since there is no need to dope the substrate 101 to form the bit line 103, the problem of the intermittent morphology of the bit line 103 formed by doping due to the difficulty in controlling the accuracy of the doping process can be avoided. The process of forming the bit line 103 in the first groove 17 by using a deposition process is easier to control, so that the morphology of the formed bit line 103 can be the same as the morphology of the first groove 17, and a continuous bit line 103 can be formed, thereby improving the electrical performance of the bit line 103, and thus improving the electrical performance of the semiconductor structure.

[0128] In some embodiments, the material of the bit line 103 includes, but is not limited to, any one of titanium, tantalum, ruthenium, molybdenum, aluminum, tungsten, silver, or copper.

[0129] refer to Fig.33After forming the bit line 103, the method further includes: removing the first dielectric layer 22 to expose a portion of the side wall of the second semiconductor layer 105; forming a word line 107, the word line 107 extending along the first direction X, and the word line 107 surrounds the side wall of each second semiconductor layer 105 in the plurality of second semiconductor layers 105 arranged at intervals along the first direction X.

[0130] In some embodiments, the second sub-isolation layer 23, the trench isolation structure 120 and the third support layer 123 located between two adjacent rows of the second stacked structures 2 can also be removed to expose the side walls of the third semiconductor layer 106 and the second semiconductor layer 105 in the second direction Y, so that the subsequently formed word line 107 can surround the entire side wall of the second semiconductor layer 105, thereby increasing the contact area between the word line 107 and the second semiconductor layer 105 and increasing the length of the channel.

[0131] It is not difficult to find that before the previous step of removing the sacrificial layer 110, the trench isolation structure 120 located between the adjacent second stacked structures 2 along the second direction Y is removed, the trench isolation structure 120 located between the adjacent sacrificial layers 110 is removed, and the trench isolation structure 120 located between the adjacent first semiconductor layers 102 is removed. In order to form a word line 107 extending along the first direction X, a filling layer can be formed between the sacrificial layer 110, the first sub-semiconductor layer and the first sub-isolation layer 21 adjacent to each other along the first direction X. The sidewalls of the filling layer are in contact with the sidewalls of the first supporting layer 121 and the second supporting layer 122. The surface of the filling layer away from the substrate 101 is flush with the surface of the first sub-isolation layer 21 away from the substrate 101. The filling layer is used to provide support for the formed word line 107 so that the formed word line 107 can extend along the first direction X.

[0132] In some embodiments, a deposition process may be used to form the filling layer. The deposition process may be an atomic layer deposition process or a chemical vapor deposition process.

[0133] In some embodiments, the filling layer may include a first filling layer and a second filling layer stacked in sequence in a direction away from the surface of the substrate 101. The material of the first filling layer may be the same as the material of the first supporting layer 121, and the surface of the first filling layer away from the substrate 101 is flush with the surface of the first supporting layer 121 away from the substrate 101. The material of the second filling layer may be the same as the material of the second supporting layer 122, and the surface of the second filling layer away from the substrate 101 is flush with the surface of the second supporting layer 122 away from the substrate 101. In this way, the bonding degree between the first filling layer and the first supporting layer 121 is high, and the bonding degree between the second filling layer and the second supporting layer 122 is high, which improves the stability of the formed first filling layer and the second filling layer, and thus can play a better supporting role for the word line 107.

[0134] In some embodiments, the material of the first filling layer and the material of the first supporting layer 121 may both be silicon nitride, and the material of the second filling layer and the material of the second supporting layer 122 may both be silicon nitride.

[0135] After the filling layer is formed, a word line 107 is formed on the exposed sidewall of the second semiconductor layer 105 . The formed word line 107 is located on the top surface of the filling layer and extends along the first direction X.

[0136] In some embodiments, a deposition process may be used to form the initial word line 107 on the sidewall of the second semiconductor layer 105, the top surface of the filling layer, the top surface of the first sub-isolation layer 21 between two adjacent rows of second stacked structures 2 along the second direction Y, and the top surface of the second support layer 122 between two adjacent rows of second stacked structures 2 along the second direction Y. In some embodiments, the material of the initial word line 107 may be a conductive material, for example, a metal material, including but not limited to at least one of titanium, tantalum, ruthenium, molybdenum, aluminum, tungsten, silver, or copper.

[0137] Next, the initial word line 107 is patterned, including: forming a fourth mask layer covering the surface of the initial word line 107, and forming a fourth opening in the fourth mask layer by using either the SADP process or the SAQP process, wherein the fourth opening exposes a portion of the surface of the initial word line 107, and the fourth opening is directly opposite to the gap between two adjacent rows of second stacked structures 2 along the second direction Y. In this way, after the initial word line 107 is subsequently etched along the fourth opening, the formed multiple word lines 107 are arranged at intervals along the second direction Y.

[0138] The initial word line 107 is etched along the fourth opening to form a plurality of word lines 107 arranged at intervals along the second direction Y, and each word line 107 extends along the first direction X, and each word line 107 surrounds the sidewall of each second semiconductor layer 105 in the plurality of second semiconductor layers 105 arranged at intervals along the first direction X.

[0139] refer to Figure 3 After forming the word line 107, an isolation structure 109 is formed, which covers the surface of the word line 107, covers the top surface of the first sub-isolation layer 21 between two rows of second stacked structures 2 adjacent to each other along the second direction Y, and covers the surface of the second support layer 122 between two rows of second stacked structures 2 adjacent to each other along the second direction Y. The isolation structure 109 is also located between adjacent second stacked structures 2, and serves to isolate the adjacent second stacked structures 2. The top surface of the isolation structure 109 is flush with the top surface of the second stacked structure 2, exposing the top surface of the third semiconductor layer 106.

[0140] In some embodiments, a deposition process, such as an atomic layer deposition process, may be used to form the isolation structure 109. In some embodiments, the material of the isolation structure 109 may be silicon nitride.

[0141] refer to Figure 6 In some embodiments, after forming the word line 107, a capacitor structure 108 may be formed on the top surface of the third semiconductor layer 106, and the capacitor structure 108 is located on the top surface of the third semiconductor layer 106. In some embodiments, the capacitor structure 108 may include a first electrode layer, a first dielectric located on the sidewall of the first electrode layer, and a second electrode layer located on the sidewall of the first dielectric layer.

[0142] In some embodiments, the material of the first electrode layer may be a conductive material, for example, titanium nitride. In some embodiments, the material of the first electrode layer may also be a metal material, for example, at least one of titanium, tantalum, ruthenium, molybdenum, aluminum, tungsten, silver, or copper. In some embodiments, the material of the second electrode layer may be a conductive material, for example, titanium nitride. In some embodiments, the material of the second electrode layer may also be a metal material, for example, at least one of titanium, tantalum, ruthenium, molybdenum, aluminum, tungsten, silver, or copper. In some embodiments, the material of the first dielectric layer may be any one of silicon nitride, silicon oxynitride, or silicon oxide.

[0143] In the method for preparing the semiconductor structure provided in the above embodiment, a sacrificial layer 110 is used as a placeholder layer. After the first semiconductor layer 102 is formed, the sacrificial layer 110 is removed, and then a bit line 103 is formed at the position where the sacrificial layer 110 was originally located, thereby avoiding the formation of the bit line 103 by doping the substrate 101, thereby improving the problem of poor morphology of the formed bit line 103 due to the difficulty in controlling the doping accuracy of the substrate 101 corresponding to the bottom of the first semiconductor layer 102.

[0144] Those skilled in the art can understand that the above-mentioned embodiments are specific examples for realizing the present disclosure, and in practical applications, various changes can be made to them in form and details without departing from the spirit and scope of the present disclosure. Any person skilled in the art can make their own changes and modifications without departing from the spirit and scope of the present disclosure, so the protection scope of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that: include: substrate; A plurality of first stacked structures located on the substrate, the first stacked structures are arranged at intervals along a first direction, the first stacked structures include bit lines and a first semiconductor layer stacked in sequence along a vertical direction, the bit lines are in electrical contact with the first semiconductor layer; The supporting layer is located on the substrate and contacts at least a portion of the sidewall of the first semiconductor layer.

2. The semiconductor structure according to claim 1, characterized in that: The semiconductor structure further includes: a second stacked structure located on the first stacked structure, each of the first stacked structures includes a plurality of second stacked structures arranged at intervals along a second direction, the second stacked structure includes a second semiconductor layer and a third semiconductor layer sequentially stacked in a vertical direction, the size of the first semiconductor layer in the first direction is larger than the size of the third semiconductor layer in the first direction, the second semiconductor layer includes a first sublayer, a second sublayer and a third sublayer, the size of the second sublayer in the second direction is smaller than the sizes of the first sublayer and the third sublayer in the second direction; the semiconductor structure further includes: A word line extending along the first direction, and the word line surrounds the side wall of the second sublayer of each second semiconductor layer in a plurality of second stacked structures arranged at intervals along the first direction, and the size of the word line in the second direction is less than or equal to the size of the second stacked structure in the second direction.

3. The semiconductor structure according to claim 2, characterized in that: The first semiconductor layer and the bit line both extend along the second direction, and their projections on the substrate overlap. The first stacking structure includes a first segment and a second segment adjacent to each other in sequence along the second direction, the first segment contacts the second semiconductor layer, the second segment is adjacent to the first segments arranged at intervals along the second direction, and the size of the first segment in the first direction is larger than the size of the second segment in the first direction; the supporting layer contacts two opposite side walls of the second segment, and contacts a portion of the side wall of the first segment adjacent to the second segment, and the supporting layer is also located between the second stacking structures arranged along the second direction.

4. The semiconductor structure according to claim 2 or 3, characterized in that: The supporting layer includes a first supporting layer, a second supporting layer and a third supporting layer stacked in sequence along a vertical direction, the material of the second supporting layer is different from the materials of the first supporting layer and the third supporting layer, the upper surface of the first supporting layer is flush with the upper surface of the first stacking structure, and the upper surface of the second supporting layer is flush with the upper surface of the first sub-layer.

5. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate; forming a plurality of initial first stacked structures spaced apart along a first direction on the substrate, wherein the initial first stacked structures include a sacrificial layer and a first semiconductor layer sequentially stacked along a vertical direction; forming a support layer on the substrate, wherein the support layer is located on a portion of the sidewall of the initial first stacked structure and at least contacts the first semiconductor layer; Removing the sacrificial layer to form a first groove, wherein the first groove exposes the bottom surface of the first semiconductor layer; A plurality of bit lines are formed and arranged at intervals along the first direction. Each bit line fills a first groove and is in electrical contact with the first semiconductor layer.

6. The method for preparing a semiconductor structure according to claim 5, characterized in that: Also includes: Forming a second stacked structure arranged in an array on the surface of the initial first stacked structure, wherein the second stacked structure arranged in an array is arranged at intervals along the first direction and the second direction, and the second stacked structure comprises a second semiconductor layer and a third semiconductor layer sequentially stacked in a vertical direction, and the second semiconductor layer is in electrical contact with the first semiconductor layer; A word line is formed, the word line extending along the first direction, and the word line surrounds a side wall of each of the second semiconductor layers in a plurality of second semiconductor layers arranged at intervals along the first direction.

7. The method for preparing a semiconductor structure according to claim 5 or 6, characterized in that: The method of forming the initial first stacking structure comprises: An initial sacrificial layer and an initial first semiconductor layer are formed on the substrate and are stacked in sequence along a direction away from the substrate; the initial sacrificial layer and the initial first semiconductor layer are etched to form a plurality of sacrificial layers arranged at intervals along the first direction and a plurality of first semiconductor layers arranged at intervals along the first direction, one of the first semiconductor layers is located on the top surface of one of the sacrificial layers to form the initial first stacked structure, and each of the first semiconductor layers and each of the sacrificial layers extends along the second direction.

8. The method for preparing a semiconductor structure according to claim 7, characterized in that: Also includes: A second stacked structure arranged in an array is formed on the surface of the initial first semiconductor layer, and a method for forming the second stacked structure includes: forming an isolation layer on the top surface of the initial first semiconductor layer; Etching the isolation layer to form a plurality of first through holes arranged in an array in the isolation layer, wherein the plurality of first through holes are arranged at intervals along the first direction and the second direction, and the first through holes expose a portion of the top surface of the initial first semiconductor layer; forming a second semiconductor layer filled in a portion of the first through hole, wherein the second semiconductor layer is located on a top surface of the initial first semiconductor layer; A third semiconductor layer is formed, where the third semiconductor layer is located on the top surface of the second semiconductor layer and together with the second semiconductor layer constitutes the second stacking structure.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that: A method of arranging a plurality of second stacking structures spaced apart along the second direction into a row to form the initial first stacking structure includes: Part of the isolation layer and part of the initial first stacking structure located between two adjacent columns of the second stacking structures are etched until the substrate is exposed to form a first groove and a plurality of the initial first stacking structures isolated by the first groove, wherein the first groove extends along the second direction, and the size of the second stacking structure in the first direction is smaller than the size of the initial first stacking structure in the first direction.

10. The method for preparing a semiconductor structure according to claim 9, characterized in that: The second stacked structures arranged at intervals along the first direction are arranged in a row, and the isolation layer located between two adjacent rows of the second stacked structures includes a first portion and a second portion arranged alternately along the first direction, the second portion is directly opposite to the second stacked structure, and the size of the second portion in the first direction is less than or equal to the size of the second stacked structure in the first direction. The method for forming the support layer includes: The first portion is etched until a portion of the surface of the initial first stacking structure is exposed; the exposed initial first stacking structure is etched until a portion of the substrate surface is exposed to form a second through hole; the remaining initial first stacking structure forms a first region and a second region which are adjacent to each other in sequence along the second direction, wherein the second region is opposite to the gap between two second stacking structures adjacent to each other along the second direction, the first region is opposite to the second stacking structure, and a size of the first region in the first direction is larger than a size of the second region in the first direction; the supporting layer filled in the second through hole is formed, the supporting layer is in contact with two opposite side walls of the second region, and is in contact with a portion of the side walls of the first region adjacent to the second region.

11. The method for preparing a semiconductor structure according to claim 10, characterized in that: The isolation layer comprises: a first sub-isolation layer, a first dielectric layer and a second sub-isolation layer stacked in sequence along a direction perpendicular to the surface of the substrate, the first dielectric layer, the first sub-isolation layer and the second sub-isolation layer all surround the second semiconductor layer, and the material of the first dielectric layer is different from the materials of the first sub-isolation layer and the second sub-isolation layer; etching the isolation layer to form a plurality of first through holes arranged in an array in the isolation layer, comprising: etching the isolation layer to form a plurality of initial first through holes arranged in an array in the isolation layer; etching the first sub-isolation layer and the second sub-isolation layer laterally along the initial first through holes to form a first through hole, wherein the aperture of the first through hole corresponding to the first sub-isolation layer and the second sub-isolation layer is larger than the aperture of the first through hole corresponding to the first dielectric layer; After forming the bit line, the method further comprises: removing the first dielectric layer to expose a portion of the sidewall of the second semiconductor layer; A word line is formed, the word line extending along the first direction, and the word line surrounds a side wall of each of the second semiconductor layers in a plurality of second semiconductor layers arranged at intervals along the first direction.

12. The method for preparing a semiconductor structure according to claim 11, characterized in that: The method of forming the supporting layer filled in the second through hole includes: The first supporting layer, the second supporting layer and the third supporting layer are filled in sequence in the second through hole, the material of the second supporting layer is different from the materials of the first supporting layer and the third supporting layer, the upper surface of the first supporting layer is flush with the upper surface of the initial first stacking structure, and the upper surface of the second supporting layer is in contact with the lower surface of the first dielectric layer.

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