Volatile memristor based on CMOS (Complementary Metal-Oxide-Semiconductor Transistor) process and manufacturing method thereof

Abstract

The invention discloses a volatile memristor based on a CMOS (Complementary Metal Oxide Semiconductor) process. The volatile memristor comprises a P-type substrate, a first N-Well region, a first P-Well region and a second N-Well region, an N + injection region, a polysilicon gate and a P + injection region which are connected with an electrode are arranged in each of the first N-Well region and the second N-Well region; two polysilicon gates and a P + injection region are arranged in the first P-Well region and are electrically connected with each other; and the two potential floating N + injection regions are respectively bridged at the joint of the first N-Well region, the second N-Well region and the first P-Well region. The device utilizes a positive feedback path to generate a resistance change effect, can continuously change between a low resistance state and a high resistance state, and can be applied to large-scale on-chip integrated neuromorphic calculation. Meanwhile, the device is manufactured based on a commercial CMOS process, does not need an additional mask, and has the advantages of simple structure, low manufacturing cost and high integration level.

Description

Technical Field

[0001] The present invention belongs to the technical field of memristors, and in particular relates to a volatile memristor based on a CMOS process and a manufacturing method thereof. Background Art

[0002] In recent years, with the rapid development of artificial intelligence and the Internet of Things, the demand for low-power, high-speed, and high-parallel computing resources in the information age has continued to increase. Since the data transfer between the central processing unit and the memory generates a lot of energy consumption, the storage and processing of massive data poses severe challenges to the computing system of the traditional von Neumann system. The human brain has a unique way of processing information, which transmits information through neurons and synaptic connections. The brain-like neuromorphic computing architecture has a high degree of parallelism and an event-driven computing mode, and has great application prospects in the field of artificial intelligence.

[0003] Neurons are important processing units in neuromorphic computing systems. Among various emerging devices, threshold-shift memristors have become important candidate devices for building artificial neurons due to their rich dynamic characteristics and volatile storage characteristics. Volatile memristors can simulate the volatile behavior of neuronal potentials through the volatility of internal conductance, and have been widely used in neuromorphic computing. However, existing volatile memristors such as threshold-shift memristors often have poor stability due to the breakage of internal metal wires and the randomness of formation. In addition, memristors designed based on nanomaterials are difficult to be fully compatible with standard CMOS processes, and the preparation process is complex and costly, making it impossible to achieve large-scale on-chip integration. Summary of the invention

[0004] In order to solve the above technical bottlenecks, the present invention provides a volatile memristor with a simple structure and based on CMOS process and a manufacturing method thereof, which can reduce manufacturing costs and improve device stability, and is expected to solve the problems of high array complexity and difficulty in large-scale on-chip integration in brain-like neuromorphic computing systems.

[0005] In order to achieve the above-mentioned purpose, the technical solution of the present invention is: a volatile memristor based on CMOS technology, characterized in that: it comprises a P-type substrate, on which a first N-well (102), a P-well (103), and a second N-well (104) are arranged in sequence from left to right; the right edge of the first N-well (102) is connected to the left edge of the P-well (103), and the right edge of the P-well (103) is connected to the left edge of the second N-well (104); The first N-well (102) is provided with a first N+ injection region (105), a first polysilicon gate (207), a first P+ injection region (109), and a second N+ injection region (106) in sequence from left to right; the P-well (103) is provided with a second N+ injection region (106), a second polysilicon gate (208), a second P+ injection region (110), a third polysilicon gate (209), and a third N+ injection region (107) in sequence from left to right; the second N-well (104) is provided with a third N+ injection region (107), a third P+ injection region (111), a fourth polysilicon gate (210), and a fourth N+ injection region (108) in sequence from left to right; the second N+ injection region (106) is bridged between the first N-well (102) and the P-well (103), and the third N+ injection region (107) is bridged between the P-well (103) and the second N-well (104).

[0006] A first shallow trench isolation region (201) is provided on the left side of the first N+ injection region (105), a second shallow trench isolation region (202) is provided between the first polysilicon gate (207) and the first P+ injection region (109), a third shallow trench isolation region (203) is provided between the first P+ injection region (109) and the second N+ injection region (106), a fourth shallow trench isolation region (204) is provided between the third N+ injection region (107) and the third P+ injection region (111), and the third P+ injection region (112) is provided between the third N+ injection region (107) and the third P+ injection region (113). A fifth shallow trench isolation region (205) is provided between the region (111) and the fourth polysilicon gate (210), and a sixth shallow trench isolation region (206) is provided on the right side of the fourth N+ injection region (108); the edges of the first to sixth shallow trench isolation regions are all connected to the injection region or the edge of the polysilicon gate; the left edge of the first shallow trench isolation region (201) is flush with the left edge of the P-type substrate (101), and the right edge of the sixth shallow trench isolation region (206) is flush with the right edge of the P-type substrate (101).

[0007] The first N+ implantation region (105), the first polysilicon gate (207), and the first P+ implantation region (109) are connected together through metal to serve as a device anode; The third P+ injection region (111), the fourth polysilicon gate (210), and the fourth N+ injection region (108) are connected together through metal to serve as a device cathode; The second polysilicon gate (208), the second P+ injection region (110), and the third polysilicon gate (209) are connected together through metal and share a common potential.

[0008] Furthermore, when a pulse signal is applied to the anode of the device, the second N+ injection region (106), the second polysilicon gate (208), the P well (103), and the second P+ injection region (110) constitute a first gate-controlled diode D1, the second P+ injection region (110), the third polysilicon gate (209), the P well (103), and the third N+ injection region (107) constitute a second gate-controlled diode D2, the first N+ injection region (105), the first N well (102), the P well (103), the second N well (104), and the fourth N+ injection region (108) constitute a parasitic NPN transistor, and the first P+ injection region (109), the first N well (102), and the P well (103) constitute a parasitic PNP1 transistor; The collector of the PNP1 transistor is connected to the base of the NPN transistor via a parasitic resistor RP of the P well (103), and the base of the PNP1 transistor is connected to the collector of the NPN transistor via a parasitic resistor R of the first N well (102). N1 connected, that is, the PNP1 transistor and the NPN transistor form a positive feedback path; When the pulse signal amplitude applied by the anode does not reach the device turn-on threshold, the first gate diode D1 is in a reverse bias state, the device is in a high resistance state, and the leakage current is small; when the pulse signal amplitude is greater than the device turn-on threshold, the first gate diode D1 undergoes avalanche breakdown, and the current flows through the parasitic resistance R of the P well (103). P This causes the potential of the P well (103) to rise and causes the NPN transistor and the PNP1 transistor to be turned on, a positive feedback path is formed, a negative differential resistance effect is generated, and the device is transformed into a low resistance state; in the same time domain, the changes in voltage and current are continuous, and the device can achieve a continuously variable resistance value; when the pulse excitation disappears, the first gate diode D1 returns to a reverse bias state, and the device returns to a high resistance state, so the device has a volatile memristive characteristic under a pulse excitation signal.

[0009] When a pulse signal is applied to the cathode of the device, the fourth N+ injection region (108), the second N well (104), the P well (103), the first N well (102), and the first N+ injection region (105) form a parasitic NPN transistor, and the third P+ injection region (111), the second N well (104), and the P well (103) form a parasitic PNP2 transistor; The collector of the PNP2 transistor and the base of the NPN transistor are connected via a parasitic resistor R of the P well (103). P The base of the PNP2 transistor and the collector of the NPN transistor are connected via a parasitic resistor R of the second N well (104). N2 connected, that is, the PNP2 transistor and the NPN transistor form a positive feedback path; When the pulse signal amplitude applied to the cathode does not reach the device turn-on threshold, the second gate diode D2 is in a reverse bias state, the device is in a high resistance state, and the leakage current is small; when the pulse signal amplitude is greater than the device turn-on threshold, the second gate diode D2 undergoes avalanche breakdown, and the current flows through the parasitic resistance R of the P well (103). P This causes the potential of the P well (103) to rise and causes the NPN transistor and the PNP2 transistor to be turned on, a positive feedback path is formed, a negative differential resistance effect is generated, and the device is transformed into a low resistance state; in the same time domain, the changes in voltage and current are continuous, and the device can achieve a continuously variable resistance value; when the pulse excitation disappears, the second gate diode D2 returns to a reverse bias state, and the device returns to a high resistance state, so the device has a volatile memristive characteristic under a pulse excitation signal.

[0010] A method for manufacturing a volatile memristor based on CMOS technology, comprising the following steps: Step 1: A layer of silicon dioxide film is grown on a P-type substrate using furnace thermal oxidation to relieve the stress on the substrate caused by the silicon nitride formed in subsequent steps; a layer of silicon nitride is deposited using chemical vapor deposition (CVD) technology as a stop layer for subsequent chemical mechanical polishing (CMP).

[0011] Step 2: photoresist coating, exposure and development, define the first to sixth shallow trench isolation areas, use Ar and CF4 to form a plasma slurry to remove the silicon nitride and silicon dioxide layers not covered by the photoresist, use O2 and HBr to form a plasma slurry to remove the area not covered by the photoresist, the etching depth is 0.45~0.55μm, and the angle of the shallow trench sidewall is 75°~80°; remove the photoresist by dry etching and wet etching, use CVD to deposit a layer of silicon dioxide with a thickness of about 0.5~1.0μm, and then use CMP to remove the surface oxide layer until the silicon nitride layer, and then use hot phosphoric acid (H3PO4) wet etching to remove silicon nitride at a temperature of about 180°C.

[0012] Step 3: Transfer the patterns on the first N-well and second N-well masks to the wafer through micro-development technology to form a photoresist pattern for the N-well, and retain the photoresist in the non-N-well area; inject high-energy phosphorus ions to form a local N-well and remove the photoresist.

[0013] Step 4: Transfer the pattern on the P-well mask to the wafer through micro-development technology to form a P-well photoresist pattern, and retain the photoresist in the non-P-well area; inject high-energy boron ions to form a local P-well, and remove the photoresist; Step 5: Anneal the N-well and P-well by heating and annealing in a H2 environment using RTA to activate the impurity ions in the N-well and P-well, repair the silicon substrate lattice damage caused by ion implantation, and further cause the diffusion of impurities; Step 6: Grow a thick gate oxide layer. Grow a thick layer of silicon dioxide using furnace thermal oxidation at a temperature of 850°C. Deposit a layer of polysilicon with a thickness of about 150nm to 300nm using CVD, form a polysilicon gate through photolithography and etching, and remove the photoresist.

[0014] Step seven: grow a thin oxide layer on the surface of polysilicon to buffer and isolate the polysilicon and the silicon nitride formed in subsequent steps; photolithography forming, heavily doped arsenic ion implantation, to form the first to fourth N+ implantation areas; photolithography forming, heavily doped BF2+ ion implantation, to form the first to third P+ implantation areas; annealing to repair the crystal damage on the silicon surface caused by ion implantation and eliminate the migration of impurities in the implantation area.

[0015] Step 8: Connect the first N+ injection region (105), the first polysilicon gate (207), and the first P+ injection region (109) together as the anode of the device, connect the third P+ injection region (111), the fourth polysilicon gate (210), and the fourth N+ injection region (108) together as the cathode of the device, and connect the second polysilicon gate (208), the second P+ injection region (110), and the third polysilicon gate (209) together to share a potential.

[0016] The beneficial effects of the present invention are: 1. The memristor of the present invention uses the intermediate gate-controlled diodes D1 and D2 to achieve the transition between the high-resistance state and the low-resistance state. When the anode has a pulse signal greater than the turn-on threshold, D1 undergoes avalanche breakdown and quickly generates a coupling voltage drop in the P well, so that the parasitic NPN transistor is turned on and provides a base drive current for the parasitic PNP1 transistor. At the same time, it assists the rapid opening of the positive feedback loop of the device, and has the advantage of fast opening speed. At the same time, since the gate diode is in a reverse biased state in the high-resistance state, the overall leakage current of the device is small.

[0017] 2. The present invention uses the positive feedback path formed by the internal parasitic transistor to realize the negative differential resistance effect. Since there is no growth and breaking process of the conductive wire in the traditional oxide memristor, the device will not have the problem of poor stability caused by the randomness of the internal metal wire breaking and formation. Therefore, the stability of the device is higher.

[0018] 3. The process of the present invention is simple and easy to operate. The volatile memristor based on the CMOS process does not violate the layout design rules, nor does it use layers other than the CMOS process. It can achieve volatile memristor characteristics and meet the needs of artificial neuron devices in the fields of artificial perception systems and neuromorphic computing. At the same time, manufacturing based on the CMOS process is easy to achieve large-scale integration and production, with lower manufacturing costs and broad application prospects. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required to be used in the embodiments are briefly introduced below.

[0020] Figure 1 is a cross-sectional view of a volatile memristor based on CMOS technology in an embodiment of the present invention; Figure 2 is an equivalent circuit schematic diagram of a volatile memristor based on CMOS technology in an embodiment of the present invention; Figure 3 is a top view of a volatile memristor based on CMOS technology in an embodiment of the present invention; Figure 4 : is an IV curve of a volatile memristor based on CMOS process under 20V square wave pulse excitation in an embodiment of the present invention; The figure includes: a P-type substrate (101), a first N-well (102), a P-well (103), a second N-well (104), a first N+ injection region (105), a second N+ injection region (106), a third N+ injection region (107), a fourth N+ injection region (108), a first P+ injection region (109), a second P+ injection region (110), a third P+ injection region (111), a first shallow trench isolation region (201), a second shallow trench isolation region (202), a third shallow trench isolation region (203), a fourth shallow trench isolation region (204), a fifth shallow trench isolation region (205), a sixth shallow trench isolation region (206), a first multi-layer A crystalline silicon gate (207), a second polysilicon gate (208), a third polysilicon gate (209), a fourth polysilicon gate (210), a first metal layer (211), a second metal layer (212), a third metal layer (213), a fourth metal layer (214), a fifth metal layer (215), a sixth metal layer (216), a seventh metal layer (217), an eighth metal layer (218), a ninth metal layer (219), a tenth metal layer (301), an eleventh metal layer (303), a twelfth metal layer (305), a first metal through hole (302), a second metal through hole (304), and a third metal through hole (306). DETAILED DESCRIPTION

[0021] The present invention is described in detail below with reference to the accompanying drawings and specific embodiments.

[0022] The purpose of the present invention is to provide a volatile memristor based on CMOS technology, which provides a device prototype and reference scheme for volatile artificial neurons in neuromorphic computing. The device is simple to manufacture and can be realized using existing CMOS technology without requiring additional process modifications, and is easy to achieve large-scale integration.

[0023] In order to make the above-mentioned purposes, features and advantages of the present invention more clear, the present invention is briefly introduced below in conjunction with the accompanying drawings and specific implementation methods. Obviously, the described embodiments are only part of the present invention, and for ordinary technicians in this field, other embodiments obtained without creative work belong to the protection scope of the present invention.

[0024] like Figure 1 and Figure 3 As shown, the present invention provides a volatile memristor based on CMOS technology, comprising a P-type substrate, on which a first N-well (102), a P-well (103), and a second N-well (104) are arranged in sequence from left to right; the right edge of the first N-well (102) is connected to the left edge of the P-well (103), and the right edge of the P-well (103) is connected to the left edge of the second N-well (104); The first N-well (102) is provided with a first N+ injection region (105), a first polysilicon gate (207), a first P+ injection region (109), and a second N+ injection region (106) in sequence from left to right; the P-well (103) is provided with a second N+ injection region (106), a second polysilicon gate (208), a second P+ injection region (110), a third polysilicon gate (209), and a third N+ injection region (107) in sequence from left to right; the second N-well (104) is provided with a third N+ injection region (107), a third P+ injection region (111), a fourth polysilicon gate (210), and a fourth N+ injection region (108) in sequence from left to right; the second N+ injection region (106) is bridged between the first N-well (102) and the P-well (103), and the third N+ injection region (107) is bridged between the P-well (103) and the second N-well (104).

[0025] A first shallow trench isolation region (201) is provided on the left side of the first N+ injection region (105), a second shallow trench isolation region (202) is provided between the first polysilicon gate (207) and the first P+ injection region (109), a third shallow trench isolation region (203) is provided between the first P+ injection region (109) and the second N+ injection region (106), a fourth shallow trench isolation region (204) is provided between the third N+ injection region (107) and the third P+ injection region (111), and the third P+ injection region (112) is provided between the third N+ injection region (107) and the third P+ injection region (113). A fifth shallow trench isolation region (205) is provided between the region (111) and the fourth polysilicon gate (210), and a sixth shallow trench isolation region (206) is provided on the right side of the fourth N+ injection region (108); the edges of the first to sixth shallow trench isolation regions are all connected to the injection region or the edge of the polysilicon gate; the left edge of the first shallow trench isolation region (201) is flush with the left edge of the P-type substrate (101), and the right edge of the sixth shallow trench isolation region (206) is flush with the right edge of the P-type substrate (101).

[0026] The first N+ injection region (105) is connected to the first metal layer (211), the first polysilicon gate (207) is connected to the second metal layer (212), the first P+ injection region (109) is connected to the third metal layer (213), a metal through hole (302) is provided on the tenth metal layer (301), and the first metal layer (211), the second metal layer (212), and the third metal layer (213) are all connected to the tenth metal layer (301) through the metal through hole (302), and serve as the anode of the device; The third P+ injection region (111) is connected to the seventh metal layer (217), the fourth polysilicon gate (210) is connected to the eighth metal layer (218), the fourth N+ injection region (108) is connected to the ninth metal layer (219), a metal through hole (306) is provided on the twelfth metal layer (305), and the seventh metal layer (217), the eighth metal layer (218) and the ninth metal layer (219) are all connected to the twelfth metal layer (305) through the metal through hole (306), and serve as the cathode of the device; The second polysilicon gate (208) is connected to the fourth metal layer (214), the second P+ injection region (110) is connected to the fifth metal layer (215), the third polysilicon gate (209) is connected to the sixth metal layer (216), a metal through hole (304) is provided on the eleventh metal layer (303), and the fourth metal layer (214), the fifth metal layer (215), and the sixth metal layer (216) are all connected to the eleventh metal layer (303) through the metal through hole (304) and share a common potential.

[0027] Specifically, the cross-sectional view and the equivalent circuit schematic diagram of a volatile memristor based on CMOS technology in an embodiment of the present invention are respectively as follows: Figure 1 and Figure 2 As shown. The second N+ injection region (106), the second polysilicon gate (208), the P well (103), and the second P+ injection region (110) constitute a first gate-controlled diode D1; the second P+ injection region (110), the third polysilicon gate (209), the P well (103), and the third N+ injection region (107) constitute a second gate-controlled diode D2; the first N+ injection region (105), the first N well (102), the P well (103), the second N well (104), and the fourth N+ injection region (108) constitute a parasitic NPN transistor; the first P+ injection region (109), the first N well (102), and the P well (103) constitute a parasitic PNP1 transistor; The collector of the PNP1 transistor is connected to the base of the NPN transistor via a parasitic resistor RP of the P well (103), and the base of the PNP1 transistor is connected to the collector of the NPN transistor via a parasitic resistor R of the first N well (102). N1connected, that is, the PNP1 transistor and the NPN transistor form a positive feedback path; The fourth N+ injection region (108), the second N well (104), the P well (103), the first N well (102), and the first N+ injection region (105) constitute a parasitic NPN transistor, and the third P+ injection region (111), the second N well (104), and the P well (103) constitute a parasitic PNP2 transistor; The collector of the PNP2 transistor and the base of the NPN transistor are connected via a parasitic resistor R of the P well (103). P The base of the PNP2 transistor and the collector of the NPN transistor are connected via a parasitic resistor R of the second N well (104). N2 connected, that is, the PNP2 transistor and the NPN transistor form a positive feedback path; When the pulse signal amplitude applied by the anode does not reach the device turn-on threshold, the first gate diode D1 is in a reverse bias state, the device is in a high resistance state, and the leakage current is small; when the pulse signal amplitude is greater than the device turn-on threshold, the first gate diode D1 undergoes avalanche breakdown, and the current flows through the parasitic resistance R of the P well (103). P The potential of the P well (103) rises and the NPN transistor and the PNP1 transistor are turned on, a positive feedback path is formed, a negative differential resistance effect is generated, and the device is transformed into a low resistance state; the voltage and current change continuously in the same time domain, and the device can achieve a continuously variable resistance value; when the pulse excitation disappears, the first gate diode D1 returns to the reverse bias state, and the device returns to the high resistance state, so the device has a volatile memristive characteristic under the pulse excitation signal. When the amplitude of the pulse signal applied to the cathode does not reach the device turn-on threshold, the second gate diode D2 is in a reverse bias state, the device is in a high resistance state, and the leakage current is small; when the pulse signal amplitude is greater than the device turn-on threshold, the second gate diode D2 undergoes avalanche breakdown, and the current passes through the parasitic resistance R of the P well (103). P This causes the potential of the P well (103) to rise and turns on the NPN transistor and the PNP2 transistor, forming a positive feedback path, generating a negative differential resistance effect, and the device is transformed into a low resistance state; the changes in voltage and current are continuous in the same time domain, and the device can achieve a continuously variable resistance value; when the pulse excitation disappears, the second gate diode D2 returns to the reverse bias state, and the device returns to the high resistance state. Therefore, the device has a volatile memristive characteristic under the pulse excitation signal. Figure 4As shown, square wave pulses of 20V and -20V are applied to the anode of the embodiment of the present invention, the rising and falling edges of the pulses are both 10ns, and the pulse width is 100ns. Under the excitation of a bipolar periodic pulse signal, the IV characteristic of the device is a symmetrical hysteresis loop. Under the same time domain conditions, the device exhibits two states of high resistance and low resistance, achieving a continuous change in resistance value, meeting the needs of artificial neuron devices in the fields of artificial perception systems, neuromorphic computing, etc.

[0028] The P-type substrate, N-well, P-well, N+ implantation region, P+ implantation region, polysilicon gate, shallow trench isolation region, metal via, and metal connection in the present invention can be realized by using existing standard CMOS manufacturing processes without the need for additional mask and process modification.

[0029] The present invention provides a method for manufacturing a volatile memristor based on a CMOS process, comprising the following steps: Step 1: A layer of silicon dioxide film is grown on the P-type substrate by thermal oxidation in a furnace tube to relieve the stress caused by the silicon nitride formed in the subsequent steps on the substrate; a layer of silicon nitride is deposited by chemical vapor deposition (CVD) technology as a stop layer for subsequent chemical mechanical polishing (CMP); Step 2: photoresist coating, exposure and development, defining the first to sixth shallow trench isolation areas, using Ar and CF4 to form a plasma slurry to remove the silicon nitride and silicon dioxide layers not covered by the photoresist, using O2 and HBr to form a plasma slurry to remove the area not covered by the photoresist, the etching depth is 0.45-0.55μm, and the angle of the shallow trench sidewall is 75°-80°; removing the photoresist by dry etching and wet etching, using CVD to deposit a layer of silicon dioxide with a thickness of about 0.5-1.0μm, and then using CMP to remove the surface oxide layer until the silicon nitride layer, and then using hot phosphoric acid (H3PO4) wet etching to remove silicon nitride, the temperature is about 180°C; Step 3: Transfer the patterns on the first N-well and the second N-well mask to the wafer through micro-development technology to form a photoresist pattern of the N-well, and retain the photoresist in the non-N-well area; inject high-energy phosphorus ions to form a local N-well, and remove the photoresist; Step 4: Transfer the pattern on the P-well mask to the wafer through micro-development technology to form a P-well photoresist pattern, and retain the photoresist in the non-P-well area; inject high-energy boron ions to form a local P-well, and remove the photoresist; Step 5: Anneal the N-well and P-well by heating and annealing in a H2 environment using RTA to activate the impurity ions in the N-well and P-well, repair the silicon substrate lattice damage caused by ion implantation, and further cause the diffusion of impurities; Step 6: Grow a thick gate oxide layer. Use furnace thermal oxidation to grow a thick layer of silicon dioxide at a temperature of 850°C. Use CVD to deposit a layer of polysilicon with a thickness of about 150nm to 300nm, form a polysilicon gate through photolithography and etching, and remove the photoresist; Step 7: growing a thin oxide layer on the surface of polysilicon to buffer and isolate the polysilicon and the silicon nitride formed in the subsequent steps; photolithography forming, heavily doped arsenic ion implantation, forming the first to fourth N+ implantation regions; photolithography forming, heavily doped BF2+ ion implantation, forming the first to third P+ implantation regions; annealing, repairing the crystal damage on the silicon surface caused by ion implantation, and eliminating the migration of impurities in the implantation region; Step 8: Connect the first N+ injection region (105), the first polysilicon gate (207), and the first P+ injection region (109) together as the anode of the device, connect the third P+ injection region (111), the fourth polysilicon gate (210), and the fourth N+ injection region (108) together as the cathode of the device, and connect the second polysilicon gate (208), the second P+ injection region (110), and the third polysilicon gate (209) together to share a potential.

[0030] The matters not described in detail in the present invention are all known technologies to those skilled in the art.

[0031] The embodiments of the present invention are described in detail above, but the present invention is not limited to the described embodiments. For those skilled in the art, various changes, modifications, substitutions and variations of these embodiments based on the prior art according to the concept of the present invention still fall within the protection scope of the present invention.

Claims

1. A volatile memristor based on CMOS technology, characterized in that: It comprises a P-type substrate, on which a first N-well (102), a P-well (103), and a second N-well (104) are arranged in sequence from left to right; the right edge of the first N-well (102) is connected to the left edge of the P-well (103), and the right edge of the P-well (103) is connected to the left edge of the second N-well (104); The first N-well (102) is provided with a first N+ injection region (105), a first polysilicon gate (207), a first P+ injection region (109), and a second N+ injection region (106) in sequence from left to right; the P-well (103) is provided with a second N+ injection region (106), a second polysilicon gate (208), a second P+ injection region (110), a third polysilicon gate (209), and a third N+ injection region (107) in sequence from left to right; the second N-well (104) is provided with a third N+ injection region (107), a third P+ injection region (111), a fourth polysilicon gate (210), and a fourth N+ injection region (108) in sequence from left to right; the second N+ injection region (106) is connected across the first N-well (102) and the P-well (103), and the third N+ injection region (107) is connected across the P-well (103) and the second N-well (104).

2. A volatile memristor based on CMOS technology according to claim 1, characterized in that: A first shallow trench isolation region (201) is provided on the left side of the first N+ injection region (105), a second shallow trench isolation region (202) is provided between the first polysilicon gate (207) and the first P+ injection region (109), a third shallow trench isolation region (203) is provided between the first P+ injection region (109) and the second N+ injection region (106), a fourth shallow trench isolation region (204) is provided between the third N+ injection region (107) and the third P+ injection region (111), and the third P+ injection region (112) is provided between the third N+ injection region (107) and the third P+ injection region (113). A fifth shallow trench isolation region (205) is provided between the region (111) and the fourth polysilicon gate (210), and a sixth shallow trench isolation region (206) is provided on the right side of the fourth N+ injection region (108); the edges of the first to sixth shallow trench isolation regions are all connected to the injection region or the edge of the polysilicon gate; the left edge of the first shallow trench isolation region (201) is flush with the left edge of the P-type substrate (101), and the right edge of the sixth shallow trench isolation region (206) is flush with the right edge of the P-type substrate (101).

3. The volatile memristor based on CMOS technology according to claim 2, characterized in that: The first N+ implantation region (105), the first polysilicon gate (207), and the first P+ implantation region (109) are connected together through metal to serve as a device anode; The third P+ injection region (111), the fourth polysilicon gate (210), and the fourth N+ injection region (108) are connected together through metal to serve as a device cathode; The second polysilicon gate (208), the second P+ injection region (110), and the third polysilicon gate (209) are connected together through metal and share a common potential.

4. The volatile memristor based on CMOS technology according to claim 3, characterized in that: When a pulse signal is applied to the anode of the device, the second N+ injection region (106), the second polysilicon gate (208), the P well (103), and the second P+ injection region (110) form a first gate-controlled diode D1, the second P+ injection region (110), the third polysilicon gate (209), the P well (103), and the third N+ injection region (107) form a second gate-controlled diode D2, the first N+ injection region (105), the first N well (102), the P well (103), the second N well (104), and the fourth N+ injection region (108) form a parasitic NPN transistor, and the first P+ injection region (109), the first N well (102), and the P well (103) form a parasitic PNP1 transistor; The collector of the PNP1 transistor and the base of the NPN transistor are connected via a parasitic resistor R of the P well (103). P The base of the PNP1 transistor and the collector of the NPN transistor are connected via a parasitic resistor R of the first N well (102). N1 connected, that is, the PNP1 transistor and the NPN transistor form a positive feedback path; When the pulse signal amplitude applied by the anode does not reach the device turn-on threshold, the first gate diode D1 is in a reverse bias state, the device is in a high resistance state, and the leakage current is small; when the pulse signal amplitude is greater than the device turn-on threshold, the first gate diode D1 undergoes avalanche breakdown, and the current flows through the parasitic resistance R of the P well (103). P This causes the potential of the P well (103) to rise and causes the NPN transistor and the PNP1 transistor to be turned on, a positive feedback path is formed, a negative differential resistance effect is generated, and the device is transformed into a low resistance state; in the same time domain, the changes in voltage and current are continuous, and the device can achieve a continuously variable resistance value; when the pulse excitation disappears, the first gate diode D1 returns to a reverse bias state, and the device returns to a high resistance state, so the device has a volatile memristive characteristic under a pulse excitation signal.

5. A method for manufacturing a volatile memristor based on CMOS technology according to any one of claims 1 to 4, comprising the following steps: Step 1: A layer of silicon dioxide film is grown on a P-type substrate by thermal oxidation in a furnace tube to relieve the stress of the silicon nitride formed in the subsequent steps on the substrate; Depositing a layer of silicon nitride using chemical vapor deposition (CVD) technology as a stop layer for subsequent chemical mechanical polishing (CMP); Step 2: photoresist coating, exposure and development, defining the first to sixth shallow trench isolation areas, using Ar and CF4 to form a plasma slurry to remove the silicon nitride and silicon dioxide layers not covered by the photoresist, using O2 and HBr to form a plasma slurry to remove the area not covered by the photoresist, the etching depth is 0.45-0.55μm, and the angle of the shallow trench sidewall is 75°-80°; removing the photoresist by dry etching and wet etching, using CVD to deposit a layer of silicon dioxide with a thickness of about 0.5-1.0μm, and then using CMP to remove the surface oxide layer until the silicon nitride layer, and then using hot phosphoric acid (H3PO4) wet etching to remove silicon nitride, the temperature is about 180°C; Step 3: Transferring the patterns on the first N-well and the second N-well masks to the wafer by micro-development technology to form a photoresist pattern for the N-well, and retaining the photoresist in the non-N-well area; Inject high-energy phosphorus ions to form a local N-well and remove the photoresist; Step 4: Transfer the pattern on the P-well mask to the wafer through micro-development technology to form a P-well photoresist pattern, and retain the photoresist in the non-P-well area; Inject high-energy boron ions to form a local P-well and remove the photoresist; Step 5: Anneal the N-well and P-well by heating and annealing in a H2 environment using RTA to activate the impurity ions in the N-well and P-well, repair the silicon substrate lattice damage caused by ion implantation, and further cause the diffusion of impurities; Step 6: Grow a thick gate oxide layer. Use furnace thermal oxidation to grow a thick layer of silicon dioxide at a temperature of 850°C. Use CVD to deposit a layer of polysilicon with a thickness of about 150nm to 300nm, form a polysilicon gate through photolithography and etching, and remove the photoresist; Step 7: growing a thin oxide layer on the surface of polysilicon to buffer and isolate the polysilicon and the silicon nitride formed in subsequent steps; photolithography forming, heavily doped arsenic ion implantation, forming the first to fourth N+ implantation regions; photolithography forming, heavily doped BF2+ ion implantation, forming the first to third P+ implantation regions; Annealing, repairing the crystal damage on the silicon surface caused by ion implantation and eliminating the migration of impurities in the implanted area; Step 8: Connect the first N+ injection region (105), the first polysilicon gate (207), and the first P+ injection region (109) together as the anode of the device, connect the third P+ injection region (111), the fourth polysilicon gate (210), and the fourth N+ injection region (108) together as the cathode of the device, and connect the second polysilicon gate (208), the second P+ injection region (110), and the third polysilicon gate (209) together to share a potential.

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