Display panel, display device and preparation method of display panel

Abstract

The invention provides a display panel, a display device and a preparation method of the display panel, the display panel is provided with a first area and a second area surrounding the first area, the display panel comprises a substrate, a gate drive circuit, a power signal line and a dam structure, and the gate drive circuit is located on one side of the substrate and located in the second area. The power signal line is located on the side, away from the substrate, of the gate drive circuit, and the orthographic projection of the power signal line on the substrate and the orthographic projection of the gate drive circuit on the substrate are arranged in an overlapped mode. The dam structure is at least partially located on the side, away from the substrate, of the power signal line, and the orthographic projection of the dam structure on the substrate and the orthographic projection of the gate drive circuit on the substrate are arranged in an overlapped mode. In the embodiment of the invention, the dam structure is at least partially located on the side, deviating from the substrate, of the power signal line, and the orthographic projection of the dam structure on the substrate can be overlapped with the orthographic projection of the gate drive circuit on the substrate, so that the distance between the dam structure and the first region is reduced, and a narrow frame effect is realized.

Description

Technical Field

[0001] The present application relates to the technical field of display devices, and in particular to a display panel, a display device, and a method for manufacturing a display panel. Background Art

[0002] Flat display panels such as Organic Light Emitting Diode (OLED) panels and display panels using light emitting diode (LED) devices have the advantages of high image quality, power saving, thin body and wide application range. They are widely used in various consumer electronic products such as mobile phones, televisions, personal digital assistants, digital cameras, laptops, desktop computers, etc., becoming the mainstream in display devices. Summary of the invention

[0003] The embodiments of the present application provide a display panel, a display device, and a method for manufacturing a display panel, which can improve the narrow frame effect.

[0004] In a first aspect, an embodiment of the present application provides a display panel, the display panel having a first area and a second area surrounding the first area, the display panel comprising a substrate, a gate driving circuit, a power signal line, and a dam structure, the gate driving circuit being located on one side of the substrate and located in the second area. The power signal line is located on a side of the gate driving circuit away from the substrate, and the orthographic projection of the power signal line on the substrate overlaps with the orthographic projection of the gate driving circuit on the substrate.

[0005] The dam structure is at least partially located on a side of the power signal line away from the substrate, and an orthographic projection of the dam structure on the substrate overlaps with an orthographic projection of the gate driving circuit on the substrate.

[0006] In some embodiments, the orthographic projection of the dam structure on the substrate overlaps with the orthographic projection of the power signal line on the substrate;

[0007] In some embodiments, an orthographic projection of the dam structure on the substrate is located within an orthographic projection of the gate driving circuit on the substrate;

[0008] In some embodiments, an orthographic projection of the power signal line on the substrate is located within an orthographic projection of the gate driving circuit on the substrate.

[0009] In some embodiments, the gate driving circuit includes a light emitting control circuit and a scanning driving circuit located on a side of the light emitting control circuit close to the first region, and an orthographic projection of the dam structure on the substrate overlaps with an orthographic projection of the light emitting control circuit on the substrate;

[0010] In some embodiments, an orthographic projection of the dam structure on the substrate overlaps with an orthographic projection of the scan driving circuit on the substrate.

[0011] In some embodiments, the dam structure includes a first blocking portion and a second blocking portion located on a side of the first blocking portion close to the first region, and an orthographic projection of the second blocking portion on the substrate overlaps with an orthographic projection of the power signal line on the substrate;

[0012] In some embodiments, the first barrier portion and the second barrier portion include the same material;

[0013] In some embodiments, the orthographic projection of the first blocking portion on the substrate overlaps with the orthographic projection of the power signal line on the substrate;

[0014] In some embodiments, in a thickness direction of the substrate, a size of the first barrier portion is greater than a size of the second barrier portion.

[0015] In some embodiments, the orthographic projection portion of the power signal line on the substrate is located outside the orthographic projection of the dam structure on the substrate;

[0016] In some embodiments, the display panel further includes a light-emitting functional layer and a thin film encapsulation layer located on a side of the light-emitting functional layer away from the substrate, the thin film encapsulation layer includes a first inorganic layer, an organic encapsulation layer and a second inorganic layer stacked in sequence in a direction away from the substrate, and the first inorganic layer is disposed in contact with the power signal line;

[0017] In some embodiments, the dam structure includes an insulating material.

[0018] In some embodiments, the dam structure includes a first insulating portion disposed in close contact with the power signal line, and an orthographic projection of the power signal line on the substrate is located outside the orthographic projection of the first insulating portion on the substrate;

[0019] In some embodiments, the display panel includes a pixel defining portion located in the first region, and a pixel opening formed by the pixel defining portion;

[0020] The dam structure includes a second insulating portion located on one side of the first insulating portion substrate, and the second insulating portion is arranged in the same layer as the pixel defining portion;

[0021] In some embodiments, the dam structure further includes a support portion located on a side of the second insulating portion facing away from the substrate, and the display panel further includes a support column located in the first region and disposed on a side of the pixel defining portion facing away from the substrate;

[0022] The supporting part and the supporting column are arranged at the same layer.

[0023] In some embodiments, the display panel includes an active layer located on one side of a substrate, and a first conductor layer located on a side of the active layer facing away from the substrate;

[0024] The gate driving circuit includes a first transistor, the first transistor includes a first electrode, a second electrode and a control terminal, and the first electrode and the second electrode are located in the first conductor layer;

[0025] Wherein, the power signal line and the dam structure are both located on a side of the first conductor layer away from the substrate;

[0026] In some embodiments, an orthographic projection of the power signal line on the substrate overlaps with an orthographic projection of the first transistor on the substrate;

[0027] In some embodiments, an orthographic projection of the dam structure on the substrate overlaps with an orthographic projection of the first transistor on the substrate.

[0028] In some embodiments, the display panel further includes a light-emitting functional layer, a first electrode layer located on a side of the light-emitting functional layer facing the substrate, and a fourth conductor layer located between the first electrode layer and the first conductor layer;

[0029] The power signal line includes a first sub-portion located in the first electrode layer and a second sub-portion located in the fourth conductor layer.

[0030] In some embodiments, the gate drive circuit further includes a clock signal line;

[0031] The power signal line is located on the side of the clock signal line facing away from the substrate;

[0032] In some embodiments, an orthographic projection of the power signal line on the substrate overlaps with an orthographic projection of the clock signal line on the substrate.

[0033] In some embodiments, the display panel further includes a second conductor layer located on a side of the first conductor layer facing the substrate, and a third conductor layer located on a side of the second conductor layer facing the substrate;

[0034] The gate driving circuit also includes a storage capacitor, which includes a first electrode plate and a second electrode plate that are arranged opposite to each other. The first electrode plate is located in the second conductor layer, and the second electrode plate is located in the third conductor layer.

[0035] In some embodiments, the clock signal line is at least partially located in the first conductor layer, and / or the clock signal line is at least partially located on a side of the first conductor layer facing away from the substrate;

[0036] In some embodiments, the display panel further includes a reset signal line located in the second area, the reset signal line being located on a side of the gate driving circuit close to the substrate;

[0037] In some embodiments, the reset signal line and the clock signal line are arranged on the same layer;

[0038] In some embodiments, the reset signal line and the power signal line are arranged on the same layer.

[0039] In a second aspect, an embodiment of the present application provides a display device, comprising a display panel in any of the aforementioned embodiments.

[0040] In a third aspect, an embodiment of the present application provides a method for manufacturing a display panel, wherein the display panel has a first area and a second area surrounding the first area, and the manufacturing method includes:

[0041] forming a gate driving circuit on one side of the substrate and in the corresponding second region;

[0042] A power signal line is formed on a side of the gate driving circuit away from the substrate, and an orthographic projection of the power signal line on the substrate overlaps with an orthographic projection of the gate driving circuit on the substrate;

[0043] A dam structure is formed on the side of the power signal line away from the substrate, and the orthographic projection of the dam structure on the substrate overlaps with the orthographic projection of the gate driving circuit on the substrate.

[0044] The embodiments of the present application provide a display panel, a display device and a method for preparing a display panel. First, the relative position between the power signal line and the gate driving circuit is adjusted so that the power signal line is not located on the side of the gate driving circuit away from the first area, but is located on the side of the gate driving circuit away from the substrate, and the orthographic projection of the power signal line on the substrate can be overlapped with the orthographic projection of the gate driving circuit on the substrate.

[0045] On this basis, as the position of the power signal line is adjusted, the dam structure can also be moved inward relative to the first area, so that the dam structure is at least partially located on the side of the power signal line away from the substrate, and the positive projection of the dam structure on the substrate can overlap with the positive projection of the gate drive circuit on the substrate, which helps to reduce the distance between the dam structure and the first area, and is conducive to achieving a narrow frame effect. In addition, this design can increase the distance between the dam structure and the substrate in the thickness direction, so that while achieving a narrow frame, the end of the dam structure away from the substrate can be at a higher height position, thereby improving the cutoff effect of the dam structure on part of the flow film layer and meeting the corresponding overflow blocking needs of the dam structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solution of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0047] Figure 1 It is a partial simplified schematic diagram of a display panel in the related art;

[0048] Figure 2 is a partial simplified schematic diagram of a display panel provided in an embodiment of the present application;

[0049] Figure 3 yes Figure 2A corresponding schematic diagram of a partial cross-sectional structure of a display panel;

[0050] Figure 4 is a schematic diagram of a partial cross-sectional structure of another display panel provided in an embodiment of the present application;

[0051] Figure 5 is a partial simplified schematic diagram of another display panel provided in an embodiment of the present application;

[0052] Figure 6 yes Figure 5 A corresponding schematic diagram of a partial cross-sectional structure of a display panel;

[0053] Figure 7 is a schematic diagram of a partial cross-sectional structure of another display panel provided in an embodiment of the present application;

[0054] Figure 8 is a schematic diagram of a partial cross-sectional structure of another display panel provided in an embodiment of the present application;

[0055] Fig. 9 is a structural schematic diagram of a display device provided in an embodiment of the present application;

[0056] Fig.10 is a flow chart of a method for preparing a display panel provided in an embodiment of the present application;

[0057] Figures 11a to 11c It is a process structure schematic diagram of a method for preparing a display panel provided in an embodiment of the present application.

[0058] Marking Description:

[0059] 10. Substrate;

[0060] 20. Gate drive circuit; 21. Light emitting control circuit; 22. Scan drive circuit; 23. Clock signal line; 24. Storage capacitor; 241. First plate; 242. Second plate;

[0061] 30. power signal line; 31. first sub-section; 32. second sub-section;

[0062] 40. dam structure; 41. first blocking portion; 42. second blocking portion; 43. first insulating portion; 44. second insulating portion; 45. supporting portion;

[0063] 50. Light-emitting functional layer; 51. Light-emitting structure;

[0064] 60. Thin film encapsulation layer; 61. First inorganic layer; 62. Organic encapsulation layer; 63. Second inorganic layer;

[0065] 70. pixel definition layer; 71. pixel definition portion; 72. pixel opening;

[0066] 81. a first conductor layer; 82. a second conductor layer; 83. a third conductor layer;

[0067] 90. Active layer;

[0068] D, first electrode layer; D1 first electrode;

[0069] PS, support column;

[0070] T, first transistor; J1, first electrode; J2, second electrode; J3, control terminal;

[0071] ref, reset signal line;

[0072] A1, first zone; A2, second zone;

[0073] 20', driving circuit; 30', power supply wiring; 40', dam; AA, display area;

[0074] X, thickness direction. DETAILED DESCRIPTION

[0075] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.

[0076] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0077] With the continuous advancement of display technology, display panels are increasingly used in display products. Display panels with narrow bezels have attracted a large number of consumers because they can provide users with a better viewing experience.

[0078] As consumers' demands for display panels become higher and higher, the requirements for resolution and power consumption have made narrow bezels increasingly difficult to achieve. How to obtain a display panel with a narrower bezel while ensuring high quality is a technical problem that needs to be solved urgently.

[0079] Regarding the above issues, please refer to Figures 2 to 4 The embodiment of the present application provides a display panel, the display panel has a first area A1 and a second area A2 arranged around the first area A1, the display panel includes a substrate 10, a gate driving circuit 20, a power signal line 30 and a dam structure 40, the gate driving circuit 20 is located on one side of the substrate 10 and is located in the second area A2. The power signal line 30 is located on the side of the gate driving circuit 20 away from the substrate 10, and the orthographic projection of the power signal line 30 on the substrate 10 overlaps with the orthographic projection of the gate driving circuit 20 on the substrate 10.

[0080] The dam structure 40 is at least partially located on a side of the power signal line 30 facing away from the substrate 10 , and an orthographic projection of the dam structure 40 on the substrate 10 overlaps with an orthographic projection of the gate driving circuit 20 on the substrate 10 .

[0081] The display panel is a device for realizing the display function, the substrate 10 is a film layer structure used to support the display panel, and other film layer structures are stacked on the substrate 10. The stacking arrangement mentioned here means that the other film layers are arranged in sequence along the thickness direction X of the substrate 10. Among them, the thickness direction X of the other film layer structures located on one side of the substrate 10 is usually consistent with the thickness direction X of the substrate 10. Therefore, for the convenience of expression, the thickness direction X mentioned in the embodiments of the present application can represent the thickness direction X of the substrate 10 or the thickness direction X of other film layers.

[0082] The display panel has a first area A1 and a second area A2 arranged around the first area A1. The first area A1 may be an area in the display panel that can realize the display function, and the second area A2 is a frame area arranged around the first area A1. The embodiment of the present application does not limit the size and shape of the first area A1 and the second area A2. For example, the first area A1 may be a square structure, and the second area A2 may be a corresponding square ring structure. Or the first area A1 may be a ring structure, and the second area A2 may be a corresponding circular ring structure.

[0083] Exemplarily, the display panel may be provided with a light-emitting structure 51 and a pixel circuit in the first area A1, and the pixel circuit is used to drive and control whether the light-emitting structure 51 realizes the light-emitting function, and the gate drive circuit 20 is arranged in the second area A2. Usually, the gate drive circuit 20 is electrically connected to the pixel circuit. Specifically, the gate drive circuit 20 is a structure in the display panel for generating a scan signal or a light-emitting control signal and transmitting it to the pixel circuit. Optionally, the gate drive circuit 20 may include a device structure such as a plurality of transistors and a storage capacitor 24 formed by a plurality of film layers such as a conductor layer, an insulating layer, and a semiconductor layer.

[0084] The power signal line 30 is a conductive structure for transmitting a power signal in the display panel, wherein the power signal line 30 may be a constant voltage signal, and the power signal line 30 is disposed in the second area A2 together with the gate driving circuit 20. Further, the display panel may include a light emitting structure 51 and a first electrode and a second electrode located on both sides of the light emitting structure 51 in the thickness direction X, wherein the first electrode is located on the side of the light emitting structure 51 away from the substrate 10. On this basis, the power signal line 30 may be electrically connected to the first electrode, and the pixel circuit may be electrically connected to the second electrode, and the power signal line 30 and the pixel circuit realize control of the light emitting structure 51 by driving the first electrode and the second electrode respectively.

[0085] The dam structure 40 is located in the second area A2. The dam structure 40 is a structure in the display panel used to block overflow. Specifically, the display panel may include a variety of different types of film structures, some of which have a certain fluidity due to factors such as material composition. In order to achieve an effective cutoff effect on such film structures, the embodiment of the present application is provided with a dam structure 40 in the display panel. The dam structure 40 can block and reduce the probability of part of the film flowing to the side of the dam structure 40 away from the first area A1, thereby improving the reliability of the film structure inside the display panel.

[0086] In related technologies, such as Figure 1 As shown, the dam 40' is usually arranged adjacent to the power line 30', and the power line 30' is located on the side of the driving circuit 20' away from the display area AA. On this basis, the distance between the dam 40' and the display area AA is affected by the size of the power line 30' and the driving circuit 20', so it is difficult to shorten the distance between the dam 40' and the display area AA, which in turn has an adverse effect on the frame size of the display panel, and it is difficult to achieve a narrow frame effect.

[0087] In the embodiment of the present application, the relative position between the power signal line 30 and the gate driving circuit 20 is first adjusted, so that the power signal line 30 is not located on the side of the gate driving circuit 20 away from the first area A1, but is located on the side of the gate driving circuit 20 away from the substrate 10, and the orthographic projection of the power signal line 30 on the substrate 10 can overlap with the orthographic projection of the gate driving circuit 20 on the substrate 10.

[0088] On this basis, as the position of the power signal line 30 is adjusted, the dam structure 40 can also be moved inward relative to the first area A1, so that the dam structure 40 is at least partially located on the side of the power signal line 30 away from the substrate 10, and the positive projection of the dam structure 40 on the substrate 10 can overlap with the positive projection of the gate drive circuit 20 on the substrate 10, which helps to reduce the distance between the dam structure 40 and the first area A1, which is conducive to achieving a narrow frame effect. In addition, this design can increase the distance between the dam structure 40 and the substrate 10 in the thickness direction X, so that while achieving a narrow frame, the end of the dam structure 40 away from the substrate 10 can be at a higher height position, thereby improving the cutoff effect of the dam structure 40 on part of the flow film layer and meeting the corresponding overflow blocking needs of the dam structure 40.

[0089] It should be noted that the specific positional relationship between the dam structure 40 and the power signal line 30 is not limited in the embodiment of the present application. For example, the orthographic projection of the dam structure 40 on the substrate 10 can be overlapped with the orthographic projection of the power signal line 30 on the substrate 10, or the orthographic projection of the dam structure 40 on the substrate 10 can also be located outside the orthographic projection of the power signal line 30 on the substrate 10, as long as at least part of the structure of the dam structure 40 is located on the side of the power signal line 30 away from the substrate 10. Among them, Figure 2 FIG. 4 shows a case where the orthographic projection of the dam structure 40 on the substrate 10 is completely outside the orthographic projection of the power signal line 30 on the substrate 10. Figure 4 4 shows that the orthographic projection of part of the dam structure 40 on the substrate 10 overlaps with the orthographic projection of the power signal line 30 on the substrate 10, while the orthographic projection of the other part of the structure on the substrate 10 overlaps with the orthographic projection of the power signal line 30 on the substrate 10. Of course, in other embodiments, the orthographic projection of the dam structure 40 on the substrate 10 may also be completely located within the orthographic projection of the power signal line 30 on the substrate 10.

[0090] In addition, the dam structure 40 can be formed by stacking a plurality of film layer structures together, and the present embodiment does not limit the specific film layer composition and corresponding material types in the dam structure 40. The dam structure 40 can include only one barrier portion, or the dam structure 40 can also include two or more barrier portions at the same time, and the present embodiment does not limit this either.

[0091] In some embodiments, see Figure 5 and Figure 6 The orthographic projection of the dam structure 40 on the substrate 10 overlaps with the orthographic projection of the power signal line 30 on the substrate 10 , that is, at least part of the structure of the dam structure 40 can fit with the surface of the power signal line 30 facing away from the substrate 10 .

[0092] In the embodiment of the present application, compared with the solution in which the dam structure 40 is located on the side of the power signal line 30 away from the first area A1, the orthographic projection of the dam structure 40 on the substrate 10 is overlapped with the orthographic projection of the power signal line 30 on the substrate 10, so that the distance between the dam structure 40 and the first area A1 can be further reduced, and the narrow frame effect of the display panel can be further improved. In this design, the power signal line 30 can help increase the distance between the dam structure 40 and the substrate 10 in the thickness direction X, thereby helping to improve the overflow blocking effect of the dam structure 40, which has strong practicality.

[0093] In some embodiments, the orthographic projection of the dam structure 40 on the substrate 10 is located within the orthographic projection of the gate driving circuit 20 on the substrate 10. Specifically, the gate driving circuit 20 may have a first edge away from the first area A1, and the dam structure 40 is completely located on the side of the first edge close to the first area A1. This design further limits the distance between the side of the dam structure 40 away from the first area A1 and the first area A1, thereby improving the narrow frame effect of the display panel. Similarly, in some optional embodiments, the orthographic projection of the power signal line 30 on the substrate 10 is located within the orthographic projection of the gate driving circuit 20 on the substrate 10.

[0094] In some embodiments, Figure 5 and Figure 6 As shown, the gate driving circuit 20 includes a light emitting control circuit 21 and a scanning driving circuit 22 located on the side of the light emitting control circuit 21 close to the first area A1, and the orthographic projection of the dam structure 40 on the substrate 10 overlaps with the orthographic projection of the light emitting control circuit 21 on the substrate 10.

[0095] The light-emitting control circuit 21 is a partial structure of the gate driving circuit 20 for generating and transmitting a light-emitting control signal, and the scanning driving circuit 22 is a partial structure of the gate driving circuit 20 for generating and transmitting a scanning signal. The scanning driving circuit 22 and the light-emitting control circuit 21 may include a multi-stage shift register cascaded with each other, and the multi-stage shift register may sequentially output a conduction level to sequentially scan each row of pixel circuits located in the first area A1 to meet display needs.

[0096] The scanning driving circuit 22 and the light emitting control circuit 21 are both located in the second area A2, and the scanning driving circuit 22 is located on the side of the light emitting control circuit 21 close to the first area A1, that is, compared with the light emitting control circuit 21, the distance between the scanning driving circuit 22 and the first area A1 is closer. On this basis, in the embodiment of the present application, the orthographic projection of the dam structure 40 on the substrate 10 is overlapped with the orthographic projection of the light emitting control circuit 21 on the substrate 10, so that the side of the dam structure 40 away from the first area A1 can have a certain distance size with the first area A1, so as to improve the overflow blocking effect of the dam structure 40. Of course, in some embodiments, the orthographic projection of the dam structure 40 on the substrate 10 can also be overlapped with the orthographic projection of the scanning driving circuit 22 on the substrate 10.

[0097] In some embodiments, the dam structure 40 includes a first barrier portion 41 and a second barrier portion 42 located on a side of the first barrier portion 41 close to the first area A1 , and an orthographic projection of the second barrier portion 42 on the substrate 10 overlaps with an orthographic projection of the power signal line 30 on the substrate 10 .

[0098] The dam structure 40 includes a first barrier portion 41 and a second barrier portion 42 that are spaced apart. The first barrier portion 41 and the second barrier portion 42 may include the same material or different materials. Optionally, the first barrier portion 41 and the second barrier portion 42 include the same material, so that at least a portion of the film layer structure including the same material in the first barrier portion 41 and the second barrier portion 42 can be formed together in the same process by patterning, thereby improving the corresponding preparation efficiency of the dam structure 40 and reducing the cost.

[0099] Compared with the first blocking portion 41, the second blocking portion 42 is arranged closer to the first area A1. On this basis, since the embodiment of the present application moves the dam structure 40 inward as a whole, the orthographic projection of the second blocking portion 42 on the substrate 10 can overlap with the orthographic projection of the power signal line 30 on the substrate 10, that is, the second blocking portion 42 can be attached to the power signal line 30 and be located on the side of the power signal line 30 away from the substrate 10, thereby improving the narrow frame effect of the display panel and improving the corresponding viewing experience of the display panel.

[0100] It should be noted that, for the first blocking portion 41, the orthographic projection of the first blocking portion 41 on the substrate 10 can be arranged to overlap with the orthographic projection of the power signal line 30 on the substrate 10, or the first blocking portion 41 can also be located on the side of the power signal line 30 away from the first area A1. Optionally, the orthographic projection of the first blocking portion 41 on the substrate 10 is arranged to overlap with the orthographic projection of the power signal line 30 on the substrate 10, that is, the first blocking portion 41 and the second blocking portion 42 can be attached to the power signal line 30 together and located on the side of the power signal line 30 away from the substrate 10, thereby improving the narrow frame effect of the display panel and improving the corresponding viewing experience of the display panel.

[0101] The embodiment of the present application does not limit the size relationship between the first barrier 41 and the second barrier 42. Optionally, in the thickness direction X of the substrate 10, the size of the first barrier 41 is larger than the size of the second barrier 42, that is, the farther away from the first area A1, the higher the height of the dam structure 40. This design helps to further improve the blocking effect of the dam structure 40 on the fluid film layer, thereby improving the overflow blocking effect of the dam structure 40.

[0102] In addition, in addition to the first barrier 41 and the second barrier 42, the dam structure 40 may also include other barrier structures, or may not include other barrier structures. Other barrier structures may be located on the side of the first barrier 41 away from the first area A1, or on the side of the second barrier 42 toward the first area A1, or between the first barrier 41 and the second barrier 42, which is not limited in the present embodiment.

[0103] In some embodiments, Figure 4 and Figure 6 As shown, the orthographic projection of the power signal line 30 on the substrate 10 is located outside the orthographic projection of the dam structure 40 on the substrate 10 , that is, the power signal line 30 is not completely covered or blocked by the dam structure 40 .

[0104] In order to meet the needs of power signal transmission, the power signal line 30 usually includes a conductive material. In order to reduce the adverse effects of the preparation process corresponding to the partial film layer on the side of the power signal line 30 away from the substrate 10 on the power signal line 30, the power signal line 30 needs to be covered by a partial film layer structure to achieve a protective effect.

[0105] On this basis, since the orthographic projection of part of the structure in the power signal line 30 on the substrate 10 overlaps with the orthographic projection of the dam structure 40 on the substrate 10, the dam structure 40 can cover and protect part of the structure in the power signal line 30, thereby improving the structural reliability of the power signal line 30.

[0106] As for the part of the power signal line 30 that cannot be covered by the dam structure 40, it needs to be protected by other structures. Figures 4 to 6 As shown, the display panel also includes a light-emitting functional layer 50 and a thin film encapsulation layer 60 located on the side of the light-emitting functional layer 50 away from the substrate 10. The thin film encapsulation layer 60 includes a first inorganic layer 61, an organic encapsulation layer 62 and a second inorganic layer 63 stacked in sequence in a direction away from the substrate 10. The first inorganic layer 61 is arranged in contact with the power signal line 30.

[0107] The light-emitting functional layer 50 is a film layer structure used to realize the display function in the display panel, and the light-emitting functional layer 50 includes a light-emitting structure 51 located in the first area A1. The thin film encapsulation layer 60 is located on the side of the light-emitting functional layer 50 away from the substrate 10, that is, the thin film encapsulation layer 60 is located on the light-emitting surface side of the light-emitting structure 51. The part of the thin film encapsulation layer 60 located in the first area A1 can play a role in encapsulating and protecting the light-emitting structure 51, so as to reduce the risk of water, oxygen, etc. invading the light-emitting structure 51, and improve the reliability of the display panel.

[0108] The thin film encapsulation layer 60 includes a first inorganic layer 61, an organic encapsulation layer 62 and a second inorganic layer 63 which are stacked. The organic encapsulation layer 62 itself has a certain fluidity. The first inorganic layer 61 and the second inorganic layer 63 can limit the organic encapsulation layer 62 in the thickness direction X, and the dam structure 40 can limit the organic encapsulation layer 62 in a direction parallel to the plane of the substrate 10, thereby improving the structural reliability of the thin film encapsulation layer 60.

[0109] Furthermore, the partial structure of the first inorganic layer 61 located in the second area A2 can be arranged in contact with the power signal line 30. Under this design, the first inorganic layer 61 can provide a certain degree of covering and protection for the power signal line 30, thereby reducing the damage to the power signal line 30 caused by subsequent preparation processes and improving the reliability of the use of the power signal line 30.

[0110] In some embodiments, the dam structure 40 includes an insulating material, wherein the insulating material may be an organic material or an inorganic material. By providing the dam structure 40 with an insulating material, the dam structure 40 can protect a portion of the structure in the power signal line 30 while insulating and isolating the portion of the structure in the power signal line 30 from other structures, thereby improving the reliability of signal transmission within the power signal line 30.

[0111] In some embodiments, the dam structure 40 includes a first insulating portion 43 disposed in close contact with the power signal line 30 , and an orthographic projection of the power signal line 30 on the substrate 10 is located outside the orthographic projection of the first insulating portion 43 on the substrate 10 .

[0112] The first insulating portion 43 is a partial structure of the dam structure 40 that is close to the power signal line 30 and includes an insulating material, wherein, to meet the shape requirements of the dam structure 40, the film layer where the first insulating portion 43 is located is not a whole-surface structure, but is formed by patterning. In this case, the orthographic projection of the power signal line 30 on the substrate 10 is located outside the orthographic projection of the first insulating portion 43 on the substrate 10, that is, the first insulating portion 43 will not completely cover the entire structure of the power signal line 30, but covers and protects part of the structure of the power signal line 30.

[0113] Optionally, the display panel may include a planarization layer and a pixel definition layer 70 located on the side of the planarization layer facing away from the substrate 10 and bonded to the planarization layer. The planarization layer has a full-surface structure with vias in the first area A1 to provide a flat surface for the preparation of the pixel definition layer 70, and the first insulating portion 43 may be located in the planarization layer, that is, the first insulating portion 43 is formed by patterning a portion of the structure of the planarization layer in the second area A2.

[0114] Furthermore, in some embodiments, the display panel includes a pixel defining portion 71 located in the first area A1 and a pixel opening 72 enclosed by the pixel defining portion 71, and the dam structure 40 includes a second insulating portion 44 located on the side of the first insulating portion 43 away from the substrate 10, and the second insulating portion 44 is arranged on the same layer as the pixel defining portion 71.

[0115] The pixel defining portion 71 is a partial structure of the pixel definition layer 70 located in the first area A1, and the pixel defining portion 71 can enclose a pixel opening 72 to define the position of the light emitting structure 51. Furthermore, the embodiment of the present application also adds a second insulating portion 44 to the dam structure 40, and the second insulating portion 44 is arranged in the same layer as the pixel defining portion 71, that is, the second insulating portion 44 is formed by patterning a partial structure of the pixel definition layer 70 located in the second area A2, so that the size of the dam structure 40 in the thickness direction X can be increased by means of the second insulating portion 44, and its overflow blocking effect can be improved, and the second insulating portion 44 and the pixel defining portion 71 can also be formed together in the same process to improve the manufacturing efficiency.

[0116] In some embodiments, Figures 4 to 6 As shown, the dam structure 40 also includes a supporting portion 45 located on the side of the second insulating portion 44 away from the substrate 10, and the display panel also includes a supporting column PS located in the first area A1 and arranged on the side of the pixel defining portion 71 away from the substrate 10, and the supporting portion 45 is arranged on the same layer as the supporting column PS.

[0117] The support column PS is a columnar structure used to play a supporting role in the first area A1. For example, the cross-sectional shape of the support column PS can be a trapezoidal structure. Furthermore, the embodiment of the present application also adds a support portion 45 to the dam structure 40. The support portion 45 is arranged on the same layer as the support column PS, that is, the support portion 45 and the support column PS can be formed together in the same process. This design can further increase the size of the dam structure 40 in the thickness direction X, improve its overflow blocking effect, and at the same time, it can also play a certain supporting role for the second area A2 of the display panel with the help of the support portion 45, thereby improving the impact resistance of the display panel, and has strong practicality.

[0118] In some embodiments, Figure 5 and Figure 6 As shown, the display panel includes an active layer 90 located on one side of a substrate 10, and a first conductor layer 81 located on a side of the active layer 90 away from the substrate 10. The gate drive circuit 20 includes a first transistor T, the first transistor T includes a first electrode J1, a second electrode J2 and a control terminal J3, the first electrode J1 and the second electrode J2 are located in the first conductor layer 81, wherein the power signal line 30 is located on a side of the first conductor layer 81 away from the substrate 10.

[0119] The gate drive circuit 20 may include a plurality of transistors, and the first transistor T is one of the plurality of transistors. The embodiment of the present application does not limit the specific function and specific position relationship of the first transistor T. The first transistor T includes a first electrode J1, a second electrode J2, and a control terminal J3, and the control terminal J3 is used to control whether the first electrode J1 and the second electrode J2 are turned on or off.

[0120] The display panel includes an active layer 90 and a first conductor layer 81. The first conductor layer 81 is located on a side of the active layer 90 away from the substrate 10. The active layer 90 includes an active structure. The first conductor layer 81 includes a conductive structure including a first electrode J1 and a second electrode J2. The control terminal J3 of the first transistor T overlaps with a part of the structure in the active structure in the orthographic projection of the substrate 10 to form a channel structure corresponding to the first transistor T. The first electrode J1 and the second electrode J2 can be electrically connected to both sides of the channel structure by vias.

[0121] In combination with the above content, it can be known that the power signal line 30 and the dam structure 40 are both located on the side of the gate driving circuit 20 away from the substrate 10. Furthermore, the power signal line 30 and the dam structure 40 are both located on the side of the first conductor layer 81 away from the substrate 10. Under this design, the power signal line 30 and the dam structure 40 move inward together toward the first area A1, thereby improving the narrow frame effect of the display panel.

[0122] Further optionally, the orthographic projection of the power signal line 30 on the substrate 10 overlaps with the orthographic projection of the first transistor T on the substrate 10. Similarly, optionally, the orthographic projection of the dam structure 40 on the substrate 10 overlaps with the orthographic projection of the first transistor T on the substrate 10.

[0123] In some embodiments, see Figure 4 and Figure 7 The display panel further includes a light-emitting functional layer 50, a first electrode layer D located on the side of the light-emitting functional layer 50 facing the substrate 10, and a fourth conductor layer 84 located between the first electrode layer D and the first conductor layer 81. The power signal line 30 includes a first sub-portion 31 located in the first electrode layer D and a second sub-portion 32 located in the fourth conductor layer 84.

[0124] The light-emitting functional layer 50 includes a light-emitting structure 51, which is a component in the display panel for realizing the light-emitting function. The first electrode layer D is located on the side of the light-emitting functional layer 50 facing the substrate 10, and the first electrode layer D is provided with a plurality of first electrodes D1 in the first area A1, and the plurality of first electrodes are respectively used to drive different light-emitting structures 51 to realize the light-emitting function.

[0125] Optionally, the display panel further includes a second electrode layer located on the side of the light-emitting functional layer 50 away from the substrate 10, the second electrode layer includes a second electrode, and the orthographic projection of the second electrode on the substrate 10 covers the orthographic projections of the plurality of first electrodes D1 on the substrate 10. The first electrode D1 is an anode, and the second electrode is a cathode.

[0126] The fourth conductor layer 84 is a conductor film layer located between the first electrode layer D and the first conductor layer 81. Further, in the embodiment of the present application, the power signal line 30 is provided to include a first sub-portion 31 located in the first electrode layer D and a second sub-portion 32 located in the fourth conductor layer 84, that is, the power signal line 30 is formed by a combination of conductor structures located in different film layers. Compared with the technical solution in which the power signal line 30 is only provided in a single film layer, this design helps to reduce the overall positive projection area of ​​the power signal line 30 on the substrate 10, thereby further facilitating the power signal line 3 to move inward in a direction close to the first area A1, thereby improving the narrow frame effect of the display panel. In some embodiments, the gate drive circuit 20 also includes a clock signal line 23, and the power signal line 30 is located on the side of the clock signal line 23 away from the substrate 10.

[0127] The clock signal line 23 is a conductive structure for outputting a clock signal, and the clock signal is a specific signal with a fixed periodic frequency. The clock signal line 23 can be arranged in the same layer as the first pole J1 and the second pole J2, that is, the clock signal line 23 can be located in the first conductor layer 81, or the clock signal line 23 can be arranged in a different layer from the first pole J1 and the second pole J2, that is, the clock signal line 23 can also be located on the side of the first conductor layer 81 away from the substrate 10, and the embodiment of the present application does not limit this.

[0128] In the related art, the clock signal line 23 is usually arranged on the same layer as the power signal line 30. Due to the limitation of the clock signal line 23, it is difficult to reduce the distance between the power signal line 30 and the first area A1, which makes it difficult to reduce the distance between the dam structure 40 and the first area A1, thereby making it difficult to adjust the border size of the display panel.

[0129] In the embodiment of the present application, since the power signal line 30 is located on the side of the clock signal line 23 away from the substrate 10, the layout of the power signal line 30 is no longer limited to the clock signal line 23, so that the power signal line 30 and the dam structure 40 can be moved inwards toward the first area A1, thereby reducing the frame size of the display panel and improving the viewing experience of the display panel. Further, optionally, the orthographic projection of the power signal line 30 on the substrate 10 overlaps with the orthographic projection of the clock signal line 23 on the substrate 10.

[0130] In some embodiments, the display panel further includes a second conductor layer 82 located on the side of the first conductor layer 81 facing the substrate 10, and a third conductor layer 83 located on the side of the second conductor layer 82 facing the substrate 10. The gate drive circuit 20 further includes a storage capacitor 24, the storage capacitor 24 includes a first electrode plate 241 and a second electrode plate 242 opposite to each other, the first electrode plate 241 is located in the second conductor layer 82, and the second electrode plate 242 is located in the third conductor layer 83.

[0131] In addition to the first conductor layer 81, the display panel also includes at least two conductive layers, the second conductor layer 82 and the third conductor layer 83. Among them, there is an insulating layer between any two adjacent conductor layers of the first conductor layer 81, the second conductor layer 82 and the third conductor layer 83 to ensure the layout of the conductive structure in each conductor layer and the reliability of signal transmission.

[0132] In addition to the multiple transistors, the gate drive circuit 20 also includes a storage capacitor 24, which includes a first plate 241 located in the second conductor layer 82 and a second plate 242 located in the third conductor layer 83. Optionally, the control terminal J3 of the first transistor T can also be located in the third conductor layer 83.

[0133] It can be seen from the accompanying drawings that the power signal line 30 and the dam structure 40 are both located on the side of the first conductor layer 81, the second conductor layer 82 and the third conductor layer 83 that is away from the substrate 10, that is, the power signal line 30 and the dam structure 40 will not occupy the space within the first conductor layer 81, the second conductor layer 82 and the third conductor layer 83, so that the layout of the power signal line 30 and the dam structure 40 will not be restricted by the conductive structure within the first conductor layer 81, the second conductor layer 82 and the third conductor layer 83, thereby allowing the power signal line 30 and the dam structure 40 to move inward in the direction close to the first area A1, thereby achieving a narrow frame effect of the display panel.

[0134] In some embodiments, the clock signal line 23 is at least partially located in the first conductor layer 81, and / or the clock signal line 23 is at least partially located on a side of the first conductor layer 81 facing away from the substrate 10. Figure 6 As shown, the clock signal line 23 can be completely located in the first conductor layer 81, or as shown in FIG. Figure 8 As shown, the clock signal line 23 may be completely located on the side of the first conductor layer 81 facing away from the substrate 10 , or the clock signal line 23 may be partially located in the first conductor layer 81 and partially located on the side of the first conductor layer 81 facing away from the substrate 10 .

[0135] On this basis, if the clock signal line 23 is completely located in the first conductor layer 81, the number of all conductor layers in the display panel can be reduced, which helps to reduce the overall thickness of the display panel. At the same time, during the preparation process, some fine metal mask plates can be eliminated, thereby reducing the corresponding preparation cost of the display panel.

[0136] If the clock signal line 23 is at least partially located on the side of the first conductor layer 81 away from the substrate 10, the number of conductor layers inside the display panel will increase, which is beneficial to reduce the impedance corresponding to the power signal line 30. In addition, the picture quality of the display panel can be improved while meeting the narrow frame design.

[0137] In summary, the embodiment of the present application can set the clock signal line 23 at different positions of the display panel according to different actual needs, so as to have different advantages, thereby meeting the needs in different situations and having strong practicality and flexibility.

[0138] In some embodiments, the display panel further includes a reset signal line ref located in the second area A2 , and the reset signal line ref is located on a side of the gate driving circuit 20 close to the substrate 10 .

[0139] The reset signal line ref is a conductive structure for providing a reset signal in the display panel, and the reset signal line ref is located on a side of the gate drive circuit 20 close to the substrate 10. In the thickness direction X, the reset signal line ref can have a variety of layout modes, for example, optionally, the reset signal line ref can be arranged in the same layer as the clock signal line 23. Alternatively, the reset signal line ref is arranged in the same layer as the power signal line 30.

[0140] Second, see Fig. 9 An embodiment of the present application provides a display device, which includes a display panel in any of the aforementioned embodiments.

[0141] It should be noted that the display device provided in the embodiment of the present application has the beneficial effects of the display panel in any of the aforementioned embodiments. For details, please refer to the aforementioned description of the beneficial effects of the display panel, and the embodiment of the present application will not be repeated.

[0142] Third, see Fig.10 11 , an embodiment of the present application provides a method for manufacturing a display panel, wherein the display panel has a first area A1 and a second area A2 surrounding the first area A1 , and the manufacturing method includes:

[0143] S100: forming a gate driving circuit on one side of the substrate and corresponding to the second region.

[0144] See also Fig.11a In step S100, the gate driving circuit 20 is a structure in the display panel for generating a scanning signal or a light emitting control signal and transmitting it to the pixel circuit. Optionally, the gate driving circuit 20 may include a clock signal line 23 formed by multiple layers of conductor layers, insulating layers, and semiconductor layers, a plurality of transistors, and a storage capacitor 24.

[0145] On this basis, at least a first conductor layer 81, a second conductor layer 82, a third conductor layer 83 and an active layer 90 can be formed on one side of the substrate 10 to meet the preparation requirements of the clock signal line 23, several transistors and the storage capacitor 24 in the gate drive circuit 20.

[0146] S110: forming a power signal line on a side of the gate driving circuit away from the substrate.

[0147] In the related art, the power signal line 30 is often prepared and formed together with the clock signal line 23 in the gate drive circuit 20 in the same process, which results in the existence of the clock signal line 23 limiting the position of the power signal line 30, making it difficult to reduce the distance between the power signal line 30 and the first area A1.

[0148] In step S110, see Fig.11bSince the power signal line 30 is formed after the gate driving circuit 20, that is, the power signal line 30 is formed after the clock signal line 23, the layout of the power signal line 30 is no longer limited to the clock signal line 23. On this basis, the orthographic projection of the power signal line 30 on the substrate 10 can overlap with the orthographic projection of the gate driving circuit 20 on the substrate 10, that is, the power signal line 30 can be moved inward toward the first area A1.

[0149] S120: forming a dam structure on a side of the power signal line away from the substrate.

[0150] See also Fig.11c In step S120, the position of the dam structure 40 often corresponds to the power signal line 30. On this basis, since the power signal line 30 is relatively moved inward, the dam structure 40 can also be moved inward in a direction close to the first area A1, so that the orthographic projection of the dam structure 40 on the substrate 10 overlaps with the orthographic projection of the gate driving circuit 20 on the substrate 10, thereby achieving a narrow frame effect.

[0151] Although the embodiments disclosed in this application are as above, the contents described are only embodiments adopted for facilitating the understanding of this application and are not intended to limit the present invention. Any technician in the technical field to which this application belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in this application, but the scope of protection of this application shall still be subject to the scope defined in the attached claims.

[0152] The above is only a specific implementation of the present application. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the replacement of other connection methods described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here. It should be understood that the protection scope of the present application is not limited to this. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in this application, and these modifications or replacements should be included in the protection scope of the present application.

Claims

1. A display panel, It is characterized in that The display panel has a first area and a second area surrounding the first area, and the display panel includes: substrate; A gate driving circuit is located on one side of the substrate and in the second region; A power signal line is located at a side of the gate driving circuit away from the substrate, and the orthographic projection of the power signal line on the substrate overlaps with the orthographic projection of the gate driving circuit on the substrate; The dam structure is at least partially located on a side of the power signal line away from the substrate, and the orthographic projection of the dam structure on the substrate overlaps with the orthographic projection of the gate driving circuit on the substrate.

2. The display panel according to claim 1, It is characterized in that The orthographic projection of the dam structure on the substrate overlaps with the orthographic projection of the power signal line on the substrate; Preferably, the orthographic projection of the dam structure on the substrate is located within the orthographic projection of the gate driving circuit on the substrate; Preferably, the orthographic projection of the power signal line on the substrate is located within the orthographic projection of the gate driving circuit on the substrate; Preferably, the gate driving circuit includes a light emitting control circuit and a scanning driving circuit located on a side of the light emitting control circuit close to the first region, and the orthographic projection of the dam structure on the substrate overlaps with the orthographic projection of the light emitting control circuit on the substrate; Preferably, the orthographic projection of the dam structure on the substrate overlaps with the orthographic projection of the scan driving circuit on the substrate.

3. The display panel according to claim 2, It is characterized in that The dam structure includes a first blocking portion and a second blocking portion located on a side of the first blocking portion close to the first region, wherein the orthographic projection of the second blocking portion on the substrate overlaps with the orthographic projection of the power signal line on the substrate; Preferably, the first barrier portion and the second barrier portion comprise the same material; Preferably, the orthographic projection of the first blocking portion on the substrate overlaps with the orthographic projection of the power signal line on the substrate; Preferably, in the thickness direction of the substrate, a size of the first blocking portion is larger than a size of the second blocking portion.

4. The display panel according to claim 2, It is characterized in that The orthographic projection portion of the power signal line on the substrate is located outside the orthographic projection of the dam structure on the substrate; Preferably, the display panel further comprises a light-emitting functional layer and a thin film encapsulation layer located on a side of the light-emitting functional layer away from the substrate, the thin film encapsulation layer comprises a first inorganic layer, an organic encapsulation layer and a second inorganic layer stacked in sequence in a direction away from the substrate, and the first inorganic layer is disposed in contact with the power signal line; Preferably, the dam structure comprises insulating material.

5. The display panel according to claim 4, It is characterized in that The dam structure includes a first insulating portion that is arranged in close contact with the power signal line, and the orthographic projection of the power signal line on the substrate is located outside the orthographic projection of the first insulating portion on the substrate; Preferably, the display panel comprises a pixel defining portion located in the first area, and a pixel opening formed by the pixel defining portion; The dam structure includes a second insulating portion located on one side of the substrate of the first insulating portion, and the second insulating portion is arranged in the same layer as the pixel defining portion; Preferably, the dam structure further comprises a supporting portion located on a side of the second insulating portion away from the substrate, and the display panel further comprises a supporting column located in the first region and arranged on a side of the pixel defining portion away from the substrate; The support portion and the support column are arranged at the same layer.

6. The display panel according to claim 1, It is characterized in that The display panel comprises an active layer located on one side of the substrate, and a first conductor layer located on a side of the active layer away from the substrate; The gate drive circuit includes a first transistor, the first transistor includes a first electrode, a second electrode and a control terminal, and the first electrode and the second electrode are located in the first conductor layer; Wherein, the power signal line and the dam structure are both located on a side of the first conductor layer away from the substrate; Preferably, the power signal line is arranged so that its orthographic projection on the substrate overlaps with the orthographic projection of the first transistor on the substrate; Preferably, the orthographic projection of the dam structure on the substrate overlaps with the orthographic projection of the first transistor on the substrate; Preferably, the display panel further comprises a light-emitting functional layer and a first electrode layer located on a side of the light-emitting functional layer facing the substrate, and a fourth conductor layer located between the first electrode layer and the first conductor layer; The power signal line includes a first sub-portion located in the first electrode layer and a second sub-portion located in the fourth conductor layer.

7. The display panel according to claim 6, It is characterized in that The gate drive circuit also includes a clock signal line; The power signal line is located at a side of the clock signal line away from the substrate; Preferably, the orthographic projection of the power signal line on the substrate overlaps with the orthographic projection of the clock signal line on the substrate; Preferably, the display panel further comprises a second conductor layer located on a side of the first conductor layer facing the substrate, and a third conductor layer located on a side of the second conductor layer facing the substrate; The gate drive circuit further includes a storage capacitor, which includes a first electrode plate and a second electrode plate that are arranged opposite to each other, wherein the first electrode plate is located in the second conductor layer, and the second electrode plate is located in the third conductor layer.

8. The display panel according to claim 7, It is characterized in that The clock signal line is at least partially located in the first conductor layer, and / or the clock signal line is at least partially located on a side of the first conductor layer facing away from the substrate; Preferably, the display panel further comprises a reset signal line located in the second area, and the reset signal line is located on a side of the gate driving circuit close to the substrate; Preferably, the reset signal line and the clock signal line are arranged on the same layer; Preferably, the reset signal line and the power signal line are arranged on the same layer.

9. A display device, It is characterized in that Comprising the display panel as claimed in any one of claims 1 to 8.

10. A method for preparing a display panel, It is characterized in that The display panel comprises a first area and a second area surrounding the first area, and the preparation method comprises: forming a gate driving circuit on one side of the substrate and corresponding to the second region; A power signal line is formed on a side of the gate driving circuit away from the substrate, wherein the orthographic projection of the power signal line on the substrate overlaps with the orthographic projection of the gate driving circuit on the substrate; A dam structure is formed on the side of the power signal line away from the substrate, and the orthographic projection of the dam structure on the substrate overlaps with the orthographic projection of the gate driving circuit on the substrate.

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