Heat management method and system for heterogeneous system-on-chip, and vehicle

Abstract

The invention relates to a heat management method and system for a heterogeneous system-on-chip, and a vehicle. The heterogeneous system-on-chip comprises a micro-control unit core, a central processing unit core, a real-time clock and a power management module, the method is applied to the heterogeneous system-on-chip, and the method comprises the following steps: in response to starting of the micro-control unit core, acquiring the temperature of the micro-control unit core; in response to the fact that the temperature of the micro-control unit core is larger than a preset first threshold value, a first time threshold value is set for the real-time clock, and the power management module is controlled to power off the micro-control unit core; wherein after the micro-control unit core is powered off, when timing of the real-time clock reaches a first time threshold value, the real-time clock controls the power management module to power on the micro-control unit core; the micro-control unit core is started after being powered on; and controlling the central processing unit core to start in response to that the temperature of the micro-control unit core is not greater than the first threshold value. According to the invention, the starting of the HSoC can be controlled more accurately based on the internal temperature of the HSoC.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and more specifically, to a thermal management method, system and vehicle for a heterogeneous system-level chip. Background Art

[0002] With the rapid development of integrated circuit technology, heterogeneous system-on-chip (HSoC) has become a key technology for processing complex computing tasks and high performance requirements. HSoC can significantly improve computing efficiency and power consumption by integrating different types of processing units (such as CPU, GPU, DSP, etc.) on the same chip.

[0003] In actual applications, the temperature inside the automotive-grade HSoC generally does not exceed the set temperature, such as 125°C. When the set temperature is exceeded, it is necessary to shut down to protect the HSoC and the entire device. When the ambient temperature is high, such as above 85°C, the temperature inside the HSoC will rise faster, and the temperature will not cool down immediately after shutdown. At this time, if the external microcontroller controls the power supply to power on the HSoC, the temperature inside the HSoC may quickly reach 125°C and need to be shut down again. Therefore, due to the difference between the ambient temperature and the temperature inside the HSoC, controlling the startup of the HSoC based only on the ambient temperature may cause the HSoC to shut down and restart frequently. Summary of the invention

[0004] The present application is provided to solve the above problems existing in the prior art. According to the thermal management method, system and vehicle of the heterogeneous system-on-chip of the embodiments of the present application, the startup of the HSoC can be controlled more accurately based on the temperature inside the HSoC, avoiding frequent shutdown and restart of the HSoC.

[0005] In a first aspect, an embodiment of the present application provides a thermal management method for a heterogeneous system-level chip, wherein the heterogeneous system-level chip includes a microcontroller core, a central processing unit core, a real-time clock, and a power management module. The method is applied to the heterogeneous system-level chip, and the method includes:

[0006] In response to the microcontroller core being started, obtaining a temperature of the microcontroller core;

[0007] In response to the temperature of the microcontroller core being greater than a preset first threshold, a first time threshold is set for the real-time clock, and the power management module is controlled to power off the microcontroller core; wherein, after the microcontroller core is powered off and the real-time clock reaches the first time threshold, the real-time clock controls the power management module to power on the microcontroller core; and the microcontroller core is started after being powered on;

[0008] In response to the temperature of the micro control unit core being not greater than the first threshold, the central processing unit core is controlled to start up.

[0009] In a second aspect, an embodiment of the present application provides a thermal management system for a heterogeneous system-level chip, wherein the heterogeneous system-level chip includes a microcontroller core, a central processing unit core, a real-time clock, and a power management module. The system includes a thermal management device, which is applied to the heterogeneous system-level chip. The thermal management device includes:

[0010] an acquisition module, configured to acquire the temperature of the micro control unit core in response to the micro control unit core being started;

[0011] a control module configured to, in response to the temperature of the microcontroller core being greater than a preset first threshold, set a first time threshold for the real-time clock, and control the power management module to power off the microcontroller core; and, in response to the temperature of the microcontroller core being not greater than the first threshold, control the central processing unit core to start up;

[0012] Wherein, after the micro control unit core is powered off and the real-time clock reaches the first time threshold, the real-time clock controls the power management module to power on the micro control unit core; and the micro control unit core starts after being powered on.

[0013] In a third aspect, an embodiment of the present application provides a vehicle, comprising: a system as described in any of the above embodiments.

[0014] Any of the embodiments in the above application has the following advantages or beneficial effects: after the microcontroller core is started, if the temperature exceeds the first threshold, still starting the central processing unit core will further increase the internal temperature of the HSoC, causing the HSoC to shut down or be damaged. Therefore, the embodiment of the present application controls the microcontroller core to power off to reduce the temperature of the microcontroller core, and restarts the microcontroller core after an interval of the first time threshold, and detects again whether its temperature is higher than the first threshold, and does not start the central processing unit core until its temperature is no greater than the first threshold, thereby avoiding starting the HSoC when the internal temperature of the HSoC is high, causing the HSoC to shut down and restart frequently, or even be damaged. The embodiment of the present application controls the microcontroller core and the startup of the central processing unit core based on the temperature of the microcontroller core. The temperature of the microcontroller core belongs to the internal temperature of the HSoC. Compared with controlling the startup of the HSoC based on the ambient temperature of the HSoC, the control process is more accurate and improves the working stability of the HSoC. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In the drawings, which are not necessarily drawn to scale, the same reference numerals may describe similar parts in different views. The same reference numerals with letter suffixes or different letter suffixes may represent different instances of similar parts. The accompanying drawings generally illustrate various embodiments by way of example and not limitation, and together with the specification and claims, are used to illustrate the disclosed embodiments. When appropriate, the same reference numerals are used throughout the drawings to refer to the same or similar parts. Such embodiments are illustrative and are not intended to be exhaustive or exclusive embodiments of the present apparatus or method.

[0016] Figure 1 is a flow chart of a thermal management method for a heterogeneous system-on-chip provided by an embodiment of the present application;

[0017] Figure 2 is a flow chart of a thermal management method for a heterogeneous system-on-chip provided by another embodiment of the present application;

[0018] Figure 3 is a flow chart of a thermal management method for a heterogeneous system-on-chip provided by another embodiment of the present application;

[0019] Figure 4 is a flow chart of a thermal management method for a heterogeneous system-on-chip provided by yet another embodiment of the present application;

[0020] Figure 5 It is a schematic diagram of a thermal management device of a heterogeneous system-on-chip provided by an embodiment of the present application. DETAILED DESCRIPTION

[0021] In order to enable those skilled in the art to better understand the technical solution of the present application, the present application is described in detail below in conjunction with the accompanying drawings and specific embodiments. The embodiments of the present application are further described in detail below in conjunction with the accompanying drawings and specific embodiments, but are not intended to limit the present application. The terms "first", "second" and "third" used in the present application are only intended to distinguish the corresponding features, do not represent the need for such an order, and do not necessarily represent only the singular form.

[0022] like Figure 1 As shown, an embodiment of the present invention provides a thermal management method for a heterogeneous system-level chip, wherein the heterogeneous system-level chip includes a microcontroller core, a central processing unit core, a real-time clock, and a power management module. The method is applied to the heterogeneous system-level chip, and the method includes:

[0023] Step 101: In response to the microcontroller core being started, the temperature of the microcontroller core is acquired.

[0024] After HSoC is powered on, the MCU core starts. Since instruments and other systems run on the CPU core, if they are started at the same time as the MCU core, the internal temperature of HSoC may rise rapidly in a short period of time. In order to maintain the internal temperature of HSoC stable, the embodiment of the present application first controls the startup of the MCU core.

[0025] Step 102 : Determine whether the temperature of the microcontroller core is greater than a preset first threshold value, if yes, execute step 103 , otherwise, execute step 104 .

[0026] The first threshold can be set according to actual business requirements. For example, the first threshold is 100° C. or 95° C.

[0027] Step 103: Set a first time threshold for the real-time clock, and control the power management module to power off the micro control unit core.

[0028] After the microcontroller core is powered off and the real-time clock reaches the first time threshold, the real-time clock controls the power management module to power on the microcontroller core. The microcontroller core starts after being powered on.

[0029] The embodiment of the present application limits the power-off duration of the microcontroller core by a first time threshold, and the first time threshold can be a fixed value that is independent of the temperature of the microcontroller core, or can be determined based on the temperature of the microcontroller core. The first time threshold can be dynamically adjusted based on the temperature of the microcontroller core, so that the power management module can power on the microcontroller core in time, reducing the impact of the power-off of the microcontroller core on vehicle control.

[0030] After the microcontroller core is powered off, the HSoC enters a low power consumption mode, which can prevent the temperature inside the HSoC from rising further.

[0031] Step 104: Control the CPU core to start.

[0032] The microcontroller core may be a Cortex-M core or a Cortex-R core, etc., and the central processing unit core may be a Cortex-A core or a Cortex-M core, etc. The Android system and the instrument system are run on the central processing unit core, wherein the instrument system is a Linux system, etc.

[0033] Steps 101 to 104 may be performed in a microcontroller core. Specifically, FreeRTOS may be run in the microcontroller core, and the method may be implemented by deploying threads on FreeRTOS. FreeRTOS is a mini real-time operating system kernel. It should be noted that the method may also be implemented in a module independent of the central processing unit core and the microcontroller core.

[0034] If the temperature of the microcontroller core is not greater than the preset first threshold, it means that the internal temperature of the HSoC is within a controllable range, and the central processing unit core can be started.

[0035] After the microcontroller core is started, if the temperature exceeds the first threshold, still starting the central processing unit core will further increase the internal temperature of the HSoC, causing the HSoC to shut down or be damaged. Therefore, the embodiment of the present application controls the microcontroller core to power off to reduce the temperature of the microcontroller core, and restarts the microcontroller core after an interval of the first time threshold, and detects again whether its temperature is higher than the first threshold. The central processing unit core is not started until its temperature is no greater than the first threshold, thereby avoiding starting the HSoC when the internal temperature of the HSoC is high, causing the HSoC to shut down and restart frequently, or even be damaged. The embodiment of the present application controls the microcontroller core and the startup of the central processing unit core based on the temperature of the microcontroller core. The temperature of the microcontroller core belongs to the internal temperature of the HSoC. Compared with controlling the startup of the HSoC based on the ambient temperature of the HSoC, the control process is more accurate and improves the working stability of the HSoC.

[0036] After the central processing unit core is started, in order to ensure the stability of the internal temperature of HSoC, HSoC needs to be controlled based on the temperature of the central processing unit core. The following will take three different control strategies as examples to illustrate the control process. The specific control strategy can be selected according to the needs of the actual application scenario.

[0037] Strategy 1

[0038] In one embodiment of the present application, Figure 2 As shown, the method includes:

[0039] Step 201: In response to the microcontroller core being started, the temperature of the microcontroller core is acquired.

[0040] Step 202 : Determine whether the temperature of the microcontroller core is greater than a preset first threshold value, if yes, execute step 203 , otherwise, execute step 204 .

[0041] The first threshold can be set according to actual business requirements. For example, the first threshold is 100° C. or 95° C.

[0042] Step 203: Set a first time threshold for the real-time clock, and control the power management module to power off the micro control unit core.

[0043] Step 204: Control the CPU core to start.

[0044] Step 205: Obtain the temperature of the CPU core.

[0045] Step 206: Determine whether the temperature of the CPU core is greater than a preset second threshold value. If yes, execute step 207; otherwise, execute step 205 after a preset time interval.

[0046] Step 207: Send a control instruction to the micro control unit located outside the heterogeneous system-on-chip, so that the micro control unit located outside the heterogeneous system-on-chip controls the heterogeneous system-on-chip to power off based on the control instruction.

[0047] Among them, the second threshold is greater than the first threshold, and the second threshold can be adjusted based on the actual business scenario, such as the first threshold is 100°C and the second threshold is 125°C, or the first threshold is 90 and the second threshold is 120°C.

[0048] The embodiment of the present application controls the HSoC based on an external microcontroller unit, which can prevent the HSoC from being unable to power off by itself due to excessive temperature.

[0049] After controlling the heterogeneous system-level chip to be powered off, the external microcontroller unit can also obtain the temperature of the environment where the heterogeneous system-level chip is located, and determine whether the temperature of the environment where the heterogeneous system-level chip is located is less than a preset third threshold value. If so, the microcontroller unit core is controlled to be powered on, otherwise, the temperature of the environment where the heterogeneous system-level chip is located is obtained after a period of time. The third threshold value is less than the second threshold value.

[0050] After the heterogeneous system-level chip is powered off, the external microcontroller unit can restart the HSoC in time according to the temperature of the environment where the HSoC is located, reducing the impact of power-off on vehicle control.

[0051] The method can be implemented in a module independent of the central processing unit core and the micro control unit core, or can be implemented by the central processing unit core and the micro control unit core, such as steps 201-204 are executed in the micro control unit core, and steps 205-207 are executed in the central processing unit core.

[0052] Strategy 2

[0053] In one embodiment of the present application, Figure 3 As shown, the method includes:

[0054] Step 301: In response to the microcontroller core being started, the temperature of the microcontroller core is obtained.

[0055] Step 302 : Determine whether the temperature of the microcontroller core is greater than a preset first threshold, if yes, execute step 303 , otherwise, execute step 304 .

[0056] The first threshold can be set according to actual business requirements. For example, the first threshold is 100° C. or 95° C.

[0057] Step 303: Set a first time threshold for the real-time clock, and control the power management module to power off the micro control unit core.

[0058] Step 304: Control the CPU core to start.

[0059] Step 305: Obtain the temperature of the CPU core.

[0060] Step 306: Determine whether the temperature of the CPU core is greater than a preset second threshold value. If yes, execute step 307; otherwise, execute step 305 after a preset time interval.

[0061] Step 307: Control the power management module to power off the heterogeneous system-on-chip.

[0062] Specifically, the register of the power management module is configured so that the power management module powers off the heterogeneous system-level chip.

[0063] In the embodiment of the present application, the power management module can power off the heterogeneous system-on-chip in time to prevent the HSoC from being damaged due to overheating. Step 307 can also be replaced by: controlling the power management module to power off the central processing unit core. In other words, the power management module can only control the power off of the central processing unit core, or it can control the power off of the heterogeneous system-on-chip to prevent the temperature inside the HSoC from further increasing.

[0064] The method can be implemented in a module independent of the central processing unit core and the micro control unit core, or can be implemented by the central processing unit core and the micro control unit core, such as steps 301-304 are executed in the micro control unit core, and steps 305-307 are executed in the central processing unit core.

[0065] Strategy 3

[0066] In one embodiment of the present application, Figure 4 As shown, the method includes:

[0067] Step 401: In response to the microcontroller core being started, the temperature of the microcontroller core is acquired.

[0068] Step 402 : Determine whether the temperature of the microcontroller core is greater than a preset first threshold, if yes, execute step 403 , otherwise, execute step 404 .

[0069] The first threshold can be set according to actual business requirements. For example, the first threshold is 100° C. or 95° C.

[0070] Step 403: Set a first time threshold for the real-time clock and control the power management module to power off the micro control unit core.

[0071] Step 404: Control the CPU core to start.

[0072] Step 405: Obtain the temperature of the CPU core.

[0073] Step 406: Determine whether the temperature of the CPU core is greater than a preset second threshold value. If yes, execute step 407; otherwise, execute step 405 after a preset time interval.

[0074] Step 407: Set a second time threshold for the real-time clock, and control the power management module to power off the micro control unit core and the central processing unit core.

[0075] After the micro control unit core and the central processing unit core are powered off and the real-time clock timing reaches a second time threshold, the real-time clock controls the power management module to power on the micro control unit core.

[0076] Similar to the first time threshold, the embodiment of the present application limits the power-off duration of the microcontroller core through the second time threshold. The second time threshold can be a fixed value that is independent of the temperature of the microcontroller core, or can be determined based on the temperature of the microcontroller core. The second time threshold can be dynamically adjusted based on the temperature of the microcontroller core, so that the power management module can power on the microcontroller core in time, reducing the impact of the power-off of the microcontroller core on vehicle control.

[0077] In the embodiment of the present application, the control strategy for the central processing unit core is similar to that for the microcontroller core, that is, the temperature control of the central processing unit core is completed through the timing clock and the power management module. The embodiment of the present application controls the microcontroller core and the central processing unit core to power off through the power management module, so that the HSoC enters a low power consumption mode to prevent the temperature inside the HSoC from further increasing. At the same time, the microcontroller core is restarted through the timing clock to prevent the long-term power-off from affecting the operation of the vehicle.

[0078] Step 407 may also be replaced by: setting a second time threshold for the real-time clock, and controlling the power management module to power off the central processing unit core. That is, the power management module may control only the central processing unit core to power off, or may control both the microcontroller core and the central processing unit core to power off at the same time. In actual application scenarios, a specific control method may be selected according to business requirements.

[0079] The method can be implemented in a module independent of the central processing unit core and the micro control unit core, or can be implemented by the central processing unit core and the micro control unit core, such as steps 401-404 are executed in the micro control unit core, and steps 405-407 are executed in the central processing unit core.

[0080] It should be noted that for strategies 1-3, when the temperature of the CPU core is not greater than the preset second threshold, the method can also determine whether the temperature of the MCU core is greater than the preset first threshold after a preset time interval.

[0081] In one embodiment of the present application, the first time threshold is determined by the difference between the temperature of the microcontroller core and the first threshold. Specifically, the greater the difference between the temperature of the microcontroller core and the first threshold, the greater the first time threshold, such as the first time threshold is proportional to the difference. Considering that the greater the difference between the temperature of the microcontroller core and the first threshold, the higher the temperature of the microcontroller core, the longer the time it takes for the temperature to drop to the first time threshold, therefore, the embodiment of the present application determines the first time threshold based on the difference between the two, which can make the timing of restarting the microcontroller core more accurate, avoid frequent restarts of the microcontroller core, and reduce resource consumption. The second time threshold is similar to it and will not be repeated here.

[0082] like Figure 5 As shown, an embodiment of the present invention provides a thermal management device for a heterogeneous system-level chip, the heterogeneous system-level chip includes a microcontroller core, a central processing unit core, a real-time clock and a power management module, the thermal management device is applied to the heterogeneous system-level chip, and the thermal management device includes:

[0083] The acquisition module 501 is configured to acquire the temperature of the micro control unit core in response to the micro control unit core being started.

[0084] The control module 502 is configured to set a first time threshold for the real-time clock in response to the temperature of the microcontroller core being greater than a preset first threshold, and control the power management module to power off the microcontroller core; in response to the temperature of the microcontroller core being not greater than the first threshold, control the central processing unit core to start up.

[0085] After the microcontroller core is powered off and the real-time clock timing reaches a first time threshold, the real-time clock controls the power management module to power on the microcontroller core; and the microcontroller core is started after being powered on.

[0086] In one embodiment of the present application, the acquisition module 501 is configured to acquire the temperature of the core of the central processing unit.

[0087] The control module 502 is configured to send a control instruction to a microcontroller unit located outside the heterogeneous system-on-chip in response to the temperature of the central processing unit core being greater than a preset second threshold value, so that the microcontroller unit located outside the heterogeneous system-on-chip controls the power-off of the heterogeneous system-on-chip based on the control instruction; wherein the second threshold value is greater than the first threshold value.

[0088] In one embodiment of the present application, the acquisition module 501 is configured to acquire the temperature of the core of the central processing unit.

[0089] The control module 502 is configured to control the power management module to power off the heterogeneous system-on-chip in response to the temperature of the central processing unit core being greater than a preset second threshold.

[0090] The second threshold is greater than the first threshold.

[0091] In one embodiment of the present application, the acquisition module 501 is configured to acquire the temperature of the core of the central processing unit.

[0092] The control module 502 is configured to set a second time threshold for the real-time clock in response to the temperature of the central processing unit core being greater than a preset second threshold, and control the power management module to power off the micro control unit core and the central processing unit core.

[0093] Wherein, after the micro control unit core and the central processing unit core are powered off and the real-time clock timing reaches the second time threshold, the real-time clock controls the power management module to power on the micro control unit core.

[0094] An embodiment of the present invention provides a thermal management system for a heterogeneous system-on-chip, the system comprising any of the above-mentioned thermal management devices.

[0095] In one embodiment of the present application, the system further includes: a micro control unit located outside the heterogeneous system-level chip.

[0096] The acquisition module 501 is configured to acquire the temperature of the core of the central processing unit after the control module controls the core of the central processing unit to start;

[0097] The control module 502 is configured to send a control instruction to a microcontroller unit located outside the heterogeneous system-on-chip in response to the temperature of the central processing unit core being greater than a preset second threshold value;

[0098] A microcontroller unit located outside the heterogeneous system-on-chip, configured to control power-off of the heterogeneous system-on-chip based on a control instruction;

[0099] The second threshold is greater than the first threshold.

[0100] In one embodiment of the present application, a microcontroller unit located outside the heterogeneous system-level chip is configured to obtain the temperature of the environment where the heterogeneous system-level chip is located after controlling the heterogeneous system-level chip to be powered off, and in response to the temperature of the environment where the heterogeneous system-level chip is located being less than a preset third threshold, control the microcontroller unit core to be powered on;

[0101] The third threshold is smaller than the second threshold.

[0102] An embodiment of the present invention provides a vehicle, comprising: a system as described in any of the above embodiments.

[0103] An embodiment of the present application further provides a storage medium, which carries one or more computer programs. When the one or more computer programs are executed by a processor, the steps of the above method are implemented.

[0104] It should be understood that in the embodiments of the present application, the processor may be a central processing unit (CPU), and the processor may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc.

[0105] It should also be understood that the memory mentioned in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM) and direct RAM bus random access memory (DRRAM).

[0106] It should be noted that when the processor is a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic device, discrete hardware component, the memory (storage module) is integrated in the processor.

[0107] It should be noted that the memory described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0108] It should also be understood that the first, second, third, fourth and various numerical numbers involved in this document are only distinctions made for the convenience of description and are not intended to limit the scope of the present application.

[0109] In the implementation process, each step of the above method can be completed by an integrated logic circuit of hardware in a processor or an instruction in the form of software. The steps of the method disclosed in conjunction with the embodiment of the present application can be directly embodied as a hardware processor for execution, or a combination of hardware and software modules in a processor for execution. The software module can be located in a storage medium mature in the art such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium is located in a memory, and the processor reads the information in the memory and completes the steps of the above method in conjunction with its hardware. To avoid repetition, it is not described in detail here.

[0110] In various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0111] Those skilled in the art will appreciate that the various illustrative logical blocks (ILBs) and steps described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or in a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0112] In the several embodiments provided in the present application, it should be understood that the disclosed methods, devices and electronic devices can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0113] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0114] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0115] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integration. The available medium can be a magnetic medium, (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state hard disk), etc.

[0116] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A thermal management method for a heterogeneous system-on-chip, characterized in that: The heterogeneous system-level chip includes a microcontroller core, a central processing unit core, a real-time clock, and a power management module. The method is applied to the heterogeneous system-level chip, and the method includes: In response to the microcontroller core being started, obtaining a temperature of the microcontroller core; In response to the temperature of the microcontroller core being greater than a preset first threshold, a first time threshold is set for the real-time clock, and the power management module is controlled to power off the microcontroller core; wherein, after the microcontroller core is powered off and the real-time clock reaches the first time threshold, the real-time clock controls the power management module to power on the microcontroller core; and the microcontroller core is started after being powered on; In response to the temperature of the micro control unit core being not greater than the first threshold, the central processing unit core is controlled to start up.

2. The method according to claim 1, characterized in that After controlling the central processing unit core to start, further comprising: Obtaining the temperature of the central processing unit core; In response to the temperature of the central processing unit core being greater than a preset second threshold, sending a control instruction to a microcontroller unit located outside the heterogeneous system-on-chip, so that the microcontroller unit located outside the heterogeneous system-on-chip controls the heterogeneous system-on-chip to power off based on the control instruction; The second threshold is greater than the first threshold.

3. The method according to claim 1, characterized in that After controlling the central processing unit core to start, further comprising: Obtaining the temperature of the central processing unit core; In response to the temperature of the central processing unit core being greater than a preset second threshold, controlling the power management module to power off the heterogeneous system-on-chip; The second threshold is greater than the first threshold.

4. The method according to claim 1, characterized in that After controlling the central processing unit core to start, further comprising: Obtaining the temperature of the central processing unit core; In response to the temperature of the central processing unit core being greater than a preset second threshold, setting a second time threshold for the real-time clock, and controlling the power management module to power off the micro control unit core and the central processing unit core; Wherein, after the micro control unit core and the central processing unit core are powered off and the real-time clock timing reaches the second time threshold, the real-time clock controls the power management module to power on the micro control unit core.

5. The method according to claim 1, characterized in that The first time threshold is determined by a difference between the temperature of the micro control unit core and the first threshold.

6. The method according to claim 4, characterized in that The second time threshold is determined by a difference between the temperature of the CPU core and the second threshold.

7. A thermal management system for a heterogeneous system-on-chip, characterized in that: The heterogeneous system-level chip includes a microcontroller core, a central processing unit core, a real-time clock and a power management module. The system includes a thermal management device, which is applied to the heterogeneous system-level chip. The thermal management device includes: an acquisition module, configured to acquire the temperature of the micro control unit core in response to the micro control unit core being started; a control module configured to, in response to the temperature of the microcontroller core being greater than a preset first threshold, set a first time threshold for the real-time clock, and control the power management module to power off the microcontroller core; and, in response to the temperature of the microcontroller core being not greater than the first threshold, control the central processing unit core to start up; Wherein, after the micro control unit core is powered off and the real-time clock reaches the first time threshold, the real-time clock controls the power management module to power on the micro control unit core; and the micro control unit core starts after being powered on.

8. The system according to claim 7, characterized in that Further including: A microcontroller unit located outside the heterogeneous system-on-chip; The acquisition module is configured to acquire the temperature of the central processing unit core after the control module controls the central processing unit core to start; The control module is configured to send a control instruction to a microcontroller unit located outside the heterogeneous system-on-chip in response to the temperature of the central processing unit core being greater than a preset second threshold; A microcontroller unit located outside the heterogeneous system-on-chip, configured to control power-off of the heterogeneous system-on-chip based on the control instruction; The second threshold is greater than the first threshold.

9. The system according to claim 8, characterized in that A microcontroller unit located outside the heterogeneous system-on-chip is configured to obtain a temperature of an environment where the heterogeneous system-on-chip is located after controlling the heterogeneous system-on-chip to be powered off, and control the microcontroller core to be powered on in response to the temperature of the environment where the heterogeneous system-on-chip is located being less than a preset third threshold; The third threshold is smaller than the second threshold.

10. A vehicle, characterized in that: include: A system as claimed in any one of claims 7 to 9.

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