Simulation waveform acquisition method and device, equipment and storage medium

Abstract

The invention relates to a simulation waveform acquisition method, device and equipment and a storage medium, and is applied to the field of software and hardware co-simulation, and the method comprises the following steps: receiving configuration information sent by a software side through an SCEMI protocol, and starting simulation waveform sampling of a current clock period; analyzing the macro configuration information, generating macro configuration analysis information, and distributing the macro configuration analysis information to a plurality of probe processing modules; controlling each probe processing module to sample simulation waveform data, performing waveform compression on simulation waveforms sampled by each probe processing module, and generating a plurality of compressed simulation waveforms; all the compressed simulation waveforms are stored in a DDR memory; and when the storage capacity of the DDR memory reaches an upper limit, transmitting the compressed simulation waveform stored in the DDR memory to a software side through an SCEMI protocol. The technical effect of the invention is that flexibility and simulation verification efficiency based on hardware simulation accelerator verification are improved.

Description

Technical Field

[0001] The present application relates to the technical field of software-hardware collaborative simulation, and in particular to a simulation waveform acquisition method, device, equipment and storage medium. Background Art

[0002] As the scale of integrated circuits continues to expand, the time spent on chip verification is increasing. In addition to traditional simulators, emulators based on software-hardware collaboration are becoming more and more common, improving verification efficiency through software-hardware collaborative simulation verification.

[0003] In hardware-software co-simulation, Probe / trigger (hardware breakpoint function) / GetValue (internal value of DUT) are the most common debugging methods. The software completes the configuration of the basic unit (macro) on the hardware side through the SCEMI protocol (SCE-MI: Standard Co-EmulationModeling Interface) to achieve the purpose of debug signal. Traditional AMD and Intel FPGA manufacturers both provide FPGA online logic analyzers to provide convenience for observing waveforms for FPGA debugging. The SCEMI protocol is a standard interface protocol for hardware-software interaction, mainly used in hardware-software co-verification environments to achieve seamless communication and data interaction between software models and hardware simulators.

[0004] However, when using the original online logic analyzer to capture simulation waveforms, they need to be exported to the host computer through JTAG. Due to the slow transmission speed of JTAG, the simulation verification speed may be greatly reduced, thereby reducing the efficiency of the simulation. Summary of the invention

[0005] In order to help solve the problem that when using the original online logic analyzer to capture simulation waveforms, they need to be exported to the host computer through JTAG. Due to the slow JTAG transmission speed, the simulation verification speed may be greatly reduced, which in turn leads to low simulation efficiency. The present application provides a simulation waveform acquisition method, device, equipment and storage medium.

[0006] In a first aspect, the present application provides a simulation waveform acquisition method, which adopts the following technical solution: the method is applied to the hardware side of a simulation waveform acquisition system, the hardware side of the simulation waveform acquisition system includes a DDR memory and several probe processing modules, and the method includes: Receive the sampling start signal, clock control information and macro configuration information sent by the software side through the SCEMI protocol, and start the simulation waveform sampling of the current clock cycle; Parsing the macro configuration information and generating macro configuration parsing information, and distributing the macro configuration parsing information to a plurality of the probe processing modules; Controlling each of the probe processing modules to sample simulation waveform data, respectively compressing the simulation waveform sampled by each of the probe processing modules, and generating a plurality of compressed simulation waveforms; Storing all the compressed simulation waveforms in the DDR memory; When the storage capacity of the DDR memory reaches the upper limit, the compressed simulation waveform stored in the DDR memory is transmitted to the software side through the SCEMI protocol.

[0007] In a specific implementation scheme, the macro configuration parsing information includes macro identification information, and the distributing the macro configuration parsing information to the plurality of probe processing modules includes: The macro configuration parsing information is distributed to the corresponding probe processing module according to the macro identification information.

[0008] In a specific implementation scheme, the current clock cycle contains several frames of simulation waveform data, and the simulation waveforms sampled by each probe processing module are respectively compressed to generate several compressed simulation waveforms, including: Determine the data frame format of the simulation waveform, the data frame format of the simulation waveform includes I frame and P frame; If the data frame format of the simulation waveform is an I frame, two adjacent sets of preset bit data in the data frame of the current simulation waveform are compared bit by bit in sequence, and the data that are inconsistent with the comparison are stored to generate the compressed simulation waveform; If the data frame format of the simulation waveform is a P frame, the data of the simulation waveforms of two adjacent frames are compared bit by bit in sequence, and the data that are inconsistent with the comparison are stored to generate the compressed simulation waveform.

[0009] In a specific implementation scheme, after respectively compressing the simulation waveforms sampled by each of the probe processing modules and generating a plurality of compressed simulation waveforms, the method further includes: Controlling each of the probe processing modules to output a sampling completion signal; All the sampling completion signals are ANDed and calculated, and the results of the sampling completion signals after the ANDing calculation are transmitted to the software side.

[0010] In a specific implementation scheme, the hardware side of the simulation waveform acquisition system further includes a merging module, and before storing the compressed simulation waveform in the DDR memory, further includes: Merging the compressed simulation waveforms into one channel of data in sequence, and generating a merged simulation waveform; Wherein, the size of the compressed simulation waveform is consistent with the interface bit width of the DDR memory; The storing of all the compressed simulation waveforms into the DDR memory comprises: The combined simulation waveform is stored in the DDR memory.

[0011] In a specific possible implementation scheme, the hardware side of the simulation waveform acquisition system further includes a breakpoint module; While distributing the macro configuration parsing information to the plurality of probe processing modules, the macro configuration parsing information is transmitted to the breakpoint module.

[0012] In a specific possible implementation scheme, the hardware side of the simulation waveform acquisition system further includes a breakpoint waveform acquisition module; After respectively compressing the simulation waveforms sampled by each of the probe processing modules and generating a plurality of compressed simulation waveforms, the method further includes: Transmitting a plurality of the compression simulation waveforms to the breakpoint module, and controlling the breakpoint module to generate breakpoint signals corresponding to the compression simulation waveforms according to the macro configuration parsing information; Using the breakpoint waveform acquisition module to generate a breakpoint simulation waveform according to the breakpoint signal; The storing of all the compressed simulation waveforms into the DDR memory comprises: The breakpoint simulation waveform is stored in the DDR memory.

[0013] In a second aspect, the present application provides a simulation waveform acquisition device, which adopts the following technical solution: the device is applied to the hardware side of the simulation waveform acquisition system, the hardware side of the simulation waveform acquisition system includes a DDR memory and several probe processing modules, and the device includes: The information receiving module is used to receive the sampling start signal, clock control information and macro configuration information sent by the software side through the SCEMI protocol, and start the simulation waveform sampling of the current clock cycle; An information parsing module, used to parse the macro configuration information and generate macro configuration parsing information, and distribute the macro configuration parsing information to a number of the probe processing modules; A waveform sampling module, used for controlling each of the probe processing modules to sample simulation waveform data, respectively compressing the simulation waveform sampled by each of the probe processing modules, and generating a plurality of compressed simulation waveforms; A waveform storage module, used for storing all the compressed simulation waveforms into the DDR memory; The waveform transmission module is used to transmit the compressed simulation waveform stored in the DDR memory to the software side through the SCEMI protocol when the storage capacity of the DDR memory reaches an upper limit.

[0014] In a third aspect, the present application provides a computer device, which adopts the following technical solution: it includes a memory and a processor, and the memory stores a computer program that can be loaded by the processor and execute any of the above-mentioned simulation waveform acquisition methods.

[0015] In a fourth aspect, the present application provides a computer-readable storage medium, which adopts the following technical solution: storing a computer program that can be loaded by a processor and execute any of the above-mentioned simulation waveform acquisition methods.

[0016] In summary, this application has the following beneficial technical effects: The simulation waveform is obtained through the hardware-software co-simulation to realize the simulation verification of the chip. On the hardware side, the simulation waveform is sampled by configuring the probe processing module, and the sampled waveform data is stored in the DDR memory. Then the data in the DDR memory is read and transmitted to the software side through the SCEMI protocol for decoding and display. The whole method process does not involve the use of JTAG to capture the waveform and the transmission of the waveform. The probe processing module is used to sample the simulation waveform and output the data to the DDR memory, which can improve the access efficiency inside the hardware, thereby improving the simulation verification efficiency, and can greatly improve the flexibility of the verification method based on the hardware simulation accelerator. In addition, waveform compression of the sampled waveform data can improve the utilization rate of the DDR memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a flow chart of a simulation waveform acquisition method in an embodiment of the present application; Figure 2 It is a schematic diagram of the process framework of the simulation waveform acquisition method in the embodiment of the present application; Figure 3 It is a schematic diagram of the internal structure of a single macro module in an embodiment of the present application; Figure 4 This is a schematic diagram of multiple macro modules being aggregated in parallel in an embodiment of the present application; Figure 5 It is a schematic diagram of the framework of the simulation waveform acquisition system in the embodiment of the present application; Figure 6 is a schematic diagram of a simulation waveform acquisition device in an embodiment of the present application; Figure 7 It is a schematic diagram used to embody a computer device in an embodiment of the present application.

[0018] Reference numerals: 601, information receiving module; 602, information parsing module; 603, waveform sampling module; 604, waveform storage module; 605, waveform transmission module. DETAILED DESCRIPTION

[0019] The following combination Figure 1-Figure 7 This application is described in further detail.

[0020] The embodiment of the present application discloses a simulation waveform acquisition method, which is applied to the hardware side of the simulation waveform acquisition system, and realizes the acquisition of the simulation waveform inside the chip through the method of software-hardware co-simulation, thereby realizing the verification of the chip. Chip verification is a key link in the chip design process. By verifying the chip and timely discovering and correcting defects in the chip manufacturing process, it can ensure that the chip design meets the predetermined functional, performance and reliability requirements. At present, the method of software-hardware co-simulation verification is becoming more and more common, and software-hardware co-simulation can improve the efficiency of chip verification.

[0021] In hardware-software co-simulation, Probe / trigger (hardware breakpoint function) / GetValue (internal value of DUT) are the most common debugging methods; among them, the waveform obtained by the probe probe can be understood as obtaining the complete simulation waveform, the trigger hardware breakpoint function obtains a partial waveform, and the user can specify the start breakpoint and the end breakpoint, and GetValue obtains the specific value inside the DUT; in the present application scheme, the simulation waveform acquisition method in the present application scheme can be used to obtain the complete simulation waveform (probe waveform) and the partial simulation waveform of the breakpoint (trigger waveform), and the specific value inside the DUT (GetValue) can also be obtained. The software side completes the configuration of the basic unit (macro) on the hardware side through the SCEMI protocol to achieve the purpose of debug signal; the hardware side generally uses FPGA, and macro is the smallest processing unit of the probe module. Traditional AMD and Intel FPGA manufacturers have provided FPGA online logic analyzers to provide convenience for observing waveforms for FPGA debugging.

[0022] However, when using the original online logic analyzer to capture the simulation waveform, it needs to be exported to the host computer through JTAG. Due to the slow transmission speed of JTAG, the simulation verification speed may be greatly reduced, which in turn leads to reduced simulation efficiency. In addition, the data waveform is stored in the on-chip RAM, which requires balancing the storage resources occupied by the user design (DUT), and there are restrictions on the bit width and depth of the captured signal. In order to help improve the efficiency of chip simulation verification, this application provides a simulation waveform acquisition method.

[0023] Reference Figure 1 , the method comprises the following steps: S10, receiving the sampling start signal, clock control information and macro configuration information sent by the software side through the SCEMI protocol, and starting the simulation waveform sampling of the current clock cycle.

[0024] Specifically, in the embodiment of the present application, the simulation verification of the chip adopts the verification method of software-hardware co-simulation, which includes the software side and the hardware side. The software side can be a host computer and the hardware side can be an FPGA. The software side sends the clock control information, sampling start signal and macro configuration information to the hardware side through the SCEMI protocol. After the hardware side receives the sampling start signal sent by the software side, it stops the clock advancement and starts sampling the simulation waveform of the current clock cycle.

[0025] S20, parse the macro configuration information and generate macro configuration parsing information, and distribute the macro configuration parsing information to a plurality of macro modules.

[0026] Specifically, refer to Figure 2 , the hardware side includes an instruction distribution module (cmd_split module) and several macro modules; in an FPGA, there can be multiple macro modules running and processing data. In the flowchart of the embodiment of the present application, only two macro modules are used as examples for illustration, and the number of macros used in actual applications is not limited here, and users can set it according to actual task requirements. The software side sends the clock control information and macro configuration information to the instruction distribution module on the hardware side through the SCEMI protocol. After receiving the macro configuration information, the instruction distribution module parses the configuration information and generates macro configuration parsing information; wherein, the macro configuration parsing information includes macro identification information. The system can match the identification information obtained by parsing with the macro modules in the hardware design of the system one by one, and transmit the parsed macro configuration parsing information to the corresponding macro module, so that the macro module can sample and process the simulation waveform according to the corresponding parsing information.

[0027] Reference Figure 3, which is a schematic diagram of the internal structure of a single macro module. The DUT signals (user's design signals to be tested) are grouped according to any specified signal width (parameterized design is possible, and the signal width that is less than the set width is filled with 0), and each group is processed by a macro. The software side completes the macro configuration through the SCEMI protocol, and determines whether each function is enabled based on the flag bit. The functions can be divided into Probe / Trigger / GetValue, and the enabled function category is determined by judging the mask configuration of the corresponding function; for example, flag[0] means getting the value inside the DUT, that is, GetValue, flag[1] means the breakpoint simulation waveform, that is, the trigger waveform, and flag[2] means the probe waveform, that is, the probe waveform. Setting the required bit position to 1 can enable the function corresponding to the bit position, and all types of mask values ​​are written into the mask memory according to the address. GetValue obtains the specific value inside the DUT, and uploads it to the software side through the SCEMI protocol after removing the foam operation (RemoveFoam) and then through the parallel convergence. Trigger is transmitted to the breakpoint waveform acquisition module for processing through the parallel convergence after removing the foam operation (RemoveFoam), and directly controls the start and stop of the clock. Among them, the foam removal operation (RemoveFoam) can be understood as removing data that does not need to be paid attention to, and only paying attention to the data that the user needs to pay attention to. For example, in the data composed of 0 values ​​and 1 values, only 1 value is left through the foam removal operation, and the data composed of 1 value is the data that the user needs to pay attention to. Refer to Figure 4 , which is a schematic diagram of the parallel aggregation of multiple macro modules.

[0028] When the macro module on the hardware side is running, the software sends a configuration completion signal through the SCEMI protocol, which enables the logic to be self-sorted and dynamically utilize RAM space to improve access efficiency. Secondly, a pipeline processing structure is used to store the filtered data. In addition, multiple configurations are allowed during operation, and the data message contains configuration change information. Combined with the waveform decoding program, multiple captured waveforms can be decoded at one time.

[0029] S30, controlling each macro module to sample simulation waveform data, respectively compressing the simulation waveform sampled by each macro module, and generating a plurality of compressed simulation waveforms.

[0030] Specifically, the system controls each macro module to sample and store simulation waveform data. Specifically, the sampled simulation waveform data is written into the FIFO memory inside the macro module, and then the simulation waveform sampled by each macro module is respectively compressed to generate a number of compressed simulation waveforms. By reducing the waveform data through data compression, the utilization rate of the DDR memory can be improved when it is stored in the DDR memory.

[0031] S40, storing all compressed simulation waveforms into the DDR memory.

[0032] Specifically, the sampled compressed simulation waveform is transmitted to the DDR memory. The specific transmission and storage method can be that the hardware side design includes a DDR read-write control module, first transmitting the compressed simulation waveform to the DDR read-write control module, and then transmitting the waveform data in the DDR read-write control module to the DDR memory.

[0033] S50, when the storage capacity of the DDR memory reaches the upper limit, the compressed simulation waveform stored in the DDR memory is transmitted to the software side through the SCEMI protocol.

[0034] Specifically, when the storage capacity of the DDR memory reaches the upper limit, it can also be understood that when the DDR memory capacity is full, the data in the DDR memory is read out, and then the compressed simulation waveform stored in the DDR memory is transmitted to the software side through the SCEMI protocol. Since the simulation waveform stored on the hardware side is a compressed simulation waveform, after the waveform is transmitted to the software side, the user can decode the compressed simulation waveform according to known rules on the software side, thereby obtaining a complete simulation waveform for the user to view and analyze.

[0035] In the present application scheme, simulation waveforms are obtained through software and hardware collaborative simulation to realize simulation verification of the chip. On the hardware side, the sampling of the simulation waveform is realized by configuring the macro module, and the waveform data obtained by sampling is stored in the DDR memory, and then the data in the DDR memory is read and transmitted to the software side through the SCEMI protocol for decoding and display. The whole method process does not involve the use of JTAG to capture the waveform and the transmission of the waveform. The macro module is used to sample the simulation waveform and output the data to the DDR memory, which can improve the access efficiency inside the hardware, thereby improving the simulation verification efficiency, and can greatly improve the flexibility of the verification method based on the hardware simulation accelerator. In addition, waveform compression of the sampled waveform data can improve the utilization rate of the DDR memory.

[0036] In one embodiment, multiple frames of simulation waveform data are sampled in each clock cycle, and the simulation waveform sampled by each macro module is respectively compressed, and the steps of generating a plurality of compressed simulation waveforms can be specifically performed as follows: First, determine the data frame format of the simulation waveform, which includes I frame and P frame, and perform waveform compression according to the determined data frame format; wherein, I frame represents key frame, and P frame represents difference frame. If the data frame format of the simulation waveform is I frame, the two adjacent groups of preset bit data in the data frame of the current simulation waveform are compared bit by bit, and the data with inconsistent comparison is stored and a compressed simulation waveform is generated; for example, assuming that a frame of simulation waveform data contains 512-bit data, the 512-bit data is divided into 32-bit groups, and then the two adjacent groups of 32-bit data in a data frame are compared, and the inconsistent data is recorded and stored in the FIFO memory. If the data with consistent comparison is not recorded, it is avoided as much as possible to avoid repeated writing of the same data and occupying the memory of the DDR memory. If the data frame format of the simulation waveform is a P frame, the data of the simulation waveforms of two adjacent frames are compared bit by bit, and the inconsistent data are stored and a compressed simulation waveform is generated; specifically, the data of the current data frame and the data at the corresponding position of the previous data frame are compared bit by bit, and the inconsistent data are stored and a compressed simulation waveform is generated, thereby avoiding repeated writing of the same data and occupying the memory of the DDR memory to the greatest extent.

[0037] In the present application scheme, after data sampling, the waveform obtained by sampling is compressed, so as to avoid as much as possible the repeated data in the adjacent cycles from being written into the DDR memory, occupying the memory of the DDR memory, so that more data can be stored in the DDR memory for subsequent transmission to the software side for analysis and verification.

[0038] In one embodiment, after the simulation waveforms sampled by each macro module are respectively compressed and a plurality of compressed simulation waveforms are generated, the following steps may be performed: When the macro module simulation waveform sampling is completed and the waveform compression process is completed, the system controls each macro module to output a sampling completion signal. For example, the output sampling completion signal is a sample_done signal. When the sample_done signal value is 0, it indicates that the macro module sampling is not completed. When the sample_done signal value is 1, it indicates that the macro module sampling is completed. After that, all sampling completion signals are ANDed and the result of the sampling completion signal after the AND calculation is transmitted to the software side; AND calculation is performed. If all macro modules are sampled, the result of the AND calculation should be 1. The result of the AND calculation is transmitted to the software side. When the sampling completion signal received by the software side is 1, the software side can know that the simulation waveform sampling of the current clock cycle of the hardware side is completed, and the subsequent clock can continue to advance, and the sampling work of the next clock cycle can be performed; if the result of the AND calculation is 0, it means that at least one macro module has not completed the sampling. The sampling completion signal received by the software side is 0, and the sampling work of the next cycle will not be entered.

[0039] In the present application scheme, each macro module sends a sampling completion signal after the sampling is completed, and the sampling completion signals sent by all macro modules are calculated. The software side can judge whether all macro modules have completed sampling and can enter the sampling work of the next clock cycle based on the calculation results, thereby ensuring the normal operation of the clock cycle during internal operation, and there will be no confusion between adjacent clock cycles. It can also avoid as much as possible the confusion of the sampling simulation waveform caused by the failure of macro sampling to complete.

[0040] In one embodiment, the hardware side of the simulation waveform acquisition system further includes a merging module. Before storing the compressed simulation waveform in the DDR memory, the following steps may be performed: After the compressed simulation waveform is output through the macro module, the compressed simulation waveform is merged into one data in sequence and a merged simulation waveform is generated. Figure 2, each compressed simulation waveform is merged through a merging module. Among them, the size of the compressed simulation waveform is consistent with the interface bit width of the DDR memory. It can also be understood that when configuring the macro module, the data size output by the macro module is determined according to the interface bit width of the DDR memory; for example, since the interface bit width of the DDR memory is 512 bits, the data size output by the macro module is set to 512 bits, and multiple 512-bit data is merged into one signal and stored in the DDR memory, so that the DDR memory can run at full bandwidth, improve the operating efficiency of the DDR memory, thereby improving the efficiency of waveform acquisition, and then improve the efficiency of chip verification. Storing all compressed simulation waveforms in the DDR memory includes: storing the merged simulation waveform in the DDR memory.

[0041] In the present application scheme, the multi-channel compressed simulation waveforms output by each macro module are merged into one channel through a merging module. The design of the data size output by the macro module and the interface bit width of the DDR memory is consistent, so that the DDR memory can run at full bandwidth, thereby improving the operating efficiency of the DDR memory, improving the efficiency of waveform acquisition, and further improving the efficiency of chip simulation verification.

[0042] In one embodiment, the hardware side of the simulation waveform acquisition system also includes a breakpoint module and a breakpoint waveform acquisition module; while distributing the macro configuration parsing information to a number of macro modules, the macro configuration parsing information is transmitted to the breakpoint module.

[0043] After the simulation waveforms sampled by each macro module are respectively compressed and a number of compressed simulation waveforms are generated, the following steps may be performed: A number of compressed simulation waveforms are transmitted to the breakpoint module, and the breakpoint module is controlled to generate a breakpoint signal corresponding to the compressed simulation waveform according to the macro configuration parsing information. The macro configuration parsing information includes the breakpoint information required by the user. The breakpoint module can generate the corresponding breakpoint signal according to the parsed configuration information. Afterwards, a breakpoint simulation waveform, also known as a trigger waveform, is generated according to the breakpoint signal using the breakpoint waveform acquisition module. It can also be understood that the user can define the start point and the end point in advance, and the corresponding breakpoint signal is generated by the breakpoint module. Afterwards, the breakpoint waveform acquisition module generates the partial simulation waveform required by the user according to the breakpoint signal. Afterwards, storing all compressed simulation waveforms in the DDR memory includes: storing the breakpoint simulation waveform in the DDR memory.

[0044] In the present application scheme, during the actual chip simulation and verification process, the user may not need to analyze the entire waveform. Therefore, the user can only obtain part of the simulation waveform and analyze it, and obtain part of the simulation waveform from the sampled entire simulation waveform through breakpoints to flexibly meet user needs, thereby improving the flexibility of simulation waveform acquisition and work efficiency.

[0045] It should be noted that in the embodiment of the present application, the above method can be used to obtain a complete simulation waveform (probe), as well as a partial simulation waveform (trigger) defined by the user. In addition, the specific data value inside the DUT can be obtained (GetValue). The GetValue acquisition method can directly obtain the value inside the DUT through the macro module, and then it can be directly transmitted to the software side for the user to view or use.

[0046] Reference Figure 5 , which is a schematic diagram of the framework of the simulation waveform acquisition system in the embodiment of the present application. After the DUT design is comprehensively processed, an EDIF file is generated, and the EDIF (Electronic Design Interchange Format) file is also a netlist file; the hardware side constructs a top-level EDIF file, and can provide the netlist files of each module and the interconnection information between each module. The software side instantiates the internal netlist of each module into a specific instance and adds it to the top level; in addition, for the probe signal, any bit data can be connected in sequence as a group. The entire hardware system parses and distributes the configuration information through the instruction distribution module, and samples the simulation waveform through several probe processing units, that is, several macro modules, and compresses the sampled waveform. After that, the multiple data channels are merged into one data channel through the merging module, and then transmitted to the DDR memory through the DDR read-write control module. Among them, the data of the complete simulation waveform is output through the macro module. In addition, the user can perform secondary processing of the acquisition value and secondary processing of the breakpoint according to actual needs, that is, to obtain the specific value inside the DUT or to obtain the breakpoint waveform defined by the user. The user can flexibly choose, which enhances the flexibility of the solution.

[0047] Figure 1 FIG. 1 is a flow chart of a simulation waveform acquisition method in one embodiment. It should be understood that although Figure 1 The steps in the flowchart are shown in sequence as indicated by the arrows, but the steps are not necessarily executed in the order indicated by the arrows; unless otherwise specified in this document, there is no strict order restriction for the execution of the steps, and the steps may be executed in other orders; and Figure 1At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0048] Based on the above method, an embodiment of the present application also discloses a simulation waveform acquisition device.

[0049] Reference Figure 6 , the device includes the following modules: The information receiving module 601 is used to receive the sampling start signal, clock control information and macro configuration information sent by the software side through the SCEMI protocol, and start the simulation waveform sampling of the current clock cycle; The information parsing module 602 is used to parse the macro configuration information and generate macro configuration parsing information, and distribute the macro configuration parsing information to a number of macro modules; The waveform sampling module 603 is used to control each macro module to sample simulation waveform data, compress the simulation waveform sampled by each macro module, and generate a plurality of compressed simulation waveforms; The waveform storage module 604 is used to store all compressed simulation waveforms into the DDR memory; The waveform transmission module 605 is used to transmit the compressed simulation waveform stored in the DDR memory to the software side through the SCEMI protocol when the storage capacity of the DDR memory reaches the upper limit.

[0050] In one embodiment, the information parsing module 602 is specifically used to distribute the macro configuration parsing information to the corresponding macro module according to the macro identification information.

[0051] In one embodiment, the waveform sampling module 603 is specifically used to determine the data frame format of the simulation waveform, and the data frame format of the simulation waveform includes I frame and P frame; if the data frame format of the simulation waveform is I frame, the two adjacent groups of preset bit data in the data frame of the current simulation waveform are compared bit by bit, and the inconsistent data are stored and a compressed simulation waveform is generated; if the data frame format of the simulation waveform is P frame, the data of the simulation waveform of two adjacent frames are compared bit by bit, and the inconsistent data are stored and a compressed simulation waveform is generated.

[0052] In one embodiment, the waveform sampling module 603 is also used to control each macro module to output a sampling completion signal; perform AND calculation on all sampling completion signals, and transmit the result of the AND calculation of the sampling completion signal to the software side.

[0053] In one embodiment, the waveform transmission module 605 is also used to merge the compressed simulation waveforms into one data path in sequence and generate a merged simulation waveform; wherein the size of the compressed simulation waveform is consistent with the interface bit width of the DDR memory; storing all compressed simulation waveforms in the DDR memory includes: storing the merged simulation waveform in the DDR memory.

[0054] In one embodiment, the information parsing module 602 is further used to transmit the macro configuration parsing information to the breakpoint module while distributing the macro configuration parsing information to a plurality of macro modules.

[0055] In one embodiment, the waveform sampling module 603 is also used to transmit a number of compressed simulation waveforms to the breakpoint module, and control the breakpoint module to generate a breakpoint signal corresponding to the compressed simulation waveform according to the macro configuration parsing information; use the breakpoint waveform acquisition module to generate a breakpoint simulation waveform according to the breakpoint signal; store all compressed simulation waveforms in the DDR memory, including: storing the breakpoint simulation waveform in the DDR memory.

[0056] The simulation waveform acquisition device provided in the embodiment of the present application can be applied to the simulation waveform acquisition method provided in the above embodiment. For relevant details, refer to the above method embodiment. The implementation principle and technical effect are similar and will not be repeated here.

[0057] It should be noted that: when the simulation waveform acquisition device provided in the embodiment of the present application performs simulation waveform acquisition, only the division of the above-mentioned functional modules / functional units is used as an example for illustration. In actual applications, the above-mentioned functions can be assigned to different functional modules / functional units as needed, that is, the internal structure of the simulation waveform acquisition device is divided into different functional modules / functional units to complete all or part of the functions described above. In addition, the implementation method of the simulation waveform acquisition method provided in the above-mentioned method embodiment and the implementation method of the simulation waveform acquisition device provided in this embodiment belong to the same concept. The specific implementation process of the simulation waveform acquisition device provided in this embodiment is detailed in the above-mentioned method embodiment, which will not be repeated here.

[0058] The embodiment of the present application also discloses a computer device.

[0059] Specifically, if Figure 7As shown, the computer device can be a computer device such as a desktop computer, a laptop computer, a PDA, and a cloud server. The computer device may include, but is not limited to, a processor and a memory. The processor and the memory may be connected via a bus or other means. The processor may be a central processing unit (CPU). The processor may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, graphics processors (GPU), embedded neural network processors (NPU) or other dedicated deep learning coprocessors, discrete gates or transistor logic devices, discrete hardware components and other chips, or a combination of the above chips.

[0060] As a non-transient computer-readable storage medium, the memory can be used to store non-transient software programs, non-transient computer executable programs and modules, such as program instructions / modules corresponding to the methods in the above-mentioned embodiments of the present application. The processor executes various functional applications and data processing of the processor by running the non-transient software programs, instructions and modules stored in the memory, that is, the method in the above-mentioned method implementation is realized. The memory may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created by the processor, etc. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some embodiments, the memory may optionally include a memory remotely arranged relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network and a combination thereof.

[0061] The embodiment of the present application also discloses a computer-readable storage medium.

[0062] Specifically, the computer-readable storage medium is used to store a computer program, and when the computer program is executed by the processor, the method in the above-mentioned method implementation is implemented. Those skilled in the art can understand that the implementation of all or part of the process in the above-mentioned implementation method of the present application can be completed by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium. When the program is executed, it may include the process of the implementation of the above-mentioned methods. Among them, the storage medium can be a disk, an optical disk, a read-only memory (ROM), a random access memory (RAM), a flash memory (Flash Memory), a hard disk (Hard Disk Drive, abbreviated: HDD) or a solid-state drive (SSD), etc.; the storage medium can also include a combination of the above-mentioned types of memory.

[0063] This specific embodiment is merely an explanation of the present invention and is not a limitation of the present invention. After reading this specification, those skilled in the art may make non-creative modifications to the present embodiment as needed. However, as long as they are within the scope of the claims of the present invention, they are protected by the patent law.

Claims

1. A simulation waveform acquisition method, characterized in that: The method is applied to the hardware side of the simulation waveform acquisition system, the hardware side of the simulation waveform acquisition system includes a DDR memory and several probe processing modules, the probe processing modules are used to process data information and acquire simulation waveforms, and the method includes: Receive the sampling start signal, clock control information and macro configuration information sent by the software side through the SCEMI protocol, and start the simulation waveform sampling of the current clock cycle; Parsing the macro configuration information and generating macro configuration parsing information, and distributing the macro configuration parsing information to a plurality of the probe processing modules; Controlling each of the probe processing modules to sample simulation waveform data, respectively compressing the simulation waveform sampled by each of the probe processing modules, and generating a plurality of compressed simulation waveforms; Storing all the compressed simulation waveforms in the DDR memory; When the storage capacity of the DDR memory reaches the upper limit, the compressed simulation waveform stored in the DDR memory is transmitted to the software side through the SCEMI protocol.

2. The method according to claim 1, characterized in that: The macro configuration parsing information includes macro identification information, and the distributing the macro configuration parsing information to the plurality of probe processing modules includes: The macro configuration parsing information is distributed to the corresponding probe processing module according to the macro identification information.

3. The method according to claim 1, characterized in that: The current clock cycle contains several frames of simulation waveform data, and the simulation waveforms sampled by each probe processing module are respectively compressed to generate several compressed simulation waveforms, including: Determine the data frame format of the simulation waveform, the data frame format of the simulation waveform includes I frame and P frame; If the data frame format of the simulation waveform is an I frame, two adjacent sets of preset bit data in the data frame of the current simulation waveform are compared bit by bit in sequence, and the data that are inconsistent with the comparison are stored to generate the compressed simulation waveform; If the data frame format of the simulation waveform is a P frame, the data of the simulation waveforms of two adjacent frames are compared bit by bit in sequence, and the data that are inconsistent with the comparison are stored to generate the compressed simulation waveform.

4. The method according to claim 1, characterized in that: After respectively compressing the simulation waveforms sampled by each of the probe processing modules and generating a plurality of compressed simulation waveforms, the method further includes: Controlling each of the probe processing modules to output a sampling completion signal; All the sampling completion signals are ANDed and calculated, and the results of the sampling completion signals after the ANDing calculation are transmitted to the software side.

5. The method according to claim 1, characterized in that: The hardware side of the simulation waveform acquisition system further includes a merging module, and before storing all the compressed simulation waveforms in the DDR memory, further includes: Merging the compressed simulation waveforms into one channel of data in sequence, and generating a merged simulation waveform; Wherein, the size of the compressed simulation waveform is consistent with the interface bit width of the DDR memory; The storing of all the compressed simulation waveforms into the DDR memory comprises: The combined simulation waveform is stored in the DDR memory.

6. The method according to claim 1, characterized in that: The hardware side of the simulation waveform acquisition system also includes a breakpoint module; While distributing the macro configuration parsing information to the plurality of probe processing modules, the macro configuration parsing information is transmitted to the breakpoint module.

7. The method according to claim 6, characterized in that: The hardware side of the simulation waveform acquisition system also includes a breakpoint waveform acquisition module; After respectively compressing the simulation waveforms sampled by each of the probe processing modules and generating a plurality of compressed simulation waveforms, the method further includes: Transmitting a plurality of the compression simulation waveforms to the breakpoint module, and controlling the breakpoint module to generate a breakpoint signal corresponding to the compression simulation waveform according to the macro configuration parsing information; Using the breakpoint waveform acquisition module to generate a breakpoint simulation waveform according to the breakpoint signal; The storing of all the compressed simulation waveforms into the DDR memory comprises: The breakpoint simulation waveform is stored in the DDR memory.

8. A simulation waveform acquisition device, characterized in that: The device is applied to the hardware side of the simulation waveform acquisition system, the hardware side of the simulation waveform acquisition system includes a DDR memory and several probe processing modules, and the device includes: An information receiving module (601) is used to receive a sampling start signal, clock control information and macro configuration information sent by the software side through the SCEMI protocol, and start sampling of the simulation waveform of the current clock cycle; An information parsing module (602) is used to parse the macro configuration information and generate macro configuration parsing information, and distribute the macro configuration parsing information to a number of the probe processing modules; A waveform sampling module (603) is used to control each of the probe processing modules to sample simulation waveform data, perform waveform compression on the simulation waveform sampled by each of the probe processing modules, and generate a plurality of compressed simulation waveforms; A waveform storage module (604), used for storing all the compressed simulation waveforms in the DDR memory; The waveform transmission module (605) is used to transmit the compressed simulation waveform stored in the DDR memory to the software side through the SCEMI protocol when the storage capacity of the DDR memory reaches an upper limit.

9. A computer device, characterized in that: The method comprises a memory and a processor, wherein the memory stores a computer program that can be loaded by the processor and execute the method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: A computer program is stored which can be loaded by a processor and execute the method as claimed in any one of claims 1 to 7.

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