A method and device for processing the worst performance of integrated circuit, electronic equipment, and medium

Abstract

The present application provides a method and device for processing the worst performance of integrated circuits, electronic equipment, and medium, which are applied to the field of integrated circuit design and reliability assessment technology. By further narrowing the sampling range based on the importance sampling principle near the initially obtained failure boundary, and determining the circuit performance prediction value of the circuit performance normally distributed at the 6-sigma position, and then combining the prediction value with the linear model of the circuit performance to form an optimization problem, the process deviation vector close to the actual situation is solved, and finally the actual circuit performance value at the 6-sigma position is obtained through circuit simulation based on the process deviation vector close to the actual situation. The boundary value of the circuit performance space is quickly and accurately solved to the worst performance close to the actual situation at limited simulation points, which significantly improves the efficiency and accuracy of integrated circuit performance evaluation.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit design and reliability assessment, and in particular to a method and device for processing the worst performance of an integrated circuit, an electronic device, and a medium. Background Art

[0002] In the design and manufacturing of integrated circuits, as process nodes enter the nanometer scale, worst case analysis technology is particularly important for identifying and responding to the impact of manufacturing process deviations. Process deviation refers to the changes and inconsistencies in component parameters caused by factors such as material properties, equipment accuracy and environmental conditions in large-scale production. This deviation may affect the performance and reliability of the circuit, causing some designs that perform well under laboratory conditions to fail to achieve the expected results in actual applications. Through worst-case analysis, engineers can predict the potential impact of these deviations on circuit functions in advance, and then design circuits that are more robust to process changes. This analysis helps ensure that the design can maintain consistent high performance in mass production and long-term use, thereby reducing rework rates and warranty costs, and improving product competitiveness in the market.

[0003] Traditionally, the Monte Carlo method is used to search for the worst case of circuit design through a large number of sampling and tube-level simulations, but this method has very high computational and time costs when dealing with complex or large-scale integrated circuits. In order to reduce costs, researchers have proposed a variety of new methods to accurately evaluate the reliability of large-scale integrated circuits, such as the importance sampling method disclosed in Reference 1, and the circuit performance distribution analytical model method based on various probability distribution functions disclosed in Reference 2. However, when dealing with high-dimensional process deviation space, these technologies still face challenges in computational cost and accuracy control.

[0004] In addition, although the response surface model can improve efficiency in some cases, in nanoscale integrated circuit design, simple linear or low-order models often cannot capture all key performance changes and need to be improved through higher-order models. The use of high-order models requires dealing with non-convex optimization problems, and solving such problems can easily fall into local optimality.

[0005] Therefore, in the reliability design of integrated circuits, a key challenge is how to quickly and accurately perform worst-case analysis with a very small number of failure samples to determine the worst value of circuit performance under the influence of high-dimensional process deviations. Traditional methods are difficult to provide effective solutions, and innovative methods are urgently needed to improve the efficiency and accuracy of analysis.

[0006] References:

[0007] [1]:Tokdar ST, Kass R E.Importance sampling: a review[J].WileyInterdisciplinary Reviews Computational Statistics, 2010,2(1):54-60. DOI:10.1002 / wics.56;

[0008] [2]:Constantinescu, C.Trends and challenges in VLSI circuitreliability[J].Micro, IEEE, 2003.DOI:10.1109 / MM.2003.1225959. Summary of the invention

[0009] In view of this, the embodiments of this specification provide a method and device for processing the worst performance of an integrated circuit, an electronic device, and a medium, which determines the predicted value of the performance value at the 6-sigma position of the normal distribution of circuit performance based on the importance sampling principle near the initially obtained failure boundary, and then obtains the corresponding process deviation vector in combination with the linear model of circuit performance, and finally obtains the real circuit performance value at the 6-sigma position through simulation, that is, the boundary value of the circuit performance space. By quickly and accurately solving the failure boundary at limited simulation points, the evaluation efficiency and accuracy are significantly improved, thereby effectively evaluating the reliability of the integrated circuit under a specific failure standard.

[0010] The embodiments of this specification provide the following technical solutions:

[0011] The embodiments of this specification provide

[0012] A method for processing the worst performance of an integrated circuit, characterized by comprising:

[0013] Computational Dataset D Each sampling point x in 3 i The corresponding weight and the sampling point x i Circuit performance simulation results y i The corresponding failure rate ; Among them, the data set D 3 is the circuit performance simulation result y i The circuit performance vector y3 and the sampling point x i The data set is composed of the sampling matrix X3, and the sampling point x in the sampling matrix X3 i Corresponding circuit performance simulation results yi The circuit performance vector y3 is formed after sorting, and the points on the failure boundary found in advance are resampled according to the preset sampling number N3 to obtain the sampling point x i The sampling matrix X3 is constructed; the weights and failure rates are calculated as follows:

[0014]

[0015]

[0016] in, , pdf norm Representation dataset D 3 corresponding M The probability density function of the dimensional standard normal distribution is pdf shift Representation dataset D 3 The optimal solution x corresponding to the failure boundary nz,2 * The new standard deviation is obtained by reducing the original standard deviation by a preset multiple. M The probability density function of the dimensional normal distribution; I( y j )exist y j >= y i When , the value is 1, and in other cases it is 0; let the failure rate vector f = [ fail 1, fail 2, …, fail N3 ] represents the failure rate corresponding to the circuit performance vector y3;

[0017] Determine the failure rate based on the circuit performance vector y3 and the failure rate vector f fail 6-sigm Corresponding circuit performance prediction value y 6-sigma ; Among them, the failure rate corresponding to the position of 6 times the standard deviation is determined for the failure rate vector f according to the Gaussian distribution: , cdf norm Represents the cumulative distribution function of the standard normal distribution;

[0018] Based on linear model y = f 3(x nz ) and circuit performance prediction value y 6-sigma , construct the optimization problem:

[0019]

[0020] Among them, the cross-validated orthogonal basis pursuit algorithm is used, based on the data set D 3. Perform linear modeling on the circuit performance indicators to obtain a linear model: y = f 3(x nz )= , f 3(x nz ) is the value of linear regression, is the transpose of the vector of key variables, coef is the regression coefficient vector, is the intercept; is the vector norm of key variables;

[0021] Solve the optimization problem to get the circuit performance prediction value y 6-sigma The corresponding real sampling point x * , and for the real sampling point x * After simulation, the actual simulation results of the corresponding circuit performance space at 6-sigma are obtained. y *.

[0022] Compared with the prior art, the at least one technical solution adopted in the embodiments of this specification can achieve the following beneficial effects:

[0023] In view of the fact that the existing technology often encounters problems such as intensive computing resources, low efficiency, and difficulty in accurately predicting the probability of failure under extreme conditions when dealing with the reliability assessment of integrated circuits with high-dimensional process deviations, the purpose of the present invention is to provide an integrated circuit reliability assessment method that focuses on the rapid solution of the failure boundary under high-dimensional process deviations, that is, by quickly and accurately solving the failure boundary at limited simulation points, the assessment efficiency and accuracy are significantly improved, thereby effectively assessing the reliability of integrated circuits under specific failure standards. In addition, the invention helps to reduce resource consumption in the design and manufacturing process of integrated circuits, optimize the circuit design process, and ultimately improve the reliability and performance of products. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0025] Figure 1 It is a schematic diagram of the worst performance processing of integrated circuits based on importance sampling in this application;

[0026] Figure 2 is a flow chart of the worst performance processing of an integrated circuit in the present application;

[0027] Figure 3 It is a schematic diagram of the structure of the worst performance processing device of the integrated circuit in this application;

[0028] Figure 4 is a schematic diagram of an electronic device in this application. DETAILED DESCRIPTION

[0029] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0030] The following describes the implementation methods of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the following embodiments and the features in the embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work belong to the scope of protection of the present application.

[0031] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present application, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspect described herein can be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this device and / or practice this method.

[0032] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application. The drawings only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0033] Additionally, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the examples can be practiced without these specific details.

[0034] When estimating the worst performance of integrated circuits (such as failure rate) using existing high-dimensional process deviation variables, existing traditional solutions have been difficult to achieve ideal results. For example, traditional Monte Carlo technology usually requires a large number of random sampling to estimate extremely low failure rates. This method faces two major challenges in practice: first, the failure rate of integrated circuits is very low. Second, the process deviation dimension is high, so it may be difficult to obtain enough failure samples in a large number of samples, or even no failure samples may be collected. Therefore, the failure rate estimate obtained directly using the Monte Carlo method is often inaccurate and has large errors.

[0035] To this end, this application proposes a worst-case performance analysis scheme based on importance sampling: Figure 1 It is shown that, for the initial failure boundary that has been preliminarily found, based on the importance sampling principle, the sampling range is further narrowed at the failure boundary, that is, resampling is performed near this failure boundary, and then the weights of the new sampling points and the failure rate of the circuit performance corresponding to the sampling points are calculated, and 6-sigma is used to determine the corresponding circuit performance prediction value, and then an accurate linear model of the performance with respect to the most important process deviation variables and its optimization problem are established, and the real sampling point vector is obtained by solving the optimization problem, and finally the real simulation result vector is obtained after circuit simulation based on the real sampling points, so that the real simulation result vector more accurately represents the real failure boundary of the integrated circuit, that is, the boundary of the circuit performance space.

[0036] Therefore, for the failure problem of circuits with high-dimensional process deviations, the efficiency of solving high-dimensional problems is effectively improved by reducing the dimension of process deviation variables and establishing quadratic models and linear models for multi-level failure boundary searches. In addition, this method also uses the importance sampling principle to obtain the value at 6-sigma in the circuit performance space, which can ultimately solve a more accurate real failure boundary, reduce the computing resource requirements in the solution, and improve the accuracy and efficiency of solving the worst performance of integrated circuits.

[0037] It should be noted that, regarding the solution for finding the initial failure boundary, reference may be made to the failure boundary solution in the prior art, or to the relevant examples disclosed later in this application.

[0038] The technical solutions provided by various embodiments of the present application are described below in conjunction with the accompanying drawings.

[0039] like Figure 2 As shown, the embodiment of this specification provides a method for processing the worst performance of an integrated circuit, which may include:

[0040] Step S202: Calculate data set D Each sampling point x in 3 i The corresponding weight and the sampling point xi Circuit performance simulation results y i The corresponding failure rate .

[0041] Among them, the data set D 3 is the circuit performance simulation result y i The circuit performance vector y3 and the sampling point x i The data set is composed of the sampling matrix X3, and the sampling point x in the sampling matrix X3 i Corresponding circuit performance simulation results y i The circuit performance vector y3 is formed after sorting, and the points on the failure boundary found in advance are resampled according to the preset sampling number N3 to obtain the sampling point x i Construct a sampling matrix X3;

[0042] The weights and failure rates are calculated as follows:

[0043]

[0044]

[0045] in, , pdf norm Representation dataset D 3 corresponding M The probability density function of the dimensional standard normal distribution is pdf shift Representation dataset D 3 The optimal solution x corresponding to the failure boundary nz,2 * The new standard deviation is obtained by reducing the original standard deviation by a preset multiple. M The probability density function of the dimensional normal distribution; I( y j )exist y j >= y i When , the value is 1, and in other cases it is 0; let the failure rate vector f = [ fail 1, fail 2, …, fail N3 ] represents the failure rate corresponding to the circuit performance vector y3.

[0046] In implementation, the initial failure boundary of the integrated circuit can be solved based on existing technologies, such as by establishing a quadratic programming problem for process deviation variables to preliminarily find the initial failure boundary, or by referring to the schematic illustrations of subsequent examples in this application.

[0047] In implementation, in determining pdf shift When the original standard deviation is reduced by 0.5 times or other multiples, the new standard deviation can be obtained.

[0048] In implementation, by setting I( y j )exist y j >= y i , and 0 in other cases. That is, by y i As the failure boundary, y >= y i When the value is 1, it is considered that the circuit has failed, and when the value is 0, it is considered that the circuit has not failed.

[0049] Therefore, using the importance sampling principle to simplify the data calculation process can not only accurately allow the new data to better express the failure conditions of integrated circuits, but also simplify data calculations, reduce calculation difficulty, and save computing resources.

[0050] Step S204: Determine the failure rate according to the circuit performance vector y3 and the failure rate vector f. fail 6-sigma Corresponding circuit performance prediction value y 6-sigma .

[0051] In practice, it is usually assumed that the circuit performance y satisfies the Gaussian distribution, and the parts per million (PPM) corresponding to the 6-sigma (six times the standard deviation) position of the Gaussian distribution is less than 3.4, so the use of the 6-sigma position corresponding data for estimation can meet the high requirements of the integrated circuit for the failure rate. Therefore, the failure rate corresponding to the 6 times standard deviation position can be determined for the failure rate vector f according to the Gaussian distribution, and then the failure rate corresponding to the 6 times standard deviation position can be used to constrain the solution.

[0052] Among them, the failure rate corresponding to the 6 times standard deviation position The calculation is as follows: , Among them, cdf norm Represents the cumulative distribution function of the standard normal distribution.

[0053] Since the failure rate vector corresponds to the circuit performance vector, the failure rate corresponding to the position of 6 times the standard deviation is determined. The corresponding circuit performance prediction value can be determined from the circuit performance vector.

[0054] It should be noted that when determining the circuit performance prediction value, it is possible to find the circuit performance vector that matches the circuit performance vector. The circuit performance corresponding to (or close to) the failure rate is used as a predicted value, and the predicted value can also be obtained by interpolation (such as linear interpolation disclosed later in this application).

[0055] By Using the circuit performance value corresponding to the failure rate as the predicted value can not only make the predicted value closer to the true value, but also simplify data processing, and well take into account the difficulty, accuracy and efficiency of data processing.

[0056] Step S206: Based on the linear model y = f 3(x nz ) and circuit performance prediction value y 6-sigma , construct the optimization problem:

[0057]

[0058] Among them, the cross-validated orthogonal basis pursuit algorithm (OMP) is used based on the data set D 3. Perform linear modeling on the circuit performance indicators to obtain a linear model:

[0059]

[0060] f 3(x nz ) is the value of linear regression, is the transpose of the vector of key variables, coef is the regression coefficient vector, is the intercept; is the vector norm of the key variables.

[0061] The key variables are determined through the above linear model , and then using key variables to construct the corresponding optimization problem can improve the accuracy of the corresponding solution results of the optimization problem.

[0062] In addition, the data set is obtained by resampling the failure boundary D In 3, data dimensionality reduction has been performed, and then the linear model is used to obtain key variables, and data dimensionality reduction is completed again, which further reduces the difficulty of data processing and can also improve the efficiency and accuracy of the solution.

[0063] Step S208: Solve the optimization problem to obtain the circuit performance prediction value y 6-sigma The corresponding real sampling point x * , and for the real sampling point x *After simulation, the actual simulation results of the corresponding circuit performance space at 6-sigma are obtained. y *.

[0064] By using 6-sigma related data to construct an optimization problem, the solution of the optimization problem can be closer to the actual situation. Therefore, the sampling points (i.e., the circuit performance prediction values) obtained by solving the optimization problem are y 6-sigma The corresponding real sampling point x * ), is the process deviation variable that can represent the failure, and then the actual sampling point x * After simulation, the actual simulation results of the corresponding circuit performance space at 6-sigma are obtained. y *, which also represents the actual worst-case performance of the circuit.

[0065] In summary, based on the principle of importance sampling and combined with the use of 6-sigma data, the difficulty of data processing can be reduced, and the accuracy of data processing can be improved. It well solves the problem encountered in the field of integrated circuits in solving the failure boundary using high-dimensional process deviation variables.

[0066] In some implementations, a linear interpolation method may be used to determine a circuit performance prediction value corresponding to a 6-sigma failure rate, which can balance data processing difficulty and data accuracy.

[0067] In implementation, when determining the failure rate fail 6-sigma Corresponding circuit performance prediction value y 6-sigma When, according to D The circuit performance vector y3 and the corresponding failure rate vector f of all sampling points in the set 3 are sorted, and the circuit performance prediction value y is obtained by linear interpolation. 6-sigma .

[0068] In some embodiments, the local optimal solution x is initially obtained on the failure boundary. nz,1 * Perform local high-precision modeling near the failure boundary, and then solve the optimal solution x nz,2 * , which improves the nz,2 * is the mean pdf shift The probability density function data is accurate, thereby improving the accuracy of weights in importance sampling and ensuring that the 6-sigma data is closer to the actual situation.

[0069] In practice, the optimal solution x of the failure boundary nz,2 * Determine by following these steps:

[0070] The local optimal solution x on the failure boundary nz,1 * Perform local sparse linear regression modeling near the corresponding points, and build a linear optimization problem based on the sparse linear regression modeling to obtain the optimal solution x of the linear optimization problem nz,2 * :

[0071]

[0072] Among them, x rel for M dimensional independent process deviation random variable x= In , the process deviation variable related to the specified circuit performance index has a dimension of M1.

[0073] In practice, the local optimal solution x on the failure boundary nz,1 * , can be obtained based on existing technologies, such as using the traditional quadratic programming problem to solve the initial optimal solution x for the failure boundary found initially nz,1 * In addition, the optimal solution x nz,1 * It can also be solved by the examples in the following text of this application to further improve the optimal solution x nz,1 * accuracy, reduce the difficulty of solving, etc.

[0074] In some embodiments, the local optimal solution x of the failure boundary nz,1 * Determine by following these steps:

[0075] From the matrix X1 rel Extract the key variable x nz The corresponding columns form the matrix X1 nz , and then based on X1 nz and y 1 norm The circuit performance is modeled quadratically using the cross-validated LASSO algorithm, and the quadratic model is as follows:

[0076]

[0077] Solve the quadratic optimization problem for the quadratic model and obtain nz ||2<= dist min When the circuit performance f The worst value (i.e., the maximum value) of (x), and the corresponding x nz The optimal solution x nz,1 *, the quadratic optimization problem is as follows:

[0078]

[0079] in, is the value of the quadratic programming; is the transpose of the vector composed of key variables; A, b, and c are the constant coefficients of the quadratic programming model, where A is a square matrix whose size is the same as the number of key variables, b is a vector whose length is the same as the number of key variables, and c is a scalar.

[0080] In addition, when solving the above quadratic problem, it can be relaxed into a semidefinite programming problem for solution, that is, the solution can be completed through semidefinite programming.

[0081] In some embodiments, sparse linear regression modeling is performed to find the optimal solution x nz,2 * In the model, we can sample the variable space and use the new sampling points to construct a more targeted data set for modeling.

[0082] In implementation, it can be based on the data set D 2 Perform sparse linear regression modeling, where the data set D 2 is obtained by the following steps: For the key variable x nz Each variable in x nz,1 * The corresponding value in is the mean, keeping the original variance unchanged, and N 2 random samplings, and for all other non-critical variables, according to their original distribution, N After 2 random samplings, we finally get the matrix X2. We simulate the circuit at each sampling point of the matrix X2 and get the corresponding circuit performance vector y2 to form the data set. D 2.

[0083] Through new sampling, that is, with x nz,1 * The corresponding value in the data set is the mean, and the original variance is kept unchanged. Each variable in the joint variable is randomly sampled N2 times, and for all other non-critical variables, the original distribution is maintained and random sampling is performed N2 times to form a new data set. D 2 is used for sparse linear regression model modeling, which can improve the accuracy and solution difficulty of sparse linear regression model modeling.

[0084] In some implementations, a low-dimensional set of key variables may be obtained from a high-dimensional process deviation data set by modeling and solving the problem using a cross-validated orthogonal basis pursuit algorithm.

[0085] In implementation, the key variable vector x nz Obtained through the following steps:

[0086] Extract the relevant variables x from the matrix X1 rel The corresponding columns form the matrix X1 for linear modeling rel , and the circuit performance vector y 1 According to the following formula, normalization is performed and the normalized vector is obtained y 1 norm :

[0087]

[0088] in, i =1… N 1, N 1 is the number of random sampling; y 1,min Representation vector y The minimum value of 1, y 1,max Representation vector y The maximum value of 1;

[0089] Then, based on the matrix X1 rel With the normalized vector y 1 norm , the linear regression model of the circuit performance index is modeled by the cross-validated orthogonal basis pursuit algorithm as follows:

[0090]

[0091] in, is the value of linear regression; is the transpose of the vector of related variables; coef is the regression coefficient vector; is the intercept;

[0092] Finally, the non-zero items in the coef vector are screened out, and the process deviation variables in the related variable vector corresponding to the non-zero items are combined into the key variable vector x nz , whose length is M 2. The obtained x nz These are called key variables.

[0093] By filtering out non-zero items from the coef vector, and taking the process deviation variables in the related variable vectors corresponding to these non-zero items as key variables to form the vector x nz , while improving the accuracy of joint variables, it can also reduce the data dimension.

[0094] It should be noted that the data in the matrix X1 can be preliminarily screened out by sensitivity analysis or sensitivity analysis of the simulation waveform, which is related to the specified circuit performance index. rel , whose dimensions areM 1, and the other irrelevant variables are denoted as x irrel ; It can also be the sampling point matrix obtained by new sampling through the following example.

[0095] In some embodiments, the matrix X1 is obtained by the following sampling steps: for the relevant variables x rel For each variable in the distribution, the variance is increased at the mean position of its distribution. N 1 random sampling, and for irrelevant variables x irrel , according to its original distribution N 1 random sampling, the sampling points form the matrix X1.

[0096] In implementation, the multiple of increasing the variance can be a preset multiple, or a multiple related to the multiple of reducing in the above example, for example, increasing the variance by 2 times, correspondingly reducing the variance by 0.5 times in the above example. Therefore, the specific multiple setting can be flexibly set, and is not specifically limited here.

[0097] Another embodiment will be described below.

[0098] Assuming that the process variation in a given circuit can be M dimensional independent random variables x In which x m ( ) are independent of each other and satisfy the standard normal distribution with mean 0 and variance 1. At the same time, it is assumed that the circuit performance index can be expressed as y = f (x), f A larger value of (x) indicates a worse circuit performance. f The distribution of (x) can be approximated by a normal distribution. This example searches for the circuit performance at the position of 6 times the standard deviation (6-sigma) of the normal distribution. y = f (x) and the corresponding process deviation x. Note that at 6 times the standard deviation (6-sigma) f The smaller the value of (x), the higher the circuit reliability. In addition, in the following, ||•||2 represents the L2 norm of the vector, and dist =||x||2 measures the degree of deviation of the sampling points from the mean. dist min are preset parameters.

[0099] The steps of this embodiment are as follows:

[0100] Step 1: Preliminarily screen out the process deviation variables x related to the specified circuit performance indicators through sensitivity analysis or sensitivity analysis of the simulation waveform rel, whose dimensions are M 1, and the other irrelevant variables are denoted as x irrel ;

[0101] Step 2: For x rel For each variable in the distribution, increase the variance (for example, double the original variance) at the mean position of its distribution. N 1 random sampling; for irrelevant variables x irrel , according to its original distribution, N 1 random sampling, and finally get the matrix X1. Circuit simulation is performed on these sampling points to get the corresponding circuit performance vector y1, which constitutes the data set D 1.

[0102] The third step is based on D 1 Perform sparse linear modeling and for the relevant variables x rel Further screening is performed to extract variables that are more relevant to the target circuit performance. The specific process is as follows: First, extract the relevant variables x from the matrix X1 rel The corresponding columns form the matrix X1 for linear modeling rel , and then normalize y1 according to the following formula to get the vector y1 norm :

[0103] (1)

[0104] in , y 1,min represents the minimum value of vector y1, y 1,max Represents the maximum value of vector y1. Based on X1 rel With y1 norm The circuit performance indicators are modeled by the cross-validated orthogonal basis pursuit algorithm (OMP), and the linear model is as follows:

[0105] (2)

[0106] Filter out the non-zero items in the coef vector and associate them with the x rel The process deviation variables in the new vector x nz , whose length is M 2, called the key variable.

[0107] Step 4: Based on the key variable x nz Build a higher precision quadratic model: First, from the matrix X1 rel Extract x from nz The corresponding columns form the matrix X1 nz , and then based on X1 nz andy 1 norm The circuit performance is modeled quadratically using the cross-validated LASSO algorithm, and the quadratic model is as follows:

[0108] (3)

[0109] The fifth step is to solve the optimization problem (4) based on the high-precision quadratic model and obtain nz ||2<= dist min When the circuit performance f The worst value (i.e., the maximum value) of (x), and the corresponding x nz The optimal solution x nz,1 * :

[0110] (4)

[0111] The optimization problem (4) can be relaxed into a semidefinite programming problem for solution.

[0112] Step 6: Based on the search results of the failure boundary x nz,1 * , local high-precision modeling is performed near this point. The specific process is: for x nz Each variable in x nz,1 * The corresponding value in is the mean, the original variance is kept unchanged, and N2 random sampling is performed. For all other non-critical process deviation variables, according to their original distribution, N After 2 random samplings, we finally get the matrix X2. We simulate the circuits at these sampling points and get the corresponding circuit performance vector y2 to form the data set. D 2. Repeat step 3, that is, based on the data set D 2 After completing sparse linear modeling, we then construct the following optimization problem:

[0113] (5)

[0114] By solving the above optimization problem with a quadratic programming solver, we can get the optimal solution x nz,2 * .

[0115] Step 7: Based on the search results of the failure boundary x nz,2 * , sampling is performed near this point. nz When sampling each variable in , the variance is reduced to 0.5 times the original standard deviation. N3 random samplings; for all other non-critical process deviation variables, according to their original distribution, N Three random samplings are performed to finally obtain the matrix X3. Circuit simulation is performed on these sampling points, and they are sorted according to the simulation results to obtain the sorted circuit performance vector y3, which constitutes the data set D 3. Similar to the third step, the cross-validated orthogonal basis pursuit algorithm (OMP) is used based on D 3 Model the circuit performance indicators and obtain a new linear model y = f 3(x nz ).

[0116] Step 8: For D Each sampling point x in 3 i , based on the principle of importance sampling, calculate its weight w i :

[0117] (6)

[0118] in , pdf norm express M The probability density function of the dimensional standard normal distribution is pdf shift Indicates that the mean is x nz,2 * , the standard deviation is 0.5 times the original standard deviation M The probability density function of the 2-dimensional normal distribution.

[0119] Step 9, yes D Simulation results for each sampling point in 3 y i , calculate the failure rate fail i :

[0120] (7)

[0121] Where I( y j )exist y j >= y i The value is 1 when , and 0 otherwise. y i As the failure boundary, y >= y i When , the circuit is considered to be failed. Let f = [ fail 1, fail 2, …, fail N3 ] represents the failure rate corresponding to the sorted circuit performance vector y3.

[0122] Step 10. Since we assume that the circuit performance y The failure rate corresponding to the 6-sigma position satisfies the Gaussian distribution. f ail6-sigma The following formula can be used for calculation:

[0123] (8)

[0124] in cdf norm represents the cumulative distribution function of the standard normal distribution. Then linear interpolation is used, according to D The circuit performance vector y3 and the corresponding failure rate f of all sampling points in the set 3 are interpolated to obtain fail 6-sigm Corresponding circuit performance prediction value y 6-sigma .

[0125] Step 11: Linear model based on the linear equation established in step 7 y = f 3(x nz ), construct the following optimization problem:

[0126] (9)

[0127] Use a quadratic programming solver to solve (11) and get the predicted value y 6-sigma The corresponding sampling point x * After simulation, the actual simulation results at 6-sigma in the circuit performance space are obtained. y *.

[0128] In summary, existing methods for estimating the failure rate of integrated circuits with high-dimensional process deviation variables, such as the traditional Monte Carlo technique, usually require a large number of random samplings to estimate extremely low failure rates. However, this method faces two major challenges in practice: first, the failure rate of integrated circuits is very low, and second, the process deviation dimension is high. It may be difficult to obtain enough failure samples in a large number of samples, or even no failure samples may be collected. In this case, the failure rate estimate obtained directly using the Monte Carlo method is often inaccurate and has large errors.

[0129] In order to solve this problem, the present application proposes a worst performance analysis method. This method preliminarily screens the process deviation variables related to performance from the high-dimensional process deviation variables through sensitivity or waveform analysis, and further screens the most important process deviation variables from the preliminarily screened related high-dimensional process deviation variables through a cross-validated orthogonal basis pursuit algorithm, and further establishes a circuit performance model for these most important process deviation variables through a quadratic model, and finds the failure boundary through global optimization within a large process deviation range. After finding the preliminary failure boundary, the sampling range is further narrowed at the failure boundary, and an accurate linear model of the performance about the most important process deviation variables is established, and further optimized to obtain a more accurate failure boundary. Then, by sampling near this failure boundary, based on the principle of importance sampling, the predicted value of the performance value of the 6-sigma position of the normal distribution of circuit performance is determined, and then the corresponding process deviation vector is obtained in combination with the linear model of circuit performance, and finally the real circuit performance value of the 6-sigma position is obtained through simulation, that is, the boundary value of the circuit performance space.

[0130] The method of the present application can reduce the dimension of process deviation variables for the failure problem of circuits with high-dimensional process deviations, and establish quadratic models and linear models for multi-level failure boundary search, effectively improving the efficiency of solving high-dimensional problems. The method also uses the principle of importance sampling to obtain the value at 6-sigma in the circuit performance space.

[0131] Based on the same inventive concept, the present application also provides an integrated circuit worst performance processing device corresponding to the aforementioned method embodiment.

[0132] like Figure 3 As shown, an integrated circuit worst performance processing device 100 may include:

[0133] Importance Sampling Module 101: Computing Datasets D Each sampling point x in 3 i The corresponding weight and the sampling point x i Circuit performance simulation results y i The corresponding failure rate ; Among them, the data set D 3 is the circuit performance simulation result y i The circuit performance vector y3 and the sampling point x i The data set is composed of the sampling matrix X3, and the sampling point x in the sampling matrix X3 i Corresponding circuit performance simulation results y iThe circuit performance vector y3 is formed after sorting, and the points on the failure boundary found in advance are resampled according to the preset sampling number N3 to obtain the sampling point x i The sampling matrix X3 is constructed; the weights and failure rates are calculated as follows:

[0134]

[0135]

[0136] in, , pdf norm Representation dataset D 3 corresponding M The probability density function of the dimensional standard normal distribution is pdf shift Representation dataset D 3 The optimal solution x corresponding to the failure boundary nz,2 * The new standard deviation is obtained by reducing the original standard deviation by a preset multiple. M The probability density function of the dimensional normal distribution; I( y j )exist y j >= y i When , the value is 1, and in other cases it is 0; let the failure rate vector f = [ fail 1, fail 2, …, fail N3 ] represents the failure rate corresponding to the circuit performance vector y3;

[0137] Prediction value calculation module 103: Determine the failure rate according to the circuit performance vector y3 and the failure rate vector f fail 6-sigma Corresponding circuit performance prediction value y 6-sigma ; Among them, the failure rate corresponding to the position of 6 times the standard deviation is determined for the failure rate vector f according to the Gaussian distribution: , cdf norm Represents the cumulative distribution function of the standard normal distribution;

[0138] Optimization Problem Modeling Module 105: Based on Linear Models y = f 3(x nz ) and circuit performance prediction value y 6-sigma , construct the optimization problem:

[0139]

[0140] Among them, the cross-validated orthogonal basis pursuit algorithm is used, based on the data set D 3. Perform linear modeling on the circuit performance indicators to obtain a linear model: y = f 3(x nz )= , f 3(x nz ) is the value of linear regression, is the transpose of the vector of key variables, coef is the regression coefficient vector, is the intercept; is the vector norm of key variables;

[0141] Optimization problem solving module 107: Solving the optimization problem to obtain circuit performance prediction value y 6-sigma The corresponding real sampling point x * , and for the real sampling point x * After simulation, the actual simulation results of the corresponding circuit performance space at 6-sigma are obtained. y *.

[0142] It should be noted that the unit modules of the integrated circuit worst performance processing device can be configured accordingly according to the aforementioned method embodiment, which will not be further described here.

[0143] Based on the same inventive concept, the present application also provides an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute: the integrated circuit worst performance processing method as described in any embodiment of the present application.

[0144] like Figure 4 As shown, the present application also provides a schematic diagram of the structure of an electronic device, which shows the structure of the electronic device 500. The electronic device 500 is merely an example and should not limit the functions and scope of use of the embodiments of the present invention.

[0145] In the electronic device 500, it may include: at least one processor 510; and a memory 520 communicatively connected to the at least one processor; wherein the memory storage 520 has instructions executable by the at least one processor 510, and the instructions are executed by the at least one processor 510 so that the at least one processor 510 can execute: the integrated circuit worst performance processing method described in any embodiment of the present application.

[0146] It should be noted that the electronic device 500 may be in the form of a general-purpose computing device, for example, it may be a server device.

[0147] In implementation, the components of the electronic device 500 may include but are not limited to: the above-mentioned at least one processor 510, the above-mentioned at least one memory 520, and a bus 530 connecting different system components (including the memory 520 and the processor 510), wherein the bus 530 may include a data bus, an address bus, and a control bus.

[0148] In implementation, the memory 520 may include a volatile memory, such as a random access memory (RAM) 5201 and / or a cache memory 5202 , and may further include a read-only memory (ROM) 5203 .

[0149] The memory 520 may also include a program tool 5205 having a set (at least one) of program modules 5204, such program modules 5204 including but not limited to: an operating system, one or more application programs, other program modules and program data, each of which or some combination may include the implementation of a network environment.

[0150] The processor 510 executes various functional applications and data processing by running computer programs stored in the memory 520 .

[0151] The electronic device 500 may also communicate with one or more external devices 540 (e.g., keyboards, pointing devices, etc.). Such communication may be performed via an input / output (I / O) interface 550. In addition, the electronic device 500 may also communicate with one or more networks (e.g., a local area network (LAN), a wide area network (WAN), and / or a public network, such as the Internet) via a network adapter 560, which communicates with other modules in the electronic device 500 via a bus 530. It should be understood that, although not shown in the figure, other hardware and / or software modules may be used in conjunction with the electronic device 500, including but not limited to: microcode, device drivers, redundant processors, external disk drive arrays, RAID (disk array) systems, tape drives, and data backup storage systems, etc.

[0152] It should be noted that although several units / modules or sub-units / modules of the electronic device are mentioned in the above detailed description, this division is merely exemplary and not mandatory. In fact, according to the embodiments of the present application, the features and functions of two or more units / modules described above can be embodied in one unit / module. Conversely, the features and functions of one unit / module described above can be further divided into multiple units / modules to be embodied.

[0153] Based on the same inventive concept, the present application also provides a computer storage medium, which stores computer executable instructions. When the computer executable instructions are executed by a processor, they execute: the integrated circuit worst performance processing method as described in any embodiment of the present application.

[0154] It should be noted that the computer storage medium may include but is not limited to: a portable disk, a hard disk, a random access memory, a read-only memory, an erasable programmable read-only memory, an optical storage device, a magnetic storage device or any suitable combination thereof.

[0155] In a possible implementation, the present invention may also provide a form of a program product that implements data processing, which includes program code. When the program product runs on a terminal device, the program code is used to enable the terminal device to execute several steps of the method described in any of the aforementioned embodiments.

[0156] The program code for executing the present invention may be written in any combination of one or more programming languages, and may be executed entirely on a user device, partially on a user device, as an independent software package, partially on a user device and partially on a remote device, or entirely on a remote device.

[0157] In this specification, the same or similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the embodiments described later, the description is relatively simple, and the relevant parts can be referred to the partial description of the previous embodiments.

[0158] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A method for processing the worst performance of an integrated circuit, characterized in that: include: Computational Dataset Each sampling point in The corresponding weight and the sampling point Circuit performance simulation results The corresponding failure rate ; Among them, the data set The circuit performance simulation results are The circuit performance vector and by sampling point The first sampling matrix The data set is composed of the first sampling matrix The sampling points in Corresponding circuit performance simulation results Arrange the circuit performance vector , the sampling points obtained by resampling the points on the failure boundary found in advance according to the preset sampling number N3 Constructing the sampling matrix ; The weights and failure rates are calculated as follows: in, , Representation dataset Corresponding M The probability density function of the dimensional standard normal distribution is Representation dataset The corresponding optimal solution of the failure boundary * The new standard deviation is obtained by reducing the original standard deviation by a preset multiple. M Probability density function of the dimensional normal distribution; exist y j >= y i When the value is 1, otherwise it is 0; let the failure rate vector Represents the circuit performance vector The corresponding failure rate; According to the circuit performance vector and the failure rate vector , determine the failure rate Corresponding circuit performance prediction value ; Among them, according to the Gaussian distribution, the failure rate vector Determine the failure rate corresponding to the 6 standard deviation position: , cdf norm Represents the cumulative distribution function of the standard normal distribution; Based on linear model And circuit performance prediction value , construct the optimization problem: Among them, the cross-validated orthogonal basis pursuit algorithm is used, based on the data set Linear modeling is performed on the circuit performance indicators to obtain a linear model: , is the value of linear regression, is a vector of key variables, is the transpose of the vector of key variables, coef is the regression coefficient vector, is the intercept; is the vector norm of key variables; Solve the optimization problem to get the circuit performance prediction value The corresponding real sampling point * , and the real sampling point * After simulation, the actual simulation results of the corresponding circuit performance space at 6-sigma are obtained. *.

2. The worst performance processing method for integrated circuits according to claim 1, characterized in that: Determine the failure rate Corresponding circuit performance prediction value When, according to Circuit performance vector of all sample points in the set in sorted order and the corresponding failure rate vector , linear interpolation is used to obtain the circuit performance prediction value .

3. The worst performance processing method for integrated circuits according to claim 1, characterized in that: Optimal solution for failure boundary * Determine by following these steps: Local optimal solution on the failure boundary * Perform local sparse linear regression modeling near the corresponding points, and build a linear optimization problem based on the sparse linear regression modeling to obtain the optimal solution of the linear optimization problem * : in, for M dimensional independent process deviation random variables In , the vector consisting of process deviation variables related to the specified circuit performance indicators has a dimension of M1.

4. The method for processing the worst performance of an integrated circuit according to claim 3, characterized in that: Based on the dataset Perform sparse linear regression modeling, where the data set The following steps are used to obtain: For the key variable vector Each variable in * The corresponding value in is the mean, keeping the original variance unchanged, and N 2 random samplings, and for all other non-critical variables, according to their original distribution, N 2 random samplings, finally get the second sampling matrix , for the second sampling matrix Perform circuit simulation at each sampling point to obtain the corresponding circuit performance vector , forming a data set .

5. The worst performance processing method for integrated circuits according to claim 3, characterized in that: Local optimal solution of failure boundary * Determine by following these steps: From the third sampling matrix Extract the relevant variable vector from The corresponding columns constitute the relevant variable sampling matrix , then from the matrix Extract the key variable vector The corresponding columns form a matrix , and then based on and The circuit performance is modeled quadratically using the cross-validated LASSO algorithm, and the quadratic model is as follows: in, y norm For the simulation result vector y The new vector obtained by normalization is yes The vector obtained after normalization of the corresponding simulation results; Solve the quadratic optimization problem for the quadratic model and obtain the given range || ||2 <= dist min When the circuit performance The worst value of and the corresponding The optimal solution * , the quadratic optimization problem is as follows: in, is the value of the quadratic programming; A, b, and c are the constant coefficients of the quadratic programming model, where A is a square matrix whose size is the same as the number of key variables, b is a vector whose length is the same as the number of key variables, and c is a scalar.

6. The integrated circuit worst performance processing method according to claim 1, characterized in that: Key variable vector Obtained through the following steps: From the third sampling matrix Extract the relevant variable vector from The corresponding columns form a matrix for linear modeling , and the circuit performance vector Normalize according to the following formula and get the normalized vector : in, i =1… N 1, N 1 is the number of random sampling; Representation vector The minimum value of Representation vector The maximum value of Then, based on the matrix With the normalized vector , the linear regression model of the circuit performance index is modeled by the cross-validated orthogonal basis pursuit algorithm as follows: in, is the value of linear regression; is a vector of related variables, is the transpose of the vector of related variables; coef is the regression coefficient vector; is the intercept; Finally, filter out The non-zero items in the vector and the process deviation variables in the related variable vector corresponding to the non-zero items are combined into a key variable vector , whose length is M 2.

7. The worst performance processing method for integrated circuits according to claim 6, characterized in that: The third sampling matrix The following sampling steps are used to obtain: For each variable in the distribution, the variance is increased at the mean position of its distribution. N 1 random sampling, and for the irrelevant variable vector , according to its original distribution N 1 random sampling, the sampling points form the third sampling matrix .

8. An integrated circuit worst performance processing device, characterized in that: include: Importance Sampling Module: Calculate Dataset Each sampling point in The corresponding weight and the sampling point Circuit performance simulation results The corresponding failure rate ; Among them, the data set The circuit performance simulation results are The circuit performance vector and by sampling point The first sampling matrix The data set is composed of the first sampling matrix The sampling points in Corresponding circuit performance simulation results Arrange the circuit performance vector , the sampling points obtained by resampling the points on the failure boundary found in advance according to the preset sampling number N3 Construct the first sampling matrix ; The weights and failure rates are calculated as follows: in, , Representation dataset Corresponding M The probability density function of the dimensional standard normal distribution is Representation dataset The corresponding optimal solution x nz,2 * The new standard deviation is obtained by reducing the original standard deviation by a preset multiple. M Probability density function of the dimensional normal distribution; exist y j >= y i When the value is 1, otherwise it is 0; let the failure rate vector represents the failure rate corresponding to the circuit performance vector y3; Prediction value calculation module: According to the circuit performance vector and the failure rate vector , determine the failure rate Corresponding circuit performance prediction value ; Among them, according to the Gaussian distribution, the failure rate vector Determine the failure rate corresponding to the 6 standard deviation position: , cdf norm Represents the cumulative distribution function of the standard normal distribution; Optimization problem modeling module: based on linear model And circuit performance prediction value , construct the optimization problem: Among them, the cross-validated orthogonal basis pursuit algorithm is used, based on the data set Linear modeling is performed on the circuit performance indicators to obtain a linear model: , f 3(x nz ) is the value of linear regression, is a vector of key variables, is the transpose of the vector of key variables, is the regression coefficient vector, is the intercept; is the vector norm of key variables; Optimization problem solving module: Solve the optimization problem to obtain the circuit performance prediction value The corresponding real sampling point * , and the real sampling point * After simulation, the actual simulation results of the corresponding circuit performance space at 6-sigma are obtained. *.

9. An electronic device, characterized in that: include: at least one processor; And, a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute: the integrated circuit worst performance processing method as described in any one of claims 1-7.

10. A computer storage medium, characterized in that: The computer storage medium stores computer executable instructions, and when the computer executable instructions are executed by the processor, the worst performance processing method for integrated circuits according to any one of claims 1 to 7 is performed.

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