Multi-chip packaging structure and packaging method

Abstract

The invention provides a multi-chip packaging structure and a packaging method, and relates to the field of packaging. The multi-chip packaging structure comprises a first chip, a second chip and a substrate, the second chip is a flip chip; each of the first chip and the second chip comprises a first surface and a second surface which are opposite to each other, and the first surfaces are the surfaces where the salient points are located; part of the salient points on the first surface of the second chip are welded with the salient points on the first surface of the first chip; other salient points on the first surface of the second chip are also connected with a bonding pad on the surface of the substrate; the second surface of the first chip is electrically connected with the substrate. The multi-chip packaging structure can effectively improve the electrical performance and reduce the size.

Description

Technical Field

[0001] The present application relates to the field of packaging, and in particular, to a multi-chip packaging structure and a packaging method. Background Art

[0002] At present, when packaging chips, if there are multiple chips in the same package, the different chips in the same package are usually connected by metal wires, that is, wire bonding. The wire bonding method requires sufficient space for the metal wires to be electrically connected, which requires sufficient spacing between the two chips, which is not conducive to size reduction. In addition, the metal wires used for bonding are relatively long, which will affect the signal transmission of the chip to a certain extent, which is not conducive to improving the electrical performance of the chip after packaging. Summary of the invention

[0003] In view of this, the present application aims to provide a multi-chip packaging structure and a packaging method to improve the electrical performance of the multi-chip packaging structure and reduce the size of the multi-chip packaging structure.

[0004] In a first aspect, an embodiment of the present application provides a multi-chip packaging structure, comprising: a first chip, a second chip and a substrate; the second chip is a flip chip; the first chip and the second chip each comprise a first surface and a second surface relative to each other, the first surface being the surface where the bumps are located; some of the bumps on the first surface of the second chip are welded to the bumps on the first surface of the first chip; other bumps on the first surface of the second chip are also connected to pads on the surface of the substrate; the second surface of the first chip is electrically connected to the substrate.

[0005] When the second chip of the flip chip and other chips (such as the first chip) are packaged as a multi-chip to obtain a multi-chip packaging structure, in the embodiment of the present application, the first surfaces where the metal bumps of the first chip and the second chip are located are opposite, and the bumps of the two are welded. Compared with bonding with metal wires, the welding method can make the connection distance between the first chip and the second chip shorter, reduce the influence of the connection distance on signal transmission, and the first chip and the substrate, and the second chip and the substrate are electrically connected. This method enables the first chip and the second chip to have good electrical performance connectivity with the substrate respectively, and improves the effect of signal transmission. At the same time, compared with metal wires, the solder joints formed by welding have better conductivity and stronger connection strength. Therefore, the above-mentioned multi-chip packaging structure can effectively improve the electrical performance of the packaging structure. In addition, since the solder joint welding method does not need to reserve wire bonding metal wire space, the interval between the first chip and the second chip and the second chip and the substrate can be reduced, and the size of the multi-chip packaging structure can be reduced to a certain extent.

[0006] In one embodiment, the second chip is disposed above the first chip, and the bumps on the first surface of the second chip are welded to the pads on the surface of the substrate.

[0007] Similarly, in this embodiment, when the second chip is arranged above the first chip, the bumps of the second chip are welded to the pads of the substrate, thereby effectively improving the welding strength and conductivity between the second chip and the substrate, and further improving the reliability and electrical performance of the multi-chip packaging structure.

[0008] In one embodiment, a groove is disposed on the substrate; the first chip is disposed in the groove, and the second surface of the first chip is connected to the bottom surface of the groove.

[0009] In this embodiment, a groove is provided in the substrate so that the first chip is disposed in the groove, thereby reducing the height occupied by the first chip above the substrate and reducing the thickness of the multi-chip packaging structure.

[0010] In one embodiment, the depth of the groove is less than or equal to the thickness of the first chip.

[0011] When the groove is too deep, the welding distance between the first chip and the second chip is too long, so that the formed solder joint is too long, affecting the welding reliability and electrical performance of the first chip and the second chip. Therefore, in the embodiment of the present application, the groove depth can be made equal to the thickness of the first chip, so that when the groove eliminates the influence of the first chip on the thickness, the distance between the first chip and the second chip is reduced, thereby improving the welding reliability and electrical performance. At the same time, the depth of the groove can also be made less than the thickness of the first chip, further reducing the distance between the first chip and the second chip. Although this method will bring a certain thickness, it can improve the welding effect and improve the electrical performance connectivity between the first chip and the second chip.

[0012] In one embodiment, the bottom surface of the groove is the metal layer of the substrate, the second surface of the first chip is gold-plated, and the second surface is fixedly connected to the metal layer of the substrate so that the second surface of the first chip is electrically connected to the substrate.

[0013] In this embodiment, when the first chip and the second chip have been fixed by solder joints, the second surface of the first chip is fixedly connected to the bottom surface of the groove, so that the two can be fixed again, thereby improving the structural reliability of the multi-chip packaging structure. At the same time, since the first chip is set in the groove, the environment in which it is located is relatively closed, and the heat may not be discharged in time. Therefore, in the embodiment of the present application, the second surface of the first chip is connected to the metal layer of the substrate after being gold-plated. The metal has better heat dissipation performance, which can effectively improve the heat dissipation effect of the first chip. At the same time, since the metal of the substrate can be grounded, the electrical radiation of the first chip can be reduced after the first chip is connected to the metal of the substrate, thereby improving the electrostatic discharge performance.

[0014] In one embodiment, the bottom surface of the groove is welded to the second surface of the first chip, so that the second surface of the first chip is electrically connected to the substrate.

[0015] In this embodiment, when the first chip and the second chip have been fixed by solder joints, by welding the bottom surface of the groove to the second surface of the first chip, the electrical interconnection density between the first chip and the substrate can be increased, the electrical performance can be improved, and the reliability of the multi-chip packaging structure can be further improved.

[0016] In one embodiment, a first material is used for welding between the first chip and the second chip, a second material is used for welding between the first chip and the groove, and a third material is used for welding between the second chip and the substrate; the first material, the second material and the third material are the same or at least two of the three materials are different.

[0017] Different welding materials have different welding conditions such as solder joint spacing and solder joint height, and different welding materials also have different characteristics such as welding reliability and electrical properties. In the embodiments of the present application, it is allowed to use the same or different welding materials at different welding positions so that the solder joints formed at each welding point are more adapted to the actual situation of the welding point, thereby reducing the situation where poor connection reliability and electrical performance are caused by the mismatch between welding materials and welding conditions.

[0018] In one embodiment, a first medium is filled between the second chip and the first chip, a second medium is filled between the first chip and the substrate, and a third medium is filled between the second chip and the substrate; the first medium, the second medium, and the third medium are the same or at least two of the three mediums are different.

[0019] Due to the differences in the depth of the groove, different chip types, and sizes, there may be different spacings between the first chip and the substrate, between the first chip and the second chip, and between the second chip and the substrate, and the spacings between the solder joints are also different. This makes the flow conditions of the medium between the various regions different, and the effects of different media when filled under different flow conditions are different. In the embodiments of the present application, it is allowed to use the same or different media in different regions so that each region can be filled with a medium that is more compatible with the flow conditions of the region, thereby fully filling each region and reducing the occurrence of incomplete filling.

[0020] In one embodiment, the first chip is a front-mounted chip, and a first surface of the first chip is connected to a bottom surface of the groove through a lead.

[0021] In the embodiment of the present application, it is possible to package both upright chips and flip-chips in the same multi-chip packaging structure, effectively increasing the range of chip types allowed for packaging and reducing restrictions on packaging formats.

[0022] In one embodiment, the multi-chip packaging structure also includes: a third chip, the third chip including a first surface and a second surface; wherein: the third chip is arranged in the groove, and the bumps on the first surface of the third chip are welded to the bumps on the first surface of the second chip, and the second surface of the third chip is connected to the bottom surface of the groove; or, some of the bumps on the first surface of the third chip are welded to the bumps on the first surface of the first chip, and the bumps on the first surface of the third chip are also welded to the pads of the substrate.

[0023] In the embodiment of the present application, the multi-chip packaging structure is not limited to the packaging of two chips, but can be the packaging of more chips. When packaging more chips, the connection method of other chips except the first chip and the second chip can be the same as the first chip or the second chip, and the reliability and conductivity of the packaging structure between different chips can be improved by welding.

[0024] In a second aspect, an embodiment of the present application provides a multi-chip packaging method, comprising: obtaining a first chip, a second chip and a substrate; the second chip is a flip chip; the first chip and the second chip each include a first surface and a second surface relative to each other, the first surface being the surface where the bumps are located; electrically connecting the second surface of the first chip to the substrate; welding some of the bumps on the first surface of the second chip to the bumps on the first surface of the first chip; welding other bumps on the first surface of the second chip to the pads of the substrate to obtain the multi-chip packaging structure.

[0025] In one embodiment, a groove is provided on the substrate; electrically connecting the second surface of the first chip to the substrate comprises: placing the first chip in the groove and connecting the second surface of the first chip to the bottom surface of the groove.

[0026] In one embodiment, welding some of the bumps on the first surface of the second chip to the bumps on the first surface of the first chip includes: obtaining a first distance between the first surface of the second chip and the first surface of the first chip; determining a first material between the first surface of the second chip and the first surface of the first chip based on a first correspondence between the first distance, a preset distance and a solder joint material; and welding some of the bumps on the first surface of the second chip to the bumps on the first surface of the first chip based on the first material.

[0027] In one embodiment, the step of disposing the first chip in the groove and electrically connecting the second surface of the first chip to the bottom surface of the groove includes: obtaining a second distance between the second surface of the first chip and the bottom surface of the groove; determining a second material between the second surface of the first chip and the bottom surface of the groove based on a first correspondence between the second distance, a preset distance and a solder joint material; and disposing the first chip in the groove and soldering the second surface of the first chip to the bottom surface of the groove based on the second material.

[0028] In one embodiment, welding the other bumps on the first surface of the second chip to the pads of the substrate includes: obtaining a third distance between the first surface of the second chip and the substrate; determining a third material between the first surface of the second chip and the substrate based on a first correspondence between the third distance, a preset distance and a solder point material; and welding the other bumps on the first surface of the second chip to the pads of the substrate based on the third material.

[0029] In one embodiment, after the first surface of the second chip is connected to the substrate through solder joints, the method further includes: obtaining the chip size and solder joint spacing of the first chip and the second chip respectively; the solder joint spacing is the spacing between solder joints formed during welding; determining the dielectric materials corresponding to the first medium, the second medium and the third medium respectively based on the chip size, solder joint spacing and a preset second correspondence relationship of the first chip and the second chip respectively, the second correspondence relationship including the correspondence between the chip size, solder joint spacing and dielectric material; filling the first medium between the first chip and the substrate, filling the second medium between the second chip and the first chip, and filling the third medium between the second chip and the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without paying any creative work.

[0031] Figure 1 A schematic diagram of a multi-chip packaging structure provided in an embodiment of the present application;

[0032] Figure 2 A first schematic diagram of medium filling provided in an embodiment of the present application;

[0033] Figure 3 A schematic diagram of bonding the second chip to the substrate provided in one embodiment of the present application;

[0034] Figure 4 A schematic diagram of a shallow groove provided in an embodiment of the present application;

[0035] Figure 5 A schematic diagram of a groove-free embodiment of the present application;

[0036] Figure 6 A second schematic diagram of medium filling provided by an embodiment of the present application;

[0037] Figure 7 A schematic diagram of welding a front mounted chip and a groove provided in an embodiment of the present application;

[0038] Figure 8 A schematic diagram of a first packaging structure including a third chip provided in one embodiment of the present application;

[0039] Fig. 9 A schematic diagram of a second packaging structure including a third chip provided in an embodiment of the present application;

[0040] Fig.10 A flowchart of a multi-chip packaging method provided by one embodiment of the present application.

[0041] Icons: first chip 100; second chip 200; substrate 300; groove 310; solder joint 400; dielectric layer 500; first dielectric 510; second dielectric 520; third dielectric 530; third chip 600; solder ball 700. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0043] First, the present application embodiment provides a multi-chip packaging structure. Figure 1 , Figure 1 A structural schematic diagram of a multi-chip packaging structure provided for an embodiment of the present application, the multi-chip packaging structure includes: a first chip 100, a second chip 200 and a substrate 300, and a solder ball 700 may be provided on the bottom surface of the first chip 100 of the multi-chip packaging structure as a pin to connect other devices, and a dielectric layer 500 may be provided on the upper surface of the substrate 300 to fill with an insulating medium.

[0044] The first chip 100 and the second chip 200 are different chips packaged in the same package, and their types, sizes, functions, etc. may be the same or different, which is not limited here.

[0045] In this embodiment, the second chip 200 is a flip chip, which includes two opposite surfaces, namely a first surface and a second surface, wherein the first surface is the surface where the bumps are located, and the second surface is a semiconductor, such as a silicon layer.

[0046] The multi-chip packaging structure provided by the present application allows a normal chip and a flip chip to be packaged in the same packaging structure. Therefore, in the embodiments of the present application, the first chip 100 can be a flip chip or a normal chip, and no limitation is made here. Similarly, the first chip 100 also includes a first surface and a second surface. The second surface is a semiconductor, such as a silicon layer. The first surface is the surface where the pad is located. If the first chip is a normal chip, it can be electrically connected through wire bonding. If the first chip is a flip chip, it can be electrically connected through bumps. Therefore, the first surface of the first chip 100 is also the surface where the bumps are located.

[0047] In the embodiment of the present application, the first surface of the first chip 100 and the first surface of the second chip 200 are arranged opposite to each other, and some bumps on the first surface of the second chip 200 are welded to the bumps on the first surface of the first chip 100, and the welding joints 400 are formed at the welding places. Figure 1 As shown, a solder joint 400 is formed when the first chip 100 and the second chip 200 are soldered.

[0048] Next, the second chip 200 on the first surface is also electrically connected to the pads or metal contacts on the substrate 300 .

[0049] Compared with the use of metal wires for bonding, the welding method can make the connection distance between the first chip 100 and the second chip 200 shorter, reducing the impact of the connection distance on signal transmission. At the same time, compared with metal wires, the solder joints 400 formed by welding have better conductivity and stronger connection strength, which can also optimize the signal transmission performance. Therefore, the above-mentioned multi-chip packaging structure can effectively improve the electrical performance of the packaging structure. In addition, since the welding method does not require the reservation of wire bonding metal wire space, the interval between the first chip 100 and the second chip 200 and between the second chip 200 and the substrate 300 can be reduced, and the size of the multi-chip packaging structure can be reduced to a certain extent.

[0050] like Figure 1 As shown, in an embodiment of the present application, the first chip 100 can be arranged between the substrate 300 and the second chip 200, and the second chip 200 is arranged above the first chip 100. In this embodiment, the bumps on the first surface of the second chip 200 can be welded to the pads on the surface of the substrate 300.

[0051] As mentioned above, compared with metal wire bonding, welding has better connection strength and conductivity, which can make the structure more stable and the signal transmission performance better. Welding the second chip 200 and the substrate 300 can further improve the reliability and electrical performance of the multi-chip packaging structure.

[0052] In one embodiment of the present application, a first material is used for welding between the first chip 100 and the second chip 200 , and a third material is used for welding between the second chip 200 and the substrate 300 . The first material and the third material may be the same or different.

[0053] In this embodiment, the second chip 200 needs to be welded to the first chip 100 and the substrate 300 at the same time, and the spacing between the bumps on the first chip 100 and the spacing between the metal contacts on the substrate 300 may be different, which makes the welding spacing different. At the same time, the first chip 100 has a certain thickness, and the welding height between the first chip 100 and the second chip 200 is different from the welding height between the second chip 200 and the substrate 300. Different welding materials show different performances under different welding spacings and welding heights. Therefore, in the embodiment of the present application, the welding spacing and welding height can be determined according to the size of the first chip 100 and the second chip 200, the bump spacing, and the metal contact spacing of the substrate 300, and then the welding materials with performance matching the welding spacing and welding height are selected to weld the corresponding positions, so as to make the performance after welding better.

[0054] Similarly, when chip packaging, it is also necessary to fill the medium such as epoxy resin. Different mediums have different properties and fluidity. After the solder joint 400 is formed, it will hinder the flow of the medium, thereby affecting the filling effect of the medium, and may cause incomplete filling such as bubbles, thereby affecting the performance of the chip.

[0055] Therefore, if Figure 2 As shown, in the embodiment of the present application, a first medium 510 may be filled between the first chip 100 and the substrate 300, and a third medium may be filled between the second chip 200 and the substrate 300. The first medium 510 and the third medium 530 may be the same or different. By selecting different mediums to fill in different areas, the fluidity of the filling medium is more adapted to the distribution of the solder joints 400 in the area, thereby obtaining a better filling effect.

[0056] like Figure 3 As shown, in another embodiment of the present application, the second chip 200 may also be disposed between the first chip 100 and the substrate 300, and the first chip 100 is disposed on the second chip 200. In this embodiment, since the bumps and pads of the second chip 200 face upward, the pads of the second chip 200 and the substrate 300 may be connected by metal wire bonding.

[0057] In this embodiment, since the bumps of the first chip 100 and the second chip 200 are still connected by welding, the performance improvement achieved by bonding the second chip 200 and the substrate 300 by metal wires is limited compared to the method of directly welding the second chip 200 to the substrate 300. However, to a certain extent, this method can still improve the connection reliability and conductivity of the multi-chip packaging structure, as well as reduce the size of the multi-chip packaging structure.

[0058] like Figure 1 As shown, in an embodiment of the present application, a groove 310 may be further provided on the substrate 300 , the first chip 100 is disposed in the groove 310 , and the second surface of the first chip 100 is connected to the bottom surface of the groove 310 .

[0059] In this embodiment, by providing the groove 310, the first chip 100 is provided in the groove 310, thereby reducing or even eliminating the influence of the thickness of the first chip 100 on the thickness of the multi-chip package structure, which helps to reduce the thickness of the multi-chip package structure. The groove 310 can be obtained by processing the substrate 300 by existing laser grooving, laser grooving, chemical etching, etc., which will not be elaborated here.

[0060] In an embodiment of the present application, the depth of the groove 310 may be greater than the thickness of the first chip 100 , so that the first chip 100 may be completely accommodated by the groove 310 , thereby completely eliminating the influence of the thickness of the first chip 100 on the thickness of the packaging structure.

[0061] Accordingly, the deeper the groove 310 is, the farther the distance between the first chip 100 and the second chip 200 is, and the higher the height of the solder joint 400 formed by welding is. Therefore, in theory, the optimal depth of the groove 310 should be that after the first chip 100 is connected to the bottom surface of the groove 310, the first surface of the first chip 100 is flush with the surface of the substrate 300, that is, without considering the influence of the first chip 100 and the bottom surface of the groove 310 on the height, the thickness of the first chip 100 is the same as the depth of the groove 310. This method can not only eliminate the influence of the first chip 100 on the thickness to the greatest extent, but also avoid the welding distance between the first chip 100 and the second chip 200 being too far.

[0062] Likewise, see Figure 4 , Figure 4 In one embodiment of the present application, the depth of the groove 310 can also be made smaller than the thickness of the first chip 100. In this case, the distance between the first chip 100 and the second chip 200 can be minimized to the greatest extent, and the problem of the welding distance between the first chip 100 and the second chip 200 being too far can be avoided, and the problem of the formation of a solder joint 400 that is too long and affects the welding reliability and electrical performance can be avoided.

[0063] Furthermore, if Figure 5 As shown, in some other embodiments, the substrate 300 may not be provided with the groove 310 , and the second surface of the first chip 100 is directly connected to the surface of the substrate 300 , which is not limited here.

[0064] In an embodiment of the present application, in order to improve the reliability of the multi-chip packaging structure, the second surface of the first chip 100 and the substrate 300 can be fixedly connected. If the substrate 300 is provided with a groove 310, the bottom surface of the groove 310 and the second surface of the first chip 100 can be electrically connected.

[0065] There are many ways to make electrical connections. For example, in one embodiment, a groove 310 can be opened to the metal layer of the substrate 300, and the metal layer of the substrate 300 is used as the bottom surface of the groove 310. Then, gold is plated on the second surface of the first chip 100, and the gold-plated second surface is fixedly connected to the metal layer of the substrate 300, thereby achieving electrical connection between the bottom surface of the groove 310 and the second surface of the first chip 100.

[0066] The second surface is a semiconductor material, and gold plating on the second surface does not affect the electrical performance of the first chip 100. Since the groove 310 is a narrow space, its heat dissipation performance is limited, and metal has better heat dissipation performance. By gold plating and connecting to the metal layer of the substrate 300, the heat dissipation performance of the first chip 100 can be effectively improved, thereby achieving good grounding, reducing electromagnetic radiation, and improving electrostatic discharge capabilities.

[0067] In another embodiment of the present application, the bottom surface of the groove 310 can be welded to the second surface of the first chip 100, thereby increasing the electrical connection density between the first chip 100 and the substrate 300, shortening the electrical connection path, and improving the electrical performance. By welding, the connection reliability between the first chip 100 and the substrate 300 can also be improved.

[0068] In this embodiment, the material used for welding between the bottom surface of the groove 310 and the first chip 100 may be the second material. The first material, the second material and the third material may be the same, or at least two materials may be different between the first material, the second material and the third material. Specifically, they may be selected according to their respective welding spacing and heights to use welding materials at more appropriate welding positions to achieve better welding effects.

[0069] If welding is used, several solder joints are usually welded according to electrical requirements to form multiple solder joints 400, which will form gaps between the substrate 300 or the groove 310 of the substrate 300 and the first chip 100, and between the second chip and the bottom of the groove, and between the first chip and the second chip. Therefore, when packaging the chip, it is necessary to use a medium such as epoxy resin to fill the gap, and different media have different properties and fluidity. After the solder joints are formed, they will hinder the flow of the medium, thereby affecting the filling effect of the medium, and incomplete filling such as bubbles may occur, which in turn affects the reliability of chip packaging.

[0070] Therefore, in the embodiments of the present application, different media can be used for filling at different positions. For example, the first medium 510 is filled between the second chip 200 and the first chip 100, the second medium 520 is filled between the first chip 100 and the substrate 300, and the third medium 530 is filled between the second chip 200 and the substrate 300; the first medium 510, the second medium 520, and the third medium 530 are the same or at least two of the three mediums are different. The third medium also covers the first chip.

[0071] In an embodiment of the present application, the first medium can be selected based on the spacing between the second chip and the first chip, the spacing between solder joints, etc., and the second medium can be selected based on the spacing between the first chip and the substrate, the spacing between solder joints, etc., and the third medium can be selected based on the spacing between the second chip and the substrate, the spacing between solder joints.

[0072] For example, see Figure 6 , Figure 6 A schematic diagram of medium filling provided in an embodiment of the present application. Figure 6 As shown, the second medium 520 is filled between the first chip 100 and the bottom surface and sidewall of the groove 310, the first medium 510 is filled between the second chip 200 and the first chip 100, and the third medium 530 is filled between the second chip 200 and the substrate 300. Thus, different areas can be filled with mediums with fluidity adaptation according to the spacing and height of the solder joints 400, so that different areas can be completely filled with the medium, effectively reducing the negative impact on the performance of the multi-chip package structure caused by insufficient filling.

[0073] See also Figure 7 , Figure 7 A schematic diagram of welding a front-mounted chip and a groove 310 provided in an embodiment of the present application. In the embodiment of the present application, if the first chip 100 is a front-mounted chip, the first surface of the first chip 100 can be connected to the bottom surface of the groove 310 through a lead, and the lead can be a metal wire used in existing bonding. There is a pad on the first surface of the front-mounted chip, and this method can connect the pin to the substrate 300, so that the front-mounted chip can work normally. This method is compatible with front-mounted chips and flip-chips, and can effectively improve the scope of application of multi-chip packaging structures.

[0074] The multi-chip packaging structure provided in the present application is not limited to packaging the first chip 100 and the second chip 200. More chips can be arranged in the same packaging structure, and the connection relationship between more chips in the packaging structure can be similar to that of the first chip 100 or the second chip 200.

[0075] For example, see Figure 8 , Figure 8 A schematic diagram of a first packaging structure including a third chip 600 is provided for an embodiment of the present application. In an embodiment of the present application, some bumps on the first surface of the third chip 600 are welded to the bumps on the first surface of the first chip 100, and the bumps on the first surface of the third chip 600 are also welded to the pads of the substrate 300. Similar to the first chip 100 and the second chip 200, the first surface of the third chip 600 is the surface where the bumps are located, and the second surface is an insulating surface. In this embodiment, the packaging method of the third chip 600 can refer to the aforementioned second chip 200, which will not be expanded here.

[0076] For another example, see Fig. 9 , Fig. 9A schematic diagram of a second packaging structure including a third chip 600 provided in an embodiment of the present application. In this embodiment, the third chip 600 is disposed in the groove 310, and the bumps on the first surface of the third chip 600 are welded to the bumps on the first surface of the second chip 200, and the second surface of the third chip 600 is connected to the bottom surface of the groove 310. In this embodiment, the packaging method of the third chip 600 can refer to the aforementioned first chip 100, which will not be expanded here.

[0077] Similarly, if more chips need to be packaged in the same packaging structure, the packaging method can refer to the first chip 100 and the second chip 200, which will not be elaborated here.

[0078] In the multi-chip packaging structure provided in the above embodiment, the reliability of the connection and the conductivity can be improved by welding. At the same time, the distance between the first chip 100 and the second chip 200 and the distance between the second chip 200 and the substrate 300 can be effectively reduced, making the connection tighter, thereby reducing the size of the multi-chip packaging structure.

[0079] Based on the same inventive concept, the present application also provides a multi-chip packaging method, see Fig.10 , Fig.10 A flowchart of a multi-chip packaging method provided in one embodiment of the present application. The multi-chip packaging method includes:

[0080] S110, obtaining a first chip, a second chip, and a substrate.

[0081] In this embodiment, the second chip is a flip chip; the first chip and the second chip both include a first surface and a second surface opposite to each other, and the first surface is the surface where the bumps are located. The first chip can be a regular chip or a flip chip.

[0082] S120 , electrically connecting the second surface of the first chip to the substrate.

[0083] In one embodiment, a groove is provided on the substrate, and the groove can be obtained by processing the substrate by laser grooving, laser grooving, chemical etching, etc. Before welding part of the bumps on the first surface of the second chip to the bumps on the first surface of the first chip, the method can also include: arranging the first chip in the groove and connecting the second surface of the first chip to the bottom surface of the groove.

[0084] In one embodiment, before the groove is formed in the substrate, the thickness of the first chip can be obtained, and the depth of the groove can be made less than or equal to the thickness of the first chip.

[0085] In one embodiment, the bottom surface of the groove is the metal layer of the substrate, and connecting the second surface of the first chip to the bottom surface of the groove may include: gold plating the second surface of the first chip and fixedly connecting the gold-plated second surface to the metal layer of the substrate.

[0086] In one embodiment, connecting the second surface of the first chip to the bottom surface of the groove may include: welding the bottom surface of the groove to the second surface of the first chip.

[0087] In one embodiment, disposing the first chip in a groove and connecting the second surface of the first chip to the bottom surface of the groove may include: obtaining a second distance between the second surface of the first chip and the bottom surface of the groove; determining a second material between the second surface of the first chip and the bottom surface of the groove based on a first correspondence between the second distance, a preset distance and a solder joint material; disposing the first chip in the groove and soldering the second surface of the first chip to the bottom surface of the groove based on the second material.

[0088] S130, welding some of the bumps on the first surface of the second chip to the bumps on the first surface of the first chip.

[0089] In one embodiment, welding some bumps on the first surface of the second chip to bumps on the first surface of the first chip may include: obtaining a first spacing between the first surface of the second chip and the first surface of the first chip; determining a first material between the first surface of the second chip and the first surface of the first chip based on a first correspondence between the first spacing, a preset spacing and a solder joint material; and welding some bumps on the first surface of the second chip to the bumps on the first surface of the first chip based on the first material.

[0090] In one embodiment, if the first chip is a front-mounted chip, some bumps on the first surface of the second chip may be welded to the bumps on the first surface of the first chip, which may include: connecting the first surface of the first chip to the bottom surface of the groove through leads.

[0091] In one embodiment, if the multi-chip packaging structure also includes a third chip, the third chip can also be arranged in the groove, and the bumps on the first surface of the third chip can be welded to the bumps on the first surface of the second chip, and the second surface of the third chip can be connected to the bottom surface of the groove.

[0092] S140, welding other bumps on the first surface of the second chip to pads of the substrate to obtain a multi-chip packaging structure.

[0093] In one embodiment, welding other bumps on the first surface of the second chip to pads of the substrate may include: obtaining a third distance between the first surface of the second chip and the substrate; determining a third material between the first surface of the second chip and the substrate based on a first correspondence between the third distance, a preset distance and the solder point material; and welding other bumps on the first surface of the second chip to pads of the substrate based on the third material.

[0094] In one embodiment, after the first surface of the second chip is connected to the substrate through solder joints, the method further includes: obtaining the chip size and solder joint spacing of each of the first chip and the second chip; the solder joint spacing is the spacing between the solder joints 400 formed during welding; based on the chip size, solder joint spacing and a preset second correspondence of each of the first chip and the second chip, determining the dielectric materials corresponding to each of the first medium, the second medium and the third medium 530, wherein the second correspondence includes the correspondence between the chip size, the solder joint spacing and the dielectric material; filling the first medium between the first chip and the substrate, filling the second medium between the second chip and the first chip, and filling the third medium 530 between the second chip and the substrate.

[0095] In one embodiment, if the multi-chip packaging structure also includes a third chip, some bumps on the first surface of the third chip can be welded to the bumps on the first surface of the first chip, and the bumps on the first surface of the third chip can also be welded to the pads of the substrate.

[0096] The multi-chip packaging method is used to obtain the multi-chip packaging structure provided in the aforementioned embodiment. For details, please refer to the contents of the multi-chip packaging structure, which will not be elaborated here.

[0097] The above embodiments can be freely combined without conflict, and the embodiments obtained by the combination are included in the protection scope of this application.

[0098] The above detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0099] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0100] In the description of this application, it is also necessary to explain that, unless otherwise clearly specified and limited, the term "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0101] The above description is only an embodiment of the present application and is not intended to limit the protection scope of the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A multi-chip packaging structure, characterized in that: include: A first chip, a second chip and a substrate; The second chip is a flip chip; the first chip and the second chip both include a first surface and a second surface opposite to each other, the first surface being the surface where the bumps are located; Some of the bumps on the first surface of the second chip are welded to the bumps on the first surface of the first chip; The other bumps on the first surface of the second chip are also connected to the pads on the surface of the substrate; The second surface of the first chip is electrically connected to the substrate.

2. The multi-chip package structure according to claim 1, characterized in that: The second chip is arranged above the first chip, and the bumps on the first surface of the second chip are welded to the pads on the surface of the substrate.

3. The multi-chip package structure according to claim 2, characterized in that: The substrate is provided with a groove; The first chip is disposed in the groove, and the second surface of the first chip is connected to the bottom surface of the groove.

4. The multi-chip package structure according to claim 3, characterized in that: The depth of the groove is less than or equal to the thickness of the first chip.

5. The multi-chip package structure according to claim 3, characterized in that: The bottom surface of the groove is the metal layer of the substrate, the second surface of the first chip is gold-plated, and the second surface is fixedly connected to the metal layer of the substrate, so that the second surface of the first chip is electrically connected to the substrate.

6. The multi-chip package structure according to claim 3, characterized in that: The bottom surface of the groove is welded to the second surface of the first chip, so that the second surface of the first chip is electrically connected to the substrate.

7. The multi-chip package structure according to claim 6, characterized in that: The first chip and the second chip are welded using a first material, the first chip and the groove are welded using a second material, and the second chip and the substrate are welded using a third material; the first material, the second material and the third material are the same or at least two of the three materials are different.

8. The multi-chip package structure according to claim 3, characterized in that: A first medium is filled between the second chip and the first chip, a second medium is filled between the first chip and the substrate, and a third medium is filled between the second chip and the substrate; the first medium, the second medium, and the third medium are the same or at least two of the three mediums are different.

9. The multi-chip package structure according to claim 3, characterized in that: The first chip is a front-mounted chip, and a first surface of the first chip is connected to the bottom surface of the groove through a lead.

10. The multi-chip package structure according to claim 3, characterized in that: The multi-chip packaging structure further includes: a third chip, the third chip including a first surface and a second surface; wherein: The third chip is disposed in the groove, and the bumps on the first surface of the third chip are welded to the bumps on the first surface of the second chip, and the second surface of the third chip is connected to the bottom surface of the groove; Alternatively, some of the bumps on the first surface of the third chip are welded to the bumps on the first surface of the first chip, and the bumps on the first surface of the third chip are also welded to the pads of the substrate.

11. A multi-chip packaging method, characterized in that: include: Obtain a first chip, a second chip and a substrate; the second chip is a flip chip; the first chip and the second chip each include a first surface and a second surface opposite to each other, the first surface being the surface where the bumps are located; electrically connecting the second surface of the first chip to the substrate; Welding some of the bumps on the first surface of the second chip to the bumps on the first surface of the first chip; The other bumps on the first surface of the second chip are welded to the pads of the substrate to obtain a multi-chip packaging structure.

12. The multi-chip packaging method according to claim 11, characterized in that: The substrate is provided with a groove; The step of electrically connecting the second surface of the first chip to the substrate comprises: The first chip is disposed in the groove and the second surface of the first chip is electrically connected to the bottom surface of the groove.

13. The multi-chip packaging method according to claim 12, characterized in that: The step of welding some of the bumps on the first surface of the second chip to the bumps on the first surface of the first chip comprises: Acquire a first distance between a first surface of the second chip and a first surface of the first chip; Determine a first material between the first surface of the second chip and the first surface of the first chip based on a first corresponding relationship between the first spacing, a preset spacing, and a solder joint material; Part of the bumps on the first surface of the second chip and the bumps on the first surface of the first chip are welded based on the first material.

14. The multi-chip packaging method according to claim 12, characterized in that: The step of placing the first chip in the groove and electrically connecting the second surface of the first chip to the bottom surface of the groove comprises: Acquire a second distance between the second surface of the first chip and the bottom surface of the groove; Determine a second material between the second surface of the first chip and the bottom surface of the groove based on a first corresponding relationship between the second spacing, a preset spacing and a solder joint material; The first chip is disposed in the groove, and the second surface of the first chip is welded to the bottom surface of the groove based on the second material.

15. The multi-chip packaging method according to claim 12, characterized in that: The step of welding other bumps on the first surface of the second chip to pads of the substrate comprises: Acquire a third distance between the first surface of the second chip and the substrate; Determine a third material between the first surface of the second chip and the substrate based on a first corresponding relationship between the third spacing, a preset spacing, and a solder joint material; The other bumps on the first surface of the second chip are welded to the pads of the substrate based on the third material.

16. The multi-chip packaging method according to claim 12, characterized in that: After the first surface of the second chip is connected to the substrate through solder joints, the method further includes: Obtaining chip sizes and solder joint spacings of the first chip and the second chip, respectively; the solder joint spacing is the spacing between solder joints formed during welding; Determine dielectric materials corresponding to the first medium, the second medium, and the third medium, respectively, based on respective chip sizes, solder joint spacings, and a preset second corresponding relationship between the first chip and the second chip, wherein the second corresponding relationship includes a corresponding relationship between chip sizes, solder joint spacings, and dielectric materials; A first medium is filled between the first chip and the substrate, a second medium is filled between the second chip and the first chip, and a third medium is filled between the second chip and the substrate.

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